Semiconductor structure and manufacturing method thereof
By depositing a multi-layer dielectric layer and an insulating layer in the semiconductor structure, forming a capacitor and a character line structure, and forming a channel hole with a horn-shaped opening in the second insulating layer, the leakage phenomenon caused by the reduction of component spacing in the semiconductor structure is solved, and the effect of simplifying the process flow and improving performance is achieved.
Patent Information
- Application Number
- CN202510328126.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-17
- Filing Date
- 2025-03-19
- Publication Date
- 2025-06-13
AI Technical Summary
As the semiconductor structure size decreases, the reduction in component spacing leads to leakage, increasing process difficulty and equipment performance requirements.
By depositing a multi-layer dielectric layer and insulating layer, a capacitor and character line structure is formed, and a channel hole with a trumpet-shaped opening is formed in the second insulating layer, including a vertical channel and a landing pad, simplifying the contact formation process and reducing costs.
The formation of contacts on the substrate is achieved in one step, the process flow is simplified, the use of light masks is reduced, and the performance and manufacturing efficiency of semiconductor structures are improved.
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Figure CN120152282A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memories (DRAMs) become more highly integrated. In addition, the performance of DRAMs is improved by shortening the pitch between semiconductor structures in the DRAMs. Due to the reduction in the size of semiconductor structures, in addition to increasing the difficulty of the process, components in the semiconductor structures are also prone to leakage due to the too-close pitch. Summary of the Invention
[0003] An embodiment of the present invention provides a method for manufacturing a semiconductor structure, including depositing a first dielectric layer on a substrate; depositing a second dielectric layer on the first dielectric layer; forming a capacitor in the first dielectric layer and the second dielectric layer; depositing a first insulating layer on the second dielectric layer and the capacitor; forming a word line structure on the first insulating layer; depositing a second insulating layer on the word line structure; forming a via hole in the second insulating layer, the word line structure, and the first insulating layer, wherein the via hole includes a first section having a flared opening and a second section under the first section. The method for manufacturing a semiconductor structure further includes forming a vertical channel in the second section of the via hole; and forming a landing pad in the first section of the via hole.
[0004] In some embodiments, the step of forming a via hole in the second insulating layer, the word line structure, and the first insulating layer includes: depositing a blanket hard mask layer on the second insulating layer; forming a patterned hard mask layer on the blanket hard mask layer; and performing an etching process using the patterned hard mask layer as a mask.
[0005] In some embodiments, the etching amount of the second insulating layer adjacent to the first part of the blanket hard mask layer is greater than the etching amount of the second insulating layer away from the second part of the blanket hard mask layer.
[0006] In some embodiments, the material of the blanket hard mask layer includes silicon nitride.
[0007] In some embodiments, the method for manufacturing a semiconductor structure further includes forming a gate dielectric layer on the sidewalls of the second section of the via hole before forming the vertical channel.
[0008] In some embodiments, the method for manufacturing a semiconductor structure further includes forming a conductor layer on the vertical channel before forming the landing pad.
[0009] In some embodiments, the material of the conductor layer includes indium tin oxide, and the material of the landing pad includes tungsten.
[0010] In some embodiments, the method of fabricating a semiconductor structure further includes forming bit lines on a second insulating layer, and the bit lines are coupled to landing pads.
[0011] In some embodiments, the method of fabricating a semiconductor structure further includes forming plugs on a capacitor before forming a first insulating layer.
[0012] In some embodiments, the width of the first interval decreases gradually from top to bottom, and the width of the second interval is fixed.
[0013] Another embodiment of the present invention provides a semiconductor structure, including a first dielectric layer disposed on a substrate, a second dielectric layer disposed on the first dielectric layer, a capacitor disposed in the first dielectric layer and the second dielectric layer, a first insulating layer disposed on the second dielectric layer and the capacitor, a word line structure disposed on the first insulating layer, and a second insulating layer disposed on the word line structure. The semiconductor structure further includes a vertical channel and a landing pad. The vertical channel passes through the first insulating layer, the word line structure, and the second insulating layer, and the vertical channel is coupled to the capacitor. The landing pad is disposed in the second insulating layer and on the vertical channel, wherein the landing pad has a trumpet shape.
[0014] In some embodiments, the width of the top surface of the landing pad is greater than the width of the bottom surface of the landing pad.
[0015] In some embodiments, the width of the landing pad decreases gradually from the top surface to the bottom surface.
[0016] In some embodiments, the semiconductor structure further includes a conductor layer disposed between the landing pad and the vertical channel.
[0017] In some embodiments, the material of the conductor layer includes indium tin oxide, and the material of the landing pad includes tungsten.
[0018] In some embodiments, the semiconductor structure further includes a gate dielectric layer disposed on the sidewalls of the vertical channel.
[0019] In some embodiments, the semiconductor structure further includes bit lines disposed on the second insulating layer, and the bit lines are coupled to the landing pads.
[0020] In some embodiments, the semiconductor structure further includes plugs disposed in the second insulating layer to connect the capacitor to the vertical channel.
[0021] In some embodiments, the material of the vertical channel includes indium gallium zinc oxide.
[0022] In some embodiments, the width of the capacitor in the second insulating layer is greater than the width of the capacitor in the first insulating layer.
[0023] According to some embodiments of the present invention, the landing pad is formed in the self-aligned hole through a deposition and planarization process, so the definition of the landing pad does not require the use of an additional lithography process or an additional mask. Therefore, the process steps for fabricating the landing pad are simplified and the cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] To make the objectives, features, advantages and embodiments of the present invention more obvious and understandable, the detailed description of the accompanying drawings is as follows:
[0025] Figures 1 to 10 They are cross-sectional views of some embodiments of the method for manufacturing the semiconductor structure of the present invention at different manufacturing stages. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0026] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the sake of clear illustration, many practical details will be described together in the following description. However, it should be understood that these practical details are not used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and elements in the prior art will be shown in a simple schematic manner in the drawings, and in all the drawings, the same reference numerals will be used to represent the same or similar elements. And if possible in implementation, the features of different embodiments can be applied interactively.
[0027] In addition, for the convenience of description, spatial relative terms such as "on", "above", "below", "between", etc. can be used in the present invention to describe the relationship) or function of one element or feature and another element as shown in the drawings. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the present invention can be correspondingly interpreted.
[0028] The terms "comprising", "having", "including", etc. used in the present invention are open-ended terms, meaning including but not limited to.
[0029] In the prior art, when forming a contact for connecting an upper element and a lower element in a semiconductor structure, at least two steps are required. First, after forming a capacitor in a first dielectric layer, a contact is formed in the first dielectric layer, then a second dielectric layer is deposited, and another contact located on the contact is formed in the second dielectric layer. To simplify the process of forming the contact and save the use of photomasks, embodiments of the present invention provide a manufacturing method for forming a contact in one step on a substrate.
[0030] It should be noted that when the following drawings are described and explained in a series of operations or steps, the order of explanation of these operations or steps should not be restricted. For example, some operations or steps can be carried out in a different order from that in the present invention, or some operations or steps may occur simultaneously, or some operations may not be carried out, and / or some operations or steps can be repeated.
[0031] Referring to Figures 1 to 10 , which are cross-sectional views of some embodiments of the manufacturing method of the semiconductor structure of the present invention at different manufacturing stages. As Figure 1 shown, the manufacturing method of the semiconductor structure starts from step S10, providing a substrate 110 having a conductor layer 112 thereon. In some embodiments, the substrate 110 may comprise silicon, such as, for example, single-crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 110 may comprise an elemental semiconductor, such as germanium. In some embodiments, the substrate 110 may comprise an alloy semiconductor, such as silicon germanium, silicon carbide germanium, indium gallium phosphide, or other suitable materials. In some embodiments, the substrate 110 may comprise a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, in some embodiments, the substrate 110 may optionally have a semiconductor-on-insulator (SOI) structure. In some embodiments, the conductor layer 112 comprises tungsten (W), copper (Cu), or other suitable materials.
[0032] A first dielectric layer 120 is deposited on the conductor layer 112. In some embodiments, the first dielectric layer 120 comprises tetraethoxysilane (TEOS). In some embodiments, the first dielectric layer 120 is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable deposition processes. Then, a second dielectric layer 130 is deposited on the first dielectric layer 120. The material of the second dielectric layer 130 is different from that of the first dielectric layer 120. In some embodiments, the material of the second dielectric layer 130 comprises a nitride, such as silicon nitride. In some embodiments, the second dielectric layer 130 is deposited by CVD, PVD, or other suitable deposition processes. In some embodiments, the thickness of the first dielectric layer 120 is greater than the thickness of the second dielectric layer 130.
[0033] Next, a plurality of first openings (also referred to as capacitor openings) OP1 are formed in the first dielectric layer 120 and the second dielectric layer 130 until the top surface of the conductor layer 112 is exposed. In some embodiments, the width W1 of the first opening OP1 located in the second dielectric layer 130 is greater than the width W2 of the first opening OP1 located in the first dielectric layer 120.
[0034] A plurality of bottom capacitor plates 122 are respectively conformally deposited in each first opening OP1. Additionally, through a selective deposition process, the bottom capacitor plates 122 are deposited on the inner surfaces of the first openings OP1 in the first dielectric layer 120, and not on the inner surfaces of the first openings OP1 in the second dielectric layer 130. In some embodiments, the bottom capacitor plates 122 comprise TiN or other suitable conductive materials.
[0035] As Figure 2 shown, the manufacturing method of the semiconductor structure enters step S12, and a plurality of oxide layers 132 are conformally deposited on the bottom capacitor plates 122 and on the inner surfaces of the first openings OP1 in the second dielectric layer 130. In some embodiments, the material of the oxide layer 132 comprises a metal oxide, such as ZrO 2 . In some embodiments, the oxide layer 132 is deposited by ALD or other suitable deposition processes.
[0036] Electrode material is deposited to fill the first openings OP1, and then a back-etching process is performed to respectively form a plurality of top capacitor plates 134 in the first openings OP1. In some embodiments, the electrode material of the top capacitor plates 134 comprises TiN or other suitable conductive materials.
[0037] A plurality of plugs 136 are respectively formed on the top capacitor plates 134. In some embodiments, the material of the plugs 136 is different from the material of the top capacitor plates 134 to provide better interface performance. In some embodiments, the material of the plugs 136 comprises indium tin oxides (ITO). The top capacitor plates 134, the oxide layer 132, and the bottom capacitor plates 122 together serve as a capacitor CP.
[0038] As Figure 3 shown, the manufacturing method of the semiconductor structure enters step S14, and a first insulating layer 140 is deposited on the second dielectric layer 130 and the plugs 136 after the plugs 136 are formed. In some embodiments, the material of the first insulating layer 140 comprises an oxide, such as SiO 2Subsequently, a second opening (also referred to as a contact opening) OP2 is formed in the first insulating layer 140, the second dielectric layer 130, and the first dielectric layer 120 until a portion of the top surface of the conductor layer 112 is exposed. In some embodiments, the second opening OP2 is formed by a reactive ion etching (RIE) process. Then, a first conductive layer 152 is conformally deposited in the second opening OP2. In some embodiments, the material of the first conductive layer 152 includes TiN or other suitable conductive materials.
[0039] Next, a second conductive layer 154 is deposited on the first conductive layer 152 and fills the second opening OP2. The portion of the second conductive layer 154 that extends beyond the second opening OP2 can be removed by a planarization process. Thus, a character line contact 150 including the first conductive layer 152 and the second conductive layer 154 on the first conductive layer 152 can be formed. In some embodiments, the material of the second conductive layer 154 includes W, Cu, or other suitable materials. In some embodiments, the second conductive layer 154 is filled by a CVD, PVD, or other suitable deposition process. In some embodiments, the planarization process includes chemical mechanical polishing (CMP). In addition, the top surface of the character line contact 150 is coplanar with the top surface of the first insulating layer 140. The character line contact 150 is configured to connect the conductor layer 112 and the character line structure WL (as shown later Figure 4 ). In this way, the process of forming the character line contact 150 can be simplified, and the use of photomasks can be saved.
[0040] As Figure 4 shown, the manufacturing method of the semiconductor structure enters step S16. The character line structure WL is deposited on the first insulating layer 140 and the character line contact 150. Then, a second insulating layer 160 is deposited on the character line structure WL. A portion of the bottom surface of the character line structure WL directly contacts the top surface of the character line contact 150, thereby reducing the resistance-capacitance value between the character line structure WL and the character line contact 150. In some embodiments, the material of the character line structure WL includes W, Cu, or other suitable materials. In some embodiments, the character line structure WL is deposited by a PVD, CVD, or other suitable deposition process. In some embodiments, the character line structure WL has a protruding segment that protrudes in a direction perpendicular to the character line contact 150 and extends away from the capacitor CP. In addition, the top surface of the plug 136 is lower than the top surface of the character line structure WL.
[0041] In some embodiments, the material of the second insulating layer 160 includes nitrides, oxides, or other suitable materials, such as SiO 2 . The thickness of the second insulating layer 160 is greater than the thicknesses of the first insulating layer 140 and the word line structure WL. In some embodiments, a portion of the second insulating layer 160 is disposed on one side of the word line structure WL and directly contacts the first insulating layer 140.
[0042] As Figure 5 shown, the manufacturing method of the semiconductor structure enters step S18, and the blanket hard mask layer 170 is deposited on the second insulating layer 160. The material of the blanket hard mask layer 170 is different from that of the second insulating layer 160. In some embodiments, the material of the blanket hard mask layer 170 includes nitrides, such as silicon nitride. In some embodiments, the blanket hard mask layer 170 is deposited by an ALD process so that the blanket hard mask layer 170 deposited on the second insulating layer 160 has a relatively thin thickness.
[0043] After the blanket hard mask layer 170 is deposited on the second insulating layer 160, the patterned hard mask layer 172 is formed on the blanket hard mask layer 170. The patterned hard mask layer 172 can be formed by CVD, PVD, or other suitable deposition processes, and the thickness of the patterned hard mask layer 172 is greater than the thickness of the blanket hard mask layer 170. In addition, the material of the patterned hard mask layer 172 is different from the material of the blanket hard mask layer 170. The patterned hard mask layer 172 includes a plurality of third openings OP3, and the positions of the third openings OP3 correspond to the capacitors CP therebelow. The third openings OP3 of the patterned hard mask layer 172 at least partially overlap the capacitors CP. After the third openings OP3 in the patterned hard mask layer 172 are formed, the blanket hard mask layer 170 remains and covers the entire top surface of the second insulating layer 160.
[0044] As Figure 6 shown, the manufacturing method of the semiconductor structure enters step S20, and an etching process is performed using the patterned hard mask layer 172 (see Figure 5 ) as a mask, so that a portion of the first insulating layer 140, a portion of the word line structure WL, and a portion of the second insulating layer 160 that are not covered by the patterned hard mask layer 172 are removed after the etching process, and thus a plurality of via holes 180 are formed in the first insulating layer 140, the word line structure WL, and the second insulating layer 160. At least a portion of the top surface of the plug 136 is exposed to the via holes 180.
[0045] In some embodiments, the blanket hard mask layer 170 (see Figure 5)The blanket hard mask layer 170 and the patterned hard mask layer 172 can be completely consumed in this etching process. In some other embodiments, the blanket hard mask layer 170 and the patterned hard mask layer 172 are not completely consumed in this etching process but are removed by an additional cleaning process. In some embodiments, the etching process is a reactive ion etching process.
[0046] Because the blanket hard mask layer 170 is present between the patterned hard mask layer 172 and the second insulating layer 160, the etching process will pass through the blanket hard mask layer 170, and the etching amount of the first portion of the second insulating layer 160 adjacent to the blanket hard mask layer 170 is greater than the etching amount of the second portion of the second insulating layer 160 away from the blanket hard mask layer 170. In this way, each channel hole 180 includes a first section 182 having a flared opening and a second section 184 below the first section 182. In some embodiments, the width W3 of the first section 182 is greater than the width W4 of the second section 184. In some embodiments, the width of the first section 182 gradually decreases from top to bottom, while the width of the second section 184 is substantially fixed.
[0047] As Figure 7 shown, the manufacturing method of the semiconductor structure enters step S22, and the gate dielectric layer 190 is formed on the sidewalls of the channel holes 180. In some embodiments, the gate dielectric layer 190 is formed by conformally depositing a dielectric layer on the bottom surface and the sidewalls of the channel holes 180, and then using a directional etching process to remove the horizontal portion of the dielectric layer on the bottom surface of the channel holes 180, so that the vertical portion of the dielectric layer remaining on the sidewalls of the channel holes 180 serves as the gate dielectric layer 190. More specifically, in some embodiments, the gate dielectric layer 190 is disposed on the sidewalls of the second section 184 (see Figure 6 ) of the channel holes 180 and is not disposed on the sidewalls of the first section 182 (see Figure 6 ) of the channel holes 180 having flared openings. After the gate dielectric layer 190 is formed, the top surface of the plug 136 is exposed.
[0048] Next, a conductive material is deposited to fill the channel holes 180, and then a planarization process is performed to remove the excess portion of the conductive material. In this way, a plurality of vertical channels 200 are respectively formed in the channel holes 180. In some embodiments, the material of the vertical channels 200 is a homogeneous conductive material. In some embodiments, the material of the vertical channels 200 includes indium gallium zinc oxide (IGZO).
[0049] As Figure 8As shown, the manufacturing method of the semiconductor structure proceeds to step S24. A back-etching process is performed to recess the vertical channel 200. In some embodiments, a portion of the vertical channel 200 in the first section 182 of the channel hole 180 is removed, such that the first section 182 with a flared opening is exposed again. The remaining portion of the vertical channel 200 is substantially level with the gate dielectric layer 190.
[0050] The first section 182 of the channel hole 180 with a flared opening is directly formed above the vertical channel 200, so the first section 182 of the channel hole 180 is also referred to as a self-aligned hole over the vertical channel 200.
[0051] After the first section 182 with a flared opening is exposed, a directional deposition process is used to deposit the conductor layer 210. The conductor layer 210 is deposited on the top surface of the vertical channel 200 and on the top surface of the second insulating layer 160. The conductor layer 210 is not deposited on the sidewalls of the first section 182 of the channel hole 180. The material of the conductor layer 210 is different from the material of the vertical channel 200. In some embodiments, the material of the conductor layer 210 is ITO.
[0052] As Figure 9 shown, the manufacturing method of the semiconductor structure proceeds to step S26, depositing a metal layer on the structure as Figure 8 shown, and then performing a planarization process to remove the excess portion of the metal layer, removing a portion of the second insulating layer 160 and the conductor layer 210 thereon. The remaining metal layer is disposed in the first section 182 of the channel hole 180 as the landing pad 220. The landing pad 220 has a flared shape. The width W5 of the top surface 220T of the landing pad 220 is greater than the width W6 of the bottom surface 220B of the landing pad 220, and the width of the landing pad 220 gradually decreases from the top surface 220T to the bottom surface 220B.
[0053] In some embodiments, the material of the landing pad 220 is different from the material of the conductor layer 210. In some embodiments, the material of the landing pad 220 is W. The conductor layer 210 disposed between the landing pad 220 and the vertical channel 200 can improve the interface performance between the landing pad 220 and the vertical channel 200.
[0054] The landing pad 220 is formed in the first section 182 of the channel hole 180 through deposition and planarization processes, where the first section 182 is a self-aligned hole, so the landing pad 220 can be defined in the first section 182 without additional lithography processes and additional masks. Therefore, the landing pad 220 can also be referred to as being formed through a series of self-alignment processes.
[0055] As Figure 10As shown, the method for manufacturing the semiconductor structure proceeds to step S28. After the landing pad 220 is formed on the vertical channel 200, a plurality of bit lines 230 are formed on the landing pad 220, and the bit lines 230 are respectively coupled to the landing pad 220. In some embodiments, a plurality of recesses R are formed between the bit lines 230, and the landing pad 220 is also recessed such that the top surface 220T of the landing pad 220 is a concave surface.
[0056] In some embodiments, the plug 136 disposed on the capacitor CP serves as the drain electrode, and the landing pad 220 connected to the bit line 230 serves as the source electrode. The plug 136, the vertical channel 200, and the word line structure WL together serve as a vertical transistor. The vertical transistor and the corresponding capacitor CP together serve as a memory array.
[0057] In some embodiments of the present invention, a semiconductor structure 10 having a trumpet-shaped landing pad 220 is provided. The semiconductor structure 10 includes a substrate 110 having a conductor layer 112 thereon, a first dielectric layer 120 on the substrate 110, a second dielectric layer 130 on the first dielectric layer 120, and a plurality of capacitors CP disposed in the first dielectric layer 120 and the second dielectric layer 130. Each capacitor CP includes a top capacitor plate 134, an oxide layer 132, and a bottom capacitor plate 122, wherein the bottom capacitor plate 122 is U-shaped and connected to the conductor layer 112.
[0058] In some embodiments, the bottom capacitor plate 122 is disposed on the sidewall of the first dielectric layer 120, and the oxide layer 132 directly contacts the sidewall of the second dielectric layer 130. The top capacitor plate 134 has a first portion 135 in the second dielectric layer 130 and a second portion 137 in the first dielectric layer 120. The width W7 of the first portion 135 of the top capacitor plate 134 is greater than the width W8 of the second portion 137 of the top capacitor plate 134.
[0059] The semiconductor structure 10 further includes a plurality of plugs 136 respectively disposed on the top capacitor plate 134. The top surface of the plug 136 is coplanar with the top surfaces of the oxide layer 132 and the second dielectric layer 130. The top surface of the top capacitor plate 134 is lower than the top surface of the plug 136.
[0060] The semiconductor structure 10 further includes a first insulating layer 140 disposed on the second dielectric layer 130, a word line structure WL, and a second insulating layer 160 deposited on the word line structure WL. The semiconductor structure 10 further includes a word line contact 150 connecting the word line structure WL to the conductor layer 112. In some embodiments, the materials of the word line structure WL and the word line contact 150 include W, Cu, or other suitable materials.
[0061] The semiconductor structure 10 further includes a plurality of vertical channels 200 that vertically penetrate through the first insulating layer 140, the word line structure WL, and the second insulating layer 160. The semiconductor structure 10 further includes a gate dielectric layer 190 disposed between the vertical channels 200 and the word line structure WL. The vertical channels 200 are directly connected to the plugs 136 on the capacitor CP. In some embodiments, the top surface of the vertical channels 200 is lower than the top surface of the second insulating layer 160.
[0062] The semiconductor structure 10 further includes a plurality of landing pads 220 respectively disposed on the vertical channels 200. Each landing pad 220 has a flared shape. The width W5 of the top surface 220T of the landing pad 220 is greater than the width W6 of the bottom surface 220B of the landing pad 220, and the width of the landing pad 220 gradually decreases from top to bottom. The semiconductor structure 10 further includes a conductor layer 210 disposed between the landing pads 220 to improve the interface performance between the landing pads 220 and the vertical channels 200.
[0063] According to some embodiments of the present invention, the landing pads are formed in self-aligned holes through a deposition and planarization process, so additional lithography processes or additional masks are not required to define the landing pads. Therefore, the process steps for fabricating the landing pads are simplified and the cost is reduced.
[0064] Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended claims.
[0065]
Symbol Description
[0066] 10: Semiconductor structure
[0067] 110: Substrate
[0068] 112: Conductor layer
[0069] 120: First dielectric layer
[0070] 122: Bottom capacitor plate
[0071] 130: Second dielectric layer
[0072] 132: Oxide layer
[0073] 134: Top capacitor plate
[0074] 135: First part
[0075] 136: Plug
[0076] 137: Second part
[0077] 140: First insulating layer
[0078] 150: Character line contact
[0079] 152: First conductive layer
[0080] 154: Second conductive layer
[0081] 160: Second insulating layer
[0082] 170: Blanket hard mask layer
[0083] 172: Patterned hard mask layer
[0084] 180: Channel hole
[0085] 182: First interval
[0086] 184: Second interval
[0087] 190: Gate dielectric layer
[0088] 200: Vertical channel
[0089] 210: Conductor layer
[0090] 220: Landing pad
[0091] 220T: Top surface
[0092] 220B: Bottom surface
[0093] 230: Bit line
[0094] CP: Capacitor
[0095] OP1: First opening
[0096] OP2: Second opening
[0097] OP3: Third opening
[0098] R: Depression
[0099] S10,S12,S14,S16,S18,S20,S22,S24,S26,S28: Steps
[0100] W1,W2,W3,W4,W5,W6,W7,W8: Widths
[0101] WL: Character line structure.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: Include: depositing a first dielectric layer on the substrate; depositing a second dielectric layer on the first dielectric layer; forming a capacitor in the first dielectric layer and the second dielectric layer; Depositing a first insulating layer on the second dielectric layer and the capacitor; forming a word line structure on the first insulating layer; depositing a second insulating layer on the word line structure; Forming a channel hole in the second insulating layer, the word line structure and the first insulating layer, wherein the channel hole includes a first region having a trumpet-shaped opening and a second region under the first region; forming a vertical channel in the second section of the channel hole; as well as A landing pad is formed in the first section of the passage hole.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein the step of forming a channel hole in the second insulating layer, the word line structure and the first insulating layer comprises: depositing a blanket hard mask layer on the second insulating layer; forming a patterned hard mask layer on the blanket hard mask layer; and An etching process is performed using the patterned hard mask layer as a mask. 3 . The method for manufacturing a semiconductor structure according to claim 2 , wherein an etching amount of a first portion of the second insulating layer adjacent to the blanket hard mask layer is greater than an etching amount of a second portion of the second insulating layer away from the blanket hard mask layer. 4 . The method for fabricating a semiconductor structure according to claim 2 , wherein a material of the blanket hard mask layer comprises silicon nitride.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: Before forming the vertical channel, a gate dielectric layer is formed on the sidewall of the second region of the channel hole.
6. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: Prior to forming the landing pad, a conductor layer is formed on the vertical via. 7 . The method for manufacturing a semiconductor structure according to claim 6 , wherein a material of the conductive layer comprises indium tin oxide, and a material of the landing pad comprises tungsten.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The method also includes forming a bit line on the second insulating layer, and the bit line is coupled to the landing pad.
9. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: Before forming the first insulating layer, a plug is formed on the capacitor. 10 . The method for manufacturing a semiconductor structure according to claim 1 , wherein a width of the first region decreases gradually from top to bottom, and a width of the second region is fixed.
11. A semiconductor structure, characterized in that: Include: A first dielectric layer is disposed on the substrate; A second dielectric layer is disposed on the first dielectric layer; A capacitor is disposed in the first dielectric layer and the second dielectric layer; A first insulating layer is disposed on the second dielectric layer and the capacitor; A word line structure is disposed on the first insulating layer; A second insulating layer is disposed on the word line structure; A vertical channel passes through the first insulating layer, the word line structure and the second insulating layer, and the vertical channel is coupled to the capacitor; as well as A landing pad is disposed in the second insulating layer and located on the vertical channel, wherein the landing pad has a trumpet shape. 12 . The semiconductor structure of claim 11 , wherein a width of a top surface of the landing pad is greater than a width of a bottom surface of the landing pad. The semiconductor structure according to claim 11 , wherein a width of the landing pad decreases gradually from a top surface to a bottom surface.
14. The semiconductor structure according to claim 11, wherein: It also includes a conductor layer, which is arranged between the landing pad and the vertical channel. 15 . The semiconductor structure according to claim 14 , wherein a material of the conductive layer comprises indium tin oxide, and a material of the landing pad comprises tungsten.
16. The semiconductor structure according to claim 11, wherein: The invention also comprises a gate dielectric layer which is arranged on the side wall of the vertical channel.
17. The semiconductor structure according to claim 11, wherein: The invention also comprises a bit line which is arranged on the second insulating layer and is coupled to the landing pad.
18. The semiconductor structure according to claim 11, wherein: A plug is also included, which is disposed in the second insulating layer to connect the capacitor to the vertical channel. The semiconductor structure according to claim 11 , wherein a material of the vertical channel comprises indium gallium zinc oxide. 20 . The semiconductor structure of claim 11 , wherein a width of the capacitor in the second insulating layer is greater than a width of the capacitor in the first insulating layer.