Semiconductor structure and preparation method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a preparation method of the semiconductor structure, and the semiconductor structure comprises a substrate which is provided with a first surface and a second surface which are opposite to each other; the active columns are respectively arranged on the first surface in an array along the first direction and the second direction; the bit lines are located on the second surface, extend in the first direction and are connected with the active columns arranged in the first direction; the shielding lines are located on the second surface, extend in the first direction and are located between the adjacent bit lines; gaps are formed in the shielding wires, and the total volume of the gaps accounts for not less than 10% of the volume of the shielding wires. The active columns and the bit lines are located on the two faces of the substrate respectively, the area can be effectively saved, the storage density can be effectively improved, shielding lines are formed between the adjacent bit lines, gaps are formed in the shielding lines, the total volume of the gaps accounts for not less than 10% of the volume of the shielding lines, the coupling capacitance between the adjacent bit lines can be reduced, and the signal integrity and the anti-interference capacity can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] As the integration density of memories develops towards a higher level, higher requirements are imposed on the arrangement manner of transistors and the transistor size in a memory array structure. Researchers have developed a vertical transistor structure, which can reduce the occupied area and improve the storage density. However, the coupling capacitance between adjacent bit lines has become a key factor restricting vertical transistor memories. How to reduce the coupling capacitance between adjacent bit lines, improve signal integrity and anti-interference ability has become a hot research topic. Summary of the Invention

[0003] In view of the shortcomings of the existing methods, the present application provides a semiconductor structure and a method for manufacturing the semiconductor structure, so as to reduce the coupling capacitance between adjacent bit lines, improve signal integrity and anti-interference ability.

[0004] According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor structure, including: a substrate having a first surface and a second surface disposed opposite to each other;

[0005] Active columns arranged in an array along a first direction and a second direction respectively on the first surface;

[0006] Bit lines located on the second surface, extending along the first direction, and connected to the active columns arranged in the first direction;

[0007] Shielding lines located on the second surface, extending along the first direction, and located between adjacent bit lines;

[0008] The shielding lines have voids, and the total volume of the voids accounts for no less than 10% of the volume of the shielding lines.

[0009] In some embodiments, the shielding lines are porous conductive materials, and the pores are uniformly distributed in the shielding lines.

[0010] In some embodiments, the shielding lines are hollow conductive materials, and the shielding lines have holes.

[0011] In some embodiments, there are multiple shielding lines, which are arranged in parallel between adjacent bit lines.

[0012] In some embodiments, word lines are located on the first surface, extend along the second direction, and are connected to the active columns arranged in the second direction, and the second direction is perpendicular to the first direction.

[0013] According to a second aspect of the embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, including providing a substrate having a first surface and a second surface disposed opposite to each other;

[0014] Forming active pillars on the first surface, the active pillars being arranged in an array along a first direction and a second direction respectively, and the second direction being perpendicular to the first direction;

[0015] Forming bit lines on the second surface, the bit lines extending along the first direction and connecting the active pillars arranged in the first direction;

[0016] Forming shielding lines on the second surface, the shielding lines extending along the first direction and being located between adjacent bit lines;

[0017] There are voids in the shielding lines, and the volume ratio of the voids to the volume of the shielding lines is not less than 10%.

[0018] In some embodiments, forming active pillars on the first surface includes:

[0019] Etching on the first surface to form first grooves extending along the first direction and arranged along the second direction, and filling a first isolation layer in the first grooves;

[0020] Etching on the first surface to form second grooves extending along the second direction and arranged along the first direction, and filling a second isolation layer in the second grooves;

[0021] The depth of the first grooves is greater than the depth of the second grooves.

[0022] In some embodiments, forming bit lines on the second surface includes:

[0023] Flipping the substrate, grinding and thinning the second surface to expose the first isolation layer, depositing a metal material layer on the second surface, reacting the metal material layer with the substrate to form the bit lines, and removing the unreacted metal material layer.

[0024] In some embodiments, forming shielding lines on the second surface includes:

[0025] Etching away part of the first isolation layer, forming third grooves between adjacent bit lines, forming a shielding line material layer in the third grooves, and grinding away the shielding line material layer on the second surface to form the shielding lines.

[0026] In some embodiments, it further includes: forming word lines in the second grooves, the word lines extending along the second direction and connecting the active pillars arranged in the second direction.

[0027] In embodiments of the present disclosure, the active pillars and bit lines are respectively located on two sides of the substrate, which can effectively save area and improve storage density. A shielding line is formed between adjacent bit lines, and there are voids in the shielding line. The total volume of the voids accounts for no less than 10% of the volume of the shielding line, which can reduce the coupling capacitance between adjacent bit lines, improve signal integrity and anti-interference ability. In addition, the shielding line with voids can also relieve the stress effect of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective schematic diagram of a semiconductor structure shown according to an exemplary embodiment;

[0029] Figure 2 is a perspective schematic diagram of another semiconductor structure shown according to an exemplary embodiment;

[0030] Figure 3 is a perspective schematic diagram of another semiconductor structure shown according to an exemplary embodiment;

[0031] Figure 4 is a perspective schematic diagram of another semiconductor structure shown according to an exemplary embodiment;

[0032] Figure 5 is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

[0033] Figure 6 is a top view schematic diagram of a semiconductor structure shown according to an exemplary embodiment;

[0034] Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A and Figure 17A are cross-sectional schematic diagrams of the memory along the aa' direction during the manufacturing process of the semiconductor structure;

[0035] Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B and Figure 17B are cross-sectional schematic diagrams of the memory along the bb' direction during the manufacturing process of the semiconductor structure;

[0036] Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C and Figure 17C are schematic cross-sectional views of the memory along the cc' direction during the preparation of the semiconductor structure;

[0037] Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D are schematic cross-sectional views of the memory along the dd' direction during the preparation of the semiconductor structure.

[0038] Description of the reference numerals:

[0039] 10: Substrate; 11: Active column; 12: Bit line; 13: Shielding line; 14: Word line; 15: Isolation layer; 16: Hole; 171: First interlayer; 172: Second interlayer; 18: First isolation layer; 19: Second isolation layer; 191: First isolation sublayer; 192: Second isolation sublayer; 20: Gate oxide layer; 21: Capacitor; 211: Lower electrode; 212: High-K dielectric layer; 213: Upper electrode; 22: Carrier plate; 23: First metal material layer; T1: First groove; T2: Second groove; T3: Third groove. Detailed implementation manners

[0040] The technical solutions of the present disclosure will be further described in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] The present disclosure will be described more specifically by way of example with reference to the drawings in the following paragraphs. The advantages and features of the present disclosure will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present disclosure.

[0042] It will be understood that the terms "on", "above", and "over" in this disclosure should be construed in the broadest manner such that "on" not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0043] In the embodiments of this disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence.

[0044] In the embodiments of this disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of a lower or upper structure, or can have a scope that is less than the scope of the lower or upper structure. Additionally, the layer can be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of a continuous structure, or the layer can be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0045] It should be noted that, without conflict, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily.

[0046] Figure 1 is a three-dimensional schematic diagram of a semiconductor structure shown according to an exemplary embodiment. By Figure 1 It can be obtained that the semiconductor structure includes a substrate (not shown), the substrate having a first surface and a second surface disposed opposite to each other, active pillars 11, and the active bodies 11 are respectively arranged in an array along a first direction (e.g., the Y direction) and a second direction (e.g., the X direction) on the first surface; bit lines 12, the bit lines 12 are located on the second surface and extend along the first direction (e.g., the Y direction), connecting the active pillars 11 arranged in the first direction (e.g., the Y direction), shielding lines 13, the shielding lines 13 are located on the second surface and extend along the first direction (e.g., the Y direction), located between adjacent bit lines 12, and there are voids in the shielding lines 13, and the total volume of the voids accounts for no less than 10% of the volume of the shielding lines 13. The active pillars 11 and the bit lines 12 are respectively located on two sides of the substrate, which can effectively save area and improve the storage density. Shielding lines 13 are formed between adjacent bit lines 12, and there are voids in the shielding lines 13, and the total volume of the voids accounts for no less than 10% of the volume of the shielding lines 13, which can reduce the coupling capacitance between adjacent bit lines 12, improve the signal integrity and anti-interference ability. In addition, the shielding lines 13 with voids can also relieve the stress effect of the wafer.

[0047] Continue to refer to Figure 1, in some embodiments, the active pillars 11 are arranged perpendicular to the substrate. The active bodies 11 are arranged in an array along the first direction (e.g., the Y direction) and the second direction (e.g., the X direction) on the first surface. The active pillars 11 can be part of the substrate and are formed by etching the substrate. The material of the active pillars 11 includes semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. In the embodiments of the present application, a single-crystalline silicon substrate is taken as an example for illustration.

[0048] Continue to refer to Figure 1 , in some embodiments, the bit lines 12 are located on the second surface of the substrate, extend along the first direction (e.g., the Y direction), and are connected to one end of the active pillars 11 arranged in the first direction (e.g., the Y direction). The bit lines 12 are made of electrically conductive materials. The materials of the bit lines 12 can include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). In some embodiments, there is also a transition contact layer (not shown) between the bit lines 12 and the active pillars 11. The transition contact layer is made of a conductive material and can be a metal silicide material, which is used to reduce the contact resistance between the bit lines 12 and the active pillars 11.

[0049] Continue to refer to Figure 1, in some embodiments, the shield line 13 is located on the second surface of the substrate, extends along a first direction (e.g., the Y direction), is located between adjacent bit lines 12, and is alternately arranged with the bit lines 12 along a second direction (e.g., the X direction). The shield line 13 is made of a conductive material, and the material of the shield line 13 may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). There are voids in the shield line 13, and the total volume of the voids accounts for no less than 10% of the volume of the shield line 13. After the shield line 13 is energized, an electron barrier can be formed, which can reduce the coupling capacitance between adjacent bit lines 12, improve signal integrity and anti-interference ability. In addition, the shield line 13 with voids can also relieve the stress effect of the wafer.

[0050] Continue to refer to Figure 1 , in some embodiments, the shield line 13 is a porous conductive material, and the pores are uniformly distributed in the shield line 13. The porosity is between 10% and 90% (the porosity is the ratio of the volume of the pores to the volume of the shield line 13). The porous conductive material may be one or more of a porous titanium-containing material, a porous silicon material, graphene or graphene-based materials, and two-dimensional materials such as MoS or CoS. The porous conductive material can be prepared by one or more of methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering method, and electroplating method. The porous conductive material can reduce the coupling capacitance between adjacent bit lines 12, improve signal integrity and anti-interference ability, and the preparation process is simple, which can save a large amount of time and financial costs.

[0051] Figure 2 is a three-dimensional schematic diagram of another semiconductor structure shown according to an exemplary embodiment. Refer to Figure 2, in some embodiments, the shield wire 13 is a hollow conductive material, and there are holes 16 in the shield wire 13. The volume of the holes 16 accounts for more than 10% of the volume of the shield wire 13. The holes 16 can be a whole, or can be 2, 3 or more. The shape of the holes 16 can be oval, water droplet-shaped or irregular. The shield wire 13 with holes 16 can be prepared by one or more of the methods such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), sputtering method, electroplating method, etc.

[0052] Figure 3 is a three-dimensional schematic diagram of another semiconductor structure shown according to an exemplary embodiment. Refer to Figure 3 , in some embodiments, the shield wire 13 is a U-shaped groove, which can have an upward opening or a downward opening. A first interlayer 171 is provided in the U-shaped groove. The volume ratio of the first interlayer 171 to the volume of the shield wire 13 is greater than 10%. The first interlayer 171 can fill the entire U-shaped groove or partially fill the U-shaped groove. There can also be voids in the U-shaped groove. The material of the first interlayer 171 can be a low dielectric constant material, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride. The first interlayer 171 can be prepared by one or more of the processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, plasma enhanced deposition process and Spin-on Dielectric (SOD) process, etc.

[0053] Figure 4 is a three-dimensional schematic diagram of another semiconductor structure shown according to an exemplary embodiment. Refer to Figure 4, in some embodiments, there are multiple shielding lines 13, which are arranged in parallel between adjacent bit lines 12. A second interlayer 172 is provided between the multiple shielding lines 13, and the thickness of the second interlayer 172 can be adjusted. The volume ratio of the second interlayer 172 to the volume of the shielding lines 13 is greater than 10%. The material of the second interlayer 172 can be a low dielectric constant material, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride. The second interlayer 172 can be prepared by one or more of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD) process.

[0054] Continue to refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 , in some embodiments, an isolation layer 15 is further provided between the bit line 12 and the shielding line 13. The isolation layer 15 can isolate the bit line 12 and the shielding line 13 to prevent the bit line 12 and the shielding line 13 from contacting and forming a short circuit. The isolation layer 15 covers the surface of the bit line 12 and can also protect the bit line 12 from being damaged by subsequent processes. The material of the isolation layer 15 can be a low dielectric constant material, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride. The isolation layer 15 can be prepared by one or more of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD) process.

[0055] Continue to refer to Figure 1 , Figure 2 , Figure 3 and Figure 4, in some embodiments, the semiconductor structure further includes a word line 14 disposed on the first surface of the substrate. The word line 14 extends along a second direction (e.g., the X direction), connects the active pillars 11 along the second direction (e.g., the X direction), and the word line 14 can be disposed around the active pillars 11, or on one side, two sides, or three sides of the active pillars 11, for controlling the conduction and cutoff of the transistor. The word line 14 is made of a conductive material, and the material of the word line 14 may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co- and Ni-based alloys, Fe- and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). The method of forming the word line 14 can employ one or more of chemical vapor deposition process (CVD), physical vapor deposition process (PVD), sputtering method, electroplating method, etc.

[0056] Figure 5 Schematic flow diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure; Figure 6 Top view schematic diagram of a semiconductor structure shown according to an exemplary embodiment; Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A Cross-sectional schematic diagram of the memory along the aa' direction during the manufacturing process of the semiconductor structure; Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B Cross-sectional schematic diagram of the memory along the bb' direction during the manufacturing process of the semiconductor structure; Figure 7C , Figure 8C , Figure 9C , Figure 10C ,Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C and Figure 17C are cross-sectional views of the semiconductor structure along the cc' direction during the preparation of the memory; Figure 7D , Figure 8D , Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D are cross-sectional views of the memory along the dd' direction during the preparation of the semiconductor structure.

[0057] The following will describe in detail the method for preparing a semiconductor structure provided by an embodiment of the present disclosure with reference to the accompanying drawings. Refer to Figure 5 shown, the preparation method at least includes the following steps:

[0058] S510: Provide a substrate having opposite first and second surfaces; form active pillars on the first surface, the active pillars being arranged in an array along a first direction and a second direction respectively, the second direction being perpendicular to the first direction;

[0059] S520: Form bit lines on the second surface, the bit lines extending along the first direction and connecting the active pillars arranged in the first direction;

[0060] S530: Form shield lines on the second surface, the shield lines extending along the first direction and located between adjacent bit lines; there are voids in the shield lines, and the volume ratio of the voids to the volume of the shield lines is not less than 10%.

[0061] It should be understood that Figure 5 the steps shown in Figure 5 are not exclusive, and other steps may be performed before, after, or between any of the shown operations;

[0062] In the manufacturing method of the semiconductor structure provided by the present disclosure, in the first aspect, forming a vertical transistor structure on the first surface of the substrate can reduce the occupied area of the transistor structure and improve the storage density. In the second aspect, forming bit lines on the second surface of the substrate can reduce the process difficulty and the coupling capacitance between the bit lines and the capacitor contacts. In the third aspect, forming shield lines between adjacent bit lines can reduce the coupling capacitance between adjacent bit lines, and at the same time can improve the signal integrity and anti-interference ability. In the fourth aspect, there are voids in the shield lines, and the total volume of the voids accounts for no less than 10% of the volume of the shield lines, which can relieve the stress effect of the wafer.

[0063] Figure 6 FIG. 4 is a top view schematic diagram of a memory shown according to an exemplary embodiment. In some embodiments, a plurality of active pillars 11 are arranged in an array, a plurality of word lines 14 extend along a second direction (e.g., the X direction), are arranged along a first direction (e.g., the Y direction), and each word line 14 is connected to active body structures 11 arranged along the second direction (e.g., the X direction). A plurality of bit lines 12 extend along the first direction (e.g., the Y direction), are arranged along the second direction (e.g., the X direction), and each bit line 12 is connected to active pillars 11 arranged along the first direction (e.g., the Y direction), where the first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are perpendicular. aa' is a cross-sectional schematic diagram along the bit line 12, bb' is a cross-sectional schematic diagram between the bit lines, cc' is a cross-sectional schematic diagram along the word line 14, and dd' is a cross-sectional schematic diagram between the word lines.

[0064] Combined with Figure 5 , Figure 6 , Figure 7A , Figure 7B , Figure 7C and Figure 7D , in some embodiments, S510: Provide a substrate 10. The substrate 10 has a first surface and a second surface that are oppositely arranged. The material of the substrate 10 includes semiconductor materials, for example, elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), organic semiconductor materials or other semiconductor materials known in the art. In the embodiments of the present application, a single-crystalline silicon substrate is taken as an example for illustration.

[0065] Refer to Figure 5 , Figure 8A , Figure 8B , Figure 8C and Figure 8D, in some embodiments, S510: Form active pillars 11 on the first surface. The active pillars 11 are arranged in an array along the first direction and the second direction respectively, and the second direction is perpendicular to the first direction. The method of forming the active pillars 11 includes patterning and etching on the substrate 10 to form a plurality of first grooves T1 extending along the first direction and arranged along the second direction. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, a photoresist is deposited on the surface of the mask layer, an etching pattern is formed on the photoresist after exposure, and the mask layer and the substrate 10 are etched along the etching pattern to form the first grooves T1. The method of depositing the mask layer can include, but is not limited to, at least one of processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD). The etching method can be dry etching, wet etching, or a combination thereof.

[0066] Reference Figure 9A 、 Figure 9B 、 Figure 9C And Figure 9D , in some embodiments, deposit a first isolation material in the first grooves T1, grind and flatten to form a first isolation layer 18. The material of the first isolation layer 18 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride, so as to reduce the coupling between adjacent bit line structures 17. The first isolation layer 18 can adopt a deposition process, and the deposition process can include, but is not limited to, at least one of processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD). The embodiments of the present application are described by taking silicon oxide as an example.

[0067] Continue to refer to Figure 9A 、 Figure 9B 、 Figure 9C And Figure 9D, in some embodiments, patterning and etching are performed on the substrate 10 to form a plurality of second grooves T2 extending in the second direction and arranged in the first direction. The first groove T1 and the second groove T2 are perpendicular to each other, and the depth of the first groove T1 is greater than the depth of the second groove T2, forming the active pillars 11 perpendicular to the substrate 10. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, photoresist is deposited on the surface of the mask layer, and an etching pattern is formed on the photoresist after exposure. The mask layer, a part of the first isolation layer 18, and the substrate 10 are etched along the etching pattern to form the second groove T2. The method of depositing the mask layer can include, but is not limited to, at least one of processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, plasma enhanced deposition process, and Spin-on Dielectric (SOD). The etching method can be dry etching, wet etching, or a combination thereof.

[0068] Continue to refer to Figure 9A , Figure 9B , Figure 9C and Figure 9D, in some embodiments, a second isolation material is deposited in the second groove T2, and polished to form a second isolation layer 19, where the second isolation layer 19 includes a first isolation sub-layer 191 and a second isolation sub-layer 192. The first isolation sub-layer 191 is deposited on the sidewall of the second groove T2, and the second isolation sub-layer 192 is deposited within the first isolation sub-layer 191. The first isolation sub-layer 191 and the second isolation sub-layer 192 fill the second groove T2. The materials of the first isolation sub-layer 191 and the second isolation sub-layer 192 can be low dielectric constant materials, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride, so as to reduce the coupling between adjacent active pillars 11. The materials of the first isolation sub-layer 191 and the second isolation sub-layer 192 can be the same or different. The first isolation sub-layer 191 and the second isolation sub-layer 192 can adopt a deposition process, and the deposition process can include but is not limited to at least one of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD) process. The first isolation sub-layer 191 and the second isolation sub-layer 192 can adopt the same process or different processes. In the embodiments of the present application, the case where the first isolation sub-layer 191 uses silicon oxide and the second isolation sub-layer 192 uses silicon nitride is taken as an example for illustration.

[0069] Reference Figure 10A 、 Figure 10B 、 Figure 10C And Figure 10D, in some embodiments, part of the second isolation layer 18 and part of the first isolation sub-layer 191 are selectively etched away to expose part of the active pillars 11, and word lines 14 surrounding the active pillars 11 are formed. The word lines 14 extend in the second direction and are connected to the active pillars 11 arranged in the second direction. The word lines 14 are made of a conductive material, and the material of the word lines 14 may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co- and Ni-based alloys, Fe- and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon-germanium). The method for forming the word lines 14 may employ one or more of chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, sputtering method, electroplating method, etc. In some embodiments, before forming the word lines 14, a gate oxide layer 20 is further formed. The gate oxide layer 20 is located between the active pillars 11 and the word lines 14, and the gate oxide layer 20 may be formed by one or more of in-situ steam generation (ISSG) process, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, high density plasma (HDP) process, etc. The material of the gate oxide layer 20 is selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanate oxide, or a combination thereof.

[0070] Reference Figure 11A , Figure 11B , Figure 11C and Figure 11D, in some embodiments, after forming the word line 14, forming a storage structure at one end of the active pillar is further included. The storage structure may include one or more of a capacitor, a ferroelectric storage structure, a phase change storage structure, a resistive random access memory (RRAM) structure, and a magnetic random access memory (MRAM) structure, and is configured to store the information conducted by the bit line 12. In this application, the capacitor 21 is taken as an example. The capacitor 21 includes a lower electrode 211, a high-K dielectric layer 212, and an upper electrode 213. The lower electrode 211 is connected to the active pillar 11. The material of the lower electrode 211 may be selected from at least one of metals, metal nitrides, and metal oxides, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO 2 ), titanium oxide (TiO). The high-K dielectric layer 212 covers the surface of the lower electrode 211. The material of the high-K dielectric layer 212 may be respectively selected from at least one of high-k dielectric films with a dielectric constant higher than that of silicon dioxide, such as hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO 3 ), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO). The upper electrode 213 covers the surface of the high-K dielectric layer 212. The material of the upper electrode 213 may be selected from at least one of metals, metal nitrides, and metal oxides, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO 2 ), titanium oxide (TiO). The materials of the upper electrode 213 and the lower electrode 211 may be the same or different.

[0071] Reference Figure 5 , Figure 12A , Figure 12B , Figure 12C and Figure 13D, in some embodiments, S520: Form bit lines 12 on the second surface. The bit lines 12 extend along the first direction and are connected to the active pillars 11 arranged in the first direction. Specifically, form a carrier plate 22 on the first surface of the substrate. The carrier plate is located on the capacitor and can protect the capacitor from damage. Flip the substrate 10 and grind and thin the second surface of the substrate 10 to expose the first isolation layer 18. The carrier plate 22 can be a wafer or other carriers that can carry semiconductor structures. One or more of laser cutting process, chemical mechanical polishing process, and etching process can be used to thin the second surface of the substrate 10 to expose the first isolation layer 18. The substrate is divided into multiple strip-shaped bodies extending along the first direction by the first groove T1, and multiple active pillars 11 are arranged along the first direction and are disposed on the strip-shaped bodies extending along the first direction.

[0072] Reference Figure 13A , Figure 13B , Figure 13C and Figure 13D , in some embodiments, deposit a first metal material layer 23 on the second surface of the substrate. The metal material layer 23 covers the surface of the first isolation layer 18 and the strip-shaped bodies. The material of the metal material layer can include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). The method for forming the metal material layer 23 can adopt one or more of chemical vapor deposition process (CVD), physical vapor deposition process (PVD), sputtering method, electroplating method, etc.

[0073] Reference Figure 14A , Figure 14B , Figure 14C and Figure 14D , in some embodiments, perform a high-temperature treatment on the semiconductor structure to react the metal material layer 23 with the substrate 10 and then remove the unreacted metal material layer 23 to form bit lines 12 on the second surface of the substrate. The bit lines 12 extend along the first direction and are connected to the active pillars 11 arranged along the first direction.

[0074] Reference Figure 5 , Figure 15A , Figure 15B , Figure 15C andFigure 15D , in some embodiments, S530: Form a shielding line 13 on the second surface. The shielding line 13 extends along the first direction and is located between adjacent bit lines 12; there are voids in the shielding line 13, and the volume ratio of the voids to the volume of the shielding line is not less than 10%. Specifically, etch away part of the second isolation layer 18 to form a third groove T3. The first isolation layer 18 and the bit line 12 are made of different materials, and self-aligned selective etching can be performed using an etch selectivity ratio. Only the first isolation layer 18 is etched, and the bit line 12 is retained. Dry etching or wet etching can be used. The bottom of the third groove T3 can be slightly lower than the position where the bit line is connected to the active pillar.

[0075] Reference Figure 16A , Figure 16B , Figure 16C and Figure 16D , in some embodiments, deposit an isolation layer 15 in the third groove. The isolation layer 15 is conformally deposited in the third groove T3 and covers the surface of the bit line 12. It can also protect the bit line 12 from damage during subsequent processes. The material of the isolation layer 15 can be a low dielectric constant material, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride. The isolation layer 15 can be prepared by one or more of the following processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD) process.

[0076] Reference Figure 17A , Figure 17B , Figure 17C and Figure 17D, in some embodiments, a shielding line material is deposited on the surface of the isolation layer 15, and then ground and flattened to form the shielding line 13. The shielding line 13 extends along a first direction (e.g., the Y direction), is located between adjacent bit lines 12, and is alternately arranged with the bit lines 12 along a second direction (e.g., the X direction). The shielding line 13 is made of a conductive material, and the material of the shielding line 13 may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co- and Ni-based alloys, Fe- and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). There are voids in the shielding line 13, and the total volume of the voids accounts for no less than 10% of the volume of the shielding line 13. After the shielding line 13 is energized, an electron barrier can be formed, which can reduce the coupling capacitance between adjacent bit lines 12, improve signal integrity and anti-interference ability. In addition, the shielding line 13 with voids can also relieve the stress effect of the wafer.

[0077] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all of them should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a first surface and a second surface disposed opposite to each other; Active pillars, the active pillars are arranged in an array on the first surface along a first direction and a second direction, respectively, and the second direction is perpendicular to the first direction; A bit line, the bit line is located on the second surface, extends along a first direction, and is connected to the active pillars arranged in the first direction; a shielding line, the shielding line being located on the second surface, extending along a first direction, and being located between adjacent bit lines; The shielding wire has gaps therein, and the total volume of the gaps accounts for no less than 10% of the volume of the shielding wire.

2. The semiconductor structure according to claim 1, characterized in that: The shielding wire is a porous conductive material, and the pores are evenly distributed in the shielding wire.

3. The semiconductor structure according to claim 1, characterized in that: The shielding wire is a hollow conductive material and has holes therein.

4. The semiconductor structure according to claim 1, characterized in that: There are a plurality of shielding lines, which are arranged in parallel between adjacent bit lines.

5. The semiconductor structure according to any one of claims 1 to 4, further comprising: A word line is located on the first surface, extends along a second direction, and connects the active pillars arranged in the second direction.

6. A method for preparing a semiconductor structure, characterized in that: Providing a substrate having a first surface and a second surface disposed opposite to each other; Active pillars are formed on the first surface, and the active pillars are arranged in an array along a first direction and a second direction, respectively, and the second direction is perpendicular to the first direction; forming a bit line on the second surface, wherein the bit line extends along a first direction and connects the active pillars arranged in the first direction; forming a shielding line on the second surface, wherein the shielding line extends along a first direction and is located between adjacent bit lines; The shielding wire has a gap therein, and the volume of the gap accounts for no less than 10% of the volume of the shielding wire.

7. The preparation method according to claim 6, characterized in that: An active pillar is formed on the first surface, comprising: Etching on the first surface to form first grooves extending along the first direction and arranged along the second direction, and filling the first grooves with a first isolation layer; Etching on the first surface to form a second groove extending along a second direction and arranged along the first direction, and filling the second groove with a second isolation layer; The depth of the first groove is greater than the depth of the second groove.

8. The preparation method according to claim 7, characterized in that: forming a bit line on the second surface, comprising: The substrate is turned over, the second surface is ground and thinned to expose the first isolation layer, a metal material layer is deposited on the second surface, the metal material layer reacts with the substrate to form the bit line, and the unreacted metal material layer is removed.

9. The preparation method according to claim 8, characterized in that: Forming a shielding line on the second surface includes: Part of the first isolation layer is removed by etching to form a third groove between adjacent bit lines, a shielding line material layer is formed in the third groove, and the shielding line material layer on the second surface is removed by grinding to form the shielding line.

10. The preparation method according to any one of claims 7 to 9, further comprising: A word line is formed in the bottom of the second groove, and the word line extends along the second direction and connects the active pillars arranged in the second direction.

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