Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include: a gate structure including insulating layers and conductive layers alternately stacked over a source structure; a channel structure extending through the gate structure; an insulating support extending through the gate structure; a first seed layer surrounding a sidewall of the insulating support; and a first barrier layer between the gate structure and the first seed layer.

Description

Technical Field

[0001] The present disclosure generally relates to electronic devices and methods of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement in the integration degree of two-dimensional semiconductor devices in which memory cells are formed as a single layer on a substrate has reached a stagnation period where little or no significant further improvement is possible, three-dimensional semiconductor devices in which memory cells are stacked in multiple layers above the substrate have been proposed. In addition, efforts are currently mainly focused on developing more stable three-dimensional structures with improved operational reliability and functionality and improved manufacturing methods. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a semiconductor device may include: a gate structure including an insulating layer and a conductive layer alternately stacked above a source structure; a channel structure extending through the gate structure; an insulating support extending through the gate structure; a first seed layer surrounding a sidewall of the insulating support; and a first barrier layer located between the gate structure and the first seed layer.

[0004] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include the steps of: forming a stack by alternately stacking a first material layer and a second material layer; forming an opening in the stack; forming a seed layer in the opening; and forming an insulating support by oxidizing the seed layer.

[0005] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include the steps of: forming a stack by alternately stacking a first material layer and a second material layer; forming an opening in the stack; forming a barrier layer in the opening; forming a seed layer in the barrier layer; and forming an insulating support in the seed layer.

[0006] These and other features and advantages of the present invention will become apparent from the following drawings and the detailed description of the specific embodiments of the present disclosure. Brief Description of the Drawings

[0007] Figures 1A to 1D is a diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A and Figure 2B is a diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B is a diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 4A to 6B is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 7A to 8B is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, Detailed Embodiments

[0012] Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0013] According to the present technology, a semiconductor device having a stable structure and improved reliability can be provided.

[0014] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0015] Figures 1A to 1D is a diagram showing a semiconductor device according to an embodiment of the present disclosure. Figure 1A is a plan view, Figure 1B is along Figure 1A a cross-sectional view taken along A-A' of Figure 1C is along Figure 1A a cross-sectional view taken along B-B' of Figure 1D is along Figure 1A a cross-sectional view taken along C-C' of

[0016] Referring to Figures 1A to 1D , the semiconductor device may include at least one of a source structure 110, a first contact plug 120, a stack 130, a gate structure 130G, a first barrier layer 140A, a second barrier layer 140B, a third barrier layer 140C, a first seed layer 150A, a second seed layer 150B, a third seed layer 150C, an insulating support 160, a second contact plug 170, a contact via 180, a slit structure 190, and a spacer SP.

[0017] Stack 130 may be located above or on the source structure 110 (e.g., on the source structure 110). Stack 130 may include an insulating layer 130A and a sacrificial layer 130B that are alternately stacked in a vertical or substantially vertical direction III (also referred to as the third direction) on the top surface of the source structure 110. In the manufacturing process of the semiconductor device, the sacrificial layer 130B may be replaced with a conductive layer 130C, and thus the gate structure 130G is formed from stack 130. Stack 130 may be replaced with the gate structure 130G. That is, the gate structure 130G may be located above or on the source structure 110 (e.g., on the source structure 110), and may include an insulating layer 130A and a conductive layer 130C that are alternately stacked. In some embodiments, the conductive layer 130C may be used as a word line, a bit line, or a select line. However, in other embodiments, stack 130 may be retained without being replaced with the gate structure 130G.

[0018] The insulating layer 130A may include an insulating material such as an oxide. The sacrificial layer 130B may include a sacrificial material such as a nitride or polysilicon. The conductive layer 130C may include a conductive material such as tungsten, molybdenum, or polysilicon. The source structure 110 may include a semiconductor material, such as polysilicon.

[0019] As Figure 1D shown, the channel structure CH may pass through the gate structure 130G and partially extend into the source structure 110. Thus, the channel structure CH may be connected to the source structure 110. Each channel structure CH may include at least one of a channel layer CHA, a memory layer CHB surrounding the channel layer CHA, and an insulating core CHC in the channel layer CHA. In some embodiments, for example, in the Figure 1D embodiments of

[0020] The insulating support 160 may extend through the gate structure 130G. Alternatively, the insulating support 160 may extend through the stack 130. Alternatively, the insulating support 160 may extend between the gate structure 130G and the stack 130. For example, in some embodiments, although not shown in the figures, the insulating support 160 may extend into the source structure 110 through the stack 130 or the gate structure 130G, and may extend into the source structure 110 by extending between the stack 130 and the gate structure 130G. The insulating support 160 may have a hole shape in a plane defined by a first direction I and a second direction II intersecting the first direction I, and may have a wire shape extending in the first direction I and / or the second direction II. For example, the insulating support 160 may have a cross-sectional shape of a quadrilateral, a circle, or an ellipse. Additionally, as an example, the insulating support 160 may have a U shape extending in the first direction I and the second direction II. The insulating support 160 may minimize or prevent the stack 130 or the gate structure 130G from bending during the manufacturing process of the semiconductor device. The insulating support 160 may include an insulating material such as an oxide.

[0021] The first seed layer 150A may surround the sidewall of the insulating support 160. For example, the first seed layer 150A may extend between the stack 130, the gate structure 130G, or between the stack 130 and the gate structure 130G, and may surround the sidewall of the insulating support 160. The first seed layer 150A may include a seed material for forming the insulating support 160. The seed material of the first seed layer 150A may include at least one of polysilicon and silicon carbonitride (SiCN). The insulating support 160 may be an oxide of the first seed layer 150A.

[0022] The first barrier layer 140A may surround the sidewall of the first seed layer 150A. For example, the first barrier layer 140A may be located between the stack 130 and the first seed layer 150A, or may be located between the gate structure 130G and the first seed layer 150A. The first barrier layer 140A may prevent the first seed layer 150A from connecting to the stack 130 and the gate structure 130G. For example, when the first seed layer 150A includes a conductive material, the first barrier layer 140A may prevent the conductive material of the first seed layer 150A from connecting to the conductive material of the stack 130 or the gate structure 130G. Additionally, the first barrier layer 140A may increase the support force of the insulating support 160 together with the first seed layer 150A. The first barrier layer 140A may include an insulating material such as an oxide.

[0023] The first contact plug 120 may be located in the source structure 110. The first contact plug 120 may have a tapered cross-section, and the area of the cross-section may gradually decrease in the direction from the upper part to the lower part. The upper part may have a maximum value and may be located at the interface between the source structure 110 and the stack 130 or the gate structure 130G. The lower part may have a minimum value and may be located at the bottom height of the source structure 110. However, embodiments of the present disclosure are not limited thereto, and the first contact plug 120 may have a cross-section with the same thickness for the upper and lower parts. The first contact plug 120 may be electrically connected to a peripheral circuit (not shown) located below the source structure 110. The spacer SP may surround the sidewall of the first contact plug 120. In some embodiments, the spacer SP may prevent the first contact plug 120 and the source structure 110 from being electrically connected. The spacer SP may include an insulating material such as an oxide, and the first contact plug 120 may include a conductive material such as tungsten.

[0024] The second contact plug 170 may extend through the stack 130. For example, the second contact plug 170 may extend through the stack 130 and may be connected to the first contact plug 120. The second contact plug 170 may be electrically connected to the first contact plug 120. Thus, the second contact plug 170, the first contact plug 120, and the peripheral circuit may be electrically connected. The second contact plug 170 may include a conductive material such as tungsten.

[0025] The second seed layer 150B may surround the sidewall of the second contact plug 170. The second seed layer 150B may prevent or minimize the connection between the second contact plug 170 and the stack 130 and / or the gate structure 130G due to the inclination of the formed second contact plug 170 during the process of forming the second contact plug 170. The second seed layer 150B may include the same or substantially the same material as the first seed layer 150A. For example, the second seed layer 150B may include at least one of polysilicon and silicon carbonitride (SiCN).

[0026] The second barrier layer 140B may surround the sidewall of the second seed layer 150B. For example, the second barrier layer 140B may be located between the stack 130 and the second seed layer 150B. The second barrier layer 140B may prevent the second seed layer 150B from being connected to the stack 130. The second barrier layer 140B may include an insulating material such as an oxide.

[0027] The contact via 180 may extend inside the gate structure 130G and may be connected to at least one conductive layer 130C. A plurality of contact vias 180 may be respectively connected to different conductive layers 130C of the gate structure 130G. In this case, the heights of the contact vias 180 may be different from each other, and the contact vias 180 may be respectively connected to different conductive layers 130C at different heights of the gate structure 130G. The contact via 180 may include a conductive material such as tungsten.

[0028] The third seed layer 150C can surround the sidewall of the contact via 180. The third seed layer 150C can prevent or minimize the tilting and formation of the contact via 180 during the process of forming the contact via 180. The third seed layer 150C can include the same or substantially the same material as the first seed layer 150A. For example, the third seed layer 150C can include at least one of polysilicon and silicon carbonitride (SiCN).

[0029] The third barrier layer 140C can surround the sidewall of the third seed layer 150C. For example, the third barrier layer 140C can be located between the stack 130 and the third seed layer 150C. The third barrier layer 140C can prevent the third seed layer 150C from connecting to the gate structure 130G. The third barrier layer 140C can include an insulating material such as an oxide.

[0030] For example, in some embodiments, only the third barrier layer 140C may be present on the sidewall of the contact via 180. Alternatively, the third barrier layer 140C and / or the third seed layer 150C may not be located above or on (e.g., on the sidewall of) the contact via 180. For example, when the respective conductive layers 130C of the gate structure 130G have an exposed stepped structure, the third barrier layer 140C and / or the third seed layer 150C surrounding the sidewall of the contact via 180 may not be provided.

[0031] The slit structure 190 can extend through the gate structure 130G. For example, the slit structure 190 can extend along the gate structure 130G in the second direction II. The channel structure CH can be located between adjacent slit structures 190. The insulating support 160, the second contact plug 170, and the contact via 180 can be located between adjacent slit structures 190. The slit structure 190 can include an insulating material such as an oxide. For example, in some embodiments, the slit structure 190 can include a semiconductor material or the like.

[0032] According to the structure described above, the first seed layer 150A and the first barrier layer 140A can surround the sidewall of the insulating support 160. The first seed layer 150A and the first barrier layer 140A can increase the support force of the insulating support 160.

[0033] The second seed layer 150B and the second barrier layer 140B can surround the sidewall of the second contact plug 170. The third seed layer 150C and the third barrier layer 140C can surround the sidewall of the contact via 180. In this case, the seed layers 150B and 150C can prevent or minimize the tilting of the second contact plug 170 and the contact via 180, and the barrier layers 140B and 140C can prevent or minimize the connection of the seed layers 150B and 150C to the stack 130 and / or the gate structure 130G.

[0034] Figure 2A and Figure 2B is a diagram showing a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a plan view, Figure 2B is a cross-sectional view taken along Figure 2A D-D'. Any content repeated above may be omitted hereinafter.

[0035] Referring to Figure 2A and Figure 2B a semiconductor device may include at least one of a source structure 210, a first contact plug 220, a stack 230, a gate structure 230G, a first seed layer 250A, a second seed layer 250B, a third seed layer 250C, an insulating support 260A, a residual support 260B, a second contact plug 270, a contact via 280, a slit structure 290, and a spacer SP.

[0036] The stack 230 may be located above or on the source structure 210 (e.g., on the source structure 210). The stack 230 may include insulating layers 230A and sacrificial layers 230B stacked alternately. The stack 230 may be replaced with the gate structure 230G. The gate structure 230G may include insulating layers 230A and conductive layers 230C stacked alternately. In some embodiments, the conductive layer 230C may be used as a word line, a bit line, or a select line. The insulating layer 230A may include an insulating material such as an oxide. The sacrificial layer 230B may include a sacrificial material such as a nitride or polysilicon. The conductive layer 230C may include a conductive material such as tungsten, molybdenum, or polysilicon. The source structure 210 may include a semiconductor material such as polysilicon.

[0037] The insulating support 260A may extend through the gate structure 230G. Alternatively, the insulating support 260A may extend through the stack 230. Alternatively, the insulating support 260A may extend between the gate structure 230G and the stack 230. The insulating support 260A may have a hole shape in a plane defined by a first direction I and a second direction II intersecting the first direction I, and may have a line shape extending in the first direction I and / or the second direction II. The insulating support 260A may minimize or prevent the stack 230 or the gate structure 230G from bending during the manufacturing process of the semiconductor device. The insulating support 260A may include an insulating material such as an oxide.

[0038] The first seed layer 250A can surround the sidewall of the insulating support 260A. For example, the first seed layer 250A can extend into the stack 230 or the gate structure 230G, or extend between the stack 230 and the gate structure 230G, and can surround the sidewall of the insulating support 260A. The first seed layer 250A can include a seed material for forming the insulating support 260A. For example, the first seed layer 250A can include at least one of polysilicon and silicon carbonitride (SiCN).

[0039] The second seed layer 250B can surround the sidewall of the second contact plug 270. The second seed layer 250B can prevent or minimize the connection between the second contact plug 270 and the stack 230 and / or the gate structure 230G due to the inclination of the formed second contact plug 270 during the process of forming the second contact plug 270. The second seed layer 250B can include the same or substantially the same material as the first seed layer 250A. For example, the second seed layer 250B can include at least one of polysilicon and silicon carbonitride (SiCN).

[0040] The residual support 260B can be located between the second seed layer 250B and the second contact plug 270. The residual support 260B can be left during the process of removing the insulating support 260A formed in the second seed layer 250B before forming the second contact plug 270. For example, in some embodiments, although not shown in this figure, the residual support 260B can be located between the third seed layer 250C and the contact via 280. Alternatively, the residual support 260B may not exist between the second seed layer 250B and the second contact plug 270. In this case, the second seed layer 250B can contact the second contact plug 270 and surround the sidewall of the second contact plug 270.

[0041] Referring again to Figure 1A and Figure 1B , the first barrier layer 140A may not exist between the first seed layer 250A and the stack 230 or between the first seed layer 250A and the gate structure 230G. Additionally, the second barrier layer 140B may not exist between the second seed layer 250B and the stack 230. Additionally, the third barrier layer 140C may not exist between the third seed layer 250C and the gate structure 230G. In this case, the seed layers 250A, 250B, and 250C can contact the stack 230 or the gate structure 230G and extend along the stack 230 or the gate structure 230G. In some embodiments, the seed layers 250A, 250B, and 250C can include polysilicon and the like.

[0042] According to the above structure, the residual support 260B can be located between the seed layers 250B and 250C and the second contact plug 270 or the contact via 280. Additionally, the barrier layer may not exist between the seed layers 250A, 250B, and 250C and the stack 230 or the gate structure 230G.

[0043] Figure 3A and Figure 3B is a diagram showing a semiconductor device according to an embodiment of the present disclosure. Figure 3A is a plan view, Figure 3B is a cross-sectional view taken along Figure 3A E-E' thereof. Hereinafter, the content repeated above is omitted.

[0044] Referring to Figure 3A and Figure 3B the semiconductor device may include at least one of a source structure 310, a first contact plug 320, a stack 330, a gate structure 330G, a first barrier layer 340A, a second barrier layer 340B, a third barrier layer 340C, a first seed layer 350A, a second seed layer 350B, a third seed layer 350C, an insulating support 360, a second contact plug 370, a contact via 380, a slit structure 390, and a spacer SP.

[0045] The stack 330 and the gate structure 330G may be located above or on the source structure 310 (e.g., on the source structure 310). The stack 330 may include insulating layers 330A and sacrificial layers 330B stacked alternately. The gate structure 330G may include insulating layers 330A and conductive layers 330C stacked alternately.

[0046] The insulating support 360 may extend through the gate structure 330G. Alternatively, the insulating support 360A may extend through the stack 330. Alternatively, the insulating support 360A may extend between the gate structure 330G and the stack 330. The insulating support 360 may have a hole shape in a plane defined by a first direction I and a second direction II intersecting the first direction I, and may have a line shape extending in the first direction I and / or the second direction II.

[0047] In addition, the insulating support 360 may have an arcuate shape. For example, the insulating support 360 may have an arcuate shape including a convex portion 360P. The width of the insulating support 360 may narrow from the convex portion 360P toward the lower portion. In addition, the width of the insulating support 360 may narrow from the convex portion 360P toward the upper portion. The insulating support 360 may include a gap V. The gap V may be formed in the process of forming the insulating support 360. For example, the gap V may be formed at a position corresponding to the convex portion 360P of the insulating support 360. The insulating support 260A may include an insulating material such as an oxide. For example, in some embodiments, although not shown in the figure, the channel structure CH and / or the contact through hole 380 may have an arcuate shape.

[0048] The first barrier layer 340A and the first seed layer 350A may surround the sidewalls of the insulating supporter 360. For example, the first barrier layer 340A and the first seed layer 350A may surround the sidewalls of the insulating supporter 360 along an arcuate shape. Therefore, the first barrier layer 340A and the first seed layer 350A may have an arcuate shape. The first seed layer 350A may include at least one of polysilicon and silicon carbonitride (SiCN). The first barrier layer 340A may include an insulating material such as an oxide.

[0049] The second contact plug 370 may extend through the stack 330 and may be connected to the first contact plug 320. The second contact plug 370 may have an arcuate shape. For example, the second contact plug 370 may have an arcuate shape at a position corresponding to a height of the convex portion 360P of the insulating supporter 360. The second contact plug 370 may not include a void V. The second contact plug 370 may include a conductive material such as tungsten.

[0050] The second barrier layer 340B and the second seed layer 350B may surround the sidewalls of the second contact plug 370. Therefore, the second barrier layer 340B and the second seed layer 350B may also have an arcuate shape. The second seed layer 350B may include the same or substantially the same material as the first seed layer 350A. The second barrier layer 340B may include an insulating material such as an oxide.

[0051] According to the above structure, the insulating supporter 360, the second contact plug 370, the contact through hole 380 and the channel structure CH may have an arcuate shape. In some embodiments, the insulating supporter 360 may include a void V therein. In some embodiments, the void V may be formed at a position corresponding to the protrusion 360P of the insulating supporter 360.

[0052] Figures 4A to 6B 2 is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 4A , Figure 5A and Figure 6A It is a floor plan.Figure 4B , Figure 5B and Figure 6B are cross-sectional views taken along corresponding Figure 4A , Figure 5A and Figure 6A of F-F'. Hereinafter, any content repeated above may be omitted.

[0053] Referring to Figure 4A and Figure 4B , a preliminary source structure 410S can be formed. For example, the preliminary source structure 410S can be formed by sequentially stacking a first source layer 410A, a first protective layer 410B, a second source layer 410C, a second protective layer 410D, and a third source layer 410E. In some embodiments, the first source layer 410A, the second source layer 410C, or the third source layer 410E may include polysilicon or the like, and the first protective layer 410B or the second protective layer 410D may include an insulating material such as an oxide.

[0054] Subsequently, a first contact plug 420 can be formed in the preliminary source structure 410S. First, a preliminary spacer can be formed by forming a trench in the preliminary source structure 410S. Subsequently, a first contact plug 420 extending through the preliminary spacer can be formed. The first contact plug 420 can be formed to have a tapered shape. In this process, the preliminary spacer can serve as a spacer SP around the sidewall of the first contact plug 420. In some embodiments, the first contact plug 420 may include a conductive material such as tungsten, and the spacer SP may include an insulating material such as an oxide.

[0055] Subsequently, a stack 430 can be formed on the preliminary source structure 410S. For example, the stack 430 can be formed by alternately stacking a first material layer 430A and a second material layer 430B. In some embodiments, the first material layer 430A may include an insulating material such as an oxide, and the second material layer 430B may include a sacrificial material such as a nitride. Alternatively, the second material layer 430B may include a conductive material such as polysilicon.

[0056] Subsequently, openings OP1, OP2, OP3, OP4, and OP5 can be formed in the stack 430. For example, openings OP1, OP3, and OP5 exposing the preliminary source structure 410S can be formed through the stack 430. Alternatively, a second opening OP2 exposing the first contact plug 420 can be formed. Alternatively, a fourth opening OP4 exposing at least one second material layer 430B can be formed through the stack 430.

[0057] The openings OP1, OP2, OP3, OP4, and OP5 can have various shapes and various sizes. The openings OP1, OP2, OP3, OP4, and OP5 can have a hole shape or can have a line shape. Alternatively, the openings OP1, OP2, OP3, OP4, and OP5 can have an arcuate shape that is convex upward. Alternatively, the openings OP1, OP2, OP3, OP4, and OP5 can have a conical shape. For example, a first opening OP1 having a line shape extending in the first direction I and / or the second direction II can be formed. In some embodiments, the first opening OP1 can have a U shape. Alternatively, hole shapes of a second opening OP2, a third opening OP3, a fourth opening OP4, and a fifth opening OP5 can be formed. In some embodiments, the shapes and sizes of the openings OP2, OP3, OP4, and OP5 can be substantially equal to each other or different from each other.

[0058] Referring Figure 5A and Figure 5B , a channel structure CH can be formed. For example, a channel structure CH including a channel layer can be formed in the fifth opening OP5. The channel structure CH can further include at least one of a memory layer surrounding the channel layer and an insulating core in the channel layer.

[0059] A seed layer 450 can be formed in the openings OP1, OP2, OP3, and OP4. For example, the seed layer 450 can be conformally formed in the openings OP1, OP2, OP3, and OP4. In some embodiments, the seed layer 450 can be used to form an insulating support 460 in a subsequent process. Accordingly, the seed layer 450 can include a material that is selective with respect to the insulating support 460. For example, the seed layer 450 can include at least one of polysilicon and silicon carbonitride (SiCN).

[0060] Subsequently, the insulating support 460 can be formed by oxidizing the seed layer 450. For example, the insulating support 460 can be formed by oxidizing the seed layer 450 to fill the openings OP1, OP2, OP3, and OP4. The insulating support 460 can be used as a sacrificial structure to be removed in a subsequent process or can be used as a support to prevent or minimize bending of the stack 430 in a subsequent process. In some embodiments, a portion of the seed layer 450 can be retained. The thickness of the remaining seed layer 450 can be substantially equal to or different from the thickness of the insulating support 460. For example, the thickness of the remaining seed layer 450 can be relatively smaller than the thickness of the insulating support 460.

[0061] In the process of forming the insulating support 460, voids V may be formed in the insulating support 460. For example, in the process of oxidizing the seed layer 450, the convex portions of the openings OP1, OP2, OP3, and OP4 may be less oxidized, and thus voids V may be generated. However, according to an embodiment of the present disclosure, the seed layer 450 may be oxidized to form the insulating support 460, so the size of the voids V may be relatively smaller than the case where the insulating support 460 is formed by a deposition method in the openings OP1, OP2, OP3, and OP4 without forming the seed layer 450. Therefore, according to an embodiment of the present disclosure, cracks in the insulating support 460 can be prevented or minimized, and bridging problems and the like that occur due to the exposure of other structures through the voids V during subsequent processes can be prevented or minimized.

[0062] For example, in some embodiments, after forming the insulating support 460, additional supports may be formed in the openings OP1, OP2, OP3, and OP4. For example, although not shown in this figure, even when the insulating support 460 is formed by completely oxidizing the seed layer 450, when there are empty spaces in the openings OP1, OP2, OP3, and OP4, additional supports can be deposited and formed. In some embodiments, the additional supports may include an insulating material such as an oxide. Therefore, there may be no interface between the insulating support 460 and the additional supports, and the insulating support 460 and the additional supports can be used as one support.

[0063] Referring to Figure 6A and Figure 6B , a gate structure 430G including a first material layer 430A and a third material layer 430C alternately stacked may be formed. First, a slit SL extending in the first direction I through the stack 430 may be formed. The slits SL may be formed to be spaced apart from each other in a second direction II intersecting the first direction I. Subsequently, the second material layer 430B may be selectively removed through the slit SL and replaced with the third material layer 430C. Therefore, the stack 430 may be replaced with the gate structure 430G. In some embodiments, the insulating support 460 may prevent or minimize the bending of the stack 430 when removing the second material layer 430B. For example, the hole shape of the insulating support 460 may prevent or minimize the bending of the stack 430. The second material layer 430B may not be removed and may remain in the region where the insulating support 460 surrounds the stack 430 in a U shape. Therefore, a part of the insulating support 460 may be located between the stack 430 and the gate structure 430G. Subsequently, a slit structure 490 may be formed in the slit SL. In some embodiments, the slit structure 490 may include an insulating material such as an oxide or a semiconductor material.

[0064] For example, in some embodiments, although not shown in this figure, the slit SL may extend through the stack 430 into the preliminary source structure 410S. Before forming the slit structure 490, an opening may be formed by removing the first protective layer 410B, the second source layer 410C, and the second protective layer 410D via the slit SL, and a portion of the memory layer may be removed such that the channel layer of the channel structure CH is exposed through the opening. Subsequently, a semiconductor material or the like may be formed in the opening.

[0065] Subsequently, a second contact plug 470 extending through the stack 430 may be formed. First, the second opening OP2 may be reopened by removing the insulating support 460. In some embodiments, only a portion of the insulating support 460 may be removed. Subsequently, the second contact plug 470 may be formed by forming a conductive material in the second opening OP2. In some embodiments, the conductive material may be tungsten or the like. The insulating support 460 may act as a barrier layer together with the seed layer 450, and may prevent or minimize the exposure of the stack 430 during the process of reopening the second opening OP2. Thus, the second contact plug 470 may be prevented from tilting and formed.

[0066] A contact via 480 extending through the gate structure 430G may be formed. For example, the fourth opening OP4 may be reopened by partially removing the insulating support 460. Subsequently, the contact via 480 may be formed by forming a conductive material in the fourth opening OP4. In some embodiments, the conductive material may be a conductive material such as tungsten. For example, in some embodiments, before forming the contact via 480, each of the fourth openings OP4 may be extended to expose each of the third material layers 430C of the gate structure 430G. This may be used to electrically connect the contact via 480 to the third material layer 430C respectively.

[0067] According to the above manufacturing method, the seed layer 450 may be formed in the openings OP1, OP2, OP3, and OP4. Subsequently, the insulating support 460 may be formed by oxidizing the seed layer 450. In this case, compared with the case where the insulating support 460 is formed by a deposition method, the size of the voids V inside the insulating support 460 may be relatively small.

[0068] In addition, the seed layer 450 and the insulating support 460 may be support and / or barrier layers, which may prevent or minimize the bending of the stack 430 and / or the gate structure 430G, and prevent or minimize the tilting and formation of the second contact plug 470 and / or the contact via 480.

[0069] Figures 7A to 8B It is a diagram showing a manufacturing method of a semiconductor device according to an embodiment of the present disclosure. Figure 7A and Figure 8A is a plan view, Figure 7Band Figure 8B is a cross-sectional view taken along the corresponding Figure 7A and Figure 8A of G-G'. Hereinafter, the content repeated above is omitted.

[0070] Referring to Figure 7A and Figure 7B , a preliminary source structure 710S can be formed. For example, the preliminary source structure 710S can be formed by sequentially stacking a first source layer 710A, a first protective layer 710B, a second source layer 710C, a second protective layer 710D, and a third source layer 710E.

[0071] Subsequently, a first contact plug 720 can be formed in the preliminary source structure 710S. For example, a preliminary spacer can be formed by forming a trench in the preliminary source structure 710S, and a first contact plug 720 extending through the preliminary spacer can be formed.

[0072] Subsequently, a stack 730 can be formed by alternately stacking a first material layer 730A and a second material layer 730B on the preliminary source structure 710S. In some embodiments, the first material layer 730A can include an insulating material such as an oxide, and the second material layer 730B can include a sacrificial material such as a nitride. Alternatively, the second material layer 730B can include a conductive material such as polysilicon.

[0073] Subsequently, openings OP1, OP2, OP3, OP4, and OP5 can be formed in the stack 730. The openings OP1, OP2, OP3, OP4, and OP5 can have various shapes and various sizes. The openings OP1, OP2, OP3, OP4, and OP5 can have a hole shape, or can have a line shape. Alternatively, the openings OP1, OP2, OP3, OP4, and OP5 can have an arcuate shape with a convex portion at the top. Alternatively, the openings OP1, OP2, OP3, OP4, and OP5 can have a tapered shape. For example, a first opening OP1 having a line shape extending in a first direction I and / or a second direction II can be formed. In some embodiments, the first opening OP1 can have a U shape. Alternatively, hole shapes of a second opening OP2, a third opening OP3, a fourth opening OP4, and a fifth opening OP5 can be formed. In some embodiments, the shapes and sizes of the openings OP2, OP3, OP4, and OP5 can be substantially equal to each other or different from each other.

[0074] A barrier layer 740 may be formed in the openings OP1, OP2, OP3, and OP4. The barrier layer 740 may be formed in the openings OP1, OP2, OP3, and OP4 before forming the seed layer 750. In some embodiments, the barrier layer 740 may include an insulating material such as an oxide. Subsequently, the seed layer 750 may be formed in the barrier layer 740. The seed layer 750 may include at least one of polysilicon and silicon carbonitride (SiCN).

[0075] Subsequently, an insulating support 760 may be formed in the seed layer 750. As an example, the insulating support 760 may be formed by oxidizing the seed layer 750. As another example, the insulating support 760 may be deposited and formed in the seed layer 750. However, the embodiments of the present disclosure are not limited thereto. After forming a part of the insulating support 760 by oxidizing the seed layer 750, the remaining insulating support 760 may be formed by a deposition method. In this case, an interface between the insulating support 760 as an oxide layer and the insulating support 760 as a deposited layer may not exist.

[0076] In the process of forming the insulating support 760, voids V may be formed in the insulating support 760. However, according to the embodiments of the present disclosure, the insulating support 760 may be formed by oxidizing the seed layer 750, and in this case, the size of the voids V may be relatively small. Alternatively, according to the embodiments of the present disclosure, the insulating support 760 may be formed by oxidizing the seed layer 750, and thus the size of the voids V may be relatively small. Therefore, the embodiments of the present disclosure may prevent or minimize cracks in the insulating support 760, and may prevent or minimize bridging disorders and the like that occur due to exposure of other structures through the voids V during subsequent processes.

[0077] Refer to Figure 8A and Figure 8B , the gate structure 730G may be formed by replacing the second material layer 730B with the third material layer 730C. First, a slit SL extending in the first direction I may be formed through the stack 730. Subsequently, the second material layer 730B may be selectively removed through the slit SL and replaced with the third material layer 730C. Thus, the stack 730 may be replaced with the gate structure 730G. In some embodiments, the insulating support 760 may prevent or minimize bending of the stack 730 when removing the second material layer 430B. The insulating support 760 may be a support configured by three layers together with the barrier layer 740 and the seed layer 750, and may have improved support force. Subsequently, a slit structure 790 may be formed in the slit SL. In some embodiments, the slit structure 790 may include an insulating material such as an oxide, or may include a semiconductor material or the like.

[0078] Subsequently, a second contact plug 770 extending through the stack 730 can be formed. First, the second opening OP2 can be reopened by removing the insulating support 760. In some embodiments, the insulating support 760 can be selectively removed by the selectivity of the seed layer 750 and the insulating support 760. Subsequently, the second contact plug 770 can be formed by forming a conductive material in the second opening OP2. In some embodiments, the insulating support 760 can be completely removed. In this case, the seed layer 750 can be a barrier layer and can prevent the stack 730 from being exposed through the openings OP1, OP2, OP3, and OP4. Therefore, the second contact plug 770 can be prevented from tilting and formed.

[0079] According to the above manufacturing method, the barrier layer 740 can be formed in the openings OP1, OP2, OP3, and OP4. Subsequently, the seed layer 750 can be formed in the barrier layer 740. Subsequently, the insulating support 760 can be formed by oxidizing the seed layer 750. Alternatively, after forming a part of the insulating support 760 by oxidizing the seed layer 750, the remaining insulating support 760 can be deposited and formed. In this case, the size of the void V inside the insulating support 760 can be relatively small.

[0080] In addition, the barrier layer 740, the seed layer 750, and the insulating support 760 can be one support configured by three layers and can prevent or minimize bending of the stack 730 and / or the gate structure 730G.

[0081] Although embodiments in accordance with the technical spirit of the present disclosure have been described with reference to the accompanying drawings, this is only for describing embodiments in accordance with the concepts of the present disclosure, and the present disclosure is not limited to the above embodiments. Within the scope of the technical spirit of the present disclosure described in the claims, those skilled in the art to which the present disclosure pertains can make various forms of permutations, modifications, and changes to the embodiments, and these permutations, modifications, and changes also fall within the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

[0082] Cross - reference to related applications

[0083] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0181024, filed on December 13, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a gate structure comprising an insulating layer and a conductive layer alternately stacked over the source structure; a channel structure extending through the gate structure; an insulating support extending through the gate structure; a first seed layer, the first seed layer surrounding the sidewall of the insulating support; as well as A first barrier layer is located between the gate structure and the first seed layer.

2. The semiconductor device according to claim 1, wherein The insulating support has an arcuate shape.

3. The semiconductor device according to claim 2, wherein: In the insulating supporter, a gap is included at a height corresponding to a convex portion of the arcuate shape of the insulating supporter.

4. The semiconductor device according to claim 1, wherein The insulating support is an oxide of the first seed layer.

5. The semiconductor device according to claim 1, wherein The first seed layer includes at least one of polysilicon and silicon carbon nitride SiCN.

6. The semiconductor device according to claim 1, wherein The first barrier layer includes an oxide.

7. The semiconductor device according to claim 1, further comprising: a laminate comprising insulating layers and sacrificial layers alternately laminated; The source structure is located below the stack; a first contact plug, the first contact plug being located in the source structure; a second contact plug extending through the stack and connected to the first contact plug; a second seed layer surrounding a sidewall of the second contact plug; as well as A second barrier layer surrounds a sidewall of the second seed layer.

8. The semiconductor device according to claim 7, wherein: The second seed layer includes at least one of polysilicon and silicon carbon nitride SiCN.

9. The semiconductor device according to claim 7, wherein: The second barrier layer includes an oxide.

10. The semiconductor device according to claim 1, further comprising: a contact via extending through the gate structure and connected to at least one of the conductive layers; a third seed layer, the third seed layer surrounding the sidewall of the contact through hole; as well as A third barrier layer surrounds a side wall of the third seed layer.

11. The semiconductor device according to claim 10, wherein The third seed layer includes at least one of polysilicon and silicon carbon nitride SiCN.

12. The semiconductor device according to claim 10, wherein: The third barrier layer includes oxide.

13. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a laminate by alternately laminating layers of a first material and layers of a second material; forming an opening in the stack; forming a seed layer in the opening; as well as An insulating supporter is formed by oxidizing the seed layer.

14. The method according to claim 13, wherein: When the insulating supporter is formed, a void is formed in the insulating supporter.

15. The method according to claim 13, further comprising the steps of: Before forming the seed layer, a barrier layer is formed in the opening.

16. The method according to claim 15, wherein: The barrier layer includes an oxide.

17. The method according to claim 13, wherein: The seed layer includes a material having selectivity with respect to the insulating supporter.

18. The method according to claim 17, wherein: The seed layer includes at least one of polysilicon and silicon carbonitride SiCN.

19. The method according to claim 13, further comprising the steps of: reopening the opening by removing the insulating support; as well as A conductive material is formed in the opening.

20. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a laminate by alternately laminating layers of a first material and layers of a second material; forming an opening in the stack; forming a barrier layer in the opening; forming a seed layer in the barrier layer; as well as An insulating support is formed in the seed layer.

21. The method according to claim 20, wherein: The insulating supporter is formed by oxidizing the seed layer.

22. The method according to claim 20, wherein: The insulating supporter is formed by depositing the insulating supporter in the seed layer.

23. The method according to claim 20, wherein: When the insulating supporter is formed, a void is formed in the insulating supporter.

24. The method according to claim 20, wherein: The barrier layer includes an oxide.

25. The method according to claim 20, wherein: The seed layer includes a material having selectivity with respect to the insulating supporter.

26. The method according to claim 25, wherein: The seed layer includes at least one of polysilicon and silicon carbonitride SiCN.

27. The method according to claim 26, further comprising the steps of: reopening the opening by removing the insulating support; as well as A conductive material is formed in the opening.

Images