Manufacturing method of semiconductor memory device

Abstract

Disclosed is a method of manufacturing a semiconductor memory device, the semiconductor memory device including: a bit line overlapping a peripheral circuit layer; interlayer insulating layers and conductive patterns alternately stacked in a first direction on the bit lines; a vertical channel connected to the bit line, the vertical channel penetrating the interlayer insulating layer and the conductive pattern, the vertical channel protruding further in the first direction than the laminated interlayer insulating layer and conductive pattern; a connection pattern in contact with a portion of each of the vertical channels protruding farther in the first direction than the laminated interlayer insulating layer and the conductive pattern, the connection pattern connecting the vertical channels; a source channel in contact with the connection pattern, the source channel extending in the first direction; and a source selection line surrounding the source channel.

Description

[0001] This application is a divisional application of the invention patent application with the original application number 202110398957.6 (filing date: April 14, 2021, invention title: Semiconductor Memory Device and Method of Manufacturing the Same). Technical Field

[0002] The present disclosure generally relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same. Background Art

[0003] A semiconductor memory device includes memory cells capable of storing data. A three-dimensional semiconductor memory device includes memory cells arranged three-dimensionally, such that the number of memory cells per unit area of a substrate can be increased.

[0004] To improve the integration degree of a three-dimensional semiconductor device, the number of stacked layers of memory cells can be increased. Summary of the Invention

[0005] A semiconductor memory device according to an embodiment of the present disclosure may include: bit lines overlapping with a peripheral circuit layer; an interlayer insulating layer and conductive patterns stacked alternately on the bit lines in a first direction; vertical channels connected to the bit lines, the vertical channels penetrating the interlayer insulating layer and the conductive patterns, the vertical channels protruding further in the first direction than the stacked interlayer insulating layer and conductive patterns; connection patterns contacting portions of each vertical channel protruding further in the first direction than the stacked interlayer insulating layer and conductive patterns, the connection patterns connecting the vertical channels; source channels contacting the connection patterns, the source channels extending in the first direction; and source selection lines surrounding the source channels.

[0006] A semiconductor memory device according to an embodiment of the present disclosure may include: word lines including a first region, a second region, and a third region between the first region and the second region; first vertical channels penetrating the first region of the word lines, the first vertical channels extending in the first direction; first connection patterns overlapping with the first region of the word lines to be spaced apart from the word lines in the first direction, the first connection patterns contacting sidewalls of the first vertical channels; first source channels contacting the first connection patterns, the first source channels extending in the first direction; and first source selection lines overlapping with the first region of the word lines to be spaced apart from the first connection patterns in the first direction, the first source selection lines surrounding the first source channels.

[0007] A method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure may include: forming a source select gate layer on a sacrificial substrate; forming a first source channel penetrating the source select gate layer and contacting the sacrificial substrate; forming a preliminary connection structure connected to the first source channel; forming a cell stack structure including a first vertical channel and a conductive pattern, wherein the first vertical channel contacts the preliminary connection structure and extends in a first direction, and wherein the conductive patterns surround the first vertical channel and are stacked spaced apart from each other in the first direction; forming a bit line connected to the first vertical channel; forming a first bonding structure on the bit line; forming a peripheral circuit layer including a peripheral circuit and a second bonding structure overlapping the peripheral circuit; bonding the first bonding structure and the second bonding structure to each other; removing the sacrificial substrate to expose the first source channel; and forming a source slit insulating layer penetrating the source select gate layer and the preliminary connection structure, the source select gate layer and the preliminary connection structure overlapping the peripheral circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings, sizes may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element can be the only element between the two elements, or there can also be one or more intermediate elements. Throughout the specification, like reference numerals refer to like elements.

[0009] Figure 1 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figures 3A to 3D is a plan view illustrating source select lines, word lines, drain select lines, and bit lines of a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 4A and Figure 4B are cross-sectional views of a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figures 5A to 5C is an enlarged cross-sectional view illustrating a vertical channel and a source channel of a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figures 6A to 6D is a cross-sectional view illustrating a process of forming a source channel according to an embodiment of the present disclosure.

[0015] Figures 7A to 7D is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0016] Figure 8A and Figure 8B is a cross-sectional view illustrating a process of forming a conductive pattern according to an embodiment of the present disclosure.

[0017] Figure 9 is a cross-sectional view illustrating a process of forming a drain select line according to an embodiment of the present disclosure.

[0018] Figure 10 is a cross-sectional view illustrating a process of forming a bit line according to an embodiment of the present disclosure.

[0019] Figure 11 is a cross-sectional view illustrating a process of forming a first bonding structure according to an embodiment of the present disclosure.

[0020] Figure 12 is a cross-sectional view illustrating a bonding process according to an embodiment of the present disclosure.

[0021] Figure 13A and Figure 13B is a cross-sectional view illustrating a process of forming a source select line and a connection pattern according to an embodiment of the present disclosure.

[0022] Figure 14 is a cross-sectional view illustrating a process of forming a source layer according to an embodiment of the present disclosure.

[0023] Figure 15A and Figure 15B is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0024] Figure 16 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0025] Figure 17 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. Detailed Description

[0026] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be implemented in various forms, and they should not be construed as limited to the specific embodiments set forth herein.

[0027] Hereinafter, the terms "first" and "second" are used to distinguish one component from another, and do not imply a specific number or order of the components. These terms can be used to describe various components, but these components are not limited by these terms.

[0028] Embodiments provide a semiconductor memory device and a method of manufacturing the semiconductor memory device that can improve the stability of a manufacturing process.

[0029] Figure 1 It is a circuit diagram of a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0030] The semiconductor memory device may include a plurality of memory blocks BLK. Each memory block BLK may include a plurality of memory cell strings MS1 and MS2.

[0031] The memory cell strings MS1 and MS2 may be connected to a common source line CSL via connection patterns CP1 and CP2 and source selection transistors SST. The source selection transistors SST may be connected in parallel to the common source line CSL. The source selection transistors SST may be connected to the memory cell strings MS1 and MS2 via the connection patterns CP1 and CP2. The memory cell strings MS1 and MS2 may be connected to bit lines BL via drain selection transistors DST. Each of the memory cell strings MS1 and MS2 may include a plurality of memory cells MC connected in series.

[0032] The gates of the source selection transistors SST may be connected to source selection lines SSL1 and SSL2. A plurality of source selection transistors SST commonly connected to any one of the source selection lines SSL1 and SSL2 may be commonly connected to any one of the connection patterns CP1 and CP2.

[0033] Each of the connection patterns CP1 and CP2 may electrically connect a plurality of memory cell strings. The connection between each of the connection patterns CP1 and CP2 and the common source line CSL may be controlled by signals applied to the source selection lines SSL1 and SSL2.

[0034] The gates of the drain selection transistors DST may be connected to drain selection lines DSL1 and DSL2. The memory cell strings MS1 or MS2 may be respectively connected to drain selection transistors DST commonly connected to each of the drain selection lines DSL1 and DSL2.

[0035] The gates of the plurality of memory cells MC may be connected to a plurality of word lines WL. The word lines WL may be provided at different heights, and the gates of the memory cells MC provided at the same height may be connected to the same word line WL.

[0036] The memory cell strings MS1 and MS2 selected by each word line WL may be divided into memory cell string groups that can be individually selected by the drain selection lines DSL1 and DSL2.

[0037] To minimize read interference, the number of memory cell strings selected by each of the source select lines SSL1 and SSL2 can be less than the number of memory cell strings selected by each word line WL. In an embodiment, the memory cell strings that can be individually selected by the source select lines SSL1 and SSL2 can be the same as the memory cell strings that can be individually selected by the drain select lines DSL1 and DSL2.

[0038] Hereinafter, the present disclosure will be mainly described based on an embodiment in which the memory block BLK includes a first source select line SSL1 and a second source select line SSL2 isolated from each other and includes a first drain select line DSL1 and a second drain select line DSL2 isolated from each other. However, the present disclosure is not limited thereto, and the memory block BLK may include three or more source select lines isolated from each other and three or more drain select lines isolated from each other.

[0039] The memory cell strings MS1 and MS2 can include a first memory cell string group and a second memory cell string group. The first memory cell string group includes a first memory cell string, and the second memory cell string group includes a second memory cell string MS2. The first memory cell string MS1 can be connected in parallel to the first connection pattern CP1.

[0040] The second memory cell string MS2 can be connected in parallel to the second connection pattern.

[0041] The first memory cell string MS1 can be connected to the common source line CSL under the control of the source select transistor SST connected to the first source select line SSL1, and can be respectively connected to the bit line BL under the control of the drain select transistor DST connected to the first drain select line DSL1. The second memory cell string MS2 can be connected to the common source line CSL under the control of the source select transistor SST connected to the second source select line SSL2, and can be respectively connected to the bit line BL under the control of the drain select transistor DST connected to the second drain select line DSL2.

[0042] The drain select transistor DST can be respectively connected to the first memory cell string MS1 and the second memory cell string MS2. Each of the first connection pattern CP1 and the second connection pattern CP2 can be connected to two or more source select transistors SST. The number of source select transistors SST connected to the first connection pattern CP1 can be less than the number of the first memory cell strings MS1 connected to the first connection pattern CP1. Similarly, the number of source select transistors SST connected to the second connection pattern CP2 can be less than the number of the second memory cell strings MS2 connected to the second connection pattern CP2. A pair of the first memory cell string MS1 and the second memory cell string MS2 can be connected to each bit line BL.

[0043] Figure 2 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure. In the following drawings, a first direction D1, a second direction D2, and a third direction D3 may respectively correspond to directions facing the X-axis, Y-axis, and Z-axis orthogonal to each other in the XYZ Cartesian coordinate system. As used herein, an intersecting direction refers to a different direction. In some embodiments, the intersecting direction is an orthogonal direction.

[0044] The semiconductor memory device may include gate stack structures GST[A] and GST[B] isolated from each other. The gate stack structures GST[A] and GST[B] may be isolated from each other by a first slit SI1 and a second slit SI2 connected to each other. Figure 2 Illustrated are a first gate stack structure GST[A] and a second gate stack structure GST[B] of the semiconductor memory device. Each of the first gate stack structure GST[A] and the second gate stack structure GST[B] may constitute a memory block.

[0045] The first gate stack structure GST[A] may include a first drain select line DSL1[A], a second drain select line DSL2[A], a plurality of word lines WL[A], a plurality of first vertical channels VC1[A], a plurality of second vertical channels VC2[A], a first connection pattern CP1[A], a second connection pattern CP2[A], a first source select line SSL1[A], a second source select line SSL2[A], a first source channel SC1[A], and a second source channel SC2[A].

[0046] The word lines WL[A] may be stacked at intervals in the first direction D1. Each word line WL[A] may include a first region R1, a second region R2, and a third region R3 between the first region R1 and the second region R2.

[0047] Each of the first region R1 and the second region R2 may extend in the second direction D2 and the third direction D3. The width of the third region R3 in the third direction D3 may be defined as narrower than the width of each of the first region R1 and the second region R2 in the third direction D3. The third region R3 may extend in the second direction D2.

[0048] The first vertical channels VC1[A] may extend in the first direction D1 to penetrate the first region R1 of each word line WL[A]. The second vertical channels VC2[A] may extend in the first direction D1 to penetrate the second region R2 of each word line WL[A]. In other words, each word line WL[A] may extend to surround the first vertical channels VC1[A] and the second vertical channels VC2[A].

[0049] The first connection pattern CP1[A] may be spaced apart from the word line WL[A] in the first direction D1 and overlap with the first region R1 of each word line WL[A]. The first connection pattern CP1[A] may connect the first vertical channel VC1[A].

[0050] The second connection pattern CP2[A] may be spaced apart from the word line WL[A] in the first direction D1 and overlap with the second region R2 of each word line WL[A]. The second connection pattern CP2[A] may connect the second vertical channel VC2[A].

[0051] The first source selection line SSL1[A] may be spaced apart from the first connection pattern CP1[A] in the first direction D1 and overlap with the first region R1 of each word line WL[A]. The first source channel SC1[A] may contact the first connection pattern CP1[A] and extend in the first direction D1 to penetrate the first source selection line SSL1[A].

[0052] The second source selection line SSL2[A] may be spaced apart from the second connection pattern CP2[A] in the first direction D1 and overlap with the second region R2 of each word line WL[A]. The second source channel SC2[A] may contact the second connection pattern CP2[A] and extend in the first direction D1 to penetrate the second source selection line SSL2[A].

[0053] The first connection pattern CP1[A] may be isolated from the second connection pattern CP2[A] by a source slit SS. The source slit SS may be disposed between the first connection pattern CP1[A] and the second connection pattern CP2[A]. The source slit SS may extend between the first source selection line SSL1[A] and the second source selection line SSL2[A]. The first source selection line SSL1[A] may be isolated from the second source selection line SSL2[A] by the source slit SS. The source slit SS may overlap with the third region R3 of each word line WL[A].

[0054] The first drain selection line DSL1[A] may overlap with the first source selection line SSL1[A], and the word line WL[A] is between the first drain selection line DSL1[A] and the first source selection line SSL1[A]. The first drain selection line DSL1[A] may extend to surround the first vertical channel VC1[A].

[0055] The second drain selection line DSL2[A] may overlap with the second source selection line SSL2[A], and the word line WL[A] is between the second drain selection line DSL2[A] and the second source selection line SSL2[A]. The second drain selection line DSL2[A] may extend to surround the second vertical channel VC2[A].

[0056] The first drain selection line DSL1[A] can be isolated from the second drain selection line DSL2[A] through a drain slit SD. The drain slit SD can be disposed between the first drain selection line DSL1[A] and the second drain selection line DSL2[A]. The drain slit SD can overlap with the third region R3 of each word line WL[A] and is disposed between the first vertical channel VC1[A] and the second vertical channel VC2[A].

[0057] Similar to the first gate stack structure GST[A], the second gate stack structure GST[B] can include a first drain selection line DSL1[B], a second drain selection line DSL2[B], a plurality of word lines WL[B], a plurality of first vertical channels VC1[B], a plurality of second vertical channels VC2[B], a first connection pattern CP1[B], a second connection pattern CP2[B], a first source selection line SSL1[B], a second source selection line SSL2[B], a first source channel SC1[B], and a second source channel SC2[B].

[0058] The word line WL[A] of the first gate stack structure GST[A] can be isolated from the word line WL[B] of the second gate stack structure GST[B] through a first slit SI1. The first drain selection line DSL1[A] and the second drain selection line DSL2[A] of the first gate stack structure GST[A] can be isolated from the first drain selection line DSL1[B] and the second drain selection line DSL2[B] of the second gate stack structure GST[B] through the first slit SI1. The first source selection line SSL1[A] and the second source selection line SSL2[A] of the first gate stack structure GST[A] can be isolated from the first source selection line SSL1[B] and the second source selection line SSL2[B] of the second gate stack structure GST[B] through a second slit SI2.

[0059] According to the above structure, the respective widths WW of the word lines WL[A] and WL[B] can be formed wider than the respective widths WD of the drain selection lines DSL1[A], DSL2[A], DSL1[B], and DSL2[B], the respective widths WS of the source selection lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B], and the respective widths WC of the connection patterns CP1[A], CP2[A], CP1[B], and CP2[B].

[0060] The first source channels SC1[A] and SC2[A] of the first gate stack structure GST[A] and the first source channels SC1[B] and SC2[B] of the second gate stack structure GST[B] can be connected to a common source line CSL.

[0061] Figures 3A to 3D It is a plan view showing a source selection line, a word line, a drain selection line, and a bit line of a semiconductor memory device according to an embodiment of the present disclosure.

[0062] Figure 3A It illustrates Figure 2 the first source selection line SSL1[A] and the second source selection line SSL2[A] of the first gate stack structure GST[A] shown in Figure 2 and a plan view of an embodiment of the first source selection line SSL1[B] of the second gate stack structure GST[B] shown in

[0063] Referring to Figure 3A , the source slit SS can extend in the second direction D2. The second slit SI2 can extend in the second direction D2. The second slit SI2 and the source slit SS can have various shapes, such as a wavy shape or a straight shape.

[0064] The source selection lines SSL1[A], SSL2[A], and SSL1[B] can respectively surround the source channels SC1[A], SC2[A], and SC1[B]. The sidewalls of each of the source channels SC1[A], SC2[A], and SC1[B] can be surrounded by the gate insulating layer GI. In other words, each of the source selection lines SSL1[A], SSL2[A], and SSL1[B] can surround the source channels SC1[A], SC2[A], or SC1[B], and the gate insulating layer GI is interposed between the source selection line and the source channel.

[0065] Figure 3B It illustrates Figure 2 the word line WL[A] of the first gate stack structure GST[A] shown in Figure 2 and a plan view of an embodiment of the word line WL[B] of the second gate stack structure GST[B] shown in

[0066] Referring to Figure 3B , the first slit SI1 can extend in the second direction D2. The first slit SI1 can have various shapes, such as a wavy shape or a straight shape.

[0067] The word lines WL[A] and WL[B] can surround the vertical channels VC1[A], VC2[A], and VC1[B]. The sidewalls of each of the vertical channels VC1[A], VC2[A], and VC1[B] can be surrounded by the memory layer ML. In other words, each of the word lines WL[A] and WL[B] can surround the vertical channels VC1[A], VC2[A], or VC1[B], and the memory layer ML is interposed between the word line and the vertical channel.

[0068] The widths WB of the source channels SC1[A], SC2[A], and SC1[B] can be formed wider than the widths WA of the vertical channels VC1[A], VC2[A], and VC1[B], respectively.

[0069] The source channels SC1[A], SC2[A], and SC1[B] can be connected to the vertical channels VC1[A], VC2[A], and VC1[B] via connection patterns CP1[A], CP2[A], CP1[B] as Figure 2 shown. Accordingly, in the present disclosure, the degree of freedom in the arrangement of the source channels SC1[A], SC2[A], and SC1[B] can be improved. Specifically, even if the source channels SC1[A], SC2[A], and SC1[B] do not overlap with the vertical channels VC1[A], VC2[A], and VC1[B], the source channels SC1[A], SC2[A], and SC1[B] can be connected to the vertical channels VC1[A], VC2[A], and VC1[B]. In an embodiment, the central regions of some of the vertical channels among the vertical channels VC1[A], VC2[A], and VC1[B] may be offset from the central regions of the source channels SC1[A], SC2[A], and SC1[B] instead of overlapping with the central regions of the source channels SC1[A], SC2[A], and SC1[B].

[0070] In an embodiment, some of the vertical channels among the vertical channels VC1[A], VC2[A], and VC1[B] may not overlap with the source channels SC1[A], SC2[A], and SC1[B]. In an embodiment, two or more of the vertical channels VC1[A], VC2[A], and VC1[B] may overlap with some of the source channels among the source channels SC1[A], SC2[A], and SC1[B].

[0071] Figure 3C is an example of Figure 2 the first drain selection line DSL1[A] and the second drain selection line DSL2[A] of the first gate stack structure GST[A] shown and Figure 2 a plan view of an embodiment of the first drain selection line DSL1[B] of the second gate stack structure GST[B] shown.

[0072] Referring to Figure 3C , the drain slit SD can extend in the second direction D2. The drain slit SD can have various shapes, such as a wavy shape or a straight shape.

[0073] The vertical channels VC1[A], VC2[A], and VC1[B] can extend to penetrate the drain select lines DSL1[A], DSL2[A], and DSL1[B]. The memory layer ML can extend between each of the vertical channels VC1[A], VC2[A], and VC1[B] and each of the drain select lines DSL1[A], DSL2[A], and DSL1[B].

[0074] Figure 3D is a plan view illustrating a bit line according to an embodiment of the present disclosure.

[0075] Referring Figure 3D , each bit line BL can be connected to the vertical channels VC1[A], VC2[A], and VC1[B] via a contact plug CT. The vertical channels VC1[A], VC2[A], and VC1[B] connected to one bit line BL can be controlled by different drain select lines DSL1[A], DSL2[A], and DSL1[B] as shown in Figure 3C .

[0076] Figure 4A and Figure 4B are cross-sectional views of a semiconductor memory device according to an embodiment of the present disclosure. Figure 4A and Figure 4B Each of Figure 3D illustrates a cross-sectional structure of the semiconductor memory device taken along the line A-A' shown in

[0077] Referring Figure 4A and Figure 4B , each semiconductor memory device can include source select lines SSL1[A], SSL2[A], and SSL1[B] disposed between the bit line BL and the common source line CSL. The source select lines SSL1[A], SSL2[A], and SSL1[B] can be disposed at substantially the same height.

[0078] The multilayer structure 50 can be located between the height at which the source select lines SSL1[A], SSL2[A], and SSL1[B] are disposed and the height at which the bit line BL is disposed. The multilayer structure 50 can include an interlayer insulating layer 51 and a conductive pattern 53 alternately stacked in a first direction D1. The conductive pattern 53 of the multilayer structure 50 can be used as word lines WL[A] and WL[B] and drain select lines DSL1[A], DSL2[A], DSL1[B], and DSL2[B]. In an embodiment, the conductive pattern 53 can include a conductive pattern 53B adjacent to the bit line BL and disposed to be spaced apart from each other in the extending direction of the bit line BL. Among the conductive patterns 53, the conductive pattern 53B can be used as a drain select line, and the other conductive patterns can be used as word lines.

[0079] The connection patterns CP1[A], CP2[A], and CP1[B] can be disposed between the heights at which the source selection lines SSL1[A], SSL2[A], and SSL1[B] are disposed and the height at which the multilayer structure 50 is disposed. The connection patterns CP1[A], CP2[A], and CP1[B] can be disposed at substantially the same height.

[0080] The source selection lines SSL1[A], SSL2[A], and SSL1[B] can be disposed between the first insulating layer 23 and the second insulating layer 21. The first insulating layer 23 can extend to cover the surfaces of the source selection lines SSL1[A], SSL2[A], and SSL1[B] facing the common source line CSL. The second insulating layer 21 can extend to cover the surfaces of the source selection lines SSL1[A], SSL2[A], and SSL1[B] facing the connection patterns CP1[A], CP2[A], and CP1[B].

[0081] The source selection lines SSL1[A], SSL2[A], and SSL1[B] can be spaced apart from the connection patterns CP1[A], CP2[A], and CP1[B] in the first direction D1 through the second insulating layer 21. The source selection lines SSL1[A], SSL2[A], and SSL1[B] can be insulated from the connection patterns CP1[A], CP2[A], and CP1[B] through the second insulating layer 21.

[0082] The source selection lines SSL1[A], SSL2[A], and SSL1[B] can be penetrated by source channels SC1[A] and SC2[A]. The source channels SC1[A] and SC2[A] can extend to penetrate the second insulating layer 21 and contact the connection patterns CP1[A] and CP2[A]. The source channels SC1[A] and SC2[A] can penetrate the first insulating layer 23 and protrude further than the first insulating layer 23 in the first direction D1. The gate insulating layer GI can be disposed between the second insulating layer 21 and the first insulating layer 23 and surround the sidewalls of the source channels SC1[A] and SC2[A] respectively.

[0083] The source channels SC1[A] and SC2[A] can be connected to a common source line CSL. In an embodiment, the common source line CSL can include a first source layer SL1 and a second source layer SL2, and the first source layer SL1 and the second source layer SL2 are stacked spaced apart from each other in a first direction D1. Each of the first source layer SL1 and the second source layer SL2 can extend to overlap with the source selection lines SSL1[A], SSL2[A], and SSL1[B]. Each of the first source layer SL1 and the second source layer SL2 can include various conductive materials. The first source layer SL1 can include a conductive material that can provide an ohmic contact. In an embodiment, the first source layer SL1 can include tungsten silicide. The second source layer SL2 can include a conductive material having a resistivity lower than that of the first source layer SL1. The first source layer SL1 and the second source layer SL2 can be connected to each other through a source contact plug SCT.

[0084] Each of the source channels SC1[A] and SC2[A] can include a source core insulating layer 27, a source channel layer 25, and a doped semiconductor pattern 29. The source channel layer 25 can extend along the inner wall of the gate insulating layer GI and is formed in a tubular shape. The source core insulating layer 27 and the doped semiconductor pattern 29 can fill the central region defined by the tubular source channel layer 25 in each of the source channels SC1[A] and SC2[A].

[0085] The source core insulating layer 27 can be in contact with the first source layer SL1. The doped semiconductor pattern 29 can be in contact with any one of the connection patterns CP1[A] and CP2[A] corresponding to the doped semiconductor pattern 29.

[0086] The doped semiconductor pattern 29 can be disposed between any one of the connection patterns CP1[A] and CP2[A] and the source core insulating layer 27.

[0087] The source channel layer 25 can extend to surround the sidewalls of the source core insulating layer 27 and the sidewalls of the doped semiconductor pattern 29. The source channel layer 25 can penetrate through the first insulating layer 23 and the second insulating layer 21 and be in contact with any one of the connection patterns CP1[A] and CP2[A] and the first source layer SL1. The source channel layer 25 can include a semiconductor layer material. In an embodiment, the source channel layer 25 can include silicon. The source channel layer 25 and the source core insulating layer 27 can extend into the interior of the first source layer SL1.

[0088] The source channels SC1[A] and SC2[A] can be connected to the vertical channels VC1[A] and VC2[A] via the connection patterns CP1[A] and CP2[A]. Each of the connection patterns CP1[A], CP2[A], and CP1[B] can include a channel contact layer 33. Each of the vertical channels VC1[A], VC2[A], and VC1[B] can include sidewalls SW in contact with the channel contact layer 33.

[0089] The channel contact layer 33 can include a first surface SU1 and a second surface SU2 facing opposite directions. Hereinafter, the surface of the channel contact layer 33 facing the source selection lines SSL1[A], SSL2[A], and SSL1[B] is designated as the first surface SU1, and the surface of the channel contact layer 33 facing the bit line BL is designated as the second surface SU2.

[0090] Referring to Figure 4A , according to an embodiment, each of the connection patterns CP1[A], CP2[A], and CP1[B] can further include a first conductive layer 31 and a second conductive layer 35. The first conductive layer 31 can extend along the first surface SU1 of the channel contact layer 33. The second conductive layer 35 can extend along the second surface SU2 of the channel contact layer 33.

[0091] Each of the vertical channels VC1[A], VC2[A], and VC1[B] can protrude further in the first direction D1 than the multilayer structure 50. In an embodiment, each of the vertical channels VC1[A], VC2[A], and VC1[B] can penetrate the second conductive layer 35 and the channel contact layer 33 and extend into the interior of the first conductive layer 31. Thus, each of the vertical channels VC1[A], VC2[A], and VC1[B] can include a portion surrounded by the first conductive layer 31 and a portion surrounded by the second conductive layer 35.

[0092] The channel contact layer 33 can penetrate the memory layer ML between the first conductive layer 31 and the second conductive layer 35. Thus, the memory layer ML can be isolated by the channel contact layer 33 into a first memory pattern ML1 and a second memory pattern ML2.

[0093] The first memory pattern ML1 can extend along the sidewalls of the interlayer insulating layer 51 and the conductive pattern 53 between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the multilayer structure 50. The first memory pattern ML1 can extend between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the second conductive layer 35. The second memory pattern ML2 can be disposed between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the first conductive layer 31.

[0094] In the above, each of the first conductive layer 31, the channel contact layer 33, and the second conductive layer 35 may include a doped semiconductor layer. In an embodiment, each of the first conductive layer 31, the channel contact layer 33, and the second conductive layer 35 may include doped silicon.

[0095] Referring to Figure 4B , according to an embodiment, each of the connection patterns CP1[A], CP2[A], and CP1[B] may further include a conductive layer 31' extending along the first surface SU1 of the channel contact layer 33.

[0096] Each of the vertical channels VC1[A], VC2[A], and VC1[B] may penetrate the channel contact layer 33 and extend into the interior of the conductive layer 31'. Accordingly, each of the vertical channels VC1[A], VC2[A], and VC1[B] may include a portion surrounded by the conductive layer 31'.

[0097] The channel contact layer 33 may penetrate the memory layer ML between the conductive layer 31' and the multilayer structure 50. Accordingly, the memory layer ML may be isolated by the channel contact layer 33 into a first memory pattern ML1' and a second memory pattern ML2'.

[0098] The first memory pattern ML1' may surround the portion of each of the vertical channels VC1[A], VC2[A], and VC1[B] that penetrates the multilayer structure 50. The second memory pattern ML2' may be disposed between each of the vertical channels VC1[A], VC2[A], and VC1[B] and the conductive layer 31'.

[0099] In the above, the channel contact layer 33 may include a doped semiconductor layer. The conductive layer 31' may include a conductive material capable of providing an ohmic contact. In an embodiment, the conductive layer 31' may include tungsten silicide.

[0100] Returning to the reference Figure 4A and Figure 4B , each of the vertical channels VC1[A], VC2[A], and VC1[B] may include a core insulating layer 43, a channel layer 41, and a doped semiconductor pattern 45. The core insulating layer 43 may extend in a first direction D1 to penetrate the interlayer insulating layer 51 and the conductive pattern 53. The core insulating layer 43 may overlap with the doped semiconductor pattern 45.

[0101] The channel layer 41 may surround the sidewalls of the core insulating layer 43. The channel layer 41 may extend between the core insulating layer 43 and the first conductive layer 31 or between the core insulating layer 43 and the conductive layer 31' to enclose the end of the core insulating layer 43 facing the first source layer SL1. The channel layer 41 may extend to surround the sidewalls of the doped semiconductor pattern 45. The sidewall SW in contact with the channel contact layer 33 may be a part of the sidewall of the channel layer 41, and the channel contact layer 33 may be in direct contact with the channel layer 41. The channel layer 41 may include a semiconductor material. In an embodiment, the channel layer 41 may include silicon.

[0102] The vertical channels VC1[A], VC2[A] and VC1[B] may be connected to the bit line BL. The bit line BL may be connected to the vertical channels VC1[A], VC2[A] and VC1[B] via the contact plug CT. The contact plug CT may penetrate through the insulating layers 61 and 63 provided between the bit line BL and the multilayer structure 50 and contact the vertical channels VC1[A], VC2[A] and VC1[B]. The bit line BL may extend to overlap with the source selection lines SSL1[A], SSL2[A] and SSL1[B], and the multilayer structure 50 is interposed between the bit line and the source selection lines.

[0103] In an embodiment, the third insulating layer 61 and the fourth insulating layer 63 may be provided between the bit line BL and the multilayer structure 50. The fourth insulating layer 63 may fill the first slit SI1 and extend to overlap with the third insulating layer 61.

[0104] The third insulating layer 61 and the fourth insulating layer 63 may be penetrated by the drain slit SD. The drain slit SD may be filled with the drain slit insulating layer 65. The drain slit SD and the drain slit insulating layer 65 may extend between the conductive patterns 53B serving as drain selection lines.

[0105] The source slit SS and the second slit SI2 may be filled with the first source slit insulating layer 81A and the second source slit insulating layer 81B, respectively. The first source slit insulating layer 81A and the second source slit insulating layer 81B may extend between the source selection lines SSL1[A], SSL2[A] and SSL1[B] and between the connection patterns CP1[A], CP2[A] and CP1[B].

[0106] The multilayer structure 50 may overlap with the peripheral circuit layer 10, and the bit line BL is interposed between the multilayer structure 50 and the peripheral circuit layer 10. The bit line BL may be connected to the first bonding pad 75 via the first interconnect structure 73. The first interconnect structure 73 and the first bonding pad 75 may be buried in the first insulating structure 71. The peripheral circuit layer 10 may overlap with the bit line BL, and the first interconnect structure 73 and the first bonding pad 75 are interposed between the peripheral circuit layer 10 and the bit line BL.

[0107] The peripheral circuit layer 10 may include: a substrate 1 including an active region separated by an isolation layer 3; a peripheral circuit 5 for controlling operations of a memory block, such as a programming operation, a read operation, or an erase operation; a second interconnect structure 7 connected to the peripheral circuit 5; and a second bonding pad 15 connected to the second interconnect structure 7. The peripheral circuit 5, the second interconnect structure 7, and the second bonding pad 15 may be buried in a second insulating structure 9 disposed on the substrate 1. The peripheral circuit 5 may include a page buffer circuit for controlling a bit line BL. The second bonding pad 15 may be bonded to a first bonding pad 75. The second insulating structure 9 may be bonded to a first insulating structure 71.

[0108] Figures 5A to 5C is an enlarged cross-sectional view illustrating a vertical channel and a source channel according to an embodiment of the present disclosure.

[0109] Referring to Figure 5A , the vertical channel VC may be surrounded by a conductive pattern 53, and a memory layer ML is interposed between the vertical channel VC and the conductive pattern 53. The memory layer ML may include a tunnel insulating layer TI, a data storage layer DS, and a blocking insulating layer BI.

[0110] The tunnel insulating layer TI may extend along a surface of a channel layer 41 of the vertical channel VC. The tunnel insulating layer TI may include an insulating material through which charges can tunnel. In an embodiment, the tunnel insulating layer TI may include a silicon oxide layer.

[0111] The data storage layer DS may extend along a surface of the tunnel insulating layer TI. The data storage layer DS may include a material layer capable of storing data. In an embodiment, the data storage layer DS may include a nitride layer capable of storing data changed by using Fowler-Nordheim tunneling.

[0112] The blocking insulating layer BI may extend along a surface of the data storage layer DS. The blocking insulating layer BI may include an oxide layer.

[0113] Referring to Figure 5B , the vertical channel VC may be surrounded by a channel contact layer 33 of a connection pattern CP. The channel layer 41 of the vertical channel VC may be in contact with the channel contact layer 33.

[0114] Referring to Figure 5A and Figure 5B , a core insulating layer 43 of the vertical channel VC may fill a central region of the vertical channel VC and be surrounded by the channel layer 41.

[0115] Referring to Figure 5C, the source channel SC can be surrounded by a source select line SSL, and a gate insulating layer GI is interposed between the source channel SC and the source select line SSL.

[0116] The source channel SC can include a source channel layer 25. The region surrounded by the source channel layer 25 can be defined as the central region CR of the source channel SC. It can be filled with Figure 4A and Figure 4B the source core insulating layer 27 and the doped semiconductor pattern 29 shown in the central region CR of the source channel SC.

[0117] The gate insulating layer GI can include an oxide of the source select line SSL. In an embodiment, the gate insulating layer GI can include silicon oxide.

[0118] Figures 6A to 6D is a cross-sectional view illustrating a process of forming a source channel according to an embodiment of the present disclosure.

[0119] Referring to Figure 6A , a source select gate layer 107 can be formed on a sacrificial substrate 101. Although not shown in the drawings, the sacrificial substrate 101 can be in contact with an electrostatic chuck (ESC) of a semiconductor manufacturing apparatus. The sacrificial substrate 101 can be a silicon substrate.

[0120] Before forming the source select gate layer 107, an etch stop layer 103 can be formed on the sacrificial substrate 101. The etch stop layer 103 can include a material having etch selectivity with respect to the sacrificial substrate 101. In an embodiment, the etch stop layer 103 can include a nitride layer.

[0121] Before forming the source select gate layer 107, a first insulating layer 105 can be formed on the etch stop layer 103. After forming the source select gate layer 107, a second insulating layer 109 can be formed on the source select gate layer 107. The source select gate layer 107 can include various conductive materials. In an embodiment, the source select gate layer 107 can include doped silicon.

[0122] Subsequently, a first channel hole 111 can be formed, which penetrates the source select gate layer 107 and exposes the sacrificial substrate 101. The first channel hole 111 can extend to penetrate the etch stop layer 103, the first insulating layer 105, and the second insulating layer 109.

[0123] Referring to Figure 6B, a gate insulating layer 113A can be formed on sidewalls of the source selection gate layer 107 exposed through the first channel holes 111. In an embodiment, the gate insulating layer 113A can be formed by an oxidation process. When a part of the sidewalls of the silicon-containing source selection gate layer 107 is oxidized, the gate insulating layer 113A can extend into the interior of the first channel holes 111.

[0124] A dummy insulating layer 113B can be formed by oxidizing a part of the sacrificial substrate 101 when oxidizing the source selection gate layer 107.

[0125] Referring to Figure 6C , an etch stop pattern 115 can be formed. The etch stop pattern 115 can have an overhang structure. The etch stop pattern 115 can extend onto the sidewalls of the first channel holes 111 to cover the gate insulating layer 113A and leave the bottom surfaces of each of the first channel holes 111 open. An opening 117 having an upper end and a lower end can be defined by the overhang structure of the etch stop pattern 115. The upper end of the opening 117 can have a first width W1, and the lower end of the opening 117 can have a second width W2 wider than the first width W1.

[0126] The process of forming the etch stop pattern 115 can include a process of depositing an amorphous carbon layer by a deposition process with low step coverage and a process of removing a part of the amorphous carbon layer to expose the bottom surfaces of each of the first channel holes 111.

[0127] Subsequently, the dummy insulating layer 113B as shown in Figure 6B can be removed through the opening 117 defined by the etch stop pattern 115. Subsequently, the etch stop pattern 115 can be selectively removed to expose the gate insulating layer 113A.

[0128] Referring to Figure 6D , source channels 120A and 120B can be formed to contact the sacrificial substrate 101. The source channels 120A and 120B can fill the first channel holes 111 respectively. Each of the source channels 120A and 120B can be spaced apart from the source selection gate layer 107 by the gate insulating layer 113A.

[0129] The process of forming source channels 120A and 120B may include a process of forming a source channel layer 121 on the surface of each first channel hole 111 and a process of filling the central region opened through the source channel layer 121 of each first channel hole 111 with a source core insulating layer 123 and a doped semiconductor pattern 125. The source channel layer 121 may be formed by growing silicon from a sacrificial substrate 101 via an epitaxial process or by depositing a silicon layer. The source core insulating layer 123 may fill a partial region of each first channel hole 111 on the source channel layer 121. The doped semiconductor pattern 125 may include at least one of an n-type impurity and a p-type impurity.

[0130] The surfaces of each of the source channels 120A and 120B may be planarized by a planarization process such as a chemical mechanical polishing process. The source channels 120A and 120B may be connected to an ESC (not shown) that supports the sacrificial substrate 101.

[0131] Figures 7A to 7D is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0132] Referring to Figure 7A , a first stacked structure 130A extending to cover the source channels 120A and 120B may be formed on the second insulating layer 109. The first stacked structure 130A may include a first conductive layer 131, a first protective layer 133, a sacrificial layer 135, a second protective layer 137, and a second conductive layer 139 that are sequentially stacked on the second insulating layer 109. Each of the first conductive layer 131, the first protective layer 133, the sacrificial layer 135, the second protective layer 137, and the second conductive layer 139 may extend to overlap with the source channels 120A and 120B. The first conductive layer 131, the second conductive layer 139, and the sacrificial layer 135 may include silicon, and the first protective layer 133 and the second protective layer 137 may include oxide layers.

[0133] Subsequently, a second stacked structure 140 may be formed on the first stacked structure 130A. The second stacked structure 140 may include a first material layer 141 and a second material layer 143 that are alternately stacked on the first stacked structure 130A. In an embodiment, the first material layer 141 may be made of an insulating material for Figure 4A and Figure 4B the interlayer insulating layer 51 shown, and the second material layer 143 may be made of a conductive material for Figure 4A and Figure 4B the conductive pattern 53 shown. In another embodiment, the first material layer 141 may be made of an insulating material for Figure 4A and Figure 4BThe interlayer insulating layer 51 is made of an insulating material, and the second material layer 143 can be made of a sacrificial insulating material having an etching selectivity with respect to the first material layer 141. In an embodiment, the sacrificial insulating material may include a silicon nitride layer.

[0134] Subsequently, a second channel hole 145 may be formed. The second channel hole 145 may penetrate the second stacked structure 140 and extend into the first stacked structure 130A. The second channel hole 145 may penetrate the second conductive layer 139, the second protective layer 137, the sacrificial layer 135, and the first protective layer 133 of the first stacked structure 130A. The second channel hole 145 may have a bottom surface disposed inside the first conductive layer 131.

[0135] During the etching process of the first stacked structure 130A and the second stacked structure 140 performed to form the second channel hole 145, a ground voltage from an ESC (not shown) of a semiconductor manufacturing apparatus may be applied to the sacrificial substrate 101. The thicknesses of the first protective layer 133 and the second protective layer 137 may be formed to be thin enough not to hinder charge movement. In an embodiment, the thicknesses of the first protective layer 133 and the second protective layer 137 may be formed to be or less. Accordingly, during the etching process of the first stacked structure 130A and the second stacked structure 140, charges accumulated in the first conductive layer 131, the sacrificial layer 135, and the second conductive layer 139 of the first stacked structure 130A may be released through the sacrificial substrate 101 via the source channels 120A and 120B.

[0136] According to an embodiment of the present disclosure, charges accumulated in the first stacked structure 130A during the etching process of the first stacked structure 130A and the second stacked structure 140 are released through the source channels 120A and 120B in contact with the sacrificial substrate 101. Accordingly, according to an embodiment of the present disclosure, an arc phenomenon may be alleviated or prevented.

[0137] Subsequently, a memory layer 151 may be formed on the surface of each second channel hole 145. The memory layer 151 may include a Figure 5A barrier insulating layer BI, a data storage layer DS, and a tunnel insulating layer TI shown in.

[0138] Subsequently, a vertical channel 150 filling the second channel hole 145 may be formed on the memory layer 151. The process of forming the vertical channel 150 may include a process of forming a channel layer 153 on the surface of the memory layer 151 and a process of filling a central region opened by the channel layer 153 of each second channel hole 145 with a core insulating layer 155 and a doped semiconductor pattern 157. The channel layer 153 may include a semiconductor layer. In an embodiment, the channel layer 153 may include undoped silicon. In an embodiment, a portion of the channel layer 153 surrounding the doped semiconductor pattern 157 may include the same impurities as the impurities of the doped semiconductor pattern 157. In an embodiment, the doped semiconductor pattern 157 may include n-type doped silicon.

[0139] Referring to Figure 7B , a third insulating layer 161 may be formed on the second stacked structure 140 penetrated by the vertical channel 150. Subsequently, a first slit 163 may be formed. The first slit 163 may penetrate the third insulating layer 161 and the second stacked structure 140. The first slit 163 may penetrate the second conductive layer 139 and the second protective layer 137 of the first stacked structure 130A to expose the sacrificial layer 135 of the first stacked structure 130A.

[0140] Subsequently, a sidewall protective layer 165 may be formed on the sidewalls of the first slit 163. The sidewall protective layer 165 may include a material having an etching selectivity with respect to the sacrificial layer 135. In an embodiment, the sidewall protective layer 165 may include at least one of an oxide layer and a nitride layer.

[0141] Referring to Figure 7C , a first opening 167 may be formed. The first opening 167 may expose the sidewalls of each vertical channel 150.

[0142] The process of forming the first opening 167 may include a process of removing the sacrificial layer 135 as shown in Figure 7B and a process of removing a portion of the memory layer 151 to expose the channel layer 153. When removing the sacrificial layer 135, the first conductive layer 131 and the second conductive layer 139 may be protected by the first protective layer 133 and the second protective layer 137 shown in Figure 7B . A portion of the memory layer 151 may be removed through the region where the sacrificial layer 135 has been removed. When removing a portion of the memory layer 151, the first protective layer 133 and the second protective layer 137 shown in Figure 7B may be removed.

[0143] After the channel layer 153 is exposed through the first opening 167, the sidewall protective layer 165 shown in Figure 7B may be removed.

[0144] The memory layer 151 can be isolated into a first memory pattern 151A and a second memory pattern 151B through the first opening 167.

[0145] Referring to Figure 7D , a channel contact layer 169 can be formed. The channel contact layer 169 can fill Figure 7C the first opening 167 shown and contact the channel layer 153. The channel contact layer 169 can include a doped semiconductor layer. In an embodiment, the channel contact layer 169 can include doped silicon.

[0146] By referring to Figures 7A to 7D the process described, a preliminary connection structure 130B can be formed. The preliminary connection structure 130B can connect the channel layer 153 to the source channels 120A and 120B. The preliminary connection structure 130B can include a channel contact layer 169, a first conductive layer 131, and a second conductive layer 139. The channel contact layer 169 can contact the channel layer 153. The first conductive layer 131 can contact the bottom surface of the channel contact layer 169 and contact the source channels 120A and 120B. The second conductive layer 139 can contact the top surface of the channel contact layer 169 and can be penetrated by the first slit 163.

[0147] In an embodiment where the first material layer 141 is made of an insulating material and the second material layer 143 is made of a conductive material, the process shown in Figure 9 can be continuously performed. In an embodiment where the first material layer 141 is made of an insulating material and the second material layer 143 is made of a sacrificial insulating material, after performing the processes shown in Figure 8A and Figure 8B , the process shown in Figure 9 can be performed.

[0148] Figure 8A and Figure 8B are cross-sectional views illustrating a process of forming a conductive pattern according to an embodiment of the present disclosure.

[0149] Referring to Figure 8A , the second material layer 143 shown in Figure 7D can be selectively removed via the first slit 163 to define a second opening 171 between the first material layers 141. The first memory pattern 151A can be exposed through the second opening 171.

[0150] Referring to Figure 8B , the conductive pattern 173 can be filled in Figure 8AThe second opening 171 shown in [the figure]. The conductive pattern 173 may extend to surround each vertical channel 150, and the first memory pattern 151A is interposed between the conductive pattern and the vertical channel. The conductive patterns 173 may be spaced apart from each other by the first material layer 141 in the extending direction of the vertical channels 150.

[0151] By Figures 7A to 7D the process shown in Figure 8A and Figure 8B the process shown in, a preliminary connection structure 130B and a cell stack structure 170 may be formed. The cell stack structure 170 may include vertical channels 150 and conductive patterns 173. The vertical channels 150 may be in contact with the preliminary connection structure 130B. The conductive patterns 173 may be stacked around the vertical channels 150 and spaced apart from each other.

[0152] As referred to Figure 8A and Figure 8B described, the second material layer may be replaced with the conductive pattern 173 to form the cell stack structure 170. Although not shown in the drawings, the process of replacing the second material layer with the conductive pattern 173 may be performed before forming Figure 7B the sidewall protection layer 165 shown in [the figure].

[0153] Figure 9 is a cross-sectional view illustrating a process of forming a drain select line according to an embodiment of the present disclosure.

[0154] Referring to Figure 9 , a fourth insulating layer 177 may be formed. The fourth insulating layer 177 may fill the first slit 163 and extend above the third insulating layer 161. Subsequently, a drain slit insulating layer 179 may be formed. The drain slit insulating layer 179 may isolate at least one of the conductive patterns 173 into drain select lines 173DSL1, 173DSL2, and 173DSL. In an embodiment, the drain slit insulating layer 179 may penetrate through the third insulating layer 161 and the fourth insulating layer 177 and extend to penetrate through the uppermost conductive pattern 173T among the conductive patterns 173. The conductive pattern 173 overlapping with the drain slit insulating layer 179 may be retained as a word line.

[0155] The vertical channel 150 may include a first vertical channel 150A and a second vertical channel 150B. The drain slit insulating layer 179 may isolate the uppermost conductive pattern 173T into a first drain select line 173DSL1 surrounding the first vertical channel 150A and a second drain select line 173DSL2 surrounding the second vertical channel 150B by penetrating through the uppermost conductive pattern 173T between the first vertical channel 150A and the second vertical channel 150B.

[0156] Figure 10It is a cross-sectional view illustrating a process of forming a bit line according to an embodiment of the present disclosure.

[0157] Referring to Figure 10 , a contact plug 180 penetrating through the third insulating layer 161 and the fourth insulating layer 177 may be formed. Subsequently, a bit line 181 connected to the contact plug 180 may be formed. The bit line 181 may be connected to the vertical channel 150 via the contact plug 180. The bit line 181 may be connected to a pair of a first vertical channel 150A and a second vertical channel 150B.

[0158] Figure 10 Only the contact plug 180 connected to one bit line 181 is illustrated. Although not shown in the figure, among the vertical channels 150 shown in Figure 10 , another pair of a first vertical channel 150A and a second vertical channel 150B that are not connected to the contact plug 180 may be connected to another bit line via other contact plugs.

[0159] Figure 11 It is a cross-sectional view illustrating a process of forming a first bonding structure according to an embodiment of the present disclosure.

[0160] Referring to Figure 11 , a first bonding structure 189 may be formed on the bit line 181. The first bonding structure 189 may include a first insulating structure 183 and a first bonding pad 187. A first interconnect structure 185 may be buried in the first insulating structure 183. In an embodiment, the first interconnect structure 185 may be connected to the bit line 181. The first insulating structure 183 may include a multi-layer insulating layer having two or more layers. The first bonding pad 187 may be connected to the bit line 181 via the first interconnect structure 185. The first bonding pad 187 may include a metal.

[0161] Figure 12 It is a cross-sectional view illustrating a bonding process according to an embodiment of the present disclosure.

[0162] Referring to Figure 12 , before performing the bonding process, a peripheral circuit layer 200 may be provided. The peripheral circuit layer 200 may include: a substrate 201 including an isolation layer 203 and a peripheral circuit 205; a second interconnect structure 209 connected to the peripheral circuit 205; and a second bonding structure 210.

[0163] The second bonding structure 210 may include a second insulating structure 207 and a second bonding pad 211. The second insulating structure 207 may be disposed on the substrate 201 to cover the peripheral circuit 205. The second interconnecting structure 209 may be buried in the second insulating structure 207. The second insulating structure 207 may include a multi-layer insulating layer having two or more layers. The second bonding pad 211 may be connected to the peripheral circuit 205 via the second interconnecting structure 209. The second bonding pad 211 may include metal.

[0164] The first bonding structure 189 may be disposed to face the second bonding structure 210. The first bonding structure 189 and the second bonding structure 210 may be bonded to each other. The first bonding pad 187 may be bonded to the second bonding pad 211. The first insulating structure 183 may be bonded to the second insulating structure 207.

[0165] Figure 13A and Figure 13B is a cross-sectional view illustrating a process of forming a source selection line and a connection pattern according to an embodiment of the present disclosure.

[0166] Referring to Figure 13A it is possible to remove Figure 12 the sacrificial substrate 101 shown in. In an embodiment, the sacrificial substrate 101 may be removed by using at least one of the following processes: a chemical mechanical polishing process using a slurry having an etching selectivity with respect to the etching stop layer 103 and a wet etching process using an etchant having an etching selectivity with respect to the etching stop layer 103.

[0167] Since the sacrificial substrate 101 is removed, the source channels 120A and 120B may be exposed. When removing the sacrificial substrate 101, a part of the source channel layer 121 may be removed. Accordingly, the source core insulating layers 123 of each of the source channels 120A and 120B may be exposed.

[0168] Referring to Figure 13B it is possible to form the source slit 191A and the second slit 191B. The source slit 191A and the second slit 191B may penetrate through the source selection gate layer 107 and the preliminary connection structure 130B. The source selection gate layer 107 and the preliminary connection structure 130B may overlap with the peripheral circuit layer 200, and the unit stack structure 170 is interposed between the preliminary connection structure 130B and the peripheral circuit layer 200. Each of the source slit 191A and the second slit 191B may penetrate through the etching stop layer 103, the first insulating layer 105, the second insulating layer 109, the source selection gate layer 107, and the preliminary connection structure 130B.

[0169] The source select gate layer 107 can be isolated by the source slit 191A and the second slit 191B into source select lines 107SSL1, 107SSL2, and 107SSL. The preliminary connection structure 130B can be isolated by the source slit 191A and the second slit 191B into connection patterns 130CP1, 130CP2, and 130CP.

[0170] The second slit 191B can overlap with the first slit 163. The second slit 191B can extend to penetrate the first conductive layer 131 and the channel contact layer 169 of the preliminary connection structure 130B and extend into the interior of the first slit 163.

[0171] The source channels 120A and 120B can include a first source channel 120A and a second source channel 120B. The source slit 191A can penetrate the source select gate layer 107 between the first source channel 120A and the second source channel 120B. The source select gate layer 107 can be isolated by the source slit 191A into a first source select line 107SSL1 surrounding the first source channel 120A and a second source select line 107SSL2 surrounding the second source channel 120B.

[0172] The source slit 191A can extend between the first vertical channel 150A and the second vertical channel 150B. The preliminary connection structure 130B can be isolated by the source slit 191A into a first connection pattern 130CP1 surrounding the first vertical channel 150A and a second connection pattern 130CP2 surrounding the second vertical channel 150B.

[0173] Figure 14 is a cross-sectional view illustrating a process of forming a source layer according to an embodiment of the present disclosure.

[0174] Refer to Figure 14 , before forming the source layer 195, after filling each of the source slit 191A and the second slit 191B shown in Figure 13B with the source slit insulating layer 193, remove Figure 13B the etch stop layer 103 shown in

[0175] Subsequently, a source layer 195 connected to the first source channel 120A and the second source channel 120B can be formed, and the first source channel 120A and the second source channel 120B remain protruding farther than the first insulating layer 105. The source layer 195 can extend above the bit line 181 to overlap with the first source channel 120A and the second source channel 120B between the source layer 195 and the bit line 181. Although not shown in the figure, the source layer 195 can be isolated in units of planes.

[0176] Subsequently, an operation for formingFigure 4A Subsequent processes of the source contact plug SCT and the second source layer SL2 shown in

[0177] Figure 15A and Figure 15B is a cross-sectional view illustrating a process of forming a preliminary connection structure according to an embodiment of the present disclosure.

[0178] Referring to Figure 15A , before forming the preliminary connection structure, source channels 220A and 220B may be formed. The source channels 220A and 220B may be in contact with the sacrificial substrate 201. The source channels 220A and 220B may extend to penetrate the etch stop layer 203, the first insulating layer 205, the source selection gate layer 207, and the second insulating layer 209 stacked on the sacrificial substrate 201. Sidewalls of each of the source channels 220A and 220B may be surrounded by the gate insulating layer 213A. The gate insulating layer 213A may be disposed between each of the source channels 220A and 220B and the source selection gate layer 207.

[0179] The sacrificial substrate 201, the etch stop layer 203, the first insulating layer 205, the source selection gate layer 207, the second insulating layer 209, the source channels 220A and 220B, and the gate insulating layer 213A as described above may be formed by using the process described with reference to Figures 6A to 6D .

[0180] Subsequently, a first stacked structure 230A may be formed on the second insulating layer 209. The first stacked structure 230A may include a conductive layer 231 extending to cover the source channels 220A and 220B and a sacrificial layer 235 stacked on the conductive layer 231. The conductive layer 231 may have the ability to withstand heat generated in subsequent processes and include a conductive material that can provide an ohmic contact. In an embodiment, the conductive layer 231 may include tungsten silicide. The sacrificial layer 235 may include a material having an etch selectivity with respect to the conductive layer 231. In an embodiment, the sacrificial layer 235 may include silicon.

[0181] Subsequently, a second stacked structure 240 may be formed on the first stacked structure 230A. The second stacked structure 240 may include a first material layer 241 and a second material layer 243 stacked alternately on the first stacked structure 230A as described with reference to Figure 7A .

[0182] Subsequently, a memory layer 251 and a vertical channel 250 may be formed. The memory layer 251 and the vertical channel 250 may penetrate the second stacked structure 240 and extend into the conductive layer 231 of the first stacked structure 230A. By using the process described with reference to Figure 7AThe described process is used to form the memory layer 251 and the vertical channel 250. The vertical channel 250 may include a channel layer 253, a core insulating layer 256, and a doped semiconductor pattern 257 as described with reference to Figure 7A .

[0183] Subsequently, as described with reference to Figure 7B , a third insulating layer 261 may be formed on the second stacked structure 240, and a first slit 263 may be formed through the third insulating layer 261 and the second stacked structure 240. The first slit 263 may expose the sacrificial layer 235 of the first stacked structure 230A.

[0184] Subsequently, a sidewall protection layer 265 may be formed on the sidewalls of the first slit 263. The sidewall protection layer 265 may include a material having an etching selectivity with respect to the sacrificial layer 235. In an embodiment, the sidewall protection layer 265 may include at least one of an oxide layer and a nitride layer.

[0185] With reference to Figure 15B , similar to that described with reference to Figure 7C , with the second stacked structure 240 shown in Figure 15A protected by the sidewall protection layer 265, the sacrificial layer 235 and a part of the memory layer 251 are removed. Accordingly, the memory layer may be isolated into a first memory pattern 251A and a second memory pattern 251B, and the channel layer 253 may be exposed between the first memory pattern 251A and the second memory pattern 251B.

[0186] Subsequently, similar to that described with reference to Figure 7C , a channel contact layer 269 may be formed. The channel contact layer 269 may be disposed between the first memory pattern 251A and the second memory pattern 251B and in contact with the channel layer 253. The channel contact layer 269 may fill the region where the sacrificial layer has been removed.

[0187] Through the processes described with reference to Figure 15A and Figure 15B , a preliminary connection structure 230B may be formed. The preliminary connection structure 230B may connect the channel layer 253 to the source channels 220A and 220B.

[0188] Subsequently, the processes of forming the conductive pattern 273 described with reference to Figure 8A and Figure 8B , the process of forming the drain select line described with reference to Figure 9 , the process of forming the bit line described with reference to Figure 10 , the process of forming the first bonding structure described with reference to Figure 11 , the bonding process described with reference to Figure 12 may be sequentially performed.Figure 13A and Figure 13B the forming process of the source selection line and the connection pattern described, and with reference to Figure 14 the forming process of the source layer described. Subsequently, subsequent processes for forming Figure 4A the source contact plug SCT and the second source layer SL2 shown in

[0189] Figure 16 is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0190] With reference to Figure 16 , the memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0191] The memory device 1120 may include: vertical channels that are connected to bit lines and penetrate through drain selection lines and word lines; connection patterns that are in contact with the vertical channels; source channels that are connected to the vertical channels via the connection patterns; and source selection lines that surround the source channels.

[0192] The memory device 1120 may be a multi-chip package configured with a plurality of flash memory chips.

[0193] The memory controller 1110 controls the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as an operating memory for the CPU 1112. The CPU 1112 performs overall control operations for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for the host to connect to the memory system 1100. The error correction block 1114 detects and corrects errors included in the data read from the memory device 1120. The memory interface 1115 is interfaced with the memory device 1120. The memory controller 1110 may further include a read-only memory (ROM) or the like for storing code data for interfacing with the host.

[0194] Figure 17 is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0195] With reference to Figure 17 , the computing system 1200 may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 that are electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0196] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include: vertical channels that are connected to bit lines and penetrate through drain selection lines and word lines; connection patterns that are in contact with the vertical channels; source channels that are connected to the vertical channels via the connection patterns; and source selection lines that surround the source channels.

[0197] According to the present disclosure, charges generated in the manufacturing process of a semiconductor memory device can be released through the source channels in contact with a sacrificial substrate, and thus an arc phenomenon can be alleviated or prevented. Accordingly, the stability of the manufacturing process of the semiconductor memory device can be improved.

[0198] According to the present disclosure, after removing the sacrificial substrate, an etching process for defining the source selection lines and the connection patterns is performed. Accordingly, the difficulty level of the manufacturing process of the semiconductor memory device can be reduced.

[0199] According to the present disclosure, the vertical channels and the source channels are electrically connected to each other through the connection patterns. Accordingly, a current flow path can be formed between the bit lines connected to the vertical channels and the common source line connected to the source channels.

[0200] Cross - reference to related applications

[0201] This application claims the priority of Korean Patent Application No. 10 - 2020 - 0110578, filed with the Korean Intellectual Property Office on August 31, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method of manufacturing a semiconductor memory device, the method comprises the following steps: forming a source select gate layer on a sacrificial substrate; forming a first source channel penetrating the source select gate layer, the first source channel contacting the sacrificial substrate; forming a preliminary connection structure connected to the first source channel; forming a unit stacked structure including a first vertical channel and a conductive pattern, wherein the first vertical channel contacts the preliminary connection structure and extends in a first direction, and wherein the conductive patterns surround the first vertical channel and are stacked at intervals from each other in the first direction; forming a bit line connected to the first vertical channel; forming a first bonding structure on the bit line; forming a peripheral circuit layer including a peripheral circuit and a second bonding structure overlapping with the peripheral circuit; bonding the first bonding structure and the second bonding structure to each other; removing the sacrificial substrate to expose the first source channel; and forming a source slit insulating layer penetrating the source select gate layer and the preliminary connection structure, the source select gate layer and the preliminary connection structure overlapping with the peripheral circuit layer.

2. The method according to claim 1, the method further comprises the following steps: stacking an etch stop layer and a first insulating layer on the sacrificial substrate before forming the source select gate layer; forming a second insulating layer on the source select gate layer; and removing the etch stop layer after forming the source slit insulating layer, wherein the first source channel penetrates the second insulating layer, the first insulating layer and the etch stop layer.

3. The method according to claim 1, wherein, the step of forming the first source channel comprises the following steps: forming a channel hole exposing the sacrificial substrate, the channel hole penetrating the source select gate layer; forming a gate insulating layer on sidewalls of the source select gate layer exposed through the channel hole; forming a source channel layer along a surface of the channel hole, wherein the source channel layer contacts the sacrificial substrate and is spaced apart from the source select gate layer by the gate insulating layer; and filling a central region of the channel hole opened by the source channel layer with a source core insulating layer and a doped semiconductor pattern.

4. The method according to claim 1, wherein, the step of forming the unit stacked structure comprises the following steps: forming a first stacked structure extending to cover the first source channel; forming a second stacked structure by alternately stacking a first material layer and a second material layer on the first stacked structure; forming a channel hole penetrating the second stacked structure, the channel hole extending into the first stacked structure; forming a memory layer on a surface of the channel hole; forming the first vertical channel filling the channel hole; forming a slit penetrating the second stacked structure; and replacing the second material layer of the second stacked structure with the conductive pattern through the slit.

5. The method according to claim 1, wherein, the step of forming the preliminary connection structure comprises the following steps: Form a first stacked structure, which includes a first conductive layer covering the first source channel and a sacrificial layer disposed on the first conductive layer; Form a second stacked structure on the first stacked structure; Form a channel hole penetrating the second stacked structure, and the channel hole extends into the first conductive layer of the first stacked structure; Form a memory layer on the surface of the channel hole; Form the first vertical channel filling the channel hole; Form a slit penetrating the second stacked structure, and the slit exposes the sacrificial layer; Form a sidewall protection layer on the sidewall of the slit; By removing a part of the memory layer and the sacrificial layer through the slit, form an opening exposing the sidewall of the first vertical channel; and Fill the opening with a channel contact layer.

6. The method according to claim 5, wherein, the first stacked structure further includes: a first protection layer disposed between the first conductive layer and the sacrificial layer; a second protection layer disposed on the sacrificial layer; and a second conductive layer disposed on the second protection layer, wherein, when forming the opening, the first protection layer and the second protection layer are removed, and wherein, the channel contact layer contacts the first conductive layer and the second conductive layer.

7. The method according to claim 1, wherein, when forming the first source channel, form a second source channel contacting the sacrificial substrate, wherein, the unit stacked structure further includes a second vertical channel contacting the preliminary connection structure, and the second vertical channel extends parallel to the first vertical channel, wherein, the source selection gate layer is isolated by the source slit insulating layer into a first source selection line surrounding the first source channel and a second source selection line surrounding the second source channel, and wherein, the preliminary connection structure is isolated by the source slit insulating layer into a first connection pattern between the first source channel and the first vertical channel and a second connection pattern between the second source channel and the second vertical channel.

8. The method according to claim 7, the method further includes the following steps: Form a source layer connected to the first source channel and the second source channel, wherein, the source layer extends to overlap with the bit line, and the first source channel and the second source channel are between the source layer and the bit line.

9. The method according to claim 7, the method further includes the following steps: Form a drain slit insulating layer between the first vertical channel and the second vertical channel, the drain slit insulating layer penetrates at least one of the conductive patterns, and the drain slit insulating layer isolates the at least one conductive pattern into a first drain selection line and a second drain selection line.

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