Semiconductor device including electrode and isolation pattern and method of forming same

Abstract

The invention relates to a semiconductor device including an electrode and an isolation pattern and a method of forming the same. A semiconductor device may include a stacked structure bonded to a circuit structure and including a plurality of molding layers alternately stacked with a plurality of electrodes. A source line may be disposed on the stack structure. A channel structure may be provided extending through the stack structure into the source line. An isolation insulating pattern disposed in a slit extending through the source line and the stack structure may be provided. The isolation insulating pattern may include a first section adjacent to the source line and a second section adjacent to the stacked structure. The isolation insulating pattern may include a converging interface between the first and second sections. A converging interface may be disposed between an end of the channel structure and an end of the plurality of electrodes.

Description

Technical Field

[0001] Various embodiments of the disclosed technology generally relate to a semiconductor device including, but not limited to, electrodes and isolation patterns, and a method of forming the same. Background Art

[0002] In response to the demand for high integration of semiconductor devices, there are techniques for bonding two wafers. The bonding between a lower wafer and an upper wafer can use the coupling between insulating layers. The electrical connection between the lower wafer and the upper wafer can use the coupling between bonding pads provided in the insulating layer. Physical deformations such as warping of the upper wafer result in a reduction in the yield of the bonding process and the bonded wafers. Summary of the Invention

[0003] In an embodiment, a semiconductor device may include a stacked structure bonded to a circuit structure and including a plurality of formed layers stacked alternately with a plurality of electrodes. A source line may be provided on the stacked structure. A channel structure extending through the stacked structure to the source line may be provided. An isolation insulating pattern may be provided in a slit extending through the source line and the stacked structure. The isolation insulating pattern may include a first section adjacent to the source line and a second section adjacent to the stacked structure. The isolation insulating pattern may include a converging interface between the first section and the second section. The converging interface may be provided between an end of the channel structure provided in the source line and a surface of the plurality of electrodes closest to the source line.

[0004] In an embodiment, a semiconductor device may include a stacked structure located on a substrate. The stacked structure may include a plurality of formed layers stacked alternately with a plurality of electrodes. A source line may be provided on the stacked structure. A channel structure extending through the stacked structure to the source line may be provided. An isolation insulating pattern may be provided in a slit extending through the source line and the stacked structure. The isolation insulating pattern may include a first section adjacent to the source line and a second section adjacent to the stacked structure. A side surface of the isolation insulating pattern may include a converging interface between the first section and the second section. The converging interface may be provided between an end of the channel structure provided in the source line and a surface of the plurality of electrodes closest to the source line.

[0005] In an embodiment, a method of forming a semiconductor device may include bonding a stacked structure to a circuit structure. The stacked structure may include a plurality of formed layers stacked alternately with a plurality of sacrificial layers. After bonding the stacked structure to the circuit structure, the plurality of sacrificial layers in the stacked structure may be removed, and a plurality of electrodes may be formed. An isolation insulating pattern may be formed in a slit extending through the stacked structure.

[0006] In an embodiment, a method of forming a semiconductor device may include bonding a stacked structure to a circuit structure. The stacked structure may include a plurality of formed layers stacked alternately with a plurality of sacrificial layers. A source line may be formed on the stacked structure. A channel structure may be formed extending through the stacked structure into the source line. An isolation insulating pattern may be formed in a slit extending through the source line and the stacked structure. The isolation insulating pattern may include a first section adjacent to the source line and a second section adjacent to the stacked structure. The isolation insulating pattern may include a converging interface between the first section and the second section. The converging interface may be formed between an end of the channel structure disposed in the source line and a surface of the plurality of electrodes closest to the source line.

[0007] In an embodiment, a semiconductor device may include a stacked structure formed on a first semiconductor wafer and including a plurality of insulating layers stacked alternately with a plurality of electrodes replacing a plurality of sacrificial layers. A circuit structure may be included, which is formed on a second wafer and bonded to the stacked structure before forming the plurality of electrodes. A source line may be disposed on the stacked structure. A first insulating layer among the plurality of insulating layers may be closest to the source line. A channel structure extending through the stacked structure into the source line may be included. An end of the channel structure may extend into the source line. An isolation insulating pattern may be disposed in a slit extending through the source line and the stacked structure. The isolation insulating pattern may include a converging interface between a first section adjacent to the source line and a second section adjacent to the stacked structure. The converging interface may be disposed at a height within one of the source line and the first insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment based on the disclosed technology.

[0009] Figures 2 to 8 is a partial view showing a section of Figure 1 according to various embodiments.

[0010] Figure 9 is a flowchart showing a method of forming a semiconductor device according to an embodiment based on the disclosed technology.

[0011] Figures 10 to 25 is a cross-sectional view and a plan view of a semiconductor device formed by a method of forming a semiconductor device using various embodiments based on the disclosed technology.

[0012] Cross-hatching throughout the drawings indicates corresponding or similar regions between the drawings, rather than indicating the material of the regions. DETAILED DESCRIPTION

[0013] Various embodiments of the disclosed technology are directed to providing a semiconductor device and a method of forming the same that have excellent electrical characteristics and are conducive to increasing mass production efficiency.

[0014] Terms such as "vertical", "horizontal", "upper", "lower", "uppermost", "lowermost", "above", "bottom", and other terms that imply a specific spatial relationship and / or orientation are provided only for ease of description or reference and are not limiting.

[0015] Figure 1 is a cross-sectional view of a semiconductor device showing an embodiment based on the disclosed technology, Figures 2 to 6 is showing Figure 1 a partial view of section 10 of Figure 7 and Figure 8 is showing Figure 1 a partial view of section 15 of

[0016] Referring to Figure 1 , a semiconductor device according to an embodiment based on the disclosed technology includes a circuit structure CS on a first substrate 21. The circuit structure CS includes an isolation layer 23, transistors TR, a circuit insulating layer 25, vertical interconnects 26, and horizontal interconnects 27. A first insulating bonding layer 35 and a first bonding pad 36 are provided on the circuit structure CS.

[0017] For ease of reference with respect to the orientation of the drawings, a first direction FD, a second direction SD, and a third direction VD are shown. The first direction FD and the second direction SD are parallel to the upper surface and / or the lower surface of the first substrate 21. The second direction SD is perpendicular to the first direction FD. The third direction VD is perpendicular to the first direction FD and the second direction SD. The third direction VD is perpendicular to the upper surface and / or the lower surface of the first substrate 21.

[0018] In this example, a second insulating bonding layer 135 is bonded to the first insulating bonding layer 35 in the third direction VD. A second bonding pad 136 is bonded to the first bonding pad 36. The second bonding pad 136 is provided in the second insulating bonding layer 135. An interlayer insulating layer 125 and interconnects 126 are provided on the second insulating bonding layer 135 and the second bonding pad 136. A stacked structure ST is provided on the interlayer insulating layer 125 and the interconnects 126.

[0019] A source line 142 is provided on the stacked structure ST. A channel structure CH extends through the stacked structure ST in the third direction VD into the source line 142. An isolation insulating pattern 250 is provided in a slit 157SLT that extends through the source line 142 and the stacked structure ST in the third direction VD. The upper surface of the source line 142 and the upper surface of the isolation insulating pattern 250 are formed in substantially the same plane. The lower surface of the isolation insulating pattern 250 contacts the interlayer insulating layer 125.

[0020] The stacked structure ST includes a first stacked structure ST1, a second stacked structure ST2, and a third stacked structure ST3.

[0021] The first stacked structure ST1 includes a plurality of first forming layers 53 stacked alternately with a plurality of first horizontal electrodes 155.

[0022] The second stacked structure ST2 includes a plurality of second forming layers 63 stacked alternately with a plurality of second horizontal electrodes 165.

[0023] The third stacked structure ST3 includes a plurality of third forming layers 73 stacked alternately with a plurality of third horizontal electrodes 175. The forming layer is also referred to as an insulating layer, and the horizontal electrode is also referred to as an electrode or a conductive layer.

[0024] As Figures 2 to 8 shown, the channel structure CH includes: a core layer CO that extends through the stacked structure ST into the source line 142; a channel pattern CP that surrounds the side surface and the upper surface of the core layer CO; an information storage pattern DSL that is located between the channel pattern CP and the stacked structure ST; and a bit plug DP that contacts the core layer CO and the channel pattern CP at one end of the channel structure CH, as Figure 8 shown. The information storage pattern DSL includes a tunnel layer TL provided on the channel pattern CP, a charge trapping layer CTL provided on the tunnel layer TL, and a blocking layer BL provided on the charge trapping layer CTL. The charge trapping layer CTL is provided between the tunnel layer TL and the blocking layer BL.

[0025] As Figure 1 shown, the slit 157SLT extends completely through the source line 142 and the entire stacked structure ST in the third direction VD. The slit 157SLT includes an upper slit 157 and a lower slit 157L. The lower slit 157L is open, joined, or adjacent to the upper slit 157. The upper slit 157 extends at least partially through the source line 142 in the third direction VD. The upper slit 157 may have an inverted trapezoidal shape.

[0026] The lower slit 157L extends through the stacked structure ST in the third direction VD. The lower slit 157L includes a first lower slit 57, a second lower slit 67, and a third lower slit 77. The first lower slit 57, the second lower slit 67, and the third lower slit 77 are open, joined, or adjacent to each other. The first lower slit 57 extends through the first stacked structure ST1. The first lower slit 57 may have a trapezoidal shape. The second lower slit 67 extends through the second stacked structure ST2. The second lower slit 67 may have a trapezoidal shape. The third lower slit 77 extends through the third stacked structure ST3. The third lower slit 77 may have a trapezoidal shape.

[0027] The isolation insulating pattern 250 includes an upper section 250U (also referred to as the first section) and a lower section 250L (also referred to as the second section). The lower section 250L can be adjacent to the upper section 250U in the third direction VD. The upper section 250U is disposed in the upper slit 157. The upper section 250U can have an inverted trapezoidal shape. The lower section 250L is disposed in the lower slit 157L.

[0028] The lower section 250L includes a first lower section 250L1, a second lower section 250L2, and a third lower section 250L3. The first lower section 250L1, the second lower section 250L2, and the third lower section 250L3 can be adjacent to each other. The first lower section 250L1 is disposed in the first lower slit 57. The first lower section 250L1 can have a trapezoidal shape. The second lower section 250L2 is disposed in the second lower slit 67. The second lower section 250L2 can have a trapezoidal shape. The third lower section 250L3 is disposed in the third lower slit 77. The third lower section 250L3 can have a trapezoidal shape.

[0029] The side surface of the isolation insulating pattern 250 includes a converging interface 250CIF between the upper section 250U and the lower section 250L. The converging interface 250CIF is disposed between the height of the uppermost end of the channel structure CH and the height of the upper surface of the uppermost horizontal electrode 155 that is closest to the source line 142.

[0030] In Figures 1 to 8 the example, the source line 142 corresponds to a common source line. The plurality of horizontal electrodes 155, 165, and 175 include a plurality of word lines, a plurality of selection lines, and at least one GIDL (gate-induced drain leakage) control line. A plurality of memory cells are formed at the intersections of the channel structure CH and the plurality of word lines.

[0031] In an embodiment, at least one of the plurality of horizontal electrodes 155, 165, and 175 that is closest to the source line 142 corresponds to a source selection line. At least one of the plurality of horizontal electrodes 155, 165, and 175 that is closest to the bit plug DP corresponds to a drain selection line. One of the plurality of horizontal electrodes 155, 165, and 175 that is closest to the source line 142 and / or one of the plurality of horizontal electrodes 155, 165, and 175 that is closest to the bit plug DP corresponds to a GIDL control line. The plurality of word lines are disposed between at least one drain selection line and at least one source selection line among the plurality of horizontal electrodes 155, 165, and 175.

[0032] Referring to Figure 2, the convergence interface 250CIF is disposed at the horizontal height of the uppermost end of the channel structure CH. The upper section 250U of the isolation insulating pattern 250 is adjacent to the lower section 250L. The slopes of the upper section 250U and the lower section 250L of the isolation insulating pattern 250 may be different from each other. In an embodiment, the convergence interface 250CIF may be disposed at a horizontal height lower than the uppermost end of the channel structure CH.

[0033] The channel structure CH includes a core layer CO, a channel pattern CP, and an information storage pattern DSL. The information storage pattern DSL includes a tunnel layer TL, a charge trapping layer CTL, and a blocking layer BL. The channel pattern CP surrounds the side surface and the upper surface of the core layer CO. The information storage pattern DSL surrounds the side surface of the channel pattern CP. The channel pattern CP and the core layer CO may extend into the source line 142. The channel pattern CP may be in direct contact with the source line 142. The uppermost end of the information storage pattern DSL does not extend further or terminates at the lowermost surface of the source line 142.

[0034] The information storage pattern DSL is disposed between the channel pattern and a plurality of first shaping layers 53 that are alternately stacked with a plurality of first horizontal electrodes 155. The charge trapping layer CTL is disposed between the tunnel layer TL and the blocking layer BL. The tunnel layer TL is disposed between the charge trapping layer CTL and the channel pattern CP. The blocking layer BL is disposed between the charge trapping layer CTL and a plurality of first shaping layers 53 that are alternately stacked with a plurality of first horizontal electrodes 155.

[0035] An undercut region 157LUC that is open, joined, or adjacent to the lower slit 157L is formed between the continuous first shaping layers 53. The lower section 250L of the isolation insulating pattern 250 includes a side extension 250LUC that extends into the undercut region 157LUC. The side extension 250LUC contacts the side surface of the first horizontal electrode 155.

[0036] Refer to Figure 3 , the convergence interface 250CIF is disposed at the horizontal height where the uppermost surface of the plurality of first shaping layers 53 contacts the lowermost surface of the source line 142.

[0037] Refer to Figure 4 , the convergence interface 250CIF is disposed at a height above the uppermost surface of the plurality of first horizontal electrodes 155. In an embodiment, the convergence interface 250CIF is disposed between the uppermost surface of the plurality of first horizontal electrodes 155 and the lowermost surface of the source line 142.

[0038] Refer to Figure 5, the upper section 250U and the lower section 250L of the isolation insulating pattern 250 may have different horizontal widths, where the upper section 250U is adjacent to the lower section 250L. The horizontal width is the width in the first direction FD. At the intersection of the upper section 250U and the lower section 250L, the horizontal width of the upper section 250U of the isolation insulating pattern 250 is greater than the width of the lower section 250L. The upper section 250U of the isolation insulating pattern 250 may have an inverted trapezoidal shape, and the lower section 250L of the isolation insulating pattern 250 may have a trapezoidal shape. The converging interface 250CIF may include a step.

[0039] Reference Figure 6 , the center of the upper section 250U of the isolation insulating pattern 250 is offset from the center of the lower section 250L. Reference Figure 1 and Figure 6 , a straight line that vertically passes through the center of the upper section 250U of the isolation insulating pattern 250 and extends in the third direction VD is offset in the third direction VD from a straight line that vertically passes through the center of the lower section 250L of the isolation insulating pattern 250. The converging interface 250CIF may include a step.

[0040] Reference Figure 7 , the lowermost end of the lower section 250L of the isolation insulating pattern 250 is set at the horizontal height where the lowermost ends of the plurality of third molding layers 73 and the bit plug DP are located. The lowermost end of the lower section 250L of the isolation insulating pattern 250 is set at the horizontal height at the boundary between the lowermost surface of the plurality of third molding layers 73 and the interlayer insulating layer 125.

[0041] The channel structure CH includes a core layer CO, a channel pattern CP, an information storage pattern DSL, and a bit plug DP. The information storage pattern DSL includes a tunnel layer TL, a charge trapping layer CTL, and a blocking layer BL. The bit plug DP directly contacts the core layer CO and the channel pattern CP. The bit plug DP contacts the interconnect 126.

[0042] Reference Figure 8 , the lowermost end of the lower slit 157L extends into the interlayer insulating layer 125. The lowermost end of the lower section 250L of the isolation insulating pattern 250 extends into the interlayer insulating layer 125. The lowermost end of the lower slit 157L is set at a height lower than the uppermost surface of the interlayer insulating layer 125 and the interconnect 126. The lowermost end of the lower section 250L of the isolation insulating pattern 250 is set at a height lower than the uppermost surface of the interlayer insulating layer 125 and the interconnect 126. The lowermost end of the lower section 250L of the isolation insulating pattern 250 is set at a height lower than the boundary between the bit plug DP and the interconnect 126.

[0043] Figure 9 is a flowchart showing a method of forming a semiconductor device according to an embodiment of the disclosed technology.Figure 10 , Figure 11 , Figures 13 to 19 and Figures 21 to 24 are cross-sectional views of a semiconductor device. Figure 12 , Figure 20 and Figure 25 are plan views of semiconductor devices respectively corresponding to Figure 11 , Figure 19 and Figure 24 .

[0044] Referring to Figure 9 , a method of forming a semiconductor device according to an embodiment of the disclosed technology includes the following steps: forming a B910 circuit structure; forming a B920 stacked structure; bonding the stacked structure B930 to the circuit structure; forming a B940 source line on the stacked structure; forming a B950 slit extending through the source line and the stacked structure; removing a sacrificial layer in the B960 stacked structure; and forming a B970 horizontal electrode and forming an isolation insulating pattern in the slit.

[0045] Referring to Figure 9 and Figure 10 , a B910 circuit structure CS is formed on a first substrate 21. The circuit structure CS includes an isolation layer 23, a transistor TR, a circuit insulating layer 25, a vertical interconnect 26, and a horizontal interconnect 27. A first insulating bonding layer 35 is formed on the circuit structure CS. A first bonding pad 36 is formed in the first insulating bonding layer 35. The upper surfaces of the first insulating bonding layer 35 and the first bonding pad 36 are exposed and formed in substantially the same plane.

[0046] The first substrate 21 includes a semiconductor substrate such as a silicon wafer or an SOI (silicon-on-insulator) wafer. The first substrate 21 may include a III-V semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide GaAs. The first substrate 21 may include single crystal silicon, polycrystalline silicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof. The circuit structure CS is formed in and / or on the first substrate 21.

[0047] The circuit structure CS includes various types of active / passive elements, such as one or more transistors TR. The transistor TR may be a planar transistor, a recessed channel transistor, a vertical transistor, a fin field-effect transistor (finFET), a gate-all-around (GAA) transistor, a multi-bridge channel transistor, or a combination thereof. In an embodiment, the transistor may be part of a peripheral circuit such as a page buffer or a decoder.

[0048] An isolation layer 23 may be formed in the first substrate 21 using a shallow trench isolation (STI) method. A transistor TR may be defined on the first substrate 21 through the isolation layer 23. A circuit insulating layer 25 covers the isolation layer 23 and the transistor TR. Vertical interconnects 26 and horizontal interconnects 27 are formed in the circuit insulating layer 25. The vertical interconnects 26 and the horizontal interconnects 27 are connected to the transistor TR. A first bonding pad 36 is connected to the transistor TR through the vertical interconnects 26 and the horizontal interconnects 27.

[0049] Each of the isolation layer 23, the circuit insulating layer 25, and the first insulating bonding layer 35 may be a single layer or a multi-layer. Each of the isolation layer 23, the circuit insulating layer 25, and the first insulating bonding layer 35 may include at least two selected from the group consisting of silicon Si, oxygen O, nitrogen N, carbon C, and boron B. Each of the isolation layer 23, the circuit insulating layer 25, and the first insulating bonding layer 35 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), low-k dielectrics, high-k dielectrics, or a combination thereof. In an embodiment, the first insulating bonding layer 35 may include silicon carbonitride (SiCN).

[0050] Each of the vertical interconnects 26, the horizontal interconnects 27, and the first bonding pad 36 may be a single layer or a multi-layer. Each of the vertical interconnects 26, the horizontal interconnects 27, and the first bonding pad 36 may include a conductive material such as metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the vertical interconnects 26, the horizontal interconnects 27, and the first bonding pad 36 may include a conductive material such as copper Cu, aluminum Al, nickel Ni, cobalt Co, ruthenium Ru, tungsten W, tungsten nitride WN, titanium Ti, titanium nitride TiN, tantalum Ta, tantalum nitride TaN, tin Sn, platinum Pt, gold Au, silver Ag, or a combination thereof. In an embodiment, the first bonding pad 36 may include a Cu layer formed using an electroplating method.

[0051] Referring to Figure 9 and Figure 11 , a first stacked structure ST1 in which a plurality of first molding layers 53 and a plurality of first sacrificial layers 54 are alternately stacked is formed on or above the second substrate 51. First channel holes 56 and first lower slits 57 are formed and extend through the first stacked structure ST1 into the second substrate 51. A first channel sacrificial layer 58 is formed in each of the first channel holes 56, and a first slit sacrificial layer 59 is formed in each of the first lower slits 57.

[0052] The plurality of first sacrificial layers 54 includes a material having an etch selectivity different from that of the plurality of first shaping layers 53. In an embodiment, the plurality of first shaping layers 53 may include an insulating oxide such as silicon oxide, and the plurality of first sacrificial layers 54 may include a nitride such as silicon nitride. The lowermost layer of the first stack structure ST1 may be one of the plurality of first shaping layers 53, and the uppermost layer of the first stack structure ST1 may be one of the plurality of first sacrificial layers 54 and the plurality of first shaping layers 53.

[0053] Each of the first channel holes 56 and the first lower slits 57 extends through the first stack structure ST1 in the third direction VD into the second substrate 51. The first channel sacrificial layer 58 and the first slit sacrificial layer 59 include a material different from that of the plurality of first sacrificial layers 54 and the plurality of first shaping layers 53. In an embodiment, the first channel sacrificial layer 58 and the first slit sacrificial layer 59 may include polysilicon, carbon, or metal.

[0054] Referring to Figure 9 and Figure 12 , a plurality of first channel holes 56 are arranged at regular intervals in the first direction FD and the second direction SD. A plurality of first lower slits 57 are arranged at regular intervals in the second direction SD. In an embodiment, the first lower slits 57 may have dimensions and shapes similar to those of the first channel holes 56.

[0055] Referring to Figure 9 and Figure 13 , a second stack structure ST2 in which a plurality of second shaping layers 63 and a plurality of second sacrificial layers 64 are alternately stacked is formed on or above the first stack structure ST1. Second channel holes 66 and second lower slits 67 are formed through the second stack structure ST2. A second channel sacrificial layer 68 is formed in each of the second channel holes 66, and a second slit sacrificial layer 69 is formed in each of the second lower slits 67.

[0056] A third stack structure ST3 in which a plurality of third shaping layers 73 and a plurality of third sacrificial layers 74 are alternately stacked is formed on or above the second stack structure ST2. Third channel holes 76 and third lower slits 77 are formed through the third stack structure ST3. A third channel sacrificial layer 78 is formed in each of the third channel holes 76, and a third slit sacrificial layer 79 is formed in each of the third lower slits 77.

[0057] As described above, the first stacked structure ST1, the second stacked structure ST2, and the third stacked structure ST3 are combined to form the B920 stacked structure ST. The first channel hole 56, the second channel hole 66, and the third channel hole 76 are open, joined, or adjacent to each other in the third direction VD. Components included in the second stacked structure ST2 and the third stacked structure ST3 can be formed using a similar method to that used for forming the first stacked structure ST1. Components included in the second stacked structure ST2 and the third stacked structure ST3 can include materials that are substantially the same as those included in the first stacked structure ST1. The uppermost layer of the third stacked structure ST3 is one of the plurality of third molding layers 73. The uppermost layer of the third stacked structure ST3 corresponds to the uppermost layer of the stacked structure ST. The lowermost layer of the first stacked structure ST1 corresponds to the lowermost layer of the stacked structure ST.

[0058] Referring Figure 9 and Figure 14 , the third channel sacrificial layer 78, the second channel sacrificial layer 68, and the first channel sacrificial layer 58 are removed, and a channel structure CH is formed in the first channel hole 56, the second channel hole 66, and the third channel hole 76. The channel structure CH extends through the stacked structure ST in the third direction VD into the second substrate 51. For example, an etching process can be used to remove the sacrificial layers 58, 68, and 78.

[0059] The channel structure CH includes a core layer CO, a channel pattern CP, an information storage pattern DSL, and a bit plug DP. As Figure 7 shown, the information storage pattern DSL includes a tunnel layer TL, a charge trapping layer CTL, and a blocking layer BL. The channel pattern CP is formed to surround the side surface and ends of the core layer CO disposed in the second substrate 51. The information storage pattern DSL is formed to surround the side surface and ends of the channel pattern CP disposed in the second substrate 51. The channel pattern CP is disposed between the core layer CO and the information storage pattern DSL. The bit plug DP is formed on the channel pattern CP and the core layer CO. The bit plug DP directly contacts the core layer CO and the channel pattern CP. For example, the channel structure CH can be formed within the stacked structure ST by first forming the outermost layer and forming each successive layer toward the innermost layer, for example, successively forming the blocking layer BL, the charge trapping layer CTL, the tunnel layer TL, the channel pattern CP, and the core layer CO, and then forming the bit plug DP. The blocking layer BL, the charge trapping layer CTL, the tunnel layer TL, the channel pattern CP, and the core layer CO each penetrate the stacked structure ST and are adjacent to each other, as shown in the figure.

[0060] In an embodiment, the core layer CO can include silicon oxide, silicon nitride, silicon oxynitride, polysilicon, or a combination thereof. The channel pattern CP can include a semiconductor material such as polysilicon. The bit plug DP can include a semiconductor material such as polysilicon. The tunnel layer TL can include silicon oxide, the charge trapping layer CTL can include silicon nitride, and the blocking layer BL can include silicon oxide.

[0061] Refer to Figure 9 and Figure 15 An interlayer insulating layer 125 is formed on or above the stacked structure ST. One or more interconnects 126 are formed in the interlayer insulating layer 125. A second insulating bonding layer 135 is formed on or above the interlayer insulating layer 125 and the interconnects 126. A second bonding pad 136 is formed in the second insulating bonding layer 135. The upper surfaces of the second insulating bonding layer 135 and the second bonding pad 136 are exposed and formed in substantially the same plane.

[0062] The interconnect 126 is in direct contact with the bit plug DP. The interconnect 126 may include a vertical interconnect in the third direction VD and / or a horizontal interconnect in the first direction FD. In an embodiment, the interconnect 126 includes a bit line. The second bonding pad 136 is electrically connected to the bit plug DP through the interconnect 126.

[0063] Each of the interlayer insulating layer 125 and the second insulating bonding layer 135 may be a single layer or a multi-layer. Each of the interlayer insulating layer 125 and the second insulating bonding layer 135 may include at least two selected from the group consisting of Si, O, N, C, and B. Each of the interlayer insulating layer 125 and the second insulating bonding layer 135 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), a low-k dielectric, a high-k dielectric, or a combination thereof. In an embodiment, the second insulating bonding layer 135 includes silicon carbonitride (SiCN).

[0064] Each of the interconnect 126 and the second bonding pad 136 may be a single layer or a multi-layer. Each of the interconnect 126 and the second bonding pad 136 may include a conductive material such as a metal, a metal nitride, a metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the interconnect 126 and the second bonding pad 136 may include a conductive material such as Cu, Al, Ni, Co, Ru, W, WN, Ti, TiN, Ta, TaN, Sn, Pt, Au, Ag, or a combination thereof. In an embodiment, the second bonding pad 136 includes a Cu layer formed using an electroplating method.

[0065] Refer to Figure 9 and Figure 16 The second substrate 51 including the stacked structure ST is bonded B930 to the first substrate 21 including the circuit structure CS. The second insulating bonding layer 135 faces the first insulating bonding layer 35, and each second bonding pad 136 faces each first bonding pad 36. The first substrate 21 and the second substrate 51 may be formed on separate semiconductor wafers.

[0066] Refer toFigure 9 and Figure 17 The second insulating bonding layer 135 is bonded to the first insulating bonding layer 35. The second bonding pad 136 is bonded to the first bonding pad 36. The first slit sacrificial layer 59 and the channel structure CH are exposed by removing the second substrate 51. The channel pattern CP is exposed by removing the uppermost portion of the information storage pattern DSL.

[0067] Referring to Figure 9 and Figure 18 A source line 142 of B940 is formed on the stacked structure ST. The source line 142 is in direct contact with the channel pattern CP. The first slit sacrificial layer 59 extends into the source line 142 in the third direction VD.

[0068] The source line 142 can be single-layer or multi-layer. The source line 142 may include a conductive material such as polysilicon, metal, metal silicide, metal nitride, or a combination thereof. In an embodiment, the source line 142 may include a semiconductor material such as polysilicon.

[0069] Referring to Figure 9 and Figure 19 By patterning the source line 142, an upper slit 157 that is open, joined, or adjacent to the first lower slit 57 is formed. The first slit sacrificial layer 59 is exposed in the upper slit 157. As Figures 2 to 6 shown, the upper slit 157 can be formed to have various depths and shapes.

[0070] In an embodiment, as Figure 19 shown, the bottom of the upper slit 157 is formed at a height that is lower than the height of the uppermost end of the first slit sacrificial layer 59 in the third direction VD. The bottom of the upper slit 157 can be formed at a height that is lower than the height of the uppermost surface of the channel structure CH in the third direction VD. The bottom of the upper slit 157 can be formed at the same horizontal height as the height of the uppermost surface of the channel structure CH. The bottom of the upper slit 157 can be formed at a height that is higher than the height of the uppermost end of the plurality of first sacrificial layers 54 in the third direction VD. The bottom of the upper slit 157 can be formed at a height that is higher than the height of the upper surface of the stacked structure ST in the third direction VD. The bottom of the upper slit 157 can be formed at a height that is higher than the height of the lowermost end of the source line 142 in the third direction VD.

[0071] Referring to Figure 9 and Figure 20 The upper slit 157 extends in the second direction SD within the source line 142. In a plan view including the first direction FD and the second direction SD, when the measurement of the upper slit 157 in the second direction SD is compared with the measurement of the upper slit 157 in the first direction FD, the aspect ratio of the upper slit 157 can be from 100 times to 1e+100 times.

[0072] Reference Figure 9 and Figure 21 When the first slit sacrificial layer 59, the second slit sacrificial layer 69, and the third slit sacrificial layer 79 are removed, a B950 lower slit 157L is formed, which includes a first lower slit 57, a second lower slit 67, and a third lower slit 77 that are open, joined, or adjacent to the upper slit 157. For example, an etching process can be used to remove the sacrificial layers 59, 69, and 79.

[0073] Reference Figure 9 、 Figure 22 and Figure 25 In an embodiment, the first lower slit 57, the second lower slit 67, and the third lower slit 77 are radially expanded. The first lower slit 57, the second lower slit 67, and the third lower slit 77 form the lower slit 157L. The upper slit 157 and the lower slit 157L form the slit 157SLT. The lower slit 157L is open, joined, or adjacent to the upper slit 157. As Figure 12 shown, a plurality of first lower slits 57 aligned in the second direction SD are open, joined, or adjacent to each other after performing lateral expansion (including expansion in the first direction FD and the second direction SD or expansion in the radial direction). For example, an etching process can be used to expand the plurality of first lower slits 57. Before expansion, Figure 22 and Figure 25 The dashed lines in

[0074] show the shapes of the lower slits 57, 67, and 77, and the solid lines show the shapes of the lower slits 57, 67, and 77 after expansion. The plurality of second lower slits 67 and the plurality of third lower slits 77 can be expanded using a method similar to the method used to expand the first lower slits 57, and are open, joined, or adjacent to each other in the second direction SD.

[0075] The slit 157SLT extends completely through the source line 142 and the stacked structure ST in the third direction VD. The edges of each of the plurality of first sacrificial layers 54, the plurality of second sacrificial layers 64, and the plurality of third sacrificial layers 74 are exposed in the lower slit 157L. Figure 9 Figure 23 Reference

[0076] Figure 9 Reference Figure 9 and Figure 24, a plurality of horizontal electrodes 155, 165, and 175 are formed in a plurality of gap regions 54G, 64G, and 74G. The plurality of horizontal electrodes 155, 165, and 175 include a plurality of first horizontal electrodes 155, a plurality of second horizontal electrodes 165, and a plurality of third horizontal electrodes 175.

[0077] Each of the plurality of horizontal electrodes 155, 165, and 175 can be single-layer or multi-layer. The plurality of horizontal electrodes 155, 165, and 175 may include a conductive material such as metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. The plurality of horizontal electrodes 155, 165, and 175 may include a conductive material such as W, WN, Ti, TiN, Ta, TaN, Ru, or a combination thereof. In an embodiment, the plurality of horizontal electrodes 155, 165, and 175 includes W.

[0078] Referring to Figure 9 and Figure 25 , the lower slit 157L extends in the second direction SD. In a plan view including the first direction FD and the second direction SD, a measurement of the upper slit 157 in the second direction SD is compared with a measurement of the upper slit 157 in the first direction FD, and the aspect ratio of the lower slit 157L can be from 100 times to 1e+100 times. The sidewalls of the lower slit 157L may have a wavy shape in the second direction SD.

[0079] Referring to Figure 9 and Figure 1 , an isolation insulating pattern 250 is formed in the slit 157SLT. The upper surface of the source line 142 and the upper surface of the isolation insulating pattern 250 are formed in substantially the same plane. The isolation insulating pattern 250 includes an upper section 250U and a lower section 250L. The lower section 250L is adjacent to the upper section 250U in the third direction VD. The lower section 250L may include a first lower section 250L1, a second lower section 250L2, and a third lower section 250L3.

[0080] The isolation insulating pattern 250 can be single-layer or multi-layer. The isolation insulating pattern 250 may include a material containing at least two selected from the group consisting of Si, O, N, C, and B. The isolation insulating pattern 250 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), low-k dielectric, high-k dielectric, or a combination thereof.

[0081] According to an embodiment of the disclosed technology, a stacked structure ST is bonded B930 to a circuit structure CS, and after removing sacrificial layers 54, 64, and 74 in the stacked structure ST, B960 horizontal electrodes 155, 165, and 175 are formed. When forming the horizontal electrodes 155, 165, and 175 after bonding the stacked structure ST to the circuit structure CS, physical deformations such as warping can be relatively reduced in the stacked structure ST by utilizing the sacrificial layers 54, 64, and 74 and the second substrate 51. When the warping is reduced, bonding defects can also be reduced. Since the bonding B930 of the stacked structure ST formed on the second substrate 51 to the circuit structure CS formed on the first substrate 21 is performed before forming the B960 horizontal electrodes 155, 165, and 175, the coupling strength of the first insulating bonding layer 35 and the second insulating bonding layer 135 can be increased, and the coupling strength of the first bonding pad 36 and the second bonding pad 136 can also be increased.

[0082] Although exemplary embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the drawings should be considered only in a descriptive sense and not for limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the drawings. All changes within the meaning and equivalent scope of the claims are included within its scope.

[0083] Cross - reference to related applications

[0084] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0181003, filed with the Korean Intellectual Property Office on December 13, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Circuit structure; a stacked structure bonded to the circuit structure and comprising a plurality of molded layers alternately stacked with a plurality of electrodes; A source line, the source line is arranged on the stacked structure; a channel structure extending through the stacked structure into the source line; as well as an isolation insulating pattern disposed in a slit extending through the source line and the stacked structure, Wherein, the isolation insulating pattern includes a first section adjacent to the source line and a second section adjacent to the stacked structure; wherein the isolation insulating pattern comprises a convergent interface between the first segment and the second segment; and The convergence interface is arranged between an end portion of the channel structure arranged in the source line and a surface of the plurality of electrodes closest to the source line.

2. The semiconductor device according to claim 1, wherein A surface of the isolation insulating pattern and a surface of the source line are formed in substantially the same plane.

3. The semiconductor device according to claim 1, wherein The converging interface is disposed between the end of the channel structure and a first molded layer of the plurality of molded layers, wherein the first molded layer is closer to the source line than any other molded layer of the plurality of molded layers.

4. The semiconductor device according to claim 1, wherein A width of the first section of the isolation insulation pattern is different from a width of the second section where the first section is adjacent to the second section, and the converging interface includes a step.

5. The semiconductor device according to claim 1, wherein A slope of a side surface of the first section of the isolation insulation pattern is different from a slope of a side surface of the second section of the isolation insulation pattern.

6. The semiconductor device according to claim 1, in, The first section of the isolation insulating pattern has an inverted trapezoidal shape, and Wherein, the second section of the isolation insulating pattern has a trapezoidal shape.

7. The semiconductor device according to claim 1, further comprising: a first insulating bonding layer, the first insulating bonding layer being disposed on the circuit structure; a first bonding pad, the first bonding pad being located in the first insulating bonding layer; a second insulating bonding layer disposed between the first insulating bonding layer and the stacked structure and bonded to the first insulating bonding layer; as well as A second bonding pad is disposed in the second insulating bonding layer and bonded to the first bonding pad.

8. The semiconductor device according to claim 7, further comprising: an interlayer insulating layer, the interlayer insulating layer being located between the first insulating bonding layer and the stacked structure; as well as An interconnection is disposed in the interlayer insulating layer and connected to the channel structure.

9. The semiconductor device according to claim 8, wherein: The second section of the isolation insulation pattern extends into the interlayer insulation layer.

10. The semiconductor device according to claim 8, wherein The channel structure comprises: a channel pattern connected to the source line; and a bit plug contacting the channel pattern, Wherein, the interconnection member contacts the bit plug at a first height.

11. The semiconductor device according to claim 10, wherein The interconnector has a first surface at the first height and a second surface at a second height and opposite to the first surface, and wherein an end portion of the isolation insulating pattern is disposed between the first height and the second height.

12. The semiconductor device according to claim 10, in, The channel structure further includes a core layer extending through the stacked structure into the source line, wherein the channel pattern surrounds the side surface and the end of the core layer, and Wherein, the channel pattern directly contacts the source line.

13. The semiconductor device according to claim 10, in, The channel structure further includes an information storage pattern located between the channel pattern and the stacked structure, and Wherein, an end portion of the information storage pattern contacts the source line.

14. The semiconductor device according to claim 13, wherein: The information storage pattern comprises: a tunnel layer, the tunnel layer being located on the channel pattern; a charge trapping layer disposed on the tunneling layer; and a blocking layer, the blocking layer being located on the charge trapping layer; Wherein, the charge capture layer is arranged between the tunnel layer and the blocking layer.

15. A semiconductor device, comprising: a stacked structure including a plurality of molded layers alternately stacked with a plurality of electrodes; A source line, the source line is arranged on the stacked structure; a channel structure extending through the stacked structure into the source line; as well as an isolation insulating pattern disposed in a slit extending through the source line and the stacked structure, Wherein, the isolation insulating pattern includes a first section adjacent to the source line and a second section adjacent to the stacked structure; wherein a side surface of the isolation insulating pattern includes a convergence interface between the first segment and the second segment; and The convergence interface is arranged between an end portion of the channel structure arranged in the source line and a surface of the plurality of electrodes closest to the source line.

16. The semiconductor device according to claim 15, wherein The plurality of electrodes include: at least one source selection line, the at least one source selection line being closest to the source line; at least one drain select line, the at least one drain select line being closest to the bit plug; and A plurality of word lines are located between the at least one source select line and the at least one drain select line.

17. The semiconductor device according to claim 15, further comprising: an interlayer insulating layer, the interlayer insulating layer being located between the substrate and the stacked structure; as well as An interconnection is disposed in the interlayer insulating layer and connected to the channel structure.

18. The semiconductor device according to claim 17, wherein: The channel structure comprises: a channel pattern connected to the source line; an information storage pattern, the information storage pattern being located between the channel pattern and the stacked structure; and a bit plug contacting the channel pattern; Wherein, the interconnection member contacts the bit plug.

19. The semiconductor device according to claim 18, wherein: End portions of the isolation insulating patterns are disposed within the interlayer insulating layer.

20. The semiconductor device according to claim 18, wherein The information storage pattern comprises: a tunnel layer, the tunnel layer being located on the channel pattern; a charge trapping layer disposed on the tunneling layer; and a blocking layer, the blocking layer being located on the charge trapping layer; Wherein, the charge capture layer is arranged between the tunnel layer and the blocking layer.

21. A method of forming a semiconductor device, the method comprising the steps of: bonding a stacked structure to a circuit structure, the stacked structure comprising a plurality of molding layers alternately stacked with a plurality of sacrificial layers; After bonding the stacked structure to the circuit structure, removing the plurality of sacrificial layers in the stacked structure and forming a plurality of electrodes; as well as An isolation insulating pattern is formed in a slit extending through the stack structure.

22. A method of forming a semiconductor device, the method comprising the steps of: bonding a stacked structure to a circuit structure, the stacked structure comprising a plurality of molding layers alternately stacked with a plurality of sacrificial layers; forming a source line on the stacked structure; forming a channel structure extending through the stacked structure into the source line; as well as forming an isolation insulating pattern in a slit extending through the source line and the stacked structure; Wherein, the isolation insulating pattern includes a first section adjacent to the source line and a second section adjacent to the stacked structure; wherein the isolation insulating pattern comprises a convergent interface between the first segment and the second segment; and The convergence interface is formed between an end of the channel structure disposed in the source line and a surface of the plurality of electrodes closest to the source line.

23. A semiconductor device, comprising: a stacked structure formed on a first semiconductor wafer and including a plurality of insulating layers alternately stacked with a plurality of electrodes replacing the plurality of sacrificial layers; a circuit structure formed on a second wafer and bonded to the stacked structure before forming the plurality of electrodes; a source line, the source line being disposed on the stacked structure, wherein a first insulating layer among the plurality of insulating layers is closest to the source line; a channel structure extending through the stacked structure into the source line, wherein an end of the channel structure extends into the source line; and An isolation insulating pattern is arranged in a slit extending through the source line and the stacked structure, wherein the isolation insulating pattern includes a convergence interface between a first segment adjacent to the source line and a second segment adjacent to the stacked structure, and wherein the convergence interface is arranged at a height within the source line and one of the first insulating layers.

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