Embedded storage structure, resistive random access memory and preparation method of resistive random access memory

Abstract

The invention discloses an embedded storage structure, a resistive random access memory and a preparation method of the resistive random access memory, and belongs to the field of semiconductors. The preparation method comprises the following steps: firstly, preparing a first intermetallic dielectric layer on an interlayer dielectric layer of a first semiconductor structure; preparing a first metal circuit and a first electrode plate in the first intermetallic dielectric layer; continuously preparing a first barrier layer; opening the first intermetallic dielectric in the region on one side of the first electrode plate by adopting an etching process to form a first groove; sequentially depositing a resistive material and a conductive metal material; and flattening and staying on the first barrier layer to obtain the embedded storage structure. The resistive random access memory unit for changing the orientation of the electrode plate is prepared through a brand new process sequence, and the resistive random access memory is prepared through the structure, so that the whole resistive random access memory is compact, and the resistive random access memory can also be compatible with an MOS (Metal Oxide Semiconductor) manufacturing process in the prior art. Through simulation verification, the method is high in reliability and operability and high in manufacturing yield.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, relates to a resistive random access memory technology, and particularly relates to an embedded storage structure, a resistive random access memory, and a manufacturing method thereof. Background Art

[0002] A resistive random access memory (RRAM) is a non-volatile memory. The resistive random access memory cell is the core of the resistive random access memory technology. It usually adopts a structure similar to a parallel plate capacitor, that is, a sandwich structure formed by stacking a top electrode (TE), a switch layer, and a bottom electrode (BE) in the wafer thickness direction. Among them, the upper and lower electrodes are conductive metals, and the switch layer is usually a transition metal oxide; by applying an external electric field, a conductive filament channel based on oxygen vacancies is induced to form in the oxide switch layer. Under the excitation of the external electric field, the switch layer can reversibly transition between high and low resistance states, and its high and low resistance states can still be maintained after the external electric field is removed; specifically in use, the forming process refers to the process in which the RRAM first jumps from the initial high resistance state to the low resistance state. On the contrary, the RRAM in the low resistance state can be converted to the high resistance state after being applied with a certain voltage excitation. The process of the low resistance state jumping to the high resistance state is called Reset. The RRAM that enters the high resistance state after the Reset process can also be converted to the low resistance state by applying a voltage excitation, and this process is different from the first high resistance state jumping to the low resistance state, and is called the Set process.

[0003] In terms of process implementation, this sandwich structure can usually be directly embedded in the back-end of line (BEOL) to form between two metal layers. Although it can be directly compatible with the existing manufacturing process, the development of the RRAM structure needs to be re-embedded in the process development, and it will make the inter-metal dielectric (IMD) between the two metal layers thicker. The vias in the corresponding interconnect structure cannot reuse the existing process and new processes need to be developed, which invisibly causes the process cycle and cost of secondary development.

[0004] Therefore, it is necessary to improve and research the structure of the resistive random access memory cell to reduce costs, improve structural compactness and yield on the basis of being compatible with the existing CMOS process. Summary of the Invention

[0005] One of the purposes of the present invention is to provide an embedded storage structure, which retains the advantages of the RRAM while reducing the design and manufacturing costs.

[0006] Another object of the present invention is to provide a method for preparing an embedded memory structure, which can fabricate the above-mentioned embedded memory structure with high quality in a low-cost manner, so as to shorten the product development cycle, reduce costs and improve competitiveness.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is as follows: A method for preparing an embedded memory structure, comprising the following steps: Providing a first semiconductor structure, on which an interlayer dielectric layer is provided; Preparing a first inter-metal dielectric layer on the interlayer dielectric layer; Preparing a first metal line and a first electrode plate in the first inter-metal dielectric layer; Preparing a first barrier layer on the first metal interconnect layer; Using an etching process to open the first inter-metal dielectric on one side area of the first electrode plate to form a first groove; Filling the first groove with a resistive switching material; Depositing a conductive metal material on the resistive switching material until the first groove is filled; Using the first barrier layer as a stop layer, performing a planarization process on the resistive switching material and the conductive metal material and stopping on the first barrier layer to obtain a second electrode plate and a resistive switching layer. The first electrode plate and the adjacent resistive switching layer and the second electrode plate constitute a resistive switching unit.

[0008] Further, preparing the first inter-metal dielectric layer on the interlayer dielectric layer includes the following steps: Preparing a second barrier layer on the interlayer dielectric layer of the first semiconductor structure; Depositing an inter-metal dielectric material on the second barrier layer to form the first inter-metal dielectric layer.

[0009] Further, preparing the first metal line and the first electrode plate in the first inter-metal dielectric layer includes the following steps; Using an etching process to prepare a metal wire groove and a first electrode plate groove on the first inter-metal dielectric layer; Filling the metal wire groove and the first electrode plate groove with a conductive material and planarizing to obtain the first metal line and the first electrode plate.

[0010] Further, the thickness of the first electrode plate is 5 - 100 nm.

[0011] Further, the thickness of the resistive switching material deposited in the first groove is 3 - 30 nm.

[0012] Further, the resistive switching material filled in the first groove is a transition metal oxide or a lanthanide metal oxide or a metal oxide of Group IV, V, or VI of the periodic table.

[0013] Further, the first electrode plate and the second electrode plate are made of a metal conductive material or a metal nitride conductive material.

[0014] Further, a second metal interconnection layer is prepared on the first metal interconnection layer on which the resistive switching unit is prepared, and the electrode plates are led out by using the second metal interconnection layer.

[0015] Further, the second metal interconnection layer at least includes a second metal line, a first electrode lead, and a second electrode lead. The second metal line is used to conduct with the first metal line, and the first electrode lead and the second electrode lead lead out the first electrode plate and the second electrode plate respectively.

[0016] Further, by selecting the relative orientation of the first groove and the first electrode plate, the first electrode plates or the second electrode plates of two adjacent resistive switching units are arranged adjacent to each other.

[0017] On the other hand, the present invention provides an embedded memory structure prepared by the above preparation method.

[0018] On the other hand, the present invention provides a preparation method for an embedded memory structure, including the following steps: Provide a first semiconductor structure with an interlayer dielectric layer thereon; Successively prepare a plurality of metal interconnection layers on the interlayer dielectric layer; Prepare a metal interlayer dielectric layer on the topmost metal interconnection layer; Prepare a first metal line and a first electrode plate in the metal interlayer dielectric layer; Prepare a first barrier layer on the metal interlayer dielectric layer; Use an etching process to open the metal interlayer dielectric in the area on one side of the first electrode plate to form a first groove; Fill the resistive switching material in the first groove; Deposit a conductive metal material on the resistive switching material until the first groove is filled; Using the first barrier layer as a stop layer, perform a planarization process on the resistive switching material and the conductive metal material and stop on the first barrier layer to obtain a second electrode plate and a resistive switching layer. The first electrode plate and the adjacent resistive switching layer and the second electrode plate constitute a resistive switching unit.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: By changing the orientation of the electrode plates of the resistive random access memory (RRAM) cell, the present invention changes the stacked electrode plates in the prior art to be inserted vertically (in the direction perpendicular to the panel of the semiconductor substrate), obtaining a RRAM cell with a new structure. Together with the RRAM logic unit in the prior art, it can form a complete resistive random access memory. The unexpected technical effect is that it avoids the situation in the prior art where the existing process between two metal interconnection layers needs to be re-developed after inserting the RRAM cell, can be compatible with the MOS process in the prior art, and also makes the overall resistive random access memory compact. After simulation verification, the reliability and operability of the present invention have no obvious difference from those of the conventional technical solution stacked in the wafer thickness direction in the prior art, and the read and write speed is faster than that of the prior art under the same conditions.

[0020] The present invention creatively changes the preparation sequence of the electrode plates. First, the first electrode plate is inserted and fabricated, and then the second electrode plate and the resistive material are inserted together for fabrication. This solves the problem that it is difficult to control the lateral damage between the electrode plate and the resistive layer when etching and cutting off the electrode plate in the vertical direction during the separate deposition and etching processes of the resistive layer when embedding the resistive electrode plate in the parallel direction. In the fabrication method of the present invention, although the resistive material completely wraps the bottom and the periphery of the second electrode plate, the unexpected technical effect is that after verification, the present invention can still complete the preparation of the resistive cell with high quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of a common structure of RRAM in the prior art.

[0022] Figure 2 It is a schematic diagram of the RRAM cell of Embodiment 1 of the present invention embedded in the first metal interconnection layer.

[0023] Figure 3 It is a schematic diagram of the metal line wiring in the top view state of the second metal interconnection layer of Embodiment 1 of the present invention.

[0024] Figure 4 It is a schematic diagram of the third metal interconnection layer fabricated for the embedded storage structure in Embodiment 1.

[0025] Figure 5 It is a flowchart of fabricating an embedded storage structure in the first metal interconnection layer in Embodiment 2 of the present invention.

[0026] Figure 6 It is a schematic diagram of the first semiconductor structure provided in Embodiment 2 of the present invention.

[0027] Figure 7 It is a schematic diagram of fabricating the second barrier layer on the first semiconductor structure in Embodiment 2 of the present invention.

[0028] Figure 8Schematic diagram of preparing the first inter-metal dielectric layer on the second barrier layer in Embodiment 2 of the present invention.

[0029] Figure 9 Schematic diagram of grooving on the first inter-metal dielectric in Embodiment 2 of the present invention.

[0030] Figure 10 Schematic diagram of completing the preparation of the electrode plate in the first metal interconnect layer in Embodiment 2 of the present invention.

[0031] Figure 11 Schematic diagram of preparing the first barrier layer on the first metal interconnect layer in Embodiment 2 of the present invention.

[0032] Figure 12 Schematic diagram of coating a photoresist layer on the first barrier layer and completing the patterning of the photoresist layer in Embodiment 2 of the present invention.

[0033] Figure 13 Schematic diagram of opening the first groove on the first metal interconnect layer in Embodiment 2 of the present invention.

[0034] Figure 14 Schematic diagram of filling a resistive switching material in the first groove in Embodiment 2 of the present invention.

[0035] Figure 15 Schematic diagram of planarizing the filled resistive switching material to complete the preparation of the first metal interconnect layer in Embodiment 2 of the present invention.

[0036] Figure 16 Schematic diagram of preparing the second inter-metal dielectric layer on the first metal interconnect layer in Embodiment 2 of the present invention.

[0037] Figure 17 Flow chart of preparing an embedded memory structure in the second metal interconnect layer in Embodiment 3 of the present invention.

[0038] Figure 18 Schematic diagram of embedding a resistive switching memory cell in the second metal interconnect layer in Embodiment 3 of the present invention.

[0039] Figure 19 Schematic diagram of continuously preparing the fourth metal interconnect layer on the third metal interconnect layer in Embodiment 3 of the present invention.

[0040] 30 - RRAM cell, 30a - bottom electrode, 30b - resistive switching layer, 30c - top electrode, 30d - interlayer dielectric layer; 100 - first semiconductor structure; 110 - semiconductor substrate, 120 - STI structure, 130 - source electrode, 140 - drain electrode, 150 - gate electrode, 160 - interlayer dielectric layer, 170 - contact hole; 200 - The first metal interconnection layer, 210 - The second barrier layer, 220 - The first inter-metal dielectric layer, 230 - The first metal line, 231 - The first source lead, 232 - The first drain lead, 240 - The first groove, 241 - The first metal wire groove, 242 - The first plate groove; 300 - The resistive random access memory (RRAM) cell, 310 - The first electrode plate, 320 - The resistive change layer, 321 - The resistive change material, 330 - The second electrode plate; 340 - The photoresist layer, 331 - The conductive metal material; 400 - The second metal interconnection layer, 410 - The first barrier layer, 420 - The second inter-metal dielectric layer, 430 - The second metal line, 431 - The second source lead, 432 - The second drain lead, 440 - The first plate lead, 450 - The second plate lead; 500 - The third metal interconnection layer; 510 - The third metal line, 520 - The first plate lead, 530 - The second plate lead; 600 - The fourth metal interconnection layer, 610 - The fourth metal line. Detailed implementation manners

[0041] The following further describes the implementation manners of the present invention in detail with reference to the drawings and embodiments. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0042] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0043] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0044] As Figure 1 described, it is a common structure of RRAM in the prior art. Figure 1The first semiconductor structure 100 shown has a MOS unit, which includes an active region isolated on a semiconductor substrate 110 by two STI structures 120 (shallow trench isolation structures). An active electrode 130, a drain electrode 140, and a gate electrode 150 are arranged in the active region, where the gate electrode 150 is protected by an interlayer dielectric layer 160, and the source electrode 130 and the drain electrode 140 are led out through contact holes 170; above the interlayer dielectric layer 160 is a first metal interconnect layer 200, and a first metal line 230 for leading out the MOS unit is provided on the first metal interconnect layer 200. It should be noted that, Figure 1 This is only a schematic diagram for illustration. Multiple MOS units can be provided according to needs, and the connection and lead-out methods of the MOS units are not limited to the structure shown in the figure. For example, Figure 1 only the source lead and the drain lead are shown in the figure. In fact, there must be a gate lead. Above the first metal interconnect layer 200 is a second metal interconnect layer 400, and a second metal line 430 is provided in the second metal interconnect layer 400. The RRAM unit 30 is arranged between the first metal interconnect layer 200 and the second metal interconnect layer 400 and is wrapped by an interlayer dielectric layer 30d (IMD); the RRAM unit 30 includes a bottom electrode 30a, a resistive switching layer 30b, and a top electrode 30c stacked in the thickness direction on a barrier layer 20; the bottom electrode 30a is electrically connected to the first metal line 230 through a via; the top electrode 30c is electrically connected to the second metal line 430 through a via; in this structure, limited by the fact that the growth of the semiconductor structure is all deposition in the thickness direction, the RRAM units designed in the thickness direction are habitually used in the prior art, that is, the bottom electrode 30a, the resistive switching layer 30b, and the top electrode 30c are all flat structures and are parallel to the semiconductor substrate 110; in this way, RRAM unit design is required between the first metal interconnect layer 200 and the second metal interconnect layer 400, and the connection vias cannot reuse the existing processes, and new processes need to be developed, which invisibly causes the process cycle and cost of secondary development.

[0045] To solve the above problems, the present invention redesigned the RRAM unit and provides an embedded storage structure, which is prepared on a semiconductor structure, as Figures 2 to 4 shown, Figure 2 A semiconductor structure shown has a MOS unit, which includes an active region isolated on a semiconductor substrate 110 by two STI structures 120 (shallow trench isolation structures). An active electrode 130, a drain electrode 140, and a gate electrode 150 are arranged in the active region, where the gate electrode 150 is protected by an interlayer dielectric layer 160, and the source electrode 130 and the drain electrode 140 are led out through contact holes 170; above the interlayer dielectric layer 160 is a first metal interconnect layer 200, and a first metal line 230 for leading out the MOS unit is provided on the first metal interconnect layer 200. It should be noted that,Figure 2 For the purpose of illustration only, multiple MOS units can be set as needed, and the connection method of the leads of the MOS units is not limited to the structure shown in the figure. For example, Figure 2 only the source lead and the drain lead are shown in the figure, and in fact, there must be a gate lead.

[0046] In this embodiment, the resistive random access memory cell 300 is embedded in one of the metal interconnection layers. Taking the embedding into the first metal interconnection layer 200 as an example, as Figures 2 to 3 shown, the resistive random access memory cell 300 includes: A first electrode plate 310, which is perpendicular to the first metal interconnection layer 200; A second electrode plate 330, which is embedded in the first metal interconnection layer 200 parallel to and opposite the first electrode plate 310; and A resistive layer 320, which is embedded between the first electrode plate 310 and the second electrode plate 330.

[0047] By changing the orientation of the electrode plates of the resistive random access memory cell, the present invention changes the stacked electrode plates in the prior art to be inserted in the vertical direction, that is, the plane of the electrode plate is perpendicular to the panel direction of the semiconductor substrate 110 (or perpendicular to the plane direction of the metal interconnection layer), and a resistive random access memory cell 300 with a new structure is obtained. Together with the resistive logic unit in the prior art, it can form a complete resistive random access memory. The unexpected technical effect is that it avoids the situation where the existing process between two metal interconnection layers needs to be re-developed after inserting the resistive random access memory cell in the prior art, can be compatible with the MOS process in the prior art, and also makes the overall resistive random access memory compact. After simulation verification, the reliability and operability of the present invention have no obvious difference from the conventional technical solutions stacked in the wafer thickness direction in the prior art, and the read and write speed is faster than that of the prior art under the same conditions.

[0048] For the display of functional integrity, a first metal line 230 is also provided in the first metal interconnection layer 200. As Figure 2 shown, it includes at least a first source lead 231 and a first drain lead 232, which are respectively connected to the source 130 and the drain 140 of the MOS unit through contact holes 170; in order to electrically connect and lead out the resistive random access memory cell 300, a second metal line 430, a first plate lead 440 and a second plate lead 450 are provided in the second metal interconnection layer 400. The first plate lead 440 and the second plate lead 450 are respectively connected to the first electrode plate 310 and the second electrode plate 330 through through holes. The second metal line 430 includes a second source lead 431 and a second drain lead 432. The second source lead 431 and the second drain lead 432 are respectively connected to the first source lead 231 and the first drain lead 232 in the first metal interconnection layer 200 through through holes for leading out the MOS unit.

[0049] To completely lead out the electrode plates of the resistive random access memory (RRAM) cell 300, a third metal interconnection layer 500 needs to be fabricated. As shown in Figure 4 Figure [not provided], the third metal interconnection layer 500 includes third metal lines 510 that lead out the first electrode lead 440 and the second electrode lead 450 respectively, enabling circuit control of the RRAM cell 300.

[0050] The materials of the first electrode plate 310 and the second electrode plate 330 are metal conductive materials, metal nitride conductive materials, or similar conductive materials. The metal materials include at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitrides include nitrides formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. In one embodiment, the first electrode plate 310 and the second electrode plate 330 can be of different materials or the same materials. Preferably, both are made of TiN.

[0051] The material of the resistive layer 320 is a transition metal oxide, a lanthanide metal oxide, or a main group metal oxide of Groups IV, V, and VI. Specifically, TiO x , HfO x , AlO x , TaO x , and ZrO x and any other such materials can be used, which are well compatible with traditional CMOS processes.

[0052] In some embodiments, the areas and dimensions of the two electrode plates are the same, and the resistive layer 320 is just embedded between the two electrode plates. Taking the electrode plates as rectangular plates as an example, the corresponding resistive layer 320 is also a rectangular plate sandwiched between two rectangular plates.

[0053] In some embodiments, the thickness of the electrode plates is 5 - 100 nm, and the thickness of the resistive layer 320 is 3 - 30 nm. The thickness designs of both the electrode plates and the resistive layer 320 need to meet the design rules in the current metal interconnection layer.

[0054] In some embodiments, the area of the electrode plates is 100 - 20000 nm 2 ^2. The area designs of the electrode plates need to meet the design rules in the current metal interconnection layer. Under the premise of meeting the storage function, the smaller the area of the electrode plates, the better, in order to increase the density of the RRAM cells. Therefore, the preferred area range is 100 - 2000 nm 2 ^2.

[0055] In some embodiments, two adjacent resistive memory cells 300 can be arranged in a mirror symmetry, so that adjacent electrode plates can share a single lead wire for extraction. Refer to Figure 2 , in two adjacent resistive memory cells 300, two first electrode plates 310 are adjacent and share a first plate lead wire 440, which can save lead wires and simplify the design and manufacturing costs.

[0056] In the process of fabricating the above-mentioned embedded memory structure, the conventional process is to first fabricate two electrode plates on the metal interconnection layer to be inserted, and then insert a resistive layer between the two electrode plates. However, the applicant found a problem during the verification and use process. The thickness of the resistive layer is relatively thin, generally about 3 - 30 nm, and it has a certain depth, which makes it difficult to deposit metal conductive materials. For some conductive materials, it is easy to deposit incompletely and there are defects, thus affecting the reliability and storage / reading rate of the resistive cells. Therefore, the applicant has developed a new process to implement this structure.

[0057] Embodiment 2: As Figure 5 shown, this embodiment provides a method for fabricating an embedded memory structure, including the following steps: S100. Provide a first semiconductor structure with an interlayer dielectric layer on it; S200. Fabricate a first intermetal dielectric layer on the interlayer dielectric layer; S300. Fabricate a first metal line and a first electrode plate in the first intermetal dielectric layer; S400. Fabricate a first barrier layer on the first intermetal dielectric layer; S500. Use an etching process to open the first intermetal dielectric in the area on one side of the first electrode plate to form a first groove; S600. Fill the first groove with a resistive material; S700. Deposit a conductive metal material on the resistive material until the first groove is filled; S800. Using the first barrier layer as a stop layer, use a planarization process to planarize the resistive material and the conductive metal material and stop on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and second electrode plate form a resistive cell.

[0058] The present invention creatively changes the preparation sequence of the electrode plates. First, the first electrode plate 310 is inserted and fabricated, and then the second electrode plate and the resistive change material are inserted together for fabrication, solving the problem that it is difficult to control the lateral damage between the electrode plate and the resistive change layer when the resistive change electrode plate is embedded in the parallel direction and the resistive change layer is etched vertically during the separate deposition and etching processes. In the fabrication method of the present invention, although the resistive change material completely wraps the bottom and the periphery of the second electrode plate, an unexpected technical effect is that, after verification, the present invention can still complete the preparation of the resistive change unit with high quality.

[0059] In S100, a first semiconductor structure 100 is provided. As Figure 6 shown, a MOS unit is schematically shown on the first semiconductor structure 100. The MOS unit includes active regions isolated by two STI structures 120. An active electrode, a drain electrode, and a gate electrode are respectively fabricated in the active regions. The gate electrode is encapsulated by an interlayer dielectric layer 160. Contact holes 170 for leading out the source electrode 130 and the drain electrode 140 are provided on the interlayer dielectric layer 160. It should be emphasized that the first semiconductor structure 100 is only a schematic diagram, and different designs are actually made according to the application scenario requirements, which does not affect the present invention from solving the technical problems.

[0060] S200. A first intermetal dielectric layer 220 is fabricated on the interlayer dielectric layer 160. The fabrication method is as follows: S210. A second barrier layer 210 is fabricated on the interlayer dielectric layer 160 of the first semiconductor structure 100, as Figure 7 shown; Specifically, it can be formed by physical vapor deposition or chemical vapor deposition. The material of the second barrier layer 210 is a silicon carbide (SiC) layer, a silicon oxynitride (SiON) layer, a silicon carbonitride (SiCN), etc., preferably silicon carbonitride (SiCN).

[0061] In step S220, a first intermetal dielectric layer 220 is fabricated on the second barrier layer 210, as Figure 8 shown; The material of the first intermetal dielectric layer 220 includes oxides formed by tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), organosilicate glass (OSG), SiOC) and / or any suitable low-k dielectric material (for example, a material having a dielectric constant lower than that of silicon dioxide), and can be deposited by spin coating, CVD, FCVD, PECVD, PVD, or any suitable deposition technique.

[0062] In S300, preparing the first metal line 230 and the first electrode plate 310 in the first inter-metal dielectric layer 220 includes the following steps: S310: Coating a photoresist on the first inter-metal dielectric layer 220; S320: Patterning the photoresist using an exposure and development technique; S330: Using the second barrier layer 210 as an etch stop layer, etching by dry etching (Dry ETCH), wet etching process (WET ETCH) or a combination of both processes, preferably dry etching process, and then removing the residues by wet cleaning; opening a first metal wire groove 241 and a first electrode plate groove 242 in the first inter-metal dielectric layer 220; S340: Removing the photoresist using a wet cleaning process to obtain the first metal wire groove 241 and the first electrode plate groove 242, as Figure 9 shown.

[0063] S350: Filling the first metal wire groove 241 and the first electrode plate groove 242 with a conductive material and planarizing to complete the preparation of the first metal line 230 and the first electrode plate 310, as Figure 10 shown; the conductive material is a metal conductive material or a metal nitride conductive material, and the metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, Ge. The metal nitride includes a nitride formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, Ge, such as TiN. The thickness of the electrode plate is 5 - 100 nm, and the area is 100 - 20000 nm 2 . For the electrode plate, generally there is no special requirement for the thickness, as long as the electrical performance and process requirements are met. The area of the electrode plate should be such that it can apply enough voltage to generate high and low resistance conversion.

[0064] S400: Preparing a first barrier layer 410 on the first inter-metal dielectric layer 220, as Figure 11 shown; the function of the first barrier layer 410 is to isolate between the first electrode plate 310, the second electrode plate 330 and the second metal interconnection layer 400. The preparation process can use physical vapor deposition or chemical vapor deposition method, and the material is a silicon carbide (SiC) layer, a silicon oxynitride (SiON) layer, a silicon carbonitride (SiCN), etc., preferably silicon carbonitride (SiCN); the thickness of the first barrier layer 410 is thicker than that in the prior art for grinding and polishing consumption during the subsequent preparation of the resistive change layer 320, generally 100 - 200 nm, so that after consumption, it is approximately the same as the thickness of the barrier layer in the prior art.

[0065] S500. Open the first inter-metal dielectric layer 220 in the area on one side of the first electrode plate 310 ( Figure 13 the left side of the left first electrode plate 310 and the right side of the right first electrode plate 310) to form the first groove 240, as Figure 13 shown; including the following steps: S510. Coat a photoresist layer 340 on the first barrier layer 410, and use the exposure and development technology to open the photoresist layer 340 above the left area of the left first electrode plate 310 and the photoresist layer 340 above the right area of the right first electrode plate 310, as Figure 12 shown; S620. Use the second barrier layer 210 as the stop layer to etch and form the first groove 240; the etching process uses dry etching with high selectivity, wet etching or atomic layer etching; preferably, dry etching and wet etching are alternately performed, or a plasma dry etching process can also be used. Through plasma (such as Cl 2 , HBr, CF 4 and other gases) to generate active free radicals and ions, and under the action of an electric field, bombard the wafer surface directionally to achieve anisotropic (vertical) etching to avoid damaging the first electrode plate 310 during the etching process.

[0066] S530. Remove the photoresist material through wet cleaning to complete the opening of the first groove 240, as Figure 13 shown. Wet cleaning can efficiently remove the particulate matter or impurities remaining in the first groove 240, preventing impurities from generating voids or defects during the subsequent filling of the resistive switching material 321, thereby affecting the reliability of the resistive switching memory cell 300.

[0067] In S600, fill the resistive switching material 321 in the first groove 240, as Figure 14 shown; the resistive switching material 321 is a transition metal oxide, a lanthanide metal oxide, or a metal oxide of the IV, V, and VI main groups. Specifically, TiO x , HfO x , AlO x , TaO x and ZrO x and any one of other materials can be preferably selected. After selecting the resistive switching material 321, select the corresponding filling process for filling; the present invention can fill a single resistive switching material or a composite resistive switching material as long as the RRAM cell function can be completed.

[0068] The thickness of the resistive switching layer 320 is 3 - 30 nm. Generally, there are no special requirements for the thickness, as long as it can generate high and low resistance conversions when a voltage is applied through the electrode plate, and this conversion can stably exist under voltage control. It should be noted that since the present invention changes the distribution direction of the electrode plate and the resistive switching layer 320, and the thickness of the resistive switching layer 320 is only 3 - 30 nm, which is relatively narrow, and the depth is relatively deep during filling, therefore, a resistive switching material 321 with small particles and high filling efficiency should be preferably selected to obtain a resistive switching layer 320 with good performance.

[0069] In S700, a conductive metal material is deposited on the resistive switching material until the first groove is filled, as Figure 15 shown; the conductive material is a metal conductive material or a metal nitride conductive material. The metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a nitride formed by at least one metal selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge, such as TiN.

[0070] In S800, planarization is performed using the CMP process. After planarization, the first electrode plate 310, the adjacent resistive switching layer 320, and the second electrode plate 330 form a resistive switching unit.

[0071] On the planarized first metal interconnection layer 200, a second metal interconnection layer 400 is continuously prepared, and the electrode plates of the resistive switching unit can be led out, as Figure 2 shown; on the second metal interconnection layer 400, a third metal interconnection layer 500 is prepared, and the first electrode plate 310 and the second electrode plate 330 of the resistive switching unit can be respectively led out.

[0072] Example 3: In this example, a resistive switching unit is prepared on the second metal interconnection layer, as Figure 17 shown, and it includes the following steps: S100: Provide a first semiconductor structure with an interlayer dielectric layer on it; S200: Sequentially prepare a first metal interconnection layer on the interlayer dielectric layer; S300: Prepare a second metal interlayer dielectric layer on the first metal interconnection layer; S400: Prepare a second metal line and a first electrode plate in the second metal interlayer dielectric layer to obtain a second metal interconnection layer; S500: Prepare a first barrier layer on the second metal interlayer dielectric layer; S600: Use an etching process to open the first metal interlayer dielectric layer in the area on one side of the first electrode plate to form a first groove; S700, Fill the resistive switching material in the first groove; S800, Deposit a conductive metal material on the resistive switching material until the first groove is filled; S900, Using the first barrier layer as a stop layer, perform planarization on the resistive switching material and the conductive metal material by a planarization process and stop on the first barrier layer to obtain a second electrode plate and a resistive switching layer. The first electrode plate and the adjacent resistive switching layer and the second electrode plate form a resistive switching unit.

[0073] Continue to fabricate a third metal interconnection layer 500 on the planarized second metal interconnection layer 400, and then the electrode plates of the resistive switching unit can be led out. The structure is as Figure 18 shown; in this embodiment, the third metal interconnection layer 500 includes a third metal line 510, a first electrode plate lead 520, and a second electrode plate lead 530. The interconnection between metal layers is realized through the third metal line 510, and the leads-out of the first electrode plate 310 and the second electrode plate 330 are realized through the first electrode plate lead 520 and the second electrode plate lead 530; and at least a fourth metal interconnection layer 600 needs to be fabricated. The fourth metal interconnection layer 600 has a fourth metal line 610 to form a complete circuit control for a single resistive switching memory cell 300, as Figure 19 shown.

[0074] It should be noted that the resistive switching unit can be fabricated on the third metal interconnection layer or the fourth metal interconnection layer. The present invention will not elaborate on this one by one.

[0075] The above embodiments are only used to illustrate the present invention, rather than to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that various combinations, modifications or equivalent replacements of the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and should all be covered within the scope of the claims of the present invention.

Claims

1. A method for preparing an embedded storage structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; forming a first intermetallic dielectric layer on the interlayer dielectric layer; Preparing a first metal circuit and a first electrode plate in a first intermetallic dielectric layer; forming a first barrier layer on the first intermetallic dielectric layer; Using an etching process to open the first intermetallic dielectric in a region on one side of the first electrode plate to form a first groove; Filling the first groove with a resistive material; Depositing a conductive metal material on the resistive material until the first groove is filled; The first barrier layer is used as a stop layer, and a planarization process is used to planarize the resistive material and the conductive metal material and keep them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit.

2. The method for preparing the embedded storage structure according to claim 1, characterized in that: Preparing a first intermetallic dielectric layer on the interlayer dielectric layer comprises the following steps: preparing a second barrier layer on the interlayer dielectric layer of the first semiconductor structure; An intermetallic dielectric material is deposited on the second barrier layer to form a first intermetallic dielectric layer.

3. The method for preparing the embedded storage structure according to claim 2, characterized in that: preparing a first metal circuit and a first electrode plate in a first intermetallic dielectric layer, The steps include: Using an etching process to prepare a metal line groove and a first electrode plate groove on the first intermetallic dielectric layer; Conductive material is filled in the metal line groove and the first electrode plate groove and planarized to obtain a first metal line and a first electrode plate.

4. The method for preparing the embedded storage structure according to claim 2, characterized in that: The resistive material filled in the first groove is transition metal oxide, lanthanide metal oxide, or IV, V, VI main group metal oxide.

5. The method for preparing the embedded storage structure according to claim 2, characterized in that: The first electrode plate and the second electrode plate are made of metal conductive material or metal nitride conductive material.

6. The method for preparing the embedded storage structure according to claim 2, characterized in that: A second metal interconnection layer is prepared on the first metal interconnection layer on which the resistive switching unit is prepared, and the electrode plate is led out by using the second metal interconnection layer.

7. The method for preparing the embedded storage structure according to claim 6, characterized in that: The second metal interconnection layer at least includes a second metal circuit, a first electrode plate lead and a second electrode plate lead, the second metal circuit is used to conduct with the first metal circuit, and the first electrode plate lead and the second electrode plate lead lead out the first electrode plate and the second electrode plate respectively.

8. The method for preparing the embedded storage structure according to claim 2, characterized in that: By selecting the relative positions of the first groove and the first electrode plate, the first electrode plates or the second electrode plates of two adjacent resistive switching units are arranged adjacent to each other.

9. An embedded storage structure, characterized in that: It is prepared by the preparation method according to any one of claims 1 to 8.

10. A method for preparing an embedded storage structure, characterized in that: The following steps are involved: Providing a first semiconductor structure, wherein the first semiconductor structure has an interlayer dielectric layer; sequentially preparing a plurality of metal interconnection layers on the interlayer dielectric layer; forming an intermetallic dielectric layer on the topmost metal interconnect layer; preparing a first metal circuit and a first electrode plate in the intermetallic dielectric layer; forming a first barrier layer on the intermetallic dielectric layer; An etching process is used to open the intermetallic dielectric in a region on one side of the first electrode plate to form a first groove; Filling the first groove with a resistive material; Depositing a conductive metal material on the resistive material until the first groove is filled; The first barrier layer is used as a stop layer, and a planarization process is used to planarize the resistive material and the conductive metal material and keep them on the first barrier layer to obtain a second electrode plate and a resistive layer. The first electrode plate and the adjacent resistive layer and the second electrode plate constitute a resistive unit.

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