Capacitor, preparation method of capacitor and semiconductor device

Abstract

The invention provides a capacitor, a preparation method of the capacitor and a semiconductor device. The capacitor comprises a substrate, a first dielectric layer, a conductive plug, a bottom electrode, a top electrode and a top electrode filling layer, the top electrode wraps the bottom electrode, and a second dielectric layer is arranged between the bottom electrode and the top electrode; the top electrode includes a titanium silicon nitride layer. According to the capacitor provided by the invention, the probability of deformation such as bending of the capacitor is reduced by improving the oxidation resistance of the top electrode, so that the reliability and stability of a semiconductor device are improved.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor devices and their manufacturing, and particularly relates to a capacitor, a method for manufacturing a capacitor, and a semiconductor device. Background Art

[0002] Dynamic random access memory (DRAM) is a volatile, capacitor-based, destructive read form of semiconductor memory. It currently occupies more than 50% of the memory market size.

[0003] The memory cell of dynamic random access memory (DRAM) is made of a single transistor and a single capacitor. When writing, the transistor is turned on, and charge is pushed into the capacitor (1) or removed from the capacitor (0); when reading, the charge is extracted and measured.

[0004] Existing capacitors have technical defects such as low reliability and poor stability. Summary of the Invention

[0005] The technical objective of this application is to at least solve the technical problems of low reliability and poor stability existing in the memory cells of existing dynamic random access memories. For this purpose, this application provides a capacitor, a method for manufacturing a capacitor, and a semiconductor device. The capacitor provided by this application improves the antioxidant ability of the top electrode to reduce the probability of deformation such as bending of the capacitor, thereby improving the reliability and stability of the semiconductor device.

[0006] The first aspect of this application is to provide a capacitor, comprising:

[0007] A substrate;

[0008] A first dielectric layer: disposed on one side surface of the above-mentioned substrate, and a first through hole is provided on the above-mentioned first dielectric layer;

[0009] A conductive plug: disposed in the first through hole of the above-mentioned first dielectric layer;

[0010] A bottom electrode: disposed on one side surface of the above-mentioned first dielectric layer and connected to the above-mentioned conductive plug;

[0011] A top electrode: covering the above-mentioned bottom electrode, and a second dielectric layer is provided between the above-mentioned bottom electrode and the above-mentioned top electrode; the top electrode includes a titanium silicon nitride layer;

[0012] A top electrode filling layer: covering and connecting the above-mentioned top electrode.

[0013] In some embodiments, the above-mentioned top electrode is single-layer or laminated, and the thickness of the above-mentioned top electrode is 2 nm to 10 nm.

[0014] In some embodiments, the top electrode filling layer includes a germanium-silicon layer, and the germanium-silicon layer contains boron doping;

[0015] and / or;

[0016] The thickness of the top electrode filling layer is 10 nm to 100 nm.

[0017] In some embodiments, a barrier layer is provided between the conductive plug and the bottom electrode. One surface of the barrier layer is in contact with the conductive plug, and the other surface of the barrier layer is in contact with the bottom electrode.

[0018] In some embodiments, the barrier layer is any one or more of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), and a tungsten nitride layer (WN).

[0019] The second aspect of the present application is to provide a method for manufacturing a capacitor according to the first aspect, including the following manufacturing process:

[0020] Provide a substrate;

[0021] Form a first dielectric layer on the substrate;

[0022] Etch the first dielectric layer to form a first through hole;

[0023] Fill the conductive plug in the first through hole;

[0024] Form a bottom electrode and a second dielectric layer on one surface of the first dielectric layer in sequence;

[0025] Form a top electrode and a top electrode filling layer on one surface of the second dielectric layer in sequence.

[0026] In some embodiments, the top electrode is formed by atomic layer deposition. The deposition step includes:

[0027] Heat the surface to be deposited with the top electrode to 200 °C to 350 °C;

[0028] Introduce a titanium source precursor, a nitrogen source precursor, and a silicon source precursor into the heated surface respectively, control the pulse time to be 0.1 s to 2.0 s, and the pressure to be 1 Torr to 10 Torr;

[0029] Take the above deposition process as one cycle and repeat it multiple times.

[0030] In some embodiments, the ratio of the titanium source precursor to the silicon source precursor is 40:1 to 1:1.

[0031] In some embodiments, the titanium source precursor includes any one or more of tetrakis(dimethylamino)titanium (TDMAT) and tetraethyltitanium (TEOT);

[0032] The above nitrogen source precursor includes any one or more of ammonia and nitrogen;

[0033] The above silicon source precursor includes any one or more of tetraethyl orthosilicate (TEOS) and silane (SiH).

[0034] The third aspect of the present application is to provide a semiconductor device, including a storage unit, and the storage unit includes the capacitor described in the first aspect.

[0035] Beneficial technical effects of the present application:

[0036] 1. The capacitor provided by the present application reduces the probability of deformation such as bending of the capacitor by improving the antioxidant ability of the top electrode, thereby improving the reliability and stability of the semiconductor device.

[0037] 2. The preparation method provided by the present application is not only convenient to operate, but also beneficial to improving the antioxidant ability of the top electrode. Description of the Drawings

[0038] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present application. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0039] Figure 1 Schematically shows a structural diagram of a capacitor according to some embodiments of the present application;

[0040] Figure 2 Schematically shows a flowchart of a preparation method of a capacitor according to some embodiments of the present application;

[0041] Figures 3A to 3G Schematically shows Figure 1 A structural diagram of the capacitor preparation process.

[0042] The component numbers in the above drawings are as follows:

[0043] 1000. Capacitor;

[0044] 1001. Substrate; 1002. First dielectric layer; 1003. Conductive plug; 1004. Barrier layer; 1005. Bottom electrode; 1006. Third dielectric layer; 1007. Second dielectric layer; 1008. Top electrode; 1009. Top electrode filling layer;

[0045] 1100. Sacrificial layer. Detailed Embodiments

[0046] To make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0047] Various structural schematic diagrams according to embodiments of the present application are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes and relative positions according to actual needs.

[0048] In the context of the present application, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0049] The present application may use the term "coupled with" and its derivatives. "Coupled" can mean one or more of the following. "Coupled" can mean that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and can mean that one or more other elements are coupled or connected between the elements said to be coupled to each other. The term "directly coupled" can mean that two or more elements are in direct contact.

[0050] The capacitor in the memory cell of a dynamic random access memory (DRAM) is used to achieve the purpose of storing charge. Among them, the capacitor includes a lower electrode layer, a capacitive dielectric layer, and an upper electrode layer. Usually, a filling layer is also filled in the voids of each layer structure to stabilize the capacitor structure.

[0051] As the occupied area of the memory cell is continuously shrinking, the cell capacitance also decreases. In improving the integration degree of a dynamic random access memory (DRAM), the decrease in the cell capacitance brings the technical defect of the decrease in the reliability and stability of the memory cell. This may be because after the thickness of the upper electrode of the cell capacitance is thinned, its antioxidant ability becomes weak, and once the upper electrode is oxidized, the capacitor is prone to bending or even cracking in severe cases.

[0052] To solve the above problems, the present application provides a capacitor, a method for manufacturing a capacitor, and a semiconductor device. The capacitor provided by the present application reduces the probability of deformation such as bending of the capacitor by improving the oxidation resistance of the top electrode, thereby improving the reliability and stability of the semiconductor device.

[0053] To achieve the above technical objectives, a first aspect of the present application is to provide a capacitor, which includes a substrate, a first dielectric layer, a conductive plug, a bottom electrode, a top electrode, and a top electrode filling layer. Among them, the first dielectric layer is disposed on one surface of the substrate, and a first through hole is provided on the first dielectric layer. The conductive plug is disposed in the first through hole, and the bottom electrode is disposed on one surface of the first dielectric layer and connected to the conductive plug. At the same time, the top electrode covers the bottom electrode, and a second dielectric layer is provided between the bottom electrode and the top electrode; the top electrode includes a titanium silicon nitride layer. In addition, the top electrode filling layer covers and connects the top electrode.

[0054] The substrate of the present application is a part of a semiconductor wafer suitable for forming one or more IC devices, which may be a silicon substrate, including but not limited to silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon on nothing (SON), silicon on insulator (SOI), or silicon on replacement insulator (SRI), or a silicon germanium substrate, and the like. The substrate may additionally or alternatively include various isolation, doping, and / or device features. For example, in this embodiment, high-purity single crystal silicon is used as the substrate, and high-doped well regions are formed by implanting impurities, diffusing, and annealing into the high-purity single crystal silicon to reach the required well depth.

[0055] The dielectric layer of the present application is an insulating material layer, usually composed of oxides, nitrides, or other insulating materials, used to isolate different conductive layers or components, preventing current leakage and short circuits. Generally speaking, the dielectric constant of the dielectric layer in a capacitor directly affects the capacitance value of the capacitor. The dielectric layer in the present application includes any one or more of a silicon oxide layer, a silicon nitride layer, or other high-dielectric-constant material layers. The other high-dielectric-constant material layers in the present application include a stack formed by one or more of a zirconium oxide layer, a hafnium oxide layer, a zirconium titanium oxide layer, a rubidium oxide layer, an antimony oxide layer, and an aluminum oxide layer. The present application selects high-K dielectric materials to increase the capacitance value of the capacitor per unit area.

[0056] The conductive plug of the present application is a conductive material filled in a through hole or a contact hole, used to achieve electrical connection between different layers. It plays a role as a bridge in a multi-layer interconnect structure to ensure that current can pass through smoothly. The conductive plug in the present application includes any one or more of a tungsten metal plug, a copper metal plug, and an aluminum metal plug.

[0057] The bottom electrode and the top electrode of this application are key parts that constitute the storage unit capacitor. Among them, the bottom electrode is located at the bottom of the capacitor and is usually directly connected to the source or drain of the transistor. The shape of the bottom electrode can be columnar or planar. The conductivity of the bottom electrode directly affects the charging and discharging speed of the capacitor. And the bottom electrode has a relatively thick thickness, which can provide good mechanical support and reduce the bending and cracking of the capacitor.

[0058] In some embodiments of this application, it is disclosed that the bottom electrode includes any one or more of a polysilicon layer and a titanium nitride layer.

[0059] In some embodiments of this application, it is disclosed that the thickness of the bottom electrode is 10 nm to 20 nm.

[0060] The thickness in this application refers to the distance between one end and the other end of a single film layer along the stacking direction of the layers of the capacitor, and can be measured using a scanning electron microscope (SEM) or an atomic force microscope (AFM).

[0061] In these embodiments of this application, it is disclosed that the thickness of the bottom electrode is any one of 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm or any one that satisfies any range value between any two of the above.

[0062] The top electrode of this application is located at the top of the capacitor and covers the dielectric layer. The stress of the top electrode directly affects the bending and cracking problems of the capacitor, and the top electrode is more likely to be exposed to an oxidation environment compared to the bottom electrode. Therefore, the top electrode also affects the structural stability and reliability of the capacitor.

[0063] In some embodiments of this application, it is disclosed that the top electrode includes a silicon titanium nitride layer, and among them, the silicon titanium nitride layer can be used to reduce the probability of high stress and easy oxidation of the top electrode at a relatively thin thickness.

[0064] The top electrode filling layer of this application wraps the top electrode to reduce the contact probability between the top electrode and the oxidation environment. And the stable resistance value of this top electrode filling layer is beneficial to further ensure the stability and reliability of the capacitor.

[0065] In some embodiments, the above top electrode is a single layer or a stacked layer, and the thickness of the above top electrode is 2 nm to 10 nm.

[0066] The single layer in this application refers to one layer, and the stacked layer refers to two or more layers. The thickness in this application is the same as the above and will not be elaborated here.

[0067] The thickness of the top electrode in this application is reduced to a certain extent compared with that of existing capacitors. The top electrode with reduced thickness is also beneficial to controlling the stress of the top electrode within a reasonable range.

[0068] In these embodiments of this application, the thickness of the top electrode is disclosed as any one of 2.0nm, 2.5nm, 3.0nm, 3.5nm, 4.0nm, 4.5nm, 5.0nm, 5.5nm, 6.0nm, 6.5nm, 7.0nm, 7.5nm, 8.0nm, 8.5nm, 9.0nm, 9.5nm, 10.0nm or any one within the range of any two of the above.

[0069] In some embodiments, the orthographic projection of the top electrode on the substrate is cylindrical. This top electrode has a relatively reasonable electrode area, which is beneficial to improving the capacitance of the capacitor.

[0070] In some embodiments, the top electrode covers the third dielectric layer.

[0071] In some embodiments, the above-mentioned top electrode filling layer includes a germanium-silicon layer, and this germanium-silicon layer contains boron doping.

[0072] This application uses boron-doped silicon-germanium as the filling layer, which can reduce the process temperature for forming the filling layer. At the same time, germanium can increase the carrier mobility rate, and thus can reduce the resistance value of the filling layer.

[0073] The boron content doped in the silicon-germanium of this application affects both the resistance value of the filling layer and the deposition rate. If the deposition rate is too fast, it is easy to cause the upper electrode filling layer to seal prematurely, resulting in bubbles inside and affecting the performance of the filling layer. Therefore, during the preparation process of this application, the mass of the boron precursor is controlled to be 0.1% - 30% of the mass of the mixture.

[0074] The top electrode filling layer of this application can fully cover the top electrode layer and fill the gaps between the top electrode layers.

[0075] In some embodiments, the thickness of the above-mentioned top electrode filling layer is 10nm - 100nm.

[0076] The thickness here in this application is the same as the above, and this application will not elaborate here. In these embodiments of this application, the thickness of the above-mentioned top electrode filling layer is disclosed as any one of 10nm, 11nm, 15nm, 19nm, 20nm, 21nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm or any one within the range of any two of the above.

[0077] In some embodiments, a barrier layer is provided between the conductive plug and the bottom electrode. One surface of the barrier layer abuts against the conductive plug, and the other surface of the barrier layer abuts against the bottom electrode.

[0078] In some embodiments, the barrier layer is any one or more of a titanium nitride layer (TiN), a tantalum nitride layer (TaN), and a tungsten nitride layer (WN).

[0079] The barrier layer of the present application has conductivity, which is beneficial to reducing the probability of the conductive plug diffusing into the bottom electrode.

[0080] The second aspect of the present application is to provide a method for manufacturing the capacitor described in the first aspect. The manufacturing method is as Figure 2 shown, including the following manufacturing processes:

[0081] S100. Provide a substrate;

[0082] S200. Form a first dielectric layer on the substrate;

[0083] S300. Etch the first dielectric layer to form a first through hole;

[0084] S400. Fill a conductive plug in the first through hole;

[0085] S500. Sequentially form a bottom electrode and a second dielectric layer on one surface of the first dielectric layer;

[0086] S600. Sequentially form a top electrode and a top electrode filling layer on one surface of the second dielectric layer.

[0087] In some embodiments, the top electrode is formed by atomic layer deposition (ALD). The deposition step includes:

[0088] Heat the surface of the top electrode to be deposited to 200°C to 350°C;

[0089] Introduce a titanium source precursor, a nitrogen source precursor, and a silicon source precursor into the heated surface respectively, control the pulse time to be 0.1 s to 2.0 s, and the pressure to be 1 Torr to 10 Torr; take the above deposition process as one cycle and repeat it multiple times.

[0090] In some embodiments of the present application, the surface of the top electrode to be deposited is heated to any one of 200°C, 210°C, 220°C, 230°C, 240°C, 250°C, 260°C, 270°C, 280°C, 290°C, 300°C, 310°C, 320°C, 330°C, 340°C, 350°C or any one that satisfies the range value of any two of the above.

[0091] The pulse time of the present application refers to the time when each precursor is introduced onto the surface to be deposited during the ALD reaction.

[0092] In some embodiments of the present application, the pulse time is controlled to be any one of 0.1 s, 0.2 s, 0.3 s, 0.4 s, 0.5 s, 0.6 s, 0.7 s, 0.8 s, 0.9 s, 1 s, 1.1 s, 1.2 s, 1.3 s, 1.4 s, 1.5 s, 1.6 s, 1.7 s, 1.8 s, 1.9 s, 2.0 s or any one within the range of any two of the above.

[0093] The pressure unit of the present application is Torr, and 1 Torr = 1.33322×10 2 Pa.

[0094] In some embodiments, the above deposition process is cycled 2 to 20 times.

[0095] Atomic layer deposition (ALD) of the present application is a high-precision thin film deposition technology based on chemical vapor deposition (CVD), which is a technology for depositing material substances layer by layer on the surface of a substrate in the form of a single atomic layer. The present application uses atomic layer deposition to form the top electrode, which is convenient for controlling the thickness of the top electrode.

[0096] In some embodiments, the flow rate ratio of the above titanium source precursor to the above silicon source precursor is from 40:1 to 1:1.

[0097] In these embodiments of the present application, the flow rate ratio of the above titanium source precursor to the above silicon source precursor is any one of 40:1, 39:1, 38:1, 37:1, 36:1, 35:1, 34:1, 33:1, 32:1, 31:1, 30:1, 29:1, 28:1, 27:1, 26:1, 25:1, 24:1, 23:1, 22:1, 21:1, 20:1, 19:1, 18:1, 17:1, 16:1, 15:1, 14:1, 13:1, 12:1, 11:1, 10:1, 9:1, 8:1, 7:1, 6:1, 5:1, 4:1, 3:1, 2:1, 1:1 or any one within the range of any two of the above.

[0098] In some embodiments, the above titanium source precursor includes any one or more of tetrakis(dimethylamino)titanium (TDMAT), tetraethyltitanium (TEOT);

[0099] The above nitrogen source precursor includes any one or more of ammonia, nitrogen;

[0100] The above silicon source precursor includes any one or more of tetraethyl orthosilicate (TEOS), silane (SiH).

[0101] In some embodiments of the present application, the formation process of the top electrode filling layer is disclosed:

[0102] S601. Place a plurality of semi-finished products including a bottom electrode and a top electrode in the same chamber;

[0103] S602. Introduce a silicon precursor into the above chamber for cleaning;

[0104] S603. Introduce a silicon precursor into the cleaned chamber for pre-deposition;

[0105] S604. Introduce a mixture containing a silicon precursor, a germanium precursor, and a boron precursor into the chamber after pre-deposition for a deposition reaction to obtain a finished product including an electrode filling layer.

[0106] In the present application, "a plurality of" includes two or more. The present application adjusts the number of semi-finished products according to the accommodation volume of the chamber and the actual processing effect.

[0107] The chamber of the present application includes, but is not limited to, a chemical vapor deposition device, such as a low-pressure chemical vapor deposition furnace tube.

[0108] The silicon precursor in the present application is preferably a gas. The cleaning in the present application includes introducing a silicon precursor into any air inlet of the chamber, and at the same time, discharging the silicon precursor from any air outlet of the chamber so that the chamber is filled with an air flow containing the silicon precursor.

[0109] The pre-deposition in the present application deposits silicon on the outer surface of the upper electrode layer in advance to facilitate subsequent compensation for silicon loss during the formation of the filling layer and at the same time facilitate the deposition of the filling layer.

[0110] The deposition in the present application includes forming a germanium-silicon containing boron doping on the outer surface of the upper electrode layer. The germanium-silicon containing boron doping serves as the filling layer, and its thickness is generally 10 nm to 100 nm, which can fully cover the upper electrode layer and fill the gaps between the upper electrode layers.

[0111] Therefore, the preparation method of the electrode filling layer provided by the present application, by adopting a batch processing method, is not only convenient for operation but also beneficial to maintaining the stability of the filling effect of the electrode filling layer. Specifically, the thickness uniformity of the formed electrode filling layer is strong, the resistance value of the filling layer is stable and remains at a relatively low level. In addition, it can also reduce the short-circuit probability caused by the large thickness distribution range of the filling layer.

[0112] In some embodiments of the present application, the semiconductor device that first completes the formation of the filling layer is the first batch, and the semiconductor device that later completes the formation of the filling layer is the second batch. The time from when the first batch is transported out of the chamber to when the second batch is transported into the chamber is the time interval, and the sum of this time interval and the time for forming the filling layer in the chamber is the processing cycle of each batch.

[0113] In some embodiments of the present application, cleaning the chamber with a silicon precursor includes: introducing the silicon precursor into the chamber within a first preset time; wherein, the first preset time includes 300 s to 900 s, preferably 400 s to 700 s.

[0114] In the present application, introducing the silicon precursor within the first preset time fills the chamber with an air flow containing the silicon precursor, thereby facilitating subsequent pre-deposition and deposition processes. In these embodiments of the present application, it is disclosed that the first preset time includes but is not limited to any one of 300 s, 320 s, 350 s, 380 s, 400 s, 420 s, 450 s, 480 s, 500 s, 520 s, 550 s, 580 s, 600 s, 620 s, 650 s, 680 s, 700 s, 720 s, 750 s, 780 s, 800 s, 820 s, 850 s, 880 s, 900 s or any one satisfying the above range values. In some embodiments of the present application, it is preferred that the first preset time includes 400 s to 700 s.

[0115] In some embodiments of the present application, pre-deposition includes: introducing the silicon precursor into the cleaned chamber within a second preset time; the temperature of the pre-deposition is 415 °C to 450 °C, further 420 °C to 445 °C, and in some embodiments, 430 °C is selected. In some embodiments of the present application, it is disclosed that the temperature of the pre-deposition is any one of 415 °C, 418 °C, 420 °C, 422 °C, 425 °C, 428 °C, 430 °C, 432 °C, 435 °C, 438 °C, 440 °C, 442 °C, 445 °C, 448 °C, 450 °C or any one satisfying the above range values.

[0116] As described above, the pre-deposition of the present application is beneficial to facilitating subsequent compensation for silicon loss during the formation of the filling layer and at the same time facilitating the deposition to form the filling layer. The pre-deposition temperature of the present application is the same as or similar to the deposition temperature.

[0117] In some embodiments of the present application, deposition includes:

[0118] Within a third preset time, introducing a mixture containing a silicon precursor, a germanium precursor and a boron precursor into the chamber after pre-deposition for a deposition reaction; wherein, the third preset time is greater than the second preset time; the deposition temperature is 415 °C to 450 °C, preferably 420 °C to 445 °C, and more preferably 430 °C.

[0119] In some embodiments of the present application, it is disclosed that the third preset time is more than 100 s greater than the above second preset time to achieve effective coordination between pre-deposition and subsequent deposition.

[0120] In some embodiments of the present application, the temperature of pre - deposition is any one of 415°C, 418°C, 420°C, 422°C, 425°C, 428°C, 430°C, 432°C, 435°C, 438°C, 440°C, 442°C, 445°C, 448°C, 450°C or any one that satisfies the above - mentioned range values. The pre - deposition of the present application is to prepare for deposition. The actual deposition takes longer than the pre - deposition. The present application deposits in a chamber to form a filling layer containing boron - doped germanium - silicon. Meanwhile, the pre - deposition time of the present application can be adjusted correspondingly according to the deposition time.

[0121] In these embodiments of the present application, it is disclosed that the deposition temperature can be any one of 415°C, 420°C, 425°C, 430°C, 435°C, 440°C, 445°C, 450°C or any one that satisfies the above - mentioned range values.

[0122] In some embodiments of the present application, in the above - mentioned mixture, the flow rate ratio of the germanium precursor to the silicon precursor is (1.5 - 3):1, preferably (1.8 - 2.8):1, and more preferably 2.28:1.

[0123] The flow rate unit in the present application is cubic meters per second, which mainly refers to the gaseous precursors. The flow rate of the germanium precursor in the present application is greater than that of the silicon precursor because a part of the silicon - containing film layer has been formed during pre - deposition. Utilizing the characteristic that germanium can migrate in the silicon film layer facilitates the generation of silicon germanium. In these embodiments of the present application, it is disclosed that the flow rate ratio of the germanium precursor to the silicon precursor can be any one of 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2.0:1, 2.1:1, 2.2:1, 2.28:1, 2.3:1, 2.4:1, 2.5:1, 2.6:1, 2.7:1, 2.8:1, 2.9:1, 3.0:1 or any one that satisfies the above - mentioned range values.

[0124] In some embodiments of the present application, the mass of the boron precursor is 0.1% - 30% of the mass of the mixture; preferably 1% - 20%.

[0125] In this application, the boron content doped in silicon-germanium affects both the resistance value of the filling layer and the deposition rate. If the deposition rate is too fast, it is easy to cause the upper electrode filling layer to seal prematurely, resulting in the formation of bubbles inside and affecting the performance of the filling layer. Therefore, this application selects to control the mass of the boron precursor to be 0.1% - 30% of the mass of the mixture. In these embodiments, this application discloses that the mass of the boron precursor is any one of 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30% of the mass of the mixture or any one that satisfies the above range values.

[0126] This application uses boron-doped silicon-germanium as the filling layer, which can reduce the process temperature for forming the filling layer. At the same time, germanium can increase the migration rate of carriers, thereby reducing the resistance value of the filling layer.

[0127] In some embodiments of this application, the above-mentioned silicon precursor includes silane, and this silane includes at least one of monosilane and disilane; and / or;

[0128] The above-mentioned germanium precursor includes germane, and this germane includes at least one of monogermane and digermane; and / or;

[0129] The above-mentioned boron precursor is at least one of boron trichloride or diborane.

[0130] In some embodiments of this application, preferably, the silicon precursor includes monosilane, the germanium precursor includes monogermane, and the boron precursor includes boron trichloride.

[0131] In some embodiments of this application, the patterned mask layer includes forming a photoresist as a mask layer on one side surface of the sacrificial layer and the support layer that are alternately stacked and arranged and are far from the semiconductor substrate. Among them, the photoresist includes but is not limited to silicon nitride, etc. This application discloses in these embodiments that a lithography process is used to etch to the surface of the semiconductor substrate, and among them, the lithography process includes but is not limited to dry etching, wet etching, and a process etching combining dry etching and wet etching.

[0132] Example 1

[0133] A Figure 1 schematic capacitor 1000 is provided, and this capacitor is obtained according to Figures 3A to 3G the schematic preparation process:

[0134] As Figure 3A schematic, this embodiment provides a substrate 1001, and this substrate uses high-purity single-crystalline silicon as the substrate, as Figure 3BAs shown, a first dielectric layer 1002 of silicon oxide is formed on one side surface of a substrate 1001. Selective etching is performed on the side surface of the first dielectric layer 1002 away from the substrate 1001 to form a first through hole, and a conductive plug 1003 made of tungsten metal is filled in the first through hole.

[0135] As Figure 3C As shown, a first dielectric layer 1002 of silicon oxide is continuously formed on the side surface of the first dielectric layer 1002 away from the substrate 1001. A barrier layer 1004 is provided at the top end of the conductive plug 1003. As Figure 3D As shown, a sacrificial layer 1100 and a bottom electrode 1005 are formed on the side surface of the newly formed first dielectric layer 1002 away from the substrate 1001. A third dielectric layer 1006 of silicon oxide is formed on the side surface of the bottom electrode 1005 away from the substrate 1001. As Figure 3E As shown, as Figure 3F As shown, the sacrificial layer 1100 is removed, and the third dielectric layer 1006 and the bottom electrode 1005 are planarized by chemical mechanical polishing (CMP) to form a flush top setting; as Figure 3G As shown, a second dielectric layer 1007 of silicon oxide, a top electrode 1008, and a top electrode filling layer 1009 are sequentially formed outside the polished bottom electrode 1005. Among them, the top electrode 1008 is formed by atomic layer deposition. Deposition steps:

[0136] Under the protection of inert gas helium, the surface to be deposited with the top electrode is heated to 250 °C.

[0137] A titanium source precursor (tetrakis(dimethylamino)titanium), a nitrogen source precursor (nitrogen gas), and a silicon source precursor (silane) are respectively introduced onto the heated surface. The ratio between tetrakis(dimethylamino)titanium and silane is controlled to be 20:1; and the pulse time is controlled to be 0.5 s and the pressure is 3.5 Torr; the above deposition process is taken as one cycle and repeated 3 times. The thickness of the formed titanium silicon nitride layer is 2.5 nm.

[0138] Meanwhile, the preparation method of the electrode filling layer in this capacitor includes the following process:

[0139] (1) Place ten above-mentioned semi-finished products including the top electrode and the bottom electrode in the same low-pressure chemical vapor deposition furnace tube, and introduce an inert gas flow, such as nitrogen gas, into the furnace tube chamber for about 30 min.

[0140] (2) Introduce silane to clean the above furnace tube chamber for 700 s.

[0141] (3) Continue to introduce silane into the cleaned chamber for pre-deposition; control the pre-deposition temperature to be 425 °C to 430 °C, and the second preset time for pre-deposition is T2, where T2 is greater than 600 s.

[0142] (4) After pre-deposition, a mixture containing silane, germane, and boron trichloride is introduced into the chamber for deposition reaction to obtain a finished product containing the electrode filling layer. The deposition temperature is controlled at about 430 °C, and the third preset deposition time is T3, where T3 is 30 min. At the same time, the flow ratio of germane to silane is 2.28:1, and the mass of boron trichloride is controlled at about 1% of the total gas mass.

[0143] (5) After the above deposition is completed, nitrogen gas is continuously introduced into the furnace tube chamber.

[0144] The above steps complete the preparation of one batch of the top electrode filling layer and finally form a capacitor.

[0145] Example 2

[0146] A Figure 1 schematic capacitor is provided, and the capacitor is prepared according to the Figures 3A to 3G schematic preparation process: The difference between this preparation method and Example 1 is that the ratio of titanium tetrakis(dimethylamino) to silane is controlled at 40:1, and other aspects are the same as those in Example 1.

[0147] Comparative Example 1

[0148] The difference from Example 1 above is that the top electrode includes a titanium nitride layer, and the thickness of the titanium nitride layer is 5.0 nm.

[0149] Other aspects are the same as those in Example 1.

[0150] Performance test:

[0151] Test method for tensile stress:

[0152] Tensile stress refers to the reaction force of an object against an external force that tends to stretch the object. The test method for tensile stress includes: According to the ASTM international standard, a certain load is designed at both ends of the above capacitor along the stacking direction, and through static tensile testing, the stress-strain curve of the material is obtained, and then the tensile stress of the capacitor in different states is obtained according to this curve:

[0153] And the following ozone annealing treatment means that after the top electrode is deposited and formed, it is placed in an ozone atmosphere, and a certain temperature, such as 200 °C, is controlled, and a certain time, such as 30 min, is treated.

[0154] Table 1

[0155]

[0156] In summary, the capacitor provided by the present application reduces the probability of deformation such as bending of the capacitor by improving the antioxidant ability of the top electrode, thereby improving the reliability and stability of the semiconductor device.

[0157] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0158] The above describes the embodiments of the present application. However, these embodiments are only for illustrative purposes and

[0159] are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present application.

Claims

1. A capacitor, characterized in that: include: substrate; A first dielectric layer is disposed on a surface of one side of the substrate, and a first through hole is disposed on the first dielectric layer; Conductive plug: arranged in the first through hole of the first dielectric layer; Bottom electrode: arranged on one side surface of the first dielectric layer and connected to the conductive plug; Top electrode: covering the bottom electrode, with a second dielectric layer provided between the bottom electrode and the top electrode; the top electrode comprises a titanium silicon nitride layer; Top electrode filling layer: covers and connects the top electrode.

2. The capacitor according to claim 1, characterized in that: The top electrode is a single layer or a stacked layer, and the thickness of the top electrode is 2nm-10nm.

3. The capacitor according to any one of claims 1 to 2, characterized in that: The top electrode filling layer comprises a germanium-silicon layer, and the germanium-silicon layer is doped with boron; and / or; The thickness of the top electrode filling layer is 10nm-100nm.

4. The capacitor according to any one of claims 1 to 2, characterized in that: A barrier layer is disposed between the conductive plug and the bottom electrode, one end surface of the barrier layer is disposed against the conductive plug, and the other end surface of the barrier layer is disposed against the bottom electrode.

5. The capacitor according to claim 4, characterized in that: The barrier layer is any one or more of a titanium nitride layer, a tantalum nitride layer, and a tungsten nitride layer.

6. A method for preparing a capacitor according to claim 1, characterized in that: The preparation process includes the following: providing a substrate; forming a first dielectric layer on the substrate; Etching the first dielectric layer to form a first through hole; filling a conductive plug in the first through hole; A bottom electrode and a second dielectric layer are sequentially formed on a surface of one side of the first dielectric layer; A top electrode and a top electrode filling layer are sequentially formed on one side surface of the second dielectric layer.

7. The preparation method according to claim 6, characterized in that: The top electrode is formed by atomic layer deposition, and the deposition step includes: The surface on which the top electrode is to be deposited is heated to 200° C. to 350° C.; A titanium source precursor, a nitrogen source precursor and a silicon source precursor are introduced to the heated surface respectively, and the pulse time is controlled to be 0.1s to 2.0s and the pressure is 1Torr to 10Torr; The above deposition process is regarded as one cycle, and the cycle is repeated multiple times.

8. The preparation method according to claim 7, characterized in that: The flow ratio of the titanium source precursor to the silicon source precursor is 40:1 to 1:

1.

9. The preparation method according to any one of claims 7 to 8, characterized in that: The titanium source precursor includes any one or more of tetrakis dimethylamino titanium and tetraethyl titanium; The nitrogen source precursor includes any one or more of ammonia and nitrogen; The silicon source precursor includes any one or more of tetraethyl orthosilicate and monosilane.

10. A semiconductor device, characterized in that: A storage unit is included, wherein the storage unit includes the capacitor according to any one of claims 1 to 5.

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