Semiconductor device and method of processing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of processing the same. The semiconductor device includes a transistor device including one or more trenches formed in a first main surface of a semiconductor substrate. Each trench includes a substrate and a sidewall extending from the substrate to the first major surface, the sidewall including an upper segment, a lower segment, and a middle segment therebetween. A field plate is in the trench and a field dielectric is on the substrate and sidewalls of the trench. The field dielectric has a first thickness in an upper segment region of the sidewall, and the field dielectric has a second thickness greater than the first thickness in a lower segment region of the sidewall. In a middle region of the sidewall, a thickness of the field dielectric varies from a first thickness of a first boundary between the upper segment region and the middle segment region to a second thickness of a second boundary between the lower segment region and the middle segment region. A surface of the field dielectric has a concave form at a first boundary between the upper segment region and the middle segment region and a convex form at a second boundary between the lower segment region and the middle segment region.

Description

BACKGROUND OF THE INVENTION

[0001] Silicon (Si) semiconductor materials can be utilized to fabricate transistors used in power electronics applications. Common transistor devices for power applications include Si Si power MOSFETs and Si insulated gate bipolar transistors (IGBTs).

[0002] Transistor devices for power applications can be based on the charge compensation principle and can include an active elementary field that includes a plurality of trenches, each trench including a field plate for charge compensation. In some designs, the trenches and the mesa formed between adjacent trenches can have an elongated stripe structure. In some other designs, the trenches and the field plates can have a columnar needle shape.

[0003] Further improvements will be desirable to further improve the performance of transistor devices with field plates, for example, by reducing the on-state resistance RDS(on).Area. SUMMARY OF THE INVENTION

[0004] In an embodiment, a semiconductor device including a transistor device is provided. The transistor device includes one or more trenches formed in a first main surface of a semiconductor substrate. Each of the one or more trenches includes a base and sidewalls extending from the base to the first main surface, wherein the sidewalls include an upper section region, a lower section region, and an intermediate section region located between the lower section region and the upper section region. A field plate is located in the trench. A field dielectric is located on the base and the sidewalls of the trench and has a surface. In the upper section region of the sidewall, the field dielectric has a first thickness, and in the lower section region of the sidewall, the field dielectric has a second thickness greater than the first thickness. In the intermediate region of the sidewall, the thickness of the field dielectric varies from the first thickness at a first boundary between the upper section region and the intermediate section region to the second thickness at a second boundary between the lower section region and the intermediate section region. The surface of the field dielectric has a concave form at the first boundary between the upper section region and the intermediate section region and has a convex form at the second boundary between the lower section region and the intermediate section region. The second boundary is edge-free.

[0005] In an embodiment, a method of fabricating a field plate in a trench is provided. A semiconductor device includes at least one trench in a first main surface of a semiconductor substrate, the at least one trench having a base and sidewalls extending from the base to the first main surface. The method includes: forming a field dielectric over the base and the sidewalls of the at least one trench; implanting a species into a first section region of the field dielectric disposed on the sidewall; etching the field dielectric in at least the first section region; and inserting a conductive material into the at least one trench to form a field plate.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. Description of the Drawings

[0007] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding like parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and detailed in the following description.

[0008] FIG. 1 includes Figures 1A to 1D , whereby Figure 1A and 1B a cross-sectional view of a semiconductor device including a transistor device having a structured field dielectric in a trench, Figure 1C illustrates a comparison of transistor devices, and Figure 1D a cross-sectional view of a semiconductor device including a transistor device having a structured field dielectric and a gate electrode in a trench.

[0009] Figure 2 illustrates an embodiment in which the thickness of the field dielectric in the trench of the transistor device is non-uniform laterally.

[0010] FIG. 3 includes Figures 3A to 3E , illustrating an embodiment of a transistor device, whereby Figure 3A a top view is illustrated, Figure 3B a cross-sectional view along line A-A shown in Figure 3A is illustrated according to a first embodiment, Figure 3C a cross-sectional view along line A-A shown in Figure 3A is illustrated according to a second embodiment, Figure 3D a cross-sectional view along line B-B of the embodiment illustrated in Figure 3C is illustrated, and Figure 3E a cross-sectional view along line C-C' of the embodiment illustrated in Figure 3C is illustrated.

[0011] FIG. 4 includes Figures 4A to 4F , illustrating a method for processing a field dielectric in a trench in a semiconductor device.

[0012] Figure 5A illustrates an example of a method of implanting a field dielectric in a trench at two tilt angles.

[0013] Figure 5B illustrates an example of a method of implanting a field dielectric in a trench at more than two tilt angles. Detailed Description

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. In this regard, directional terms such as "top", "bottom", "front", "rear", "head", "tail", etc. are used with reference to the orientation of the (one or more) drawings being described. Since the components of the embodiments can be positioned in many different orientations, the directional terms are used for purposes of illustration and are in no way limiting. It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope of the invention. The following detailed description should not be taken in a limiting sense, and the scope of the invention is defined by the appended claims.

[0015] Many exemplary embodiments will be explained hereinafter. In this case, the same structural features are identified by the same or similar reference numerals in the drawings. In the context of this description, the term "lateral" or "lateral direction" should be understood to mean a direction or extent that extends generally parallel to the lateral extent of the semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast, the terms "vertical" or "vertical direction" are understood to mean a direction that extends generally perpendicular to these surfaces or sides and thus perpendicular to the lateral direction. The vertical direction thus extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0016] As used in this specification, when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending onto" another element, it can be directly on or directly extend onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, no intervening elements are present.

[0017] As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0018] As used herein, various device types and / or doped semiconductor regions may be identified as having an n-type or a p-type, but this is for convenience of description only and is not intended to be limiting, and such identification may be replaced by a more general description having a "first conductivity type" or a "second opposite conductivity type", where the first type may be n or p type and the second type is then p or n type.

[0019] The accompanying drawings illustrate relative doping concentrations by immediately indicating "-" or "+" following the doping type "n" or "p". For example, "n -” means a doping concentration lower than that of the “n” doped region, while the “n + ” doped region has a higher doping concentration than the “n” doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different “n” doped regions can have the same or different absolute doping concentrations.

[0020] One type of MOSFET device includes a compensation element, which includes a vertical trench in silicon and a vertical conductive electrode (also known as a field plate), and the field plate is located in the trench and is isolated from the silicon by a field dielectric. The field plate can be formed of polysilicon, and the field dielectric can be a field oxide (FOX), such as SiO 2 2. The field dielectric lines the base and sidewalls of the trench and typically has a constant thickness on the sidewalls in both the vertical and lateral directions.

[0021] Thinner field dielectric in the top portion of the trench and thicker field dielectric portions in the bottom portion of the trench can allow for an increase in doping in the top mesa portion while maintaining the blocking ability. This vertical structuring of the field dielectric within the trench results in significant performance gains.

[0022] According to one aspect of the present disclosure, it is proposed herein to further improve the performance of such a transistor device by providing a field dielectric structure that avoids sharp sudden changes in thickness. According to another aspect of the present disclosure, it is proposed herein to use damage implantation to process such a field dielectric structure to form a smooth curved transition between regions of different thicknesses.

[0023] For example, damage implantation into the field dielectric layer lining the sidewalls of needle-shaped trenches or elongated stripe-shaped trenches can be used to increase the wet chemical etching rate in certain lateral directions and / or vertical depths, i.e., locally increase the wet chemical etching rate in a predetermined region in at least one of the vertical and lateral directions.

[0024] In the vertical direction, damage implantation together with wet etching can be used to process a field dielectric having one or more discrete regions of different thicknesses (with a smoother and less sudden transition between the discrete regions), or can be used to process a field dielectric having a continuous taper (i.e., monotonically decreasing) in terms of the thickness of the field dielectric.

[0025] In the lateral direction, damage implantation together with wet etching can be used to form a laterally anisotropic field dielectric thickness. In some embodiments, for example, this can be used to increase the compensation efficiency along the diagonals of needle-shaped trenches arranged in a grid (e.g., a square grid), or to form a thicker field dielectric at the ends of stripe trenches.

[0026] Damage implantation and subsequent preferential etching of some regions of the field dielectric relative to other non-damaged regions can be used to structure the field dielectric and selectively reduce the thickness in some regions in the vertical direction and in the lateral plane.

[0027] In an embodiment, a method for vertical structuring of a field dielectric located on the sidewalls of needle-shaped or striped trenches is provided, the method including the following steps. Optionally, the thickness of the deposited field dielectric is increased by a few nanometers, e.g., 200 nm, to ensure sufficient thickness of the field dielectric on the substrate of the trench after the etching process. In some examples, after the damage implantation and / or etching sequence, the field dielectric on the substrate of the trench can be increased. The planar thickness of the field dielectric is measured, and then inclined damage implantation (e.g., using argon ions) is performed into the regions of the field dielectric located on the sidewalls of the trench (typically, the regions on the upper section of the sidewalls). Other regions of the field dielectric are not implanted and remain undamaged. After the implantation is completed, the field dielectric can be etched using wet or plasma chemistry. In some examples, the measured thickness can be used for etching time adjustment. Optionally, several deposition / implantation / etching sequences can be repeated to optimize bottom oxide consumption, sidewall thickness, transition point, anisotropy. Since the damaged implantation region has a higher etching rate, a larger portion of the field dielectric material can be removed in this region. This can reduce the thickness of the remaining field dielectric (such as the remaining field dielectric in the region where damage implantation is performed) relative to the thickness of the field dielectric that has not undergone implantation. Thus, two discrete regions of field dielectric with different thicknesses can be created. The method can continue by annealing the field dielectric and filling the trench with a conductive material (e.g., polysilicon) to form a field plate.

[0028] Alternatively, the field dielectric can be subjected to damage implantation and (one or more) etching processes, and then another thin field dielectric layer is deposited to increase the thickness of the field dielectric by a few nanometers, e.g., 200 nm, to ensure sufficient thickness of the field dielectric on the substrate of the trench. In some embodiments, the sequence of damage implantation, etching, and deposition of another thin field dielectric layer is repeated.

[0029] In an embodiment, the inclined damage implantation can include N discrete steps, and the N discrete steps can be created by N discrete implantations at different discrete tilt angles. This can be used to process a field dielectric having more than two steps (i.e., more than two regions of different thicknesses) or a continuous tapered form.

[0030] In another embodiment, the tilted damage implantation may include N discrete steps, where N discrete steps are created by N discrete implantations at different discrete tilt angles, using one or more desired rotation angles. For example, rotation angles of 90° and 270° are used to implant into the opposite long sidewalls of the stripe trenches, or rotation angles of 45°, 135°, 225°, and 315° are used to implant along the diagonals of the square grid array of columnar trenches. After the implantation is completed, using wet or plasma chemistry, the etch time is adjusted using the measured thickness, and the field dielectric is etched.

[0031] In a vertically structured embodiment, a continuous taper is created in the field dielectric by using a large number of discrete implantations at different tilt angles and / or energies. This large number of discrete implantations can be performed at one or more desired rotation angles, such as at rotation angles of 90° and 270° to implant into the opposite long sidewalls of the stripe trenches, or at rotation angles of 45°, 135°, 225°, and 315° to implant along the diagonals of the square grid array of columnar trenches. After the implantation is completed, using wet or plasma chemistry, the etch time is adjusted using the measured thickness, and the field dielectric is etched. Optionally, several deposition / implantation / etch sequences can be repeated to optimize bottom oxide consumption, sidewall thickness, transition point, anisotropy.

[0032] The method continues by annealing the field dielectric and filling the trenches with a conductive material (e.g., polysilicon) to form field plates.

[0033] The correlation between the area specific capacitance and the rotation angle can be used to enhance charge compensation in the diagonal direction of the square grid array, which has a wider mesa in the diagonal direction compared to the width of the mesa in the normal direction.

[0034] In an embodiment, a method for lateral structuring of a field dielectric located on the sidewalls of needle-shaped or stripe trenches is provided, the method including the following steps. Damage implantation is applied only at distinct rotation angles. The field dielectric is damaged anisotropically and then etched anisotropically in the lateral plane. This embodiment can be used in needle-shaped trenches arranged in a square grid pattern to reduce the field dielectric thickness in the diagonal direction (e.g., at 45° relative to the x and y directions), while retaining a greater field dielectric thickness in the normal direction (e.g., in the x and y directions).

[0035] In some embodiments, elements heavier than argon are used for implantation. For example, platinum can be used. This can be used to adjust the damage depth profile according to application requirements, while reducing unwanted sidewall reflections and bottom oxide thinning.

[0036] Figure 1A FIG. 1 is a cross-sectional view of a semiconductor device 10 according to an embodiment of the present disclosure. The semiconductor device 10 includes a transistor device 11. The transistor device 11 includes one or more trenches 12 formed in a first main surface 13 of a semiconductor substrate 14. The semiconductor substrate 14 may include silicon, for example, an epitaxial silicon layer or a single-crystalline silicon substrate such as a wafer or a chip. Each trench 12 includes a base 15 and sidewalls 16 extending from the base 15 to the first main surface 13. A field plate 17 is located in each trench 12.

[0037] The transistor device 11 further includes: a drift region 18 of a first conductivity type formed in the semiconductor substrate 14; a body region 19 located on the drift region 18; and a source region 20 disposed on the body region 19. The body region 19 includes a second conductivity type opposite to the first conductivity type. The source region 20 includes the first conductivity type and is more highly doped than the drift region 18. The first conductivity type may be n-type and the second conductivity type may be p-type, and vice versa. The transistor device 11 further includes: a gate electrode 21 disposed in a gate trench 22 formed in the first main surface 13 of the semiconductor device 14 and electrically insulated from the semiconductor substrate 14 by a gate dielectric 23 disposed on sidewalls 24 and a base 25 of the gate trench 22. A drain region 26 highly doped with the first conductivity type is disposed on a second main surface 13' of the semiconductor substrate 14 opposite to the first main surface 13. The trench 22 including the gate electrode 21 is laterally disposed between the trenches 12 including the field plate 17 and is separated from the trenches 12.

[0038] In a top view, the gate trench 22 may be elongated and stripe-shaped and have a longest direction extending into the plane of the drawing. The trench 12 in which the field plate 17 is located may have an elongated stripe-shaped structure and have a longest direction extending into the plane of the drawing, or may have a columnar structure. For the columnar trench and the stripe-shaped trench, the cross-sectional profiles shown in FIG. 1 are the same.

[0039] The elongated or stripe-shaped trenches 12, 22 have a length extending parallel to the first main surface, which length is greater than its depth relative to the first main surface and is also greater than its width. The gate electrode 21 or the field plate 17 within the trenches 12, 22 also respectively have an elongated stripe-shaped form having a length extending parallel to the first main surface 13, which length is greater than its depth relative to the first main surface 13 and is also greater than its width.

[0040] The columnar or needle-shaped trench 12 has a small or narrow perimeter or width that is proportional to its height / depth in the substrate. In a plan view, the columnar or needle-shaped trench 12 can have an octagonal, circular, square, or hexagonal shape. The field plate 17 in the columnar trench 12 also has a small or narrow perimeter or width that is proportional to its height / depth in the substrate 14. The columnar trenches 12 (and thus, the columnar field plates 17 disposed in the respective trenches 12) can be arranged in a regular array, such as a square grid array of rows and columns.

[0041] In an embodiment where the trench 12 and the field plate 17 are columnar, the columnar trench 12 has a longitudinal axis L that extends substantially perpendicular to the first main surface 13.

[0042] In some embodiments, the transistor device 11 has a drift path perpendicular to the main surface 13 of the semiconductor substrate 14 and can be referred to as a vertical transistor device. For example, the transistor device 11 can be a MOSFET (metal-oxide-semiconductor field-effect transistor) device.

[0043] The field dielectric 30 is located on the base 15 and the sidewall 16 of the trench 12 and completely covers the base 15 and the sidewall 16 of the trench 12. The field plate 17 is electrically insulated from the semiconductor substrate 14 by the field dielectric 30. The field dielectric 30 can include silicon oxide, such as SiO 2 , and the field plate 17 can be formed of polysilicon.

[0044] Figure 1A An embodiment is illustrated where the field dielectric 18 has a monotonically increasing thickness in the vertical direction on the sidewall 16 of the trench 12, the vertical direction being perpendicular to the first main surface 13 and extending from the first main surface 13 towards the base 15 of the trench 12. This structured field dielectric 30 enables the doping level of the mesa formed between the trenches 12 to be increased while maintaining the blocking ability of the transistor device 11 and allowing for an increase in the performance of the transistor device 11.

[0045] Figure 1B An enlarged view of the trench 12 including the field plate 17 and the field dielectric 30 according to another embodiment is illustrated. This embodiment of the field dielectric 30 and the field plate 17 can be used in Figure 1A the transistor device 11 illustrated in Figure 1A to replace the field dielectric 30 and the field plate 17 shown in

[0046] Depending on the lateral shape of the trench 12, the sidewall 16 may have sub-segment regions. For example, a circular columnar trench has a single sidewall 16, while an elongated trench that is rectangular in a plan view has four sidewall segment regions arranged perpendicular to each other.

[0047] In an embodiment, in the upper segment region 27 of the sidewall 12, the field dielectric 30 has a first thickness t1, and in the lower segment region 29 of the sidewall 12, the field dielectric 30 has a thickness t2, where the thickness t2 is greater than the first thickness t1. The difference between the first thickness t1 and the second thickness t2 is greater than the difference caused by the inherent variations in the processing conditions and is at least 10%. In other words, the difference between t1 and t2 is at least 10% of the thickness t1, or (t2 - t1) / t1 * 100 ≥ 10%. In another embodiment, (t2 - t1) / t1 * 100 ≥ 20%. The intermediate segment region 28 of the sidewall represents the vertical difference where the thickness of the field dielectric 30 increases from the smaller thickness t1 to the larger thickness t2. The first thickness t1 may be the average thickness of the field dielectric 30 located on the upper segment region 27, and the second thickness t2 may be the average thickness of the field dielectric 30 located on the lower segment region 29 of the sidewall 16. The variation of the thickness t1 is less than 5% of the thickness t1, i.e., 0.95t1 < t1 < 1.05t1. The variation of the thickness t2 is less than 5% of the thickness t2, i.e., 0.95t2 < t2 < 1.05t2.

[0048] Over the vertical distance of the intermediate segment region 28 of the sidewall 16, the thickness of the field dielectric 30 changes from the first thickness t1 at the first boundary 31 formed between the upper segment region 27 and the intermediate segment region 28 to the second thickness t2 at the second boundary 32 formed between the lower segment region 29 and the intermediate segment region 28. The second boundary 32 is edge-free. In other words, at the lower second boundary 32 between the greater thickness t2 at the bottom of the trench 12 and the reduced thickness of the field dielectric 30 in the intermediate segment region 28 of the trench, the field dielectric 30 does not include a sharp sudden change in thickness, that is, does not include an edge. The second boundary 32 is smooth and provides a smooth transition from the first thickness t1 to the increasing thickness in the vertical direction (i.e., perpendicular to the first main surface 13) as well as in the lateral direction parallel to the first main surface 13. The field dielectric 30 includes a curved form at the second boundary 32. The surface of the field dielectric 30 has a concave form at the first boundary 31 and a convex form at the second boundary 32. The second boundary 32 may have a radius of curvature, for example, a radius of curvature in the range of 100 nm and 500 nm, for example, approximately 300 nm. The first boundary 31 may have a radius of curvature, for example, a radius of curvature in the range of 100 nm and 500 nm, for example, approximately 300 nm.

[0049] In some embodiments, the recessed form extends around the entire perimeter of the trench 12 such that the surface of the field dielectric 30 includes a groove having the radius of curvature. In some embodiments, the protruding form extends around the entire perimeter of the trench 12 such that the surface of the field dielectric 30 includes a ridge having the radius of curvature.

[0050] Since the field plate 17 fills the remainder of the trench 12 not occupied by the field dielectric 30, the field plate 17 has a profile complementary to the profile of the field dielectric. In Figure 1B the illustrated embodiment, the surface of the field plate 17 thus includes a protruding form at the first boundary 31 and a recessed form at the second boundary 32.

[0051] In some embodiments, the first boundary 31 formed between the upper section region 27 and the middle section region 28 is also edge-free. In this embodiment, the transition between the thinner section of the field dielectric 30 in the upper section region 27 of the trench and the increased thickness in the middle section region 28 is smooth, e.g., having a curved form, and may have a radius of curvature in the range of 100 nm and 500 nm, e.g., approximately 300 nm.

[0052] As Figure 1B shown, the angle α 2 is formed between the surface of the field dielectric 30 located in the middle section region 28 of the sidewall 16 and the surface of the field dielectric 30 located in the lower section region 29 of the sidewall 16. The angle α 2 is measured between a first line 51 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the middle section region 28 and a second line 52 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the lower section region 29. 2 The angle α 2 is between 180° < α 2 < 270° or 200° ≤ α

[0053] Also as Figure 1B shown, the angle α 1 is formed between the surface of the field dielectric 30 located in the upper section region 27 of the sidewall 16 and the surface of the dielectric 30 located in the middle section region 28 of the sidewall 16. The angle α 1 is measured between a third line 53 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the upper section region 27 and the second line 51 at a point on the surface of the field dielectric 30 having the maximum gradient within the middle section region 28 of the sidewall 16. 1 The angle α 1 is between 90° < α 1 < 180° or 100° ≤ α

[0054] The field plate 17 fills the remainder of the trench 12 not occupied by the field dielectric 30. The field plate 17 is formed of a conductive material such as polysilicon. The field plate 17 has a lower section region 35 having a width W2 that is less than the width W1 of the upper section region 36, and the upper section region 36 is arranged adjacent to the upper section region 27 of the sidewall 16 of the trench 12. The field plate 17 includes an intermediate transition region 37 adjacent to the intermediate section region 28 of the sidewall 16 of the trench 12, and the intermediate transition region 37 has a seamless boundary between the lower section region 35 and the intermediate section region 37 and may also have a seamless boundary between the intermediate section region 37 and the upper section region 36.

[0055] The seamless shape of the field dielectric 30 at the second boundary 31 and optionally also at the first boundary 31 avoids peaks in the electric field and further improves the reliability and performance of the transistor device 11.

[0056] By using the following method, a seamless transition at the second boundary 32 and at the first boundary 31 (if the first boundary 31 exists) can be fabricated: An initial field dielectric layer 30' is formed on the substrate 15 and the sidewall 16 of the trench, and the initial field dielectric layer 30' has a substantially uniform thickness from the first main surface 13 to the substrate 15. Species (e.g., Ar ions) are implanted into regions of the initial field dielectric layer 30', e.g., into the surface of the initial field dielectric layer 30' disposed on the upper region of the trench 12 to form: an upper portion of the initial field dielectric layer 30' having a damaged structure due to the implanted ions; and a lower section region of the field dielectric 30 having an undamaged structure since this lower section region has not been subjected to ion implantation. In some embodiments, the damaged structure may have a crystalline structure with weakened chemical bond strength. For the same etching time and conditions, during a wet chemical etching process, the damaged implanted portion has a higher etching rate compared to the undamaged non-implanted portion. Thus, when the initial field dielectric layer 30' is subsequently subjected to etching, for the same etching time and conditions, more material is removed from the upper damaged section region compared to the lower non-damaged section region due to the higher etching rate of the (one or more) damaged field dielectric regions 30' compared to the etching rate of the non-implanted portion. This results in the field dielectric structure 30 having a smaller thickness t1 in the upper section region and a greater thickness t2 in the lower section region of the sidewall 16.

[0057] As a result of this implantation method, no abrupt transition occurs between the implanted and non-implanted regions. Instead, a smoother transition is formed from the portion of the initial field dielectric layer 30' with a higher ion concentration to the portion with a lower ion concentration. Thus, the etching rate of the field dielectric 30' varies more smoothly between the implanted and non-implanted regions. This can be used to form a smooth transition between a smaller thickness t1 and a larger thickness t2 in the vertical direction. The intermediate section region 28 is formed in the vertical direction between the upper section region 27 adjacent to the first main surface 13 and the lower section region 29 extending from the substrate 15. In the upper section region 27, the field dielectric 30 has a thickness t1, and in the lower section region 29, the field dielectric 30 has a thickness t2. This method results in: a first boundary 31 between the upper section region 27 and the intermediate section region 28 of the field dielectric 30, which is edge-free; and a second boundary 32 between the intermediate section region 28 and the lower section region 27 of the field dielectric 30, which is edge-free and smooth.

[0058] In some embodiments, the upper section region of the field dielectric 30 disposed on the upper section region 27 of the sidewall 16 includes ions left from the implantation process, such as Ar ions, while the lower section region of the field dielectric 30 disposed on the lower section region 29 of the sidewall 16 includes a lower concentration of ions and may not have Ar ions because ions are not directly implanted into this region. Since a portion of the ions may be reflected from the implantation site, a lower concentration of ions from this reflected portion may be present in other regions outside the implantation site (such as the lower section region of the field dielectric 30 on the sidewall and the field dielectric 30 on the substrate 15 of the trench 12).

[0059] In some embodiments, the profile of the field dielectric 30 is substantially uniform laterally. For example, the field dielectric 30 has a substantially uniform thickness around the longitudinal axis L of the columnar trench 12, or the field dielectric 30 has a substantially uniform thickness around the central plane of the elongated trench 12, and the central plane extends along the length and is perpendicular to the first main surface 13.

[0060] Figure 1C The illustrated comparison trench 12 has a field plate 17 and a field dielectric 30 on the sidewall 16 and the substrate 15 of the trench 12. The field dielectric 30 has a comparison field dielectric profile 70, and the comparison field dielectric profile 70 includes a sudden step 71 in terms of the field dielectric thickness. In this comparison trench 12, the angle α 1 = 90° is formed between a third line 53 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the upper section region 27 and a second line 51 at a point on the surface of the field dielectric 30 having the maximum gradient within the intermediate section region 28 of the sidewall 16.

[0061] For use as Figure 1COne method of forming a sudden stepped vertical thickness difference in the field dielectric 30 as shown in the comparison trench 12 includes: depositing a thick field dielectric on the sidewalls and the substrate of the trench, filling the trench by depositing a sacrificial material (e.g., polysilicon), planarizing, for example, by chemical mechanical polishing (CMP), removing a portion of the polysilicon to form a recess having a target depth, partially removing the exposed region of the field dielectric only in the region exposed by the recessed sacrificial material by wet etching, removing the remaining portion of the sacrificial material, and filling the trench having the structured field dielectric with polysilicon. This method enables processing a field dielectric 30 having a discrete step in thickness on the sidewall 16 of the trench 12. This method results in a very sudden step 71 in the field dielectric surface, which results in unwanted electric field peaks. As Figure 1C shown, the angle α 1 is formed between the surface of the field dielectric 30 located on the upper section region 72 of the sidewall 16 and the surface of the field dielectric 30 located in the lower section region 74 of the sidewall 16. The angle α is measured between a third line 53 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the upper section region 72 and a second line 51 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the middle section region 73 1 . The angle α 1 is 90°. The angle α is formed between a second line 51 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the middle section region 73 and a second line 52 or tangent at a point on the surface of the field dielectric 30 having the maximum gradient within the lower section region 74 2 . α 2 = 270°.

[0062] In Figure 1C the comparison trench, the angle α 1 = 90° and α 2 = 270° can thus be distinguished from the angle α Figure 1B as shown in 1 and α 2 , as Figure 1B shown in 1 and α 2 which are respectively greater than 90° and less than 270°.

[0063] Figure 1D The figure shows a semiconductor device 10 including a transistor device 11, where the gate electrode 21 and the field plate 17 are disposed in the same trench 12, rather than as Figure 1AIn the illustrated embodiment, they are disposed in separate gate trenches. The gate electrode 21 is arranged above the field plate 17 within the trench 12, and is electrically insulated from the field plate 17 by an intermediate dielectric layer 38, and is electrically insulated from the semiconductor substrate 10 by a gate dielectric 23 located on the upper section region of the sidewall 16 of the trench 12. In this embodiment, the gate electrode 21 is arranged in the upper section region 27 of the trench 12.

[0064] The transistor device 11 generally includes a plurality of trenches 12, and each trench 12 includes a field plate 17. In an embodiment where the trenches 12 and the field plates 17 therein are columnar, the trenches 12 (and thus, the field plates 17) can be arranged in a regular array, such as a square grid array.

[0065] Figure 2 A top view of a portion of a semiconductor device according to an embodiment is illustrated, and four columnar trenches 12 are illustrated. The four columnar trenches 12 are formed in the first main surface 13 of the substrate 14 and are arranged in a square grid array. Using a Cartesian coordinate system, the first main surface 13 of the substrate 14 lies in the x-y plane, and using a Cartesian coordinate system, the depth of the trench 12 and the sidewall 16 of the trench 12 extend in the z direction. In this example, each trench 12 has a circular form in the top view and includes a columnar field plate 17 having a circular profile. The pitch, which is the center-to-center distance between two adjacent trenches 12 in the x direction and in the y direction, is d. The distance between two columnar trenches 12 in a direction at 45° with respect to the x direction and in a direction at 45° with respect to the y direction (which directions can be referred to as diagonal directions) is greater than d, that is, d√2.

[0066] In Figure 2 the illustrated embodiment, the thickness of the field dielectric 30 on the sidewall 16 of the first main surface 13 is substantially uniform around the longitudinal axis L. In other words, the thickness of the field dielectric 30 is uniform laterally on the first main surface 13. The thickness of the field dielectric 30 varies in the vertical z direction parallel to the longitudinal axis L. In some embodiments, for example, according to the embodiment described with reference to FIG. 1, the thickness of the field dielectric 30 varies in the vertical direction along the height of the sidewall 16.

[0067] FIG. 3 illustrates an embodiment of the transistor device 11. The transistor device 11 includes at least one columnar trench, and the columnar trench includes a columnar field plate 17, wherein the thickness of the field dielectric 30 is non-uniform laterally and varies around the longitudinal axis L in at least one plane parallel to the first main surface. The sidewall 16 of the columnar trench 12 has a perimeter, and the thickness of the field dielectric 30 varies at different points along the perimeter of the sidewall 16 in at least one plane parallel to the first main surface.

[0068] In some embodiments, the thinner thickness t1 of the field dielectric 30 on the upper section region 27 of the sidewall 16 of the trench 12 is non-uniform laterally and varies around the longitudinal axis L in at least one plane parallel to the first main surface.

[0069] The lateral variation in the thickness of the field dielectric 30 on the sidewall 16 of the trench 12 may be non-uniform in the vertical direction. For example, the difference between the maximum and minimum lateral thicknesses varies along the height of the sidewall 16. The difference between the maximum and minimum lateral thicknesses in the middle section region 28 may be greater than the difference between the maximum and minimum lateral thicknesses in the upper section region 27.

[0070] In some embodiments, the thickness t1 of the field dielectric 30 in the upper section region 27 varies at different points along the perimeter of the sidewall 16 in at least one plane parallel to the first main surface 13 in the upper section region.

[0071] In some embodiments, the thickness of the field dielectric 30 in the middle section region 28 varies at different points along the perimeter of the sidewall 16 in at least one plane parallel to the first main surface 13 in the middle section region 28. The variation in the thickness in at least one plane parallel to the first main surface 13 in the middle section region 28 may be greater than the variation in the thickness in at least one plane parallel to the first main surface 13 in the upper section region.

[0072] In some embodiments, the variation in the thickness of the field dielectric in at least one plane parallel to the first main surface 13 in the middle section region 28 may be greater than the variation in the thickness of the field dielectric in at least one plane parallel to the first main surface 13 in the upper section region, and the variation in the thickness of the field dielectric in at least one plane parallel to the first main surface 13 in the lower section region 29 may be greater than the variation in the thickness of the field dielectric in at least one plane parallel to the first main surface 13 in the upper section region and less than the variation in the thickness of the field dielectric in at least one plane parallel to the first main surface 13 in the middle section region 28.

[0073] In some embodiments, the second thickness t2 of the field dielectric 30 is substantially uniform laterally and is substantially constant around the longitudinal axis in at least one plane parallel to the first main surface 13.

[0074] In some embodiments, a combination of the first thickness t1 of the field dielectric 30 and the second thickness t2 of the field dielectric 30 is used, the first thickness t1 being non-uniform laterally and varying around the longitudinal axis L in at least one plane parallel to the first main surface 13, and the second thickness t2 being substantially uniform laterally and being substantially constant around the longitudinal axis L in at least one plane parallel to the first main surface 13.

[0075] Since the conductive material forming the field plate 17 fills the remaining portion of the trench 12, the columnar trench 12 includes a columnar field plate 17 that has a first width w1 in the upper section region 27 of the sidewall 16. The first width w1 varies laterally in a plane parallel to the first main surface 13 and around the longitudinal axis L of the trench 12.

[0076] The difference between the first thickness t1 and the second thickness t2 is greater than the difference caused by variations in the processing conditions and can be at least 10%. In other words, the difference between t1 and t2 is at least 10% of the thickness t1, i.e., (t2 - t1) / t1 * 100 ≥ 10%.

[0077] Similarly, in an embodiment where the thickness of the field dielectric 30 varies laterally (i.e., in at least one plane parallel to the first main surface 13 and around the longitudinal axis of the columnar trench 12), the thickness has a maximum thickness t max and a minimum thickness t min , and t max ≥ 1.1t min . The difference between the maximum thickness t max and the minimum thickness t min in the at least one plane is greater than the difference caused by the inherent and inevitable variations in the processing conditions.

[0078] Figure 3 includes Figures 3A to 3E , and illustrates an embodiment of the transistor device 11 in which the thickness of the field dielectric 30 varies laterally, i.e., in at least one plane parallel to the x - y plane of the first main surface 13, and optionally also varies in the vertical direction. The transistor device 11 shown in Figure 3 has columnar trenches 12 arranged in a square grid array, and each columnar trench 12 has a circular shape in a top view. Four columnar trenches 12 are shown in Figure 3A . However, in other unillustrated embodiments, the columnar trenches 12 of the transistor device 11 may have a shape other than circular in a top view, such as hexagonal or octagonal, and may be arranged in another type of regular array that is not a square grid array, such as a non - staggered grid array.

[0079] Figure 3A Illustrates a top view, Figure 3B illustrates a cross - sectional view along line A - A shown in Figure 3A according to the first embodiment, Figure 3C illustrates a cross - sectional view along line A - A shown in Figure 3A according to the second embodiment, Figure 3D illustrates a cross - sectional view along line B - B of the embodiment illustrated in Figure 3C , and Figure 3E illustrates a cross - sectional view along line C - C’ of the embodiment illustrated in Figure 3C .

[0080] As can be seen in the top view of Figure 3A , the thickness of the field dielectric 30 in the 45° direction of the square grid array is less than the thickness of the field dielectric 30 in the orthogonal x and y directions of the square grid array. Since the conductive material forming the field plate 17 fills the remainder of the columnar trench 12, the field plate 17 can be regarded as having four equally spaced lobes, with the peak of each lobe aligned in the 45° direction. This lateral form lies in at least one plane parallel to the first main surface 13 and can be substantially the same at a certain depth (e.g., the upper part 27 of the sidewall 16) in the vertical direction (i.e., perpendicular to the first main surface).

[0081] The field dielectric 30 has: a minimum thickness t min , the minimum thickness t min is aligned such that it extends along the 45° direction; and a maximum thickness t max , the maximum thickness t max is aligned in the x and y directions. In an embodiment, t max ≥1.1t min . The difference between the maximum thickness t max and the minimum thickness t min in the at least one plane is greater than the difference caused by the inherent and inevitable variations in the processing conditions. The maximum thickness t max can be the same as, or less than, the thickness of the field dielectric 30 on the lower section region of the sidewall 16 of the trench.

[0082] In some embodiments, in addition to Figure 3A the lateral variation in the thickness of the field dielectric 30 shown in the top view of Figures 3B to 3E A cross-sectional view of an embodiment of the trench 12 is illustrated, in which the thickness of the field dielectric 30 varies in the lateral direction as shown in Figure 3A and in the vertical direction.

[0083] Figure 3B A cross-sectional view of the trench 12 according to an embodiment taken along the plane A-A shown in Figure 3A is illustrated, in which the thickness of the field dielectric 30 increases monotonically from the first main surface 13 in the direction of the substrate 15, i.e., monotonically increases in the z direction. In the cross-sectional view along the line A-A, the field plate 17 has a funnel shape and has a larger area at the first main surface 13 compared to its base.

[0084] In other embodiments (such as the embodiment illustrated in Figure 3C ), in addition to Figure 3AIn addition to the lateral profile shown in FIG. 1 , the field dielectric 30 also has Figure 1B The vertical profile shown in .

[0085] Figure 3C The figure shows the 45° diagonal direction of the square grid array. Figure 3A 1 is a cross-sectional view of the trench 12 in the plane AA shown in . In such a 45° direction, for example, in the first major surface 13 or in a plane substantially parallel to the upper surface 13 and located in the upper segment 27 of the sidewall 16, the field dielectric 30 has its minimum thickness. The field dielectric 30 also includes a segment having a thickness t1 on the upper segment 27 of the sidewall 16, the thickness t1 being less than the thickness t2 of the field dielectric 30 on the lower segment 29 of the sidewall 16, and the field dielectric 30 has an intermediate or transition segment 28 extending between the upper segment 27 and the lower segment 29, so that a first boundary 31 between the upper segment 27 and the intermediate segment 28 and a second boundary 32 between the intermediate segment 28 and the lower segment 29 provide a smooth edgeless transition.

[0086] Figure 3D The groove 12 is shown Figure 3A 2. The cross-sectional view in plane BB is shown in FIG. 2. The plane BB extends in the y direction. The field dielectric 30 has its maximum thickness on the sidewalls 16 of the trench in the upper section region 27.

[0087] Figure 3E Graphics Figure 3C Along the lines of Figure 3A The cross-sectional view of the line CC' is shown in FIG. The cross-sectional view CC' extends through the peak of the petal and extends between two adjacent petals. Figure 3E The thickness of the field dielectric 30 and the width of the field plate 17 are shown to be laterally non-uniform around the longitudinal axis L. At the first main surface 13, the field dielectric 30 has a thickness t in the diagonal 45° direction. min , and has t in the x direction max .

[0088] A method for processing a field dielectric in a trench in a semiconductor device (eg, a transistor device) will now be described with reference to FIG. 4 , which includes Figures 4A to 4F The method can be used to manufacture a field plate 17 and a field dielectric 30 having a form as described with reference to and as shown in one of FIGS. 1 to 3 .

[0089] A semiconductor device 10 is provided, which includes at least one trench formed in a first main surface 13 of a semiconductor substrate 14. Each trench 12 has a base 15 and a sidewall 16 extending from the base 15 to the first main surface 13. The trench 12 may be stripe-shaped or column-shaped. The semiconductor device 10 may be used to process a transistor device.

[0090] Referring to Figure 4A , an initial field dielectric layer 30' is formed over the base 15 and sidewalls 16 of each of the trenches 12 in the trench 12. In some embodiments, as Figure 4B shown in, another layer 40 of the material of the initial field dielectric layer 30' may be deposited over the initial field dielectric layer 30' to increase the thickness. Referring to Figure 4C , species (such as, argon ions) are implanted into a first segment region 41 of the initial field dielectric 30' and the another layer 40 (if the another layer 40 is present) disposed on the sidewalls 16 of the trench 12, as schematically indicated by the arrow 42. In particular, the species may be implanted into the upper segment region 41 of the field dielectric 30, and the upper segment region 41 is disposed adjacent to the first main surface 13 on the sidewalls 16. In some embodiments, the species may also be implanted into the portion of the initial field dielectric layer 30' that extends over the first main surface 13. For example, other regions of the field dielectric layer 30' towards the base 15 of the trench 12 are not directly implanted. The species may be reflected from the initial implantation site into other regions, such as into the field dielectric layer 30' on the base 15 of the trench 12 or on the opposite segment region of the sidewall of the trench. These regions into which the reflected ions impinge include a lower concentration of ions compared to the initial implantation site, and thus, have a lower etching rate compared to the initial implantation site.

[0091] In an embodiment, prior to the damage implantation process, a sacrificial material is deposited in the trench 12. The upper portion of this sacrificial material may be removed to form a recess having a certain depth d. This sacrificial material or layer shields the covered region of the field dielectric at the bottom of the trench from being implanted, and leaves other regions, such as the transition segment region and the upper segment region of the sidewall, exposed, so that these exposed regions of the field dielectric are implanted with the species. After the implantation, the remaining portion of the sacrificial material is removed. In this way, the shielded field dielectric regions do not have an increased etching rate, and after the etching process, remain thicker compared to the (one or more) exposed and implanted regions.

[0092] Referring to Figure 4D , the field dielectric 30 is then etched, that is, at least the segment region of the initial field dielectric layer 30' into which the species are implanted is etched. Wet chemical etching or plasma etching may be used. For the same etching conditions, the implanted region of the field dielectric layer 30' has a higher etching rate compared to the non-implanted region. Therefore, compared to in the non-implanted region, the rate of removal of the field dielectric material is greater in the implanted region, so that the thickness reduction is greater in the implanted region compared to in the non-implanted region. Thus, using a single etching process, a structured field dielectric 30 having a non-uniform thickness is formed.

[0093] Referring to Figure 4E, Subsequently, a conductive material is inserted into the at least one trench 12 to form a field plate 17. The conductive material fills the remaining portion of the trench 12 not occupied by the structured field dielectric 30. Thus, the profile of the field plate 17 has an outer profile complementary to the profile of the surface of the field dielectric 30.

[0094] Etching of the field dielectric 30 in at least the first section region 41 can result in the formation of a field dielectric 30 having a first thickness t1 on the upper section region 27 of the sidewall 16 and a second thickness t2 on the lower section region 29 of the sidewall, whereby the second thickness t2 is greater than the first thickness t1. The difference between t2 and t1 is greater than the inherent variation caused by process variations, such that (t2 - t1) / t1 * 100 ≥ 10%. In the intermediate section 28 of the sidewall 16 arranged between the lower section region 28 and the upper section region 27, the thickness of the field dielectric 30 varies from a first thickness t1 at a first boundary 31 between the upper section region 27 and the intermediate section region 28 to a second thickness t2 at a second boundary 32 located between the lower section region 29 and the intermediate section region 28. The second boundary 32 is edge-free and thus smooth. The first boundary 31 can also be edge-free and thus smooth.

[0095] The first section region 41 into which species are implanted has a height, which is a dimension in the z direction perpendicular to the first main surface 13, and this height is less than the height of the field dielectric 30 arranged on the sidewall 16 of the trench 12. In other words, at least one section region of the field dielectric 30 is not implanted with species. Generally, the section region of the field dielectric 30 arranged on the lower part 29 of the sidewall 16 of the trench 12 is not subjected to the implantation process.

[0096] With reference to Figures 4A to 4E The method described can be used to process a trench 12 having a field dielectric layer 30, the field dielectric layer 30 being arranged over the entire sidewall 16 but having a thickness that varies in the vertical direction, that is, in a direction perpendicular to the first main surface 13, for example, the thickness increases in the direction from the first main surface 13 to the base 15 of the trench 12. In some embodiments, the method can be implemented such that the field dielectric 30 has a thickness that varies laterally, that is, varies in at least one plane parallel to the first main surface 13. In some embodiments, the first section region 41 of the initially implanted field dielectric layer 30' has a lateral extent that is less than the extent of the inner profile of the field dielectric 30. For example, if the trench 12 is a columnar trench having a circular lateral form, the initial field dielectric 30' also has an annular shape, and species are implanted into the lateral arc section region 41 of the ring, and the lateral arc section region 41 is less than the inner perimeter of the initial field dielectric 30'.

[0097] The combination can be used such that the thickness of the field dielectric 30 is non-uniform in the vertical z-direction and also non-uniform in the lateral direction (i.e., in the x-y plane), as shown, for example, in FIG. 3.

[0098] Figure 4F FIG. shows a schematic illustration of a semiconductor wafer 100 and a possible orientation of an ion beam 101 that is used to implant species into the field dielectric 30. Using a Cartesian coordinate system, a first major surface 13 of the wafer 100 is disposed in the xy-plane, and the z-direction is orthogonal to the first major surface 13 and the x- and y-directions. The ion beam 101 is directed onto the first major surface 13, and the orientation can be selected to include an angle of tilt with respect to the z-axis and an angle of rotation with respect to the y-axis or the x-axis.

[0099] For example, in order to form Figure 3A the four-lobe structure of the field plate 17 illustrated in, the ion beam 101 can be directed towards the first major surface 13 of the wafer 100 at four different rotation angles that are separated by 90°. The tilt angle can be adjusted so as to adjust the depth of the ion beam impinging on the surface of the field dielectric 30 within the trench 12 with respect to the first major surface 13. A smaller tilt angle enables the ion beam 101 to impinge on the surface of the field dielectric 30 at a greater depth with respect to the first major surface 13, and a wider (larger) tilt angle enables the ion beam 101 to impinge on the surface of the field dielectric 30 at a smaller depth with respect to the first major surface 13.

[0100] In order to increase the extent in the vertical z-direction of the region 41 that is formed using ion implantation, implantation can be carried out at two or more different tilt angles while the wafer 100 is at the same rotation angle.

[0101] Figure 5A FIG. illustrates an example of a method in which implantation of species (such as Ar ions) in the field dielectric 30 disposed on the sidewalls 16 of the trench 12 is carried out at two or more tilt angles. The trench 12 can be columnar or elongated. At one or more predetermined rotation angles, implantation of species at two or more tilt angles can be carried out. In this embodiment, as shown, for example, in Figure 3A the field dielectric 30 can also have a laterally varying thickness on the sidewalls 16, for example, in the first major surface 13, in at least one plane.

[0102] In an embodiment, a first implantation is performed at a first tilt angle, as illustrated by arrow 60, and a second implantation is performed at a second tilt angle, as illustrated by arrow 61. The first tilt angle is less than the second tilt angle, such that the first implanted region 41 of the field dielectric 30t is at a greater depth relative to the first major surface 13 than the second region 44 into which ions are implanted during the second implantation. In some embodiments, a single etch process is used to perform the first and second implantations. After the single etch process, a structured field dielectric 30 having two regions of different thicknesses is formed on the sidewall 16 in the vertical direction.

[0103] In some embodiments, more than two implantations may be performed at different tilt angles, followed by a single etch process to form a structured field dielectric having more than two regions of different thicknesses on the sidewall 16 of the trench.

[0104] In some embodiments, after the first implantation, a first etch process is performed, then the second implantation is performed, and then the second etch process is performed. Separate etch processes may be used after each of the two or more implantations to form a field dielectric profile having a more significant variation in thickness between adjacent regions of the field dielectric.

[0105] In an example, with a first dose of 1e15 / cm 2 at an energy of 200 keV and a tilt angle of 10°, and then with a second dose of 1e15 / cm 2 at an energy of 300 keV and a tilt angle of 20°, Ar ions may be implanted into the field dielectric 30'. After the implantation process has been completed, a single etch process is then performed. The etch rate of the lower region 41 implanted with the second dose is less than the etch rate of the upper region 44 implanted with the first dose. Thus, after etching, the thickness of the field dielectric 30 remaining in the upper region is less than the thickness of the field dielectric 30 remaining in the lower region of the sidewall 16. In the example, after the etch process, the field dielectric 30 may have a thickness of 900 nm on the base 15 of the trench 12, a thickness of 940 nm on the lower segment region 29 of the sidewall 16, and a thickness of 760 nm on the upper segment region 27 of the sidewall 16 of the trench 12.

[0106] In other embodiments, three or more different tilt angles may be used.

[0107] A method including multiple implantations may be used to achieve a profile of the field dielectric 30 that monotonically increases from the first major surface 13 in a direction toward the base 15 of the trench 12, such as Figure 1A 、 3Bas shown in FIGS. 5A or 5B. These methods can be used to process the field dielectric 30 having a continuous taper such that the thickness continuously and monotonically increases in the direction from the first major surface 13 towards the substrate 15 of the trench 12, e.g., as Figure 3B shown.

[0108] At one or more predetermined rotation angles, implantation of species at multiple tilt angles can be performed. In this embodiment, the field dielectric 30 can also have a laterally varying thickness on the sidewalls 16 in at least one plane (e.g., on the first major surface 13), such as, e.g., Figure 3A shown, and the field dielectric 30 can also have a thickness varying in the vertical direction, as Figure 3B shown.

[0109] Figure 5B An example of the illustrated method, where four implantations are successively performed at the same rotation angle to form a field dielectric having a continuous taper. Using the Figure 5B arrows 62, 63, 64, 65 in, the four implantations are schematically indicated. The first implantation 62 of Ar ions uses a dose of 1e16 / cm 2 at an energy of 300 keV at a tilt angle of 7°, the second implantation 63 of Ar ions uses a dose of 1e16 / cm 2 at an energy of 300 keV at a tilt angle of 10°, the third implantation 64 of Ar ions uses a dose of 1e16 / cm 2 at an energy of 300 keV at a tilt angle of 15°, and the fourth implantation 65 of Ar ions uses a dose of 1e16 / cm 2 at an energy of 300 keV at a tilt angle of 20°. A single etching process is then performed. As an example, the thickness of the field dielectric on the sidewalls can increase from 530 nm at the first major surface to 710 nm at a depth of 5550 nm relative to the first major surface. The thickness on the substrate 15 of the trench 12 can be approximately 900 nm.

[0110] At one or more predetermined rotation angles, implantation of species at four tilt angles can be performed. In this embodiment, the field dielectric 30 can also have a laterally varying thickness on the sidewalls 16 in at least one plane (e.g., on the first major surface 13), such as, e.g., Figure 3A shown, and the field dielectric 30 can also have a thickness varying in the vertical direction, as Figure 3B shown.

[0111] These methods including multiple implantations into the field dielectric 30' on the sidewalls can be used to process the field dielectric 30 having regions of different thicknesses, whereby the thickness is substantially constant within each region and the field dielectric 30 has a smooth edge-free transition between adjacent regions of different thicknesses, e.g., asFigure 1B , 3C as shown in 3D and 3E.

[0112] In summary, a method of field dielectric structuring using damage injection is provided. A field dielectric structure is provided on the sidewalls of the trench 12, the field dielectric structure having a smooth curved transition between regions of different thicknesses, i.e., no edge boundaries. The performance of transistor devices including field plates for charge compensation in the trench is improved, the field plates having a profile complementary to the profile of such structured field dielectrics.

[0113] While the present disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of the present disclosure.

[0114] Example

[0115] 1. A semiconductor device including a transistor device, the transistor device comprising:

[0116] One or more trenches formed in a first major surface of a semiconductor substrate, each of the one or more trenches including:

[0117] A base and sidewalls extending from the base to the first major surface, the sidewalls including an upper section region, a lower section region, and an intermediate section region located between the lower section region and the upper section region,

[0118] A field plate located in the trench, and

[0119] A field dielectric located on the base and the sidewalls of the trench and having a surface;

[0120] Wherein, in the upper section region of the sidewall, the field dielectric has a first thickness,

[0121] Wherein, in the lower section region of the sidewall, the field dielectric has a second thickness greater than the first thickness,

[0122] Wherein, in the intermediate region of the sidewall, the thickness of the field dielectric varies from the first thickness at a first boundary between the upper section region and the intermediate section region to the second thickness at a second boundary between the lower section region and the intermediate section region,

[0123] Wherein the surface of the field dielectric has a concave form at the first boundary between the upper section region and the intermediate section region and a convex form at the second boundary between the lower section region and the intermediate section region, and

[0124] Wherein the second boundary is edge - free.

[0125] 2. The semiconductor device as described in Example 1, wherein the recessed form at the first boundary has a first radius of curvature of 100 nm to 500 nm.

[0126] 3. The semiconductor device as described in Example 1 or Example 2, wherein the protruding form at the second boundary has a radius of curvature of 100 nm to 500 nm.

[0127] 4. The semiconductor device as described in any one of Examples 1 to 3, wherein the trench has a depth d, where 500 nm ≤ d ≤ 20 μm.

[0128] 5. The semiconductor device as described in any one of Examples 1 to 4, wherein the angle (α 2 ) is formed between the surfaces of the field dielectrics in the middle section region and the lower section region, where 180° < α 2 < 270° or 200° ≤ α 2 ≤ 250°.

[0129] 6. The semiconductor device as described in any one of Examples 1 to 5, wherein the angle α 2 is formed between the line of the point of the maximum gradient of the surface of the field dielectric in the middle section region and the line of the point of the maximum gradient of the surface of the field dielectric in the lower section region, where 180° < α 2 < 270° or 200° ≤ α 2 ≤ 250°.

[0130] 7. The semiconductor device as described in any one of Examples 1 to 6, wherein the angle α 1 is formed between the surfaces of the field dielectrics in the upper section region and the middle section region, where 90° < α 1 < 180° or 100° ≤ α 1 ≤ 150°.

[0131] 8. The semiconductor device as described in any one of Examples 1 to 7, wherein the angle α 1 is formed between the line of the point of the maximum gradient of the surface of the field dielectric in the upper section region and the line of the point of the maximum gradient of the surface of the field dielectric in the middle section region, where 90° < α 1 < 180° or 100° ≤ α 1 ≤ 150°.

[0132] 9. The semiconductor device as described in any one of Examples 1 to 8, wherein the first boundary is edge - free.

[0133] 10. The semiconductor device as described in any one of Examples 1 to 9, wherein the first boundary is curved.

[0134] 11. The semiconductor device according to any one of Examples 1 to 10, wherein the first boundary has a radius of curvature.

[0135] 12. The semiconductor device according to any one of Examples 1 to 12, wherein 100 to 500 nm the radius of curvature is formed between the surface of the field dielectric in the middle section region of the sidewall and the surface of the field dielectric in the lower section region of the sidewall.

[0136] 13. The semiconductor device according to any one of Examples 1 to 12, wherein 100 to 500 nm the radius of curvature is formed between the surface of the field dielectric in the middle section region of the sidewall and the surface of the field dielectric in the upper section region of the sidewall.

[0137] 14. The semiconductor device according to any one of Examples 1 to 13, wherein the trench is a columnar trench and the field plate is a columnar field plate.

[0138] 15. The semiconductor device according to Example 14, wherein the columnar trench includes a longitudinal axis, and the first thickness of the field dielectric varies around the longitudinal axis in at least one plane parallel to the first main surface.

[0139] 16. The semiconductor device according to claim 15, wherein the second thickness of the field dielectric is substantially constant around the longitudinal axis in at least one plane parallel to the first main surface.

[0140] 17. The semiconductor device according to any one of Examples 14 to 16, wherein the shape of the field plate is non - convex in at least one plane parallel to the first main surface.

[0141] 18. The semiconductor device according to any one of Examples 14 to 17, wherein the columnar trench is circular in a top view.

[0142] 19. The semiconductor device according to any one of Examples 14 to 18, wherein the columnar trench is circular in a top view, and the field dielectric has a thickness on the sidewall of the columnar trench, and the thickness is non - uniform in at least one plane parallel to the first main surface.

[0143] 20. The semiconductor device according to any one of Examples 14 to 19, wherein the thickness of the field dielectric on the sidewall of the columnar trench is non - uniform in a plane coplanar with the first main surface.

[0144] 21. The semiconductor device according to any one of Examples 1 to 20, wherein the difference between the first thickness and the second thickness is greater than 10%.

[0145] 22. The semiconductor device according to any one of Examples 14 to 21, wherein the columnar field plate has a width that varies at an angle around the rotation axis.

[0146] 23. The semiconductor device according to any one of Examples 14 to 22, wherein the thickness of the field dielectric varies between a minimum thickness t min and a maximum thickness t max , where t max ≥1.1t min .

[0147] 24. The semiconductor device according to any one of Examples 1 to 23, wherein in the upper section region of the sidewall, the field dielectric includes ions of a noble gas or Ar ions, and in the lower section region of the sidewall, the field dielectric on the sidewall does not include ions of a noble gas or Ar ions, or

[0148] in the upper section region of the sidewall, the field dielectric has a concentration of Ar ions of 1e17 cm -3 to 1e19 cm -3 , for example 1e18 cm -3 , and in the lower section region of the sidewall, the field dielectric has a concentration of Ar ions of 1e14 cm -3 to 1e16 cm -3 , for example 1e15 cm -3 .

[0149] 25. The semiconductor device according to any one of Examples 1 to 24, wherein the semiconductor substrate has a first conductivity type, and the mesa formed by the semiconductor substrate adjacent to the columnar trench includes a drift region of the first conductivity type, a body region of a second conductivity type opposite to the first conductivity type disposed on the drift region, and a source region of the first conductivity type disposed on or in the body region.

[0150] 26. The semiconductor device according to Example 25, further comprising: a gate trench formed in the first main surface of the mesa, wherein the gate trench includes a gate electrode, and the gate electrode is separated from the semiconductor substrate by a gate dielectric.

[0151] 27. A method of fabricating a semiconductor device, the semiconductor device comprising:

[0152] at least one trench located in a first main surface of a semiconductor substrate, the at least one trench having a base and sidewalls extending from the base to the first main surface, wherein the method includes:

[0153] forming a field dielectric over the base and the sidewalls of the at least one trench,

[0154] injecting a species into a first section region of the field dielectric disposed on the sidewalls,

[0155] Etch the field dielectric at least in the first section region.

[0156] Insert a conductive material into the at least one trench to form a field plate.

[0157] 28. The method according to Example 27, wherein etching the field dielectric at least in the first section region includes:

[0158] Form the field dielectric, the field dielectric having a first thickness in the upper section region of the sidewall and a second thickness in the lower section region of the sidewall, the second thickness being greater than the first thickness, wherein in an intermediate region of the sidewall disposed between the lower section region and the upper section region, the thickness of the field dielectric varies from the first thickness at a first boundary between the upper section region and the intermediate section region to the second thickness at a second boundary between the lower section region and the intermediate section region, and

[0159] wherein the second boundary is edge - free.

[0160] 29. The method according to Example 27 or Example 28, wherein the first section region has a certain height, the height being greater than the height of the field dielectric disposed on the sidewall of the trench.

[0161] 30. The method according to any one of Examples 27 to 29, wherein the first section region has a lateral extent, the lateral extent being less than the extent of the inner profile of the field dielectric.

[0162] 31. The method according to any one of Examples 27 to 30, wherein the trench is a columnar trench and the field plate is a columnar field plate.

[0163] 32. The method according to Example 31, wherein the columnar trench has a longitudinal axis, and etching the field dielectric at least in the first section region includes forming a field dielectric having a thickness around the longitudinal axis, the thickness being non - uniform in at least one plane parallel to the first main surface.

[0164] 33. The method according to any one of Examples 27 to 32, wherein etching the field dielectric at least in the first section region includes forming a field dielectric having a first thickness in the upper section region of the sidewall of the trench, the first thickness being non - uniform around the longitudinal axis in at least one plane parallel to the first main surface.

[0165] 34. The method according to any one of Examples 27 to 33, wherein the species is Ar ions.

[0166] 35. The method according to any one of Examples 27 to 33, wherein the species is one or more of the group consisting of Group 18 of the Periodic Table of the Elements, As ions, Ar ions, As, Pt, Ge, Kr, and Xe.

[0167] 36. The method according to any one of Examples 27 to 35, wherein the species is implanted using a dose of 1e13 / cm2 to 1e17 / cm2 and / or at an energy of 10 keV to 1000 keV.

[0168] 37. The method according to any one of Examples 27 to 36, wherein the method further comprises:

[0169] implanting the species into the first section region of the field dielectric located on the sidewall at a first tilt angle with respect to the first major surface;

[0170] implanting the species into the second section region of the field dielectric located on the sidewall at a second tilt angle with respect to the first major surface, the second section region overlapping or adjoining the first section region in the vertical direction, wherein the second tilt angle is greater than the first tilt angle.

[0171] 38. The method according to Example 37, further comprising: implanting the species into the third section region of the field dielectric located on the sidewall at a third tilt angle with respect to the first major surface, the third section region overlapping or adjoining the second section region in the vertical direction, wherein the third tilt angle is greater than the second tilt angle.

[0172] 39. The method according to any one of Examples 27 to 38, further comprising: depositing a field dielectric layer on the field dielectric, then implanting the species, and after implanting the species, etching the field dielectric layer and the field dielectric.

[0173] 40. The method according to any one of Examples 27 to 39, wherein

[0174] the thickness of the field dielectric continuously decreases / tapers in the direction from the base of the columnar trench towards the first major surface, or

[0175] the thickness of the field dielectric discontinuously decreases in the direction from the base of the columnar trench towards the first major surface and includes at least one step.

[0176] 41. The method according to any one of Examples 31 to 40, wherein a plurality of columnar grooves are provided, the plurality of columnar grooves being arranged in a square grid array having a pitch d in directions x and y and a pitch d√2 in the directions of x±45°, the directions x and y being parallel to the first main surface and extending perpendicular to each other, and the directions of x±45° being parallel to the first main surface and extending, wherein at an azimuth angle θ1 around the axis, species are implanted into a segment region of the field dielectric on the sidewall, and θ1 is aligned with the directions of x±45°.

[0177] 42. The method according to Example 41, further comprising: at an azimuth angle θ2 around the axis, implanting species into a segment region of the field dielectric located on the sidewall, wherein θ2 = θ1±45° and / or θ2 = θ1±180°.

[0178] 43. The method according to any one of Examples 31 to 42, wherein in the upper part of the columnar groove, the field dielectric has a thickness t1 in directions x and y and a thickness t2 in the diagonal directions of x±45°, where t2 < t1.

[0179] 44. The method according to any one of Examples 27 to 43, wherein the semiconductor substrate has a first conductivity type, and the mesa formed by the semiconductor substrate adjacent to the columnar groove includes a drift region of the first conductivity type, a body region of a second conductivity type opposite to the first conductivity type disposed on the drift region, and a source region of the first conductivity type disposed on or in the body region.

[0180] 45. The method according to Example 44, further comprising: a gate trench formed in the first main surface of the mesa, wherein the gate trench includes a gate electrode, and the gate electrode is separated from the semiconductor substrate by a gate dielectric.

[0181] 46. A semiconductor device including a transistor device, the transistor device comprising:

[0182] a plurality of columnar grooves formed in a first main surface of a semiconductor substrate, the columnar grooves including a columnar field plate and a field dielectric located in the columnar grooves,

[0183] wherein the columnar grooves include a base and sidewalls extending from the base to the first main surface, and the field dielectric is located on the base and sidewalls of the columnar grooves,

[0184] wherein the plurality of columnar grooves are arranged in a regular array having a center-to-center pitch p,

[0185] wherein the field dielectric has a thickness d1 on the sidewalls of the columnar trench in a lateral direction aligned with the center-to-center pitch p, and has a thickness d2 on the sidewalls of the columnar trench in a lateral direction not aligned with the center-to-center pitch p, where d2 < d1.

[0186] 47. The semiconductor device according to Example 46, wherein d1 and d2 are in a common plane parallel to the first main surface, and (d1 - d2) is greater than the process variation.

[0187] 48. The semiconductor device according to Example 46 or Example 47, wherein the columnar trenches each have a lateral square shape or a lateral circular shape or a lateral hexagonal shape or a lateral octagonal shape.

[0188] 49. The semiconductor device according to any one of Examples 45 to 47, wherein the plurality of columnar trenches are arranged in a square grid array, the square grid array having a center-to-center pitch p in directions x and y and having a spacing p√2 in the directions x ± 45°, the directions x and y being parallel to the first main surface and extending perpendicular to each other, and the directions x ± 45° extending parallel to the first main surface,

[0189] wherein the field dielectric has a thickness d1 on the sidewalls of the trenches in the lateral directions x and y and has a thickness d2 on the sidewalls of the trenches in the directions x ± 45°.

[0190] 50. The semiconductor device according to Example 49, wherein the columnar trenches each have a lateral square shape, and the corners of the lateral square shape are in the directions x ± 45.

[0191] 51. The semiconductor device according to any one of Examples 45 to 50, wherein the plurality of columnar trenches are arranged in a hexagonal grid array, the hexagonal grid array having a center-to-center pitch p in directions a and b, the directions a and b extending parallel to the first main surface and being 60° relative to each other, wherein the field dielectric has a thickness d1 on the sidewalls of the trenches in the lateral directions a and b and has a thickness d2 on the sidewalls of the trenches in the directions x ± 30°.

[0192] 52. A semiconductor device, comprising:

[0193] a plurality of columnar trenches formed in a first main surface of a semiconductor substrate, the columnar trenches including columnar field plates and a field dielectric located in the columnar trenches,

[0194] wherein the columnar trenches include a base and sidewalls extending from the base to the first main surface, and the field dielectric is located on the base and the sidewalls of the columnar trenches,

[0195] Wherein the plurality of columnar grooves are arranged in a square grid array, the square grid array having a pitch d in directions x and y and a pitch d√2 in directions x±45°, the directions x and y being parallel to the first major surface and extending perpendicular to each other, and the directions x±45° being parallel to the first major surface and extending,

[0196] Wherein the field dielectric has a thickness d1 on the sidewalls of the grooves in the lateral directions x and y and a thickness d2 on the sidewalls of the grooves in the directions x±45°, where d2 < d1, and where (d1 - d2) is greater than the process variation.

[0197] 53. The semiconductor device according to Example 52, wherein the field dielectric has a thickness d1 and a thickness d2 in a plane coplanar with the first major surface.

[0198] 54. The semiconductor device according to Example 52 or Example 53, wherein the columnar groove has a rotation axis extending perpendicular to the first major surface, and the thickness of the field dielectric on the sidewall varies according to an angular variation around the rotation axis.

[0199] 55. The semiconductor device according to Example 54, wherein the columnar field plate has a width that varies according to an angular variation around the rotation axis.

[0200] Spatial relative terms, such as "under", "below", "lower", "above", "upper", etc., are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to those depicted in the figures. Additionally, terms such as "first", "second", etc. are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Like terms always refer to like elements throughout the description.

[0201] As used herein, the terms "having", "including", "comprising", etc. are open-ended terms that indicate the presence of the stated element or feature, but do not preclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It should be understood that the features of the various embodiments described herein may be combined with each other unless specifically stated otherwise.

[0202] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A method for processing a semiconductor device, the semiconductor device comprising: At least one trench located in a first main surface of a semiconductor substrate, the at least one trench having a base and sidewalls extending from the base to the first main surface, wherein the method comprises: forming a field dielectric over the base and sidewalls of the at least one trench, implanting species into a first segment of a field dielectric disposed on the sidewall, etching the field dielectric at least in the first segment region, A conductive material is inserted into the at least one trench to form a field plate.

2. The method of claim 1 , wherein etching the field dielectric at least in the first segment region comprises: forming the field dielectric, the field dielectric having a first thickness in an upper section of the sidewall and a second thickness in a lower section of the sidewall, the second thickness being greater than the first thickness, wherein in a middle section of the sidewall arranged between the lower section and the upper section, the thickness of the field dielectric changes from the first thickness at a first boundary between the upper section and the middle section to the second thickness at a second boundary between the lower section and the middle section, and Wherein the second boundary is edgeless. 3 . The method of claim 1 , wherein the first segment has a height that is greater than a height of a field dielectric disposed on the sidewalls of the trench.

4. The method of any one of claims 1 to 3, wherein the trench is a pillar-shaped trench and the field plate is a pillar-shaped field plate.

5. The method of claim 4, wherein the columnar trench has a longitudinal axis, and etching the field dielectric in at least the first segment region includes forming a field dielectric having a thickness around the longitudinal axis, the thickness being non-uniform in at least one plane parallel to the first major surface.

6. The method of any one of claims 1 to 5, wherein the species comprises one or more of the group consisting of Group 18 of the periodic table, As ions, Ar ions, Pt, Ge, Kr and Xe.

7. The method according to any one of claims 1 to 6, further comprising: implanting a species into the first segment of the field dielectric on the sidewall at a first tilt angle with respect to the first major surface; Species are implanted into a second segment of the field dielectric on the sidewall at a second tilt angle to the first major surface, the second segment vertically overlapping or adjoining the first segment, wherein the second tilt angle is greater than the first tilt angle.

8. The method according to any one of claims 1 to 7, further comprising: implanting a species into a first segment of the field dielectric on the sidewall at a first rotation angle about an axis perpendicular to the first major surface; A species is implanted into a second segment of the field dielectric on the sidewall at a second rotation angle about the axis, wherein the second rotation angle is different from the first rotation angle.

9. A semiconductor device comprising a transistor device, the transistor device comprising: One or more trenches are formed in the first main surface of the semiconductor substrate, wherein each of the one or more trenches comprises: a substrate and a sidewall extending from the substrate to the first major surface, wherein the sidewall comprises an upper section, a lower section, and an intermediate section between the lower section and the upper section, a field plate located in the trench, and a field dielectric disposed on the base and the sidewalls of the trench and having a surface; wherein, in the upper region of the sidewall, the field dielectric has a first thickness, wherein, in the lower section of the sidewall, the field dielectric has a second thickness greater than the first thickness, wherein, in the middle region of the sidewall, the thickness of the field dielectric changes from the first thickness at a first boundary between the upper segment region and the middle segment region to the second thickness at a second boundary between the lower segment region and the middle segment region, wherein the first boundary of the surface of the field dielectric between the upper segment area and the middle segment area has a concave form and the second boundary between the lower segment area and the middle segment area has a convex form, and Wherein the second boundary is edgeless. 10 . The semiconductor device of claim 9 , wherein the concave form at the first boundary has a first radius of curvature of 100 nm to 500 nm.

11. The semiconductor device of claim 9 or claim 10, wherein the convex form at the second boundary has a second radius of curvature of 100 nm to 500 nm. 12 . The semiconductor device according to claim 9 , wherein the trench is a columnar trench, and the field plate is a columnar field plate. 13 . The semiconductor device of claim 12 , wherein the pillar trench includes a longitudinal axis, and the first thickness of the field dielectric varies about the longitudinal axis in at least one plane parallel to the first major surface.

14. The semiconductor device of claim 13, wherein the second thickness of the field dielectric is substantially constant about the longitudinal axis in at least one plane parallel to the first major surface.

15. The semiconductor device of any one of claims 9 to 13, wherein the pillar-shaped trench comprises a longitudinal axis, and the second thickness of the field dielectric varies about the longitudinal axis in at least one plane parallel to the first major surface.

16. A semiconductor device comprising a transistor device, the transistor device comprising: A plurality of columnar trenches are formed in a first main surface of a semiconductor substrate, the columnar trenches comprising columnar field plates and field dielectrics located in the columnar trenches, wherein the columnar trench comprises a base and sidewalls extending from the base to the first major surface, and the field dielectric is located on the base and the sidewalls of the columnar trench, wherein the plurality of columnar grooves are arranged in a regular array having a center-to-center spacing p, Wherein the field dielectric has a thickness d1 on the sidewalls of the columnar trench in a lateral direction aligned with the center-to-center pitch p, and has a thickness d2 on the sidewalls of the columnar trench in a lateral direction not aligned with the center-to-center pitch p, where d2 < d1, and (d1 - d2) is greater than the process variation.

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