Semiconductor device

Abstract

The invention provides a semiconductor device. In a semiconductor device, it is desirable to increase the ratio of the area of an active part to the area of a semiconductor substrate. The semiconductor device includes: a semiconductor substrate having an upper surface; an active part provided on the semiconductor substrate and having a transistor; and a gate runner provided above the upper surface of the semiconductor substrate, the transistor including a MOS gate having a gate electrode, the gate runner being electrically connected to the gate electrode, the gate runner being provided above the upper surface of the semiconductor substrate between the active portion and one side of the semiconductor substrate, and the gate runner being electrically connected to the gate electrode. The semiconductor substrate is not provided between the active part and the other side of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, a semiconductor device having gate fingers provided in the center of a semiconductor body has been known (for example, see Patent Document 1). In addition, a semiconductor device using a contact plug in a gate trench has been known (for example, see Patent Document 2 or Patent Document 3). Furthermore, a trench-type MOSFET using polysilicon with different doping concentrations for a gate electrode in a trench has been known (for example, see Patent Document 4).

[0003] Prior Art Documents Patent Documents Patent Document 1: Japanese Patent No. 6732715 Patent Document 2: Japanese Patent No. 5975543 Patent Document 3: Japanese Unexamined Patent Application Publication No. 2009-99872 Patent Document 4: Japanese Unexamined Patent Application Publication No. 2008-218527 Summary of the Invention

[0004] Technical Problem In a semiconductor device, it is desired to increase the ratio of the area of an active portion to the area of a semiconductor substrate.

[0005] Technical Solution In one embodiment of the present invention, there is provided a semiconductor device including a semiconductor substrate having an upper surface. The semiconductor device may include an active portion provided on the semiconductor substrate and having a transistor. Any of the semiconductor devices may include a gate runner provided above the upper surface of the semiconductor substrate. In any of the semiconductor devices, the transistor may include a MOS gate having a gate electrode. In any of the semiconductor devices, the gate runner may be electrically connected to the gate electrode. In any of the semiconductor devices, the gate runner may be provided between the active portion and one side of the semiconductor substrate above the upper surface of the semiconductor substrate, and may not be provided between the active portion and any other side of the semiconductor substrate.

[0006] In any of the semiconductor devices, the gate electrode of the transistor may have a metal portion.

[0007] In any of the semiconductor devices, the MOS gate may have a trench provided on the upper surface of the semiconductor substrate. In any of the semiconductor devices, the metal portion may be provided inside the trench.

[0008] In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type and a channel region of a second conductivity type. The channel region of the second conductivity type is disposed between the upper surface of the semiconductor substrate and the drift region and is in contact with the trench. In any of the above semiconductor devices, the metal portion may be disposed to a position deeper than the channel region.

[0009] Inside the trench of any of the above semiconductor devices, the metal portion and polysilicon may be stacked.

[0010] In any of the above semiconductor devices, the trench may have sidewalls and a bottom. In any of the above semiconductor devices, the polysilicon may be disposed between the sidewalls of the trench and the metal portion.

[0011] In any of the above semiconductor devices, the thickness of the polysilicon stacked with the metal portion in a direction perpendicular to the sidewalls may be 0.2 μm or less.

[0012] In any of the above semiconductor devices, the thickness of the polysilicon formed at the bottom in the depth direction of the trench may be greater than the thickness of the polysilicon disposed between the sidewalls and the metal portion.

[0013] Any of the above semiconductor devices may further include an emission electrode disposed above the upper surface of the semiconductor substrate. Any of the above semiconductor devices may further include an interlayer insulating film that insulates the gate electrode from the emission electrode. In any of the above semiconductor devices, the interlayer insulating film may be disposed inside the trench.

[0014] In any of the above semiconductor devices, the metal portion may contain tungsten.

[0015] Inside the trench of any of the above semiconductor devices, a barrier metal of a metal different from the metal portion may be disposed between the metal portion and the polysilicon.

[0016] In any of the above semiconductor devices, the barrier metal may contain titanium.

[0017] Any of the above semiconductor devices may further include an emission electrode disposed above the upper surface of the semiconductor substrate. Any of the above semiconductor devices may further include an interlayer insulating film that insulates the gate electrode from the emission electrode. In any of the above semiconductor devices, a contact hole connecting the gate runner to the gate electrode may be provided in the interlayer insulating film. In any of the above semiconductor devices, tungsten may be filled in the contact hole. In any of the above semiconductor devices, a barrier metal may be provided between the tungsten that can be filled in the contact hole and the tungsten of the metal portion.

[0018] Any of the above semiconductor devices may further include a well region that surrounds the active portion in a plan view and is formed from the upper surface of the semiconductor substrate toward the inside to a position deeper than the trench. In any of the above semiconductor devices, the well region may include a first well region formed on one side of the semiconductor substrate where the gate runner is provided. In any of the above semiconductor devices, there may be a second well region formed on at least one other side of the semiconductor substrate where the gate runner is not provided. In any of the above semiconductor devices, the width of the second well region may be smaller than the width of the first well region.

[0019] In any of the above semiconductor devices, the difference between the width of the second well region and the width of the first well region may be more than half of the width of the gate runner.

[0020] In any of the above semiconductor devices, the trench may extend in a direction perpendicular to one side of the semiconductor substrate where the gate runner is provided in a plan view. In any of the above semiconductor devices, the first well region and the second well region may overlap with the end of the trench in the extending direction. In any of the above semiconductor devices, the length of the overlap between the first well region and the trench may be greater than the length of the overlap between the second well region and the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 FIG. is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0022] Figure 2 FIG. is a view showing Figure 1 a cross-section taken along line A-A' in

[0023] Figure 3 FIG. is a view showing Figure 1 a cross-section taken along line B-B' in

[0024] Figure 4 FIG. is a view showing Figure 1 a cross-section taken along line C-C' in

[0025] Figure 5 FIG. is a view showing Figure 1 a cross-section taken along line D-D' in

[0026] Figure 6 FIG. is Figure 5 an enlarged view of region A in

[0027] Figure 7 FIG. is a view showing Figure 1 a cross-section taken along line E-E' in

[0028] Figure 8 FIG. is a view showingFigure 1 Another example of the D-D' cross-section in

[0029] Symbol Explanation 10 Semiconductor substrate, 11 First well region, 12 Emitter region, 14 Channel region, 15 Contact region, 16 Accumulation region, 18 Drift region, 21 Upper surface, 22 Second well region, 38 Interlayer insulating film, 40 MOS gate, 41 Trench, 42 Gate insulating film, 44 Polysilicon, 45 Gate electrode, 46 Barrier metal, 48 Metal part, 52 Emitter electrode, 54 Contact hole, 55 Contact hole, 56 Tungsten, 58 Barrier metal, 60 Protective film, 62 Terrace part, 66 Sidewall, 68 Bottom, 70 Transistor, 90 Edge termination structure part, 92 Guard ring, 93 Field plate, 100 Semiconductor device, 112 Gate pad, 120 Active part, 130 Gate runner, 140 Peripheral end, 142 First end edge, 143 Other edges Detailed Implementation Modes

[0030] Hereinafter, the present invention will be described by way of embodiments of the invention. However, the following embodiments do not limit the invention recited in the claims. In addition, all combinations of the features described in the embodiments are not necessarily essential to the technical solution of the invention. In this specification, sometimes the same parts are denoted by the same reference numerals in the respective drawings and the description thereof is omitted. In addition, sometimes a part of the configuration is not illustrated for convenience of explanation.

[0031] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0032] In this specification, an orthogonal coordinate system of the X-axis, Y-axis, and Z-axis is sometimes used to explain technical matters. The orthogonal coordinate system only determines the relative positions of the components and does not limit a specific direction. For example, the Z-axis direction does not limit to represent the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is described without indicating positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0033] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are set as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is set as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction parallel to the upper surface and the lower surface of the semiconductor substrate including the X-axis and the Y-axis is sometimes referred to as the horizontal direction.

[0034] In this specification, in the case of being referred to as "the same" or "equal", it may also include the case having an error caused by manufacturing deviation or the like. This error is, for example, within 10%.

[0035] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, the impurity sometimes particularly refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into the semiconductor substrate to form a semiconductor having an N-type conductivity type or a semiconductor having a P-type conductivity type.

[0036] Figure 1 is a top view showing an example of the semiconductor device 100 according to an embodiment of the present invention. In Figure 1 it, the positions obtained by projecting each component onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1 it, only a part of the components of the semiconductor device 100 are shown, and a part of the components are omitted.

[0037] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate or a silicon carbide substrate. In this specification, the end portion of the outer periphery of the semiconductor substrate 10 in a plan view is defined as an outer peripheral end 140. A plan view means a view observed parallel to the Z axis from the upper surface side of the semiconductor substrate 10. In addition, any one of the end edges of the outer peripheral end 140 of the semiconductor substrate 10 in a plan view is defined as a first end edge 142. In a plan view, the direction parallel to the first end edge 142 is defined as the X-axis direction, and the direction perpendicular to the first end edge 142 is defined as the Y-axis direction. In addition, the edges other than the first end edge 142 are defined as other edges 143. The semiconductor substrate 10 in this example has three other edges 143-1, 143-2, and 143-3.

[0038] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An upper surface electrode such as an active electrode or an emission electrode is provided above the active portion 120, but is omitted in Figure 1 this case.

[0039] The active portion 120 may include a transistor 70. All of the active portions 120 in this example are transistors 70. A transistor 70 may also be provided in a part of the active portion 120. As an example, the transistor 70 is a MOSFET or an IGBT. In this specification, the case where an IGBT is provided in the active portion 120 as the transistor 70 is described as an embodiment, but the configuration of the active portion 120 is not limited thereto. The active portion 120 may also include a diode.

[0040] The active portion 120 may be a portion that overlaps with an emission electrode in a plan view. Here, the emission electrode may be a pad connected to a wire, an electrode connected to a wire and through which a main current flows, or an electrode connected to the emitter region of the transistor 70. The emission electrode may also be connected by solder via a nickel film. In the case of having a plurality of emission electrodes, the one with the largest area may be used as the emission electrode. For example, a pad for current sensing may not be included in the emission electrode.

[0041] The transistor 70 includes a MOS gate having a gate electrode 45. The MOS gate in this example has a trench provided on the upper surface of the semiconductor substrate 10, and a gate electrode 45 is provided inside the trench. The gate electrode 45 in this example includes polysilicon 44 and a metal portion 48. In other examples, the gate electrode 45 may be entirely polysilicon 44 or entirely a metal portion 48. The configuration of the MOS gate will be described later.

[0042] In Figure 1In [the figure], the configurations of the metal portion 48 and the polysilicon 44 in the active portion 120 are shown. When viewed from above, the metal portion 48 and the polysilicon 44 can extend in a predetermined direction. That is, it can be set such that the trenches also extend in a predetermined direction when viewed from above. In this example, the polysilicon 44 and the metal portion 48 extend in the Y-axis direction.

[0043] The edge terminal structure portion 90 is provided on the upper surface of the semiconductor substrate 10 between the active portion 120 and the outer peripheral end 140 of the semiconductor substrate 10. The edge terminal structure portion 90 can be configured in a ring shape so as to surround the active portion 120 on the upper surface of the semiconductor substrate 10. In this example, the edge terminal structure portion 90 is arranged along the outer peripheral end 140 of the semiconductor substrate 10. The edge terminal structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure portion 90 has, for example, a guard ring, a field plate, a surface electric field reduction portion, and a structure formed by combining them.

[0044] A gate pad 112 is provided above the upper surface of the semiconductor substrate 10. The gate pad 112 is provided between the active portion 120 and the first end edge 142. The gate pad 112 may not be included in the active portion.

[0045] A gate voltage is applied to the gate pad 112, and this gate voltage is applied to the gate electrode 45 of the MOS gate of the transistor 70 via a gate runner described later. Other pads for current sensing, for example, may also be provided above the upper surface of the semiconductor substrate 10. The pads can be formed of a metal material such as aluminum. An overhead wiring such as a wire can be connected to the upper surface of the gate pad 112. The gate pad 112 can have a rectangular shape when viewed from above.

[0046] The semiconductor device 100 includes a gate runner 130 provided above the upper surface of the semiconductor substrate 10. The gate runner 130 is electrically connected to the gate electrode 45. The gate runner 130 is also electrically connected to the gate pad 112 and transmits the gate voltage to the gate electrode 45. In this example, the gate runner 130 is made of metal. However, the gate runner 130 can also be made of polysilicon.

[0047] The gate runner 130 can be provided above the upper surface of the semiconductor substrate 10 between the active portion 120 and one side of the semiconductor substrate 10, and is not provided between the active portion 120 and any other side of the semiconductor substrate 10. In this example, the gate runner 130 is provided only between the active portion 120 and the first end edge 142. In this example, the gate runner 130 is connected to the gate electrode 45 only between the active portion 120 and the first end edge 142.

[0048] The first end edge 142 of this example is an edge parallel to the X-axis. The width of the gate runner 130 in the Y-axis direction can be smaller than the width of the gate pad 112 in the Y-axis direction. The width of the gate runner 130 in the Y-axis direction can be less than half of the width of the gate pad 112 in the Y-axis direction.

[0049] The length of the gate runner 130 in the X-axis direction is larger than the length of the gate pad 112 in the X-axis direction. The gate runner 130 can be connected to all the gate electrodes 45 arranged side by side in the X-axis direction in the active part 120. The gate runner 130 of this example is arranged to extend from the position facing the gate electrode 45 at one end arranged in the X-axis direction among the plurality of gate electrodes 45 to the position facing the gate electrode 45 at the other end.

[0050] In Figure 1 the example, the gate runner 130 is arranged between the gate pad 112 and the first end edge 142. In other examples, the gate runner 130 can also have a part arranged between the gate pad 112 and the active part 120. The gate runner 130 can also be arranged to surround the gate pad 112 in a top view. That is, the gate runner 130 can also have a bent part.

[0051] The groove of this example extends in the extending direction (Y-axis direction) perpendicular to the first end edge 142 where the gate runner 130 is arranged in a top view. Among them, this perpendicular can have an amplitude of about ±10°.

[0052] The semiconductor device 100 can further include a well region. The well region can be formed from the upper surface of the semiconductor substrate 10 toward the inside and surround the active part 120 in a top view. The well region can be arranged to at least partially overlap the gate runner 130 in a top view. Among them, the well region is not shown in Figure 1 this figure.

[0053] When transmitting the gate voltage from the gate pad 112 to each gate electrode 45, a deviation occurs during the time until the gate voltage is transmitted due to the resistance of the transmission path. In this specification, the situation of the transmission delay of the gate voltage is called gate delay. If the gate delay is large, for example, when the semiconductor device 100 is turned off, compared with the region with a small gate delay, the time for the region with a large gate delay to become disconnected increases, resulting in current concentration in the region with a large gate delay.

[0054] To reduce the gate delay, various configurations are considered for the gate runner 130. For example, sometimes the gate runner 130 is arranged to surround the active portion 120 along the outer periphery of the active portion 120. Generally, the gate electrode 45 of the MOS gate is formed of polysilicon, and the gate runner 130 is formed of a metal having a resistivity smaller than that of polysilicon. Therefore, by connecting the gate runner 130 to the gate electrode 45, the gate delay can be reduced, and the gate runner 130 is provided between the active portion 120 and the other side 143 of the semiconductor substrate 10. However, since the area of the gate runner 130 increases, the area of the active portion 120 decreases, or the area of the semiconductor substrate 10 increases.

[0055] As another example, sometimes the gate runner 130 is arranged to cross the center of the active portion 120. Since the gate runner 130 is connected to the gate electrode 45 at the center of the active portion 120, the gate delay can be reduced. However, in this case, the emitter electrode is divided into two due to the gate runner 130. In this case, since wires are bonded to the respective emitter electrodes, the resistance values of the respective bonding portions are different, and current imbalance may occur in the respective emitter electrodes, or oscillation may occur in one emitter electrode.

[0056] Since the gate runner 130 of this example is only provided between the active portion 120 and the first end side 142, the ratio of the area of the active portion 120 to the area of the semiconductor substrate 10 can be increased compared to the case where the gate runner 130 is also provided on the other side. Or, the area of the semiconductor substrate 10 having the active portion 120 with the same area can be reduced. In addition, in the case of configuring the gate runner 130 of the embodiment, the emitter electrode is one, so current imbalance and / or oscillation deviation do not occur.

[0057] However, in the configuration of the gate runner 130 of the embodiment, sometimes the gate delay becomes large. Therefore, the gate electrode 45 of the transistor 70 may have a metal portion 48. The structure of the MOS gate will be described later.

[0058] Figure 2 It is a diagram showing Figure 1 the A-A' cross section in. The A-A' cross section is the YZ cross section of the edge termination structure portion 90, the gate runner 130, and the MOS gate 40 of the transistor 70. In the A-A' cross section, the semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a gate runner 130, a field plate 93, and a protective film 60. The semiconductor substrate 10 has an upper surface 21 and a lower surface. Among them, in Figure 2 the subsequent figures, the configuration on the lower surface side is omitted. The first end side 142 is on the positive Y-axis side of the A-A' cross section.

[0059] The semiconductor substrate 10 has a drift region 18 of a first conductivity type and a channel region 14 of a second conductivity type. The channel region 14 is provided between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. In this example, the drift region 18 is of N-type and the channel region 14 is of P-type. A MOS gate 40 is provided inside the semiconductor substrate 10 of this example. The MOS gate 40 controls the switching of the transistor 70 according to the applied gate voltage. The channel region 14 is in contact with the MOS gate 40. The channel region 14 is a region where, when a predetermined gate voltage is applied to the gate electrode 45, a channel formed by an inversion layer of electrons is formed on the surface layer of the interface in contact with the MOS gate 40. Let the length in the depth direction of the channel region 14 starting from the upper surface 21 be t3.

[0060] In the A-A' cross section, the semiconductor substrate 10 has a first well region 11, and the first well region 11 is formed on one side of the semiconductor substrate 10 where the gate runner 130 is provided. The first well region of this example is provided along the first end edge 142. At least a part of the first well region 11 is provided between the first end edge 142 and the active portion 120 in a top view. The first well region 11 is provided from the upper surface 21 of the semiconductor substrate 10 to a position deeper than the channel region 14. The first well region 11 is a region of the second conductivity type with a doping concentration higher than that of the channel region 14. The first well region 11 of this example is of P+ type. As described above, a P+ type well region surrounding the active portion 120 in a top view may be provided in the semiconductor substrate 10. The first well region 11 may refer to the part of the well region that extends along the first end edge 142.

[0061] The transistor 70 has a MOS gate 40 provided toward the inside from the upper surface 21 of the semiconductor substrate 10. As Figure 1 shown, a plurality of MOS gates 40 may be provided. The MOS gates 40 of this example are arranged along the X-axis direction and extend in the Y-axis direction. In this example, the MOS gate 40 is described as a trench gate structure.

[0062] The MOS gate 40 has a trench 41, a gate insulating film 42, and a gate electrode 45. The trench 41 is a groove provided on the upper surface 21 of the semiconductor substrate 10 and formed in the depth direction from the upper surface 21. The trench 41 of this example reaches the drift region 18. The channel region 14 is adjacent to the trench 41. Figure 2 The channel region 14 shown is in contact with the end of the trench 41 in the Y-axis direction. Let the length in the depth direction of the trench 41 starting from the upper surface 21 be t2. In other words, Figure 2 the length in the depth direction of the MOS gate 40 in

[0063] The gate insulating film 42 is provided to cover the inner wall of the trench 41. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the trench 41, or can be formed by a deposition method. The gate electrode 45 is disposed inside the trench 41 at a position closer to the inside than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate electrode 45 from the semiconductor substrate 10.

[0064] The gate electrode 45 in this example has a polysilicon 44 and a metal portion 48. Impurities for improving conductivity can be implanted into the polysilicon 44. The metal portion 48 is made of a metal material. As an example, the metal portion 48 contains tungsten. The resistivity of the metal portion 48 is smaller than the resistivity of the polysilicon 44. By having the metal portion 48 with a small resistivity, the gate electrode 45 can reduce the above-mentioned gate delay.

[0065] Inside the trench 41, a barrier metal 46 can be provided between the metal portion 48 and the polysilicon 44. In this case, the barrier metal 46 can also be included in the gate electrode 45. The barrier metal 46 can be made of a metal different from the metal portion 48. As an example, the barrier metal 46 can contain titanium. The barrier metal 46 can also have a stacked structure of a titanium nitride layer and a titanium layer from the metal portion 48 toward the polysilicon 44. By providing the barrier metal 46, the metal elements of the emitter electrode 52 can be prevented from diffusing into the semiconductor substrate 10.

[0066] The metal portion 48 can be disposed inside the trench 41. In other words, the metal portion 48 can be disposed inside the semiconductor substrate 10 below the upper surface 21 of the semiconductor substrate 10. In this specification, the direction from the upper surface 21 of the semiconductor substrate 10 toward the lower surface is sometimes referred to as downward, and the opposite direction is referred to as upward. The length of the metal portion 48 in the depth direction starting from the upper surface 21 is set as t1. The metal portion 48 in this example is disposed to a position deeper than the channel region 14. That is, the length t1 is larger than the length t3 in the depth direction of the channel region 14. By making the length t1 larger than the length t3, the gate delay in the channel region 14 can be reduced at least. The length t1 can be 1.1 times or more the length t3, can be 1.2 times or more the length t3, can be 1.5 times or more the length t3, and further can be 2 times or more the length t3.

[0067] The MOS gate 40 is not limited to the trench gate structure. The gate electrode 45 of the transistor 70 can have a metal portion 48. As an example, the gate electrode 45 of the planar MOS gate 40 can have a metal portion 48. In this case, the gate delay can also be reduced.

[0068] As an example of the method for manufacturing the MOS gate 40 of this example, first, polysilicon 44 is filled into the inside of the trench 41 by CVD method. Thereafter, the polysilicon 44 in the trench 41 is etched to form a trench contact portion, and tungsten and barrier metal are filled into the trench contact portion by sputtering. Since the front end (-Z axis direction) of the trench 41 sometimes becomes thin, it is difficult for the metal portion 48 to enter the front end of the trench 41. By disposing polysilicon 44 at the front end portion of the trench 41, the formation of voids in the front end portion of the trench 41 can be suppressed.

[0069] In the MOS gate 40 of this example, the metal portion 48 and the polysilicon 44 are stacked inside the trench 41. The metal portion 48 and the polysilicon 44 may be stacked with the barrier metal 46 therebetween. Inside the trench 41, the metal portion 48 and the polysilicon 44 may be stacked in the depth direction. In this example, the metal portion 48 is exposed on the upper surface 21 of the semiconductor substrate 10. In the Z-axis direction, the polysilicon 44 is disposed below the metal portion 48. Inside the trench 41, the metal portion 48 and the polysilicon 44 may be stacked in the horizontal direction (particularly the arrangement direction of the MOS gate 40) as described later.

[0070] The first well region 11 may cover the end portion of the trench 41 in the extending direction (Y-axis direction) of the trench 41. The first well region 11 of this example covers the entire side wall of the end portion of the trench 41 in the Y-axis direction and a part of the lower surface of the trench 41 extending from the side wall. The side wall of the trench 41 may be in contact with the channel region 14. The first well region 11 may also cover the channel region 14 in contact with the side wall of the trench 41. The length of the overlap between the first well region 11 and the trench 41 is set as t8. By the first well region 11 covering the end portion of the trench 41, the electric field concentration at the end portion of the trench 41 can be alleviated.

[0071] The width of the first well region 11 in the extending direction (Y-axis direction) of the trench 41 is set as t9. The width t9 is the width of the first well region 11 at the YZ cross section where the gate pad 112 is not provided. The width of the gate runner 130 in the extending direction (Y-axis direction) of the trench 41 is set as tg. The width t9 may be larger than the width tg. In a plan view, at least a part of the gate runner 130 may overlap with the first well region 11, or the entire gate runner 130 may overlap with the first well region 11. By overlapping the gate runner 130 with the first well region 11, the electric field distribution can be smoothed from the end portion of the trench 41 to the edge termination structure portion 90 outside the gate runner 130 in a plan view. Thereby, local electric field concentration can be prevented.

[0072] In the transistor 70, an emitter electrode 52 is provided above the upper surface 21 of the semiconductor substrate 10. An interlayer insulating film 38 is provided in contact with the upper surface 21 of the semiconductor substrate 10 and insulates the gate electrode 45 from the emitter electrode 52. The interlayer insulating film 38 is a film including at least one of insulating films such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A gate runner 130 is provided above the interlayer insulating film 38.

[0073] A contact hole 54 connecting the gate runner 130 and the gate electrode 45 is provided in the interlayer insulating film 38. Tungsten 56 is filled in the contact hole 54. Therefore, in the semiconductor device 100 of this example, the metal gate runner 130 is in direct contact with the metal of the gate electrode 45. It should be noted that the tungsten 56 and the barrier metal 58 described later may also be included in the gate runner 130.

[0074] A barrier metal 58 is provided in the contact hole 54. The barrier metal 58 of this example is provided between the tungsten 56 filled in the contact hole 54 and the tungsten of the metal portion 48. By providing the barrier metal 58, diffusion of the metal element of the emitter electrode 52 into the interior of the semiconductor substrate 10 can be prevented. The barrier metal 58 may also be provided on the side wall of the contact hole 54.

[0075] In the edge termination structure portion 90, a guard ring 92 is provided in the semiconductor substrate 10. The guard ring 92 is a region of a second conductivity type formed by ion implantation from the upper surface 21 of the semiconductor substrate 10 toward the interior. The doping concentration of the guard ring 92 may be equal to the doping concentration of the first well region 11. The depth of the guard ring 92 may be equal to the depth of the first well region 11.

[0076] In the edge termination structure portion 90, the interlayer insulating film 38 is also provided in contact with the upper surface 21 of the semiconductor substrate 10. A field plate 93 is provided above the interlayer insulating film 38. The field plate 93 is formed of a conductive material such as metal such as aluminum or polysilicon.

[0077] A contact hole 55 connecting the field plate 93 and the guard ring 92 is provided in the interlayer insulating film 38. Similarly to the transistor 70, a barrier metal 58 is provided in the contact hole 55 and filled with tungsten 56.

[0078] A protective film 60 is provided above the interlayer insulating film 38, the emitter electrode 52, the gate runner 130, and the field plate 93. As an example, the protective film 60 is formed of polyimide.

[0079] Figure 3 It shows Figure 1The figure of the B-B' cross-section. The B-B' cross-section is the YZ cross-section passing through the edge terminal structure portion 90, the gate runner 130, the gate pad 112, and the MOS gate 40 of the transistor 70. Different from the A-A' cross-section, the B-B' cross-section crosses the gate pad 112. Since other aspects are the same as those of the A-A' cross-section, the description is omitted.

[0080] The gate pad 112 is provided above the interlayer insulating film 38. In the interlayer insulating film 38, a contact hole 54 for connecting the gate pad 112 to the gate electrode 45 is provided under the gate pad 112. Figure 2 Similarly, a barrier metal 58 is also provided in the contact hole 54 of this example, and tungsten 56 is filled therein. Among them, Figure 3 In, a part of the region including the gate pad 112 is omitted for illustration. In addition, the protective film 60 of this example is separated from above the gate pad 112 in the Y-axis direction.

[0081] The first well region 11 is formed to a position closer to the active portion 120 side than the gate pad 112. In a plan view, the entire gate pad 112 can overlap with the first well region 11. In the B-B' cross-section, the first well region 11 also covers the end portion in the extending direction of the trench 41.

[0082] Figure 4 It shows Figure 1 The figure of the C-C' cross-section. The C-C' cross-section is the YZ cross-section passing through the edge terminal structure portion 90, the gate runner 130, the gate pad 112, and the mesa portion of the transistor 70. The mesa portion refers to the region clamped by the MOS gate 40 in the transistor 70. Different from the B-B' cross-section, the C-C' cross-section crosses the mesa portion. Since other aspects are the same as those of the B-B' cross-section, the description is omitted.

[0083] The semiconductor substrate 10 has a channel region 14, an emitter region 12, a contact region 15, and an accumulation region 16 in the mesa portion. The first well region 11 can also be included in the mesa portion at the end portion in the extending direction (Y-axis direction) of the trench 41. The first well region 11 and the channel region 14 can be the same as the first well region 11 and the channel region 14 described in Figure 2 . For the accumulation region 16, see the following description.

[0084] The emitter region 12 is a region of a first conductivity type that is provided between the upper surface 21 of the semiconductor substrate 10 and the channel region 14 and has a doping concentration higher than that of the drift region 18. The emitter region 12 in this example is of N+ type. The contact region 15 is a region of a second conductivity type that is provided between the upper surface 21 of the semiconductor substrate 10 and the channel region 14 and has a concentration higher than that of the channel region 14. The contact region 15 in this example is of P+ type. The emitter region 12 and the contact region 15 are exposed on the upper surface 21. The emitter region 12 and the contact region 15 in this example are alternately arranged in the extending direction (Y-axis direction) of the trench 41.

[0085] In the mesa portion, an interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. Contact holes 54 for connecting the emitter electrode 52 to the emitter region 12 and for connecting the emitter electrode 52 to the contact region 15 are provided in the interlayer insulating film 38. Figure 2 Similarly, a barrier metal 58 is also provided in the contact hole 54 of this example, and tungsten 56 is filled therein. The contact holes 54 of the active portion 120 extend in the extending direction (Y-axis direction) of the trench 41.

[0086] Figure 5 is a diagram showing Figure 1 the D-D' cross section in. The D-D' cross section is an XZ cross section of the emitter region 12 of the transistor 70 through the edge termination structure portion 90. Since the D-D' cross section crosses Figure 1 the other side 143-3 of the semiconductor substrate 10 in, the gate runner 130 is not provided. The other side 143-3 is present on the negative X-axis side of the D-D' cross section. The edge termination structure portion 90 of the D-D' cross section is the same as the edge termination structure portion 90 shown in Figures 2 to 4 and thus the description thereof is omitted.

[0087] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. Contact holes 54 are also provided in the interlayer insulating film 38 of this example. A barrier metal 58 is provided inside the contact hole 54, and tungsten 56 is filled therein.

[0088] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. Above the emitter electrode 52, a protective film 60 is provided so as to partially overlap with the emitter electrode 52.

[0089] The transistor 70 has a plurality of MOS gates 40 provided from the upper surface 21 of the semiconductor substrate 10 toward the inside. The MOS gates 40 in this example are arranged along the X-axis direction and have long sides in the Y-axis direction. As described above, the MOS gate 40 has a trench 41, a gate insulating film 42, and a gate electrode 45, and the gate electrode 45 has polysilicon 44, a barrier metal 46, and a metal portion 48. The MOS gate 40 can function as a gate trench or as a dummy trench. It is also possible to mix the functions of both in the plurality of MOS gates 40. A metal portion can be provided in the gate electrode 45 of the MOS gate 40 that functions as a dummy trench. By providing the metal portion, it is difficult to generate a potential distribution between the MOS gates 40 when the potential of the emitter electrode 52 fluctuates. Among them, in the MOS gate 40 that functions as a dummy trench, polysilicon 44 can be provided instead of the metal portion 48.

[0090] In the arrangement direction, a mesa portion 62 is provided between the MOS gates 40 of the transistor 70. The mesa portion 62 refers to the region between the MOS gates 40 inside the semiconductor substrate 10. As an example, the upper end of the mesa portion 62 is the upper surface 21 of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 62 is the same as the depth position Zt of the lower end of the trench 41. The mesa portion 62 in this example is provided to extend in the Y-axis direction along the MOS gates 40 on the upper surface 21 of the semiconductor substrate 10. A channel region 14 is provided in the mesa portion 62.

[0091] The transistor 70 has an emitter region 12 provided on the upper surface 21. The emitter region 12 is provided to be exposed on the upper surface 21 of the semiconductor substrate 10 and in contact with the MOS gate 40. The emitter region 12 can also be in contact with the MOS gates 40 on both sides of the mesa portion 62. When the D-D' cross section crosses the contact region 15, Figure 5 the emitter region 12 in it becomes the contact region 15.

[0092] The channel region 14 is provided below the emitter region 12. The channel region 14 in this example is provided to be in contact with the emitter region 12. The channel region 14 can also be in contact with the MOS gates 40 on both sides of the mesa portion 62.

[0093] The accumulation region 16 is provided below the channel region 14. The accumulation region 16 is a region of the first conductivity type with a doping concentration higher than that of the drift region 18. The accumulation region 16 in this example is of the N+ type. By providing a high-concentration accumulation region 16 between the drift region 18 and the channel region 14, the carrier injection enhancement effect (IE effect) can be improved to reduce the on-state voltage. The accumulation region 16 can be provided to cover the entire lower surface of the channel region 14 in each mesa portion 62.

[0094] As described above, the metal portion 48 is provided to be deeper than the channel region 14 in the depth direction. In this example, the metal portion 48 is provided in the depth direction to overlap with the storage region 16. The metal portion 48 may also be provided to be deeper than the storage region 16.

[0095] A second well region 22-1 is provided on the outer periphery of the active portion 120. The second well region 22-1 is a region of the second conductivity type provided from the upper surface 21 of the semiconductor substrate 10 to the inside. The doping concentration of the second well region 22-1 may be equal to the doping concentration of the first well region (refer to Figures 2 to 4 ). The depth at which the second well region 22-1 is provided may be equal to the depth at which the first well region is provided. The first well region 11 and the second well region 22 provided on each side may be connected at the corners of the semiconductor device 100.

[0096] The width of the second well region 22-1 in the direction (X-axis direction) perpendicular to the other side 143-3 is set to t10. The width t10 may be smaller than the width t9 of the first well region 11. As described above, no gate runner 130 is provided between the active portion 120 and the other side 143-3. Therefore, the width t10 can be made smaller than the width t9. Thereby, the ratio of the area of the active portion 120 to the area of the semiconductor substrate 10 can be increased. Or, the area of the semiconductor substrate 10 having the same area of the active portion 120 can be reduced.

[0097] The difference between the width t10 and the width t9 may be more than half of the width tg of the gate runner 130 (refer to Figure 2 ). When the entire gate runner 130 overlaps with the first well region 11, the difference between the width t10 and the width t9 may be equal to or more than the width tg of the gate runner 130.

[0098] In the cross section from the edge termination structure portion 90 on the other side 143-1 to the active portion 120, a second well region 22 may also be provided. The relationship between the width of the second well region 22 and the width t9 of the first well region 11 may be the same as the relationship between the width t10 and the width t9.

[0099] The second well region 22-1 may be in contact with the MOS gate 40 provided on the outermost side of the active portion 120, or may cover the MOS gate 40. In this example, the second well region 22-1 is in contact with approximately half of the MOS gate 40.

[0100] The interlayer insulating film 38 may have a contact hole 54 located between the MOS gate 40 provided on the outermost side of the active portion 120 and the edge termination structure portion 90. In this example, the emitter electrode 52 is electrically connected to the second well region 22-1 via the contact hole 54.

[0101] Figure 6 is Figure 5An enlarged view of region A in []. Region A is a region including the MOS gate 40, the emitter region 12, the channel region 14, and the accumulation region 16.

[0102] The trench 41 may have sidewalls 66 and a bottom 68. The sidewalls 66 may be the wall portions of the trench 41 from the upper surface 21 to the depth of the channel region 14, or may be the wall portions of the trench 41 perpendicular to the upper surface 21. Among them, there is usually a case where the wall portions of the trench 41 are not strictly perpendicular to the upper surface 21, so this perpendicularity may have a range of about ±10°. The bottom 68 may be the part in the trench 41 other than the sidewalls 66. The bottom 68 in this example is the curved part at the front end of the trench 41. The bottom 68 may be the part where the tangent line in the XZ cross-section has an inclination greater than 10° with respect to the normal of the upper surface 21. In Figure 6 The sidewalls 66 are shown by thick lines.

[0103] The polysilicon 44 in this example is disposed between the sidewalls 66 of the trench 41 and the metal portion 48. Generally, if the material of the gate electrode 45 changes, the threshold voltage changes. Therefore, by disposing the polysilicon 44 between the sidewalls 66 and the metal portion 48, it is possible to suppress the fluctuation of the threshold voltage caused by the setting of the metal portion 48. In addition, pores are likely to form in the tungsten of the metal portion 48. Therefore, if the metal portion 48 is in contact with the sidewalls 66, there may be a part where the channel is not formed due to the pores. On the other hand, pores are not formed in the polysilicon 44. Therefore, it is possible to form a channel throughout the channel region 14. The polysilicon 44 may be disposed throughout the region between the sidewalls 66 of the trench 41 and the metal portion 48. In other words, the metal portion 48 may not be in contact with the sidewalls 66. In the direction (X-axis direction) perpendicular to the sidewalls 66 of the trench 41 passing through the emitter region 12, the polysilicon 44 and the metal portion 48 may be stacked.

[0104] The thickness of the polysilicon 44 stacked with the metal portion 48 in the direction (X-axis direction) perpendicular to the sidewalls 66 is set as t4. In other words, the thickness t4 is the thickness of the polysilicon 44 disposed between the sidewalls 66 and the metal portion 48. The thickness t4 may be 0.2 μm or less. Although the thickness t4 is small, it also has the above-mentioned effect of suppressing the fluctuation of the threshold voltage. The thickness t4 may be 0.1 μm or less. The thickness t4 may be 0.05 μm or more.

[0105] The thickness of the polysilicon 44 formed on the bottom 68 in the depth direction of the trench 41 is set as t5. The thickness t5 may be larger than the thickness t4. As described above, polysilicon easily enters the front end of the trench 41. In addition, the deeper the trench 41, the better the IE effect, and the conduction voltage can be reduced. Therefore, the trench 41 is formed to a position deeper than the channel region 14. On the other hand, the metal portion 48 may not be provided to the bottom 68 either. As a result, the polysilicon 44 on the bottom 68 becomes thicker.

[0106] The width in the direction perpendicular to the sidewall 66 (X-axis direction) of the metal portion 48 and the barrier metal 46 is set as t6. The width in the direction perpendicular to the sidewall 66 (X-axis direction) of the trench 41 is set as t7. The width t7 is larger than the width t6. Thereby, polysilicon 44 can be provided between the sidewall 66 and the metal portion 48. As an example, the width t6 is 0.5 μm or more and 1 μm or less.

[0107] Figure 7 is a diagram showing Figure 1 the E-E' cross section in. The E-E' cross section is a YZ cross section passing through the edge termination structure portion 90 and the MOS gate 40 of the transistor 70. Hereinafter, the differences from the A-A' cross section ( Figure 2 ) will be described.

[0108] Since the E-E' cross section crosses Figure 1 the other side 143-2 of the semiconductor substrate 10 in, the gate runner 130 is not provided. The other side 143-2 is present on the negative Y-axis side of the E-E' cross section. In addition, the second well region 22-2 is provided along the other side 143-2. The doping concentration and depth of the second well region 22-2 may be the same as those of the second well region 22-1 (refer to Figure 5 ).

[0109] The width of the second well region 22-2 is set as t12. The width t12 may be smaller than the width t9 of the first well region 11. As described above, the gate runner 130 is not provided between the active portion 120 and the other side 143-2. Therefore, the width t12 can be made smaller than the width t9. Thereby, the ratio of the area of the active portion 120 to the area of the semiconductor substrate 10 can be increased. Or, the area of the semiconductor substrate 10 having the same area of the active portion 120 can be reduced.

[0110] The difference between the width t12 and the width t9 may be half or more of the width tg of the gate runner 130 (refer to Figure 2 ). When the entire gate runner 130 overlaps with the first well region 11, the difference between the width t12 and the width t9 may be the width tg or more of the gate runner 130.

[0111] The second well region 22-2 overlaps with the end portion of the trench 41 in the extending direction of the trench 41. The length of the overlap between the second well region 22-2 and the trench 41 is set as t11. The length t8 of the overlap between the first well region and the trench 41 (refer to Figure 2 ) may be larger than the length t11. Since the gate runner 130 is not provided in the E-E' cross section, in this cross section, the gate electrode 45 of the MOS gate 40 is not electrically connected to other electrodes or the like. On the other hand, in the portion where the first well region 11 overlaps with the trench 41, the gate runner 130 is connected to the gate electrode 45 (refer toFigure 2 ). Therefore, in the overlapping portion of the first well region 11 and the trench 41, the electric field is likely to concentrate.

[0112] However, a gate runner can also be provided in the E-E' cross-section. That is, a gate runner can also be provided between the active portion 120 and the other side 143-2 along the other side 143-2 of the semiconductor substrate 10. The gate runner can be connected to the gate electrodes 45 of the respective MOS gates 40. The gate runner is not connected to the gate runner 130 provided along Figure 1 the first end side 142 as shown, etc.

[0113] Figure 8 is a diagram showing Figure 1 another example of the D-D' cross-section in. For the D-D' cross-section of this example, the configuration of the interlayer insulating film 38 is different from that of the D-D' cross-section shown in Figure 5 Since the other positions are the same as those in Figure 5 they are omitted from the description.

[0114] In the semiconductor device 100 of this example, an interlayer insulating film 38-1 and an interlayer insulating film 38-2 are provided. The interlayer insulating film 38-1 is provided above the upper surface 21 of the semiconductor substrate 10 from the edge termination structure portion 90 to the active portion 120. The interlayer insulating film 38-2 is provided in the active portion 120. The interlayer insulating film 38-2 insulates the gate electrode 45 of the MOS gate 40 from the emission electrode 52. In this example, the interlayer insulating film 38-2 is provided inside the trench 41. At least a part of the interlayer insulating film 38-2 can be provided inside the trench 41, or the entire interlayer insulating film 38-2 can be provided inside the trench 41. Along with this, the contact hole 54 in this example is provided to straddle a plurality of mesa portions 62. By providing the interlayer insulating film 38-2 inside the trench 41, the positioning accuracy when forming the contact hole 54 can be reduced, and the miniaturization of the mesa portion 62 can be facilitated.

[0115] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clearly understood from the description of the claims that the embodiments to which such changes or improvements are applied can also be included in the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate having an upper surface; an active portion, which is disposed on the semiconductor substrate and has a transistor; and a gate channel disposed above the upper surface of the semiconductor substrate, The transistor comprises a MOS gate having a gate electrode, The gate channel is electrically connected to the gate electrode, The gate flow channel is provided above the upper surface of the semiconductor substrate between the active portion and one side of the semiconductor substrate, and is not provided between the active portion and any other side of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein: The gate electrode of the transistor has a metal portion.

3. The semiconductor device according to claim 2, wherein: The MOS gate has a groove disposed on the upper surface of the semiconductor substrate. The metal portion is disposed inside the groove.

4. The semiconductor device according to claim 3, wherein: The semiconductor substrate has: A drift region of a first conductivity type; and a second conductive type channel region, which is disposed between the upper surface of the semiconductor substrate and the drift region and contacts the trench, The metal portion is provided to a position deeper than the channel region.

5. The semiconductor device according to claim 4, wherein: The metal portion and polysilicon are stacked inside the trench.

6. The semiconductor device according to claim 5, wherein: The groove has sidewalls and a bottom, The polysilicon is disposed between the sidewall of the trench and the metal portion.

7. The semiconductor device according to claim 6, wherein: The thickness of the polysilicon stacked on the metal portion in a direction perpendicular to the sidewall is 0.2 μm or less.

8. The semiconductor device according to claim 6, wherein: The thickness of the polysilicon formed at the bottom in a depth direction of the trench is greater than the thickness of the polysilicon provided between the sidewall and the metal portion.

9. The semiconductor device according to claim 3, wherein: The semiconductor device further comprises: an emitting electrode disposed above the upper surface of the semiconductor substrate; and an interlayer insulating film that insulates the gate electrode from the emitter electrode, The interlayer insulating film is provided to the inside of the trench.

10. The semiconductor device according to claim 3, wherein: The metal portion includes tungsten.

11. The semiconductor device according to claim 5, wherein: Inside the trench, a barrier metal made of a metal different from the metal portion is provided between the metal portion and the polysilicon.

12. The semiconductor device according to claim 11, wherein: The barrier metal includes titanium.

13. The semiconductor device according to claim 10, wherein: The semiconductor device further comprises: an emitting electrode disposed above the upper surface of the semiconductor substrate; and an interlayer insulating film that insulates the gate electrode from the emitter electrode, The interlayer insulating film is provided with a contact hole for connecting the gate channel to the gate electrode. The contact hole is filled with tungsten, A barrier metal is provided between the tungsten filled in the contact hole and the tungsten of the metal portion.

14. The semiconductor device according to any one of claims 3 to 13, characterized in that The semiconductor device further includes a well region, the well region surrounding the active portion in a plan view and formed from the upper surface of the semiconductor substrate toward the inside to a position deeper than the trench. The well region has: A first well region formed on a side of the semiconductor substrate where the gate channel is disposed; as well as A second well region is formed on at least one other side of the semiconductor substrate where the gate channel is not provided, The width of the second well region is smaller than that of the first well region.

15. The semiconductor device according to claim 14, wherein: A difference between a width of the second well region and a width of the first well region is greater than or equal to half a width of the gate channel.

16. The semiconductor device according to claim 14, wherein: The trench extends in a direction perpendicular to a side of the semiconductor substrate on which the gate channel is provided when viewed from above. The first well region and the second well region overlap with ends of the trench in the extending direction, The length by which the first well region overlaps with the trench is greater than the length by which the second well region overlaps with the trench.

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