Field effect transistor and preparation method thereof

Abstract

The invention relates to a field effect transistor and a preparation method thereof, and the field effect transistor comprises an insulating substrate, a two-dimensional material Bi2O2Se channel layer which grows on the insulating substrate in situ, a first electrode and a second electrode which are arranged on the two-dimensional material Bi2O2Se channel layer, a two-dimensional material MoO3 layer which is arranged on the two-dimensional material Bi2O2Se channel layer, and a third electrode which is arranged on the two-dimensional material MoO3 layer, the two-dimensional material MoO3 layer completely covers the two-dimensional material Bi2O2Se channel layer; the width of a depletion region of the Bi2O2Se channel layer is controlled through voltage applied to the MoO3 layer, so that the switching function of the transistor is achieved, a good sub-threshold characteristic is obtained, meanwhile, due to the high carrier mobility characteristic of the two-dimensional Bi2O2Se material, a remarkable electrical response can be obtained only by applying small source and drain voltage, and the performance of the transistor is improved. And excellent sub-threshold characteristics and conduction current performance are presented.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a field effect transistor and a preparation method thereof. Background Art

[0002] With the rapid development of mobile terminal and Internet of Things technologies, device power consumption optimization has become a key challenge in the semiconductor field. To meet the increasingly stringent energy efficiency requirements, while reducing the operating voltage, it is necessary to effectively improve the subthreshold characteristics of transistors to solve the problem of the sharp increase in leakage current caused by device miniaturization. MOSFET devices optimize the gate control ability through dielectric engineering solutions such as introducing high-k dielectrics, ferroelectric materials, or negative capacitance dielectrics, but these methods often face inherent problems such as interface charge trapping and ferroelectric hysteresis effects, resulting in a decrease in carrier mobility and device performance degradation.

[0003] The present invention innovatively uses self-grown two-dimensional semiconductors to construct field effect transistors. Its interface characteristics without dangling bonds can effectively suppress the generation of interface states, thereby obtaining junction characteristic parameters close to the ideal values. Summary of the Invention

[0004] Aiming at the technical problems existing in the prior art, the primary object of the present invention is to provide a field effect transistor and a preparation method thereof, which use a two-dimensional material Bi 2 O 2 Se layer grown in-situ on an insulating substrate as a channel layer, and transfer a two-dimensional material MoO 2 O 2 layer on the two-dimensional material Bi 3 Se channel layer as a gate dielectric layer to construct a field effect transistor. The obtained field effect transistor has advantages such as large current response, excellent optoelectronic performance, and low subthreshold swing.

[0005] On the one hand, the present invention provides a field effect transistor, including an insulating substrate, a two-dimensional material Bi 2 O 2 Se channel layer grown in-situ on the insulating substrate, a first electrode and a second electrode disposed on the two-dimensional material Bi 2 O 2 Se channel layer, a two-dimensional material MoO 2 O 2 layer disposed on the two-dimensional material Bi 2 O 2 Se channel layer, a third electrode disposed on the two-dimensional material MoO 3 layer, wherein the two-dimensional material MoO 3 layer completely covers the two-dimensional material Bi 3 O 2 O 2 Se channel layer.

[0006] On the one hand, the present invention provides a method for manufacturing a field effect transistor, comprising the following steps:

[0007] Growing a two-dimensional material Bi 2 O 2 Se channel layer on the insulating substrate;

[0008] Fabricating a first electrode and a second electrode on the two-dimensional material Bi 2 O 2 Se channel layer;

[0009] Transferring a two-dimensional material MoO 2 O 2 layer onto the two-dimensional material Bi 3 O 3 Se channel layer by using a dry transfer process, such that the two-dimensional material MoO 2 O 2 layer completely covers the two-dimensional material Bi

[0010] Fabricating a third electrode on the two-dimensional material MoO 3 layer;

[0011] Further, the dry transfer process is a PVA / PDMS dry transfer process.

[0012] Further, the thickness of the two-dimensional material Bi 2 O 2 Se channel layer is 10 - 20 nm, and the thickness of the two-dimensional material MoO 3 layer is 10 - 30 nm.

[0013] Further, the first electrode and the second electrode are a Cr / Au electrode layer, where the thickness of the Cr layer is 20 - 80 nm and the thickness of the Au layer is 20 - 80 nm; the third electrode is an Au electrode layer, and the thickness of the Au electrode layer is 30 - 120 nm.

[0014] Further, the insulating substrate is a mica substrate.

[0015] Further, the first electrode is the source electrode, the second electrode is the drain electrode, and the third electrode is the gate electrode.

[0016] The present invention uses in-situ grown high-quality two-dimensional material Bi 2 O 2 Se as the channel layer, and transfers a two-dimensional material MoO 2 O 2 layer onto the two-dimensional material Bi 3 Se channel layer to construct a field effect transistor, whose interface characteristics without dangling bonds effectively suppress the generation of interface states. At the same time, based on its high-quality two-dimensional material Bi 2 O2 The excellent electrical properties of Se significantly reduce the source-channel capacitance and achieve relatively excellent subthreshold characteristics.

[0017] In the absence of gate voltage, a space charge region is formed inside the field-effect transistor, and the two-dimensional material Bi 2 O 2 Se layer is partially depleted, which is in the off state. By changing the gate voltage, a negative gate voltage narrows the space charge region, and a positive gate voltage widens the space charge region, achieving the purpose of regulating the width of the space charge region and realizing the switching of the field-effect transistor. This device achieves a relatively excellent subthreshold swing (SS), and the two-dimensional material Bi 2 O 2 Se layer has a high carrier concentration, and a large current response can be achieved under a small source-drain voltage. The field-effect transistor of the present invention has the advantages of a large current response, excellent optical response performance, and a low subthreshold swing.

[0018] In addition, the field-effect transistor provided by the present invention has a simple structure and is easy to fabricate, which is beneficial for applications. Brief Description of the Drawings

[0019] Figure 1 is a micrograph of the field-effect transistor of a preferred embodiment of the present invention.

[0020] Figure 2 is the output curve measured for the field-effect transistor of a preferred embodiment of the present invention.

[0021] Figure 3 is the subthreshold swing curve of the field-effect transistor of a preferred embodiment of the present invention.

[0022] Figure 4 is the optical response diagram of the field-effect transistor of a preferred embodiment of the present invention under 635 nm laser irradiation.

[0023] Figure 5 is the I-T curve of the field-effect transistor of a preferred embodiment of the present invention under 635 nm laser irradiation with a gate voltage of -2 V and a source-drain voltage of 1 V.

[0024] Figure 6 is the I-T curve of the field-effect transistor of a preferred embodiment of the present invention under the irradiation of 635 nm polarized laser with a 30-degree change in direction, with a gate voltage of -2 V and a fixed source-drain voltage of 1 V. Detailed Description of the Invention

[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention. The experimental methods described in the following embodiments are all conventional methods unless otherwise specified; the reagents and materials described are all available from public commercial channels unless otherwise specified.

[0026] Spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used in this specification to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to those different from the orientations shown in the figures.

[0027] In addition, terms such as "first", "second", etc. are used to describe each element, layer, region, section, etc., and are not intended to be limiting. The terms "having", "containing", "including", "comprising", etc. are open-ended terms, indicating the presence of the stated element or feature, but not excluding additional elements or features. Unless the context clearly dictates otherwise.

[0028] An embodiment of the present invention provides a field effect transistor, as Figure 1 shown, which includes a mica substrate, a two-dimensional material Bi 2 O 2 Se channel layer stacked on the mica substrate, and a two-dimensional material MoO 3 layer. In this preferred embodiment, the substrate thickness is 1 - 5 mm, and the length and width are 1 cm × 1 cm.

[0029] The two-dimensional material Bi 2 O 2 Se channel layer is grown on the mica substrate by an in-situ growth process. For example, the existing chemical vapor deposition (CVD) process is used to grow the two-dimensional material Bi 2 O 2 Se layer on the mica substrate to obtain a high-quality channel layer.

[0030] A first electrode and a second electrode are provided on the two-dimensional material Bi 2 O 2 Se layer, and the first electrode and the second electrode do not contact. A third electrode is provided on the two-dimensional material MoO 3 layer, and the third electrode does not contact the two-dimensional material Bi 2 O 2 Se layer. The first electrode and the second electrode are the source electrode and the drain electrode respectively, and the third electrode is the gate electrode. Wherein MoO 3 acts as a gate dielectric layer. The two-dimensional material Bi 2 O2 The thickness of the Se channel layer is 10 - 20 nm. The thickness of the two-dimensional material MoO 3 layer is 10 - 30 nm.

[0031] By regulating the voltage applied to the gate dielectric layer, the width of the depletion region of the channel layer is regulated to realize the turn-on and turn-off of the field-effect transistor. As Figure 1 shown, the source electrode and the drain electrode are Cr / Au 1 electrode and Cr / Au2 electrode respectively, and the thicknesses of the Cr / Au1 electrode and the Cr / Au2 electrode are both 30 - 120 nm. The gate electrode is an Au electrode with a thickness of 30 - 120 nm.

[0032] This field-effect transistor achieves a relatively excellent subthreshold swing (SS). In a preferred embodiment, the two-dimensional material Bi 2 O 2 Se layer is in-situ grown on a mica substrate, has a high concentration of carriers, and can achieve a large current response under a small source-drain voltage. The field-effect transistor designed by the present invention has an extremely small subthreshold swing and a large on-state current, and is suitable for devices with low power consumption and large current design.

[0033] A preferred embodiment of the present invention introduces the preparation method of this field-effect transistor. As Figure 1 shown, an insulating mica substrate is selected. On the cleaned mica substrate, the two-dimensional Bi 2 O 2 Se material layer is grown by using the existing chemical vapor deposition process, where the growth process of Bi 2 O 2 Se is synthesized from two precursor materials, which are Bi 2 Se 3 (99.99% mass fraction) and Bi 2 O 3 (99.99% mass fraction). Select the appropriate ratio of the above two precursor materials, place the two precursor materials in a quartz boat. Using mica as the substrate, the growth set temperature is 600 - 700 °C, pure argon is used as the carrier gas, and the growth time varies from 15 to 30 minutes. Finally, the whole system is naturally cooled to room temperature. Finally, Bi 2 O 2 Se nanosheets are obtained on the mica substrate.

[0034] Select the Bi 2 O 2 Se nanosheets in the target area, spin-coat photoresist to form a photoresist layer with a thickness of 2 microns. Subsequently, through photolithography processes such as soft baking, exposure, and development, the photoresist is removed to form a patterned electrode pattern.

[0035] Next, a 50-nm-thick thin Cr layer and Au layer were deposited on the mica substrate using an electron beam evaporation device. Subsequently, the substrate was immersed in an acetone solution, and the excess metal automatically fell off, obtaining a substrate with a first electrode Cr / Au 1 and a second electrode Cr / Au 2.

[0036] A PDMS film was selected, and a PVA solution was evenly applied on the PDMS plate. Subsequently, it was heated at 70 °C for 5 minutes to form a PVA glue layer on the PDMS plate. Using a dry transfer platform, a two-dimensional material MoO 3 layer was transferred onto this PVA glue layer. The target two-dimensional material MoO 3 layer area was selected and adhered to Bi 2 O 2 Se. After heating, the PDMS plate was peeled off from the substrate, and then the PVA glue layer was removed after soaking in deionized water.

[0037] Among them, the growth process of MoO 3 was to grow layered MoO 3 nanosheets by an existing physical vapor deposition (PVD) method. Specifically, an appropriate amount of MoO 3 powder was placed in a ceramic boat, and a clean SiO 2 / Si was used as the substrate. The reaction was carried out at atmospheric pressure, and pure argon gas was used as the carrier gas. The reaction temperature was between 740 and 790 °C. The growth time varied from 10 to 30 minutes. Finally, the whole system was naturally cooled to room temperature. Finally, MoO 2 nanosheets were obtained on the SiO 3 / Si substrate.

[0038] Subsequently, using photolithography and an evaporation platform, a third electrode Au 3 was photolithographed in the MoO 3 layer area to complete the preparation of the device.

[0039] The optoelectronic performance of the field-effect transistor provided in the above preferred embodiment was tested. Among them, Figure 2 is the output curve graph of the field-effect transistor provided by the present invention. The source-drain voltage ranges from 0 V to 1 V, and the gate voltage was tested under the conditions of 0 V, -2 V, -1 V, 1 V, and 2 V respectively. The maximum source-drain current of this device reached more than 1.1 μA, showing good regulation properties; Figure 3 is the subthreshold swing curve of an embodiment of the present invention. It can be seen from the figure that the minimum subthreshold swing is about 238 mV / dec. Figure 4 is the field-effect transistor device of an embodiment of the present invention. Under the condition of applying a voltage from 0 V to 1 V, the current responses under different power densities from 0.77 mw / cm 2 to 108.5 mw / cm 2 were measured in the dark and under a 635-nm laser environment.Figure 5 For the field-effect transistor according to an embodiment of the present invention, when irradiated with 635-nm laser and with a bias voltage of 1 V and a gate voltage of -2 V, its time-resolved optical switch (IT) curve is shown according to Figure 6 It can be seen that the field-effect transistor of the present invention has good polarized light detectability and adjustable polarization ratio of the gate voltage (source-drain voltage) under 635-nm light illumination. The above test results of optoelectronic properties show that the field-effect transistor provided by the present invention has advantages such as a low subthreshold swing, a large current, and polarized light detection.

[0040] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A field effect transistor, characterized in that: It includes an insulating substrate, a two-dimensional material Bi2O2Se channel layer in-situ grown on the insulating substrate, a first electrode and a second electrode arranged on the two-dimensional material Bi2O2Se channel layer, a two-dimensional material MoO3 layer arranged on the two-dimensional material Bi2O2Se channel layer, and a third electrode arranged on the two-dimensional material MoO3 layer, wherein the two-dimensional material MoO3 layer completely covers the two-dimensional material Bi2O2Se channel layer.

2. The field effect transistor according to claim 1, characterized in that The first electrode is a source electrode, the second electrode is a drain electrode, and the third electrode is a gate electrode.

3. The field effect transistor according to claim 1 or 2, characterized in that: The thickness of the two-dimensional material Bi2O2Se channel layer is 10-20 nm, and the thickness of the two-dimensional material MoO3 layer is 10-30 nm.

4. The field effect transistor according to claim 3, characterized in that: The first electrode and the second electrode are Cr / Au electrode layers, wherein the thickness of the Cr layer is 20-80 nm, and the thickness of the Au layer is 20-80 nm; the third electrode is an Au electrode layer, and the thickness of the Au electrode layer is 30-120 nm.

5. The field effect transistor according to any one of claims 1, 2 and 4, characterized in that: The insulating substrate is a mica substrate.

6. A method for preparing a field effect transistor, characterized in that: The following steps are involved: Growing a two-dimensional material Bi2O2Se channel layer on the insulating substrate; Preparing a first electrode and a second electrode on the two-dimensional material Bi2O2Se channel layer; A two-dimensional material MoO3 layer is transferred onto the two-dimensional material Bi2O2Se channel layer by a dry transfer process, and the two-dimensional material MoO3 layer completely covers the two-dimensional material Bi2O2Se layer; A third electrode is prepared on the two-dimensional material MoO3 layer.

7. The preparation method according to claim 6, characterized in that: The dry transfer process is a PVA / PDMS dry transfer process.

8. The preparation method according to claim 6 or 7, characterized in that: The thickness of the two-dimensional material Bi2O2Se layer is 10-20 nm, and the thickness of the two-dimensional material MoO3 layer is 10-30 nm.

9. The preparation method according to claim 8, characterized in that: The first electrode and the second electrode are Cr / Au electrode layers, wherein the thickness of the Cr layer is 20-80 nm, and the thickness of the Au layer is 20-80 nm; the third electrode is an Au electrode layer, and the thickness of the Au electrode layer is 30-120 nm.

10. The preparation method according to any one of claims 6, 7 and 9, characterized in that: The insulating substrate is a mica substrate; The first electrode is a source electrode, the second electrode is a drain electrode, and the third electrode is a gate electrode.

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