Semiconductor device, method for manufacturing semiconductor device, and electronic device

Abstract

According to the semiconductor device, the manufacturing method of the semiconductor device and the electronic device provided by the invention, two semiconductor layers with different carrier mobility are arranged, the semiconductor layer with low carrier mobility covers the semiconductor layer with high carrier mobility, and the semiconductor layer with high carrier mobility is located in the coverage range of the first electrode, so that the reliability of the semiconductor device is improved. Therefore, when ion implantation is carried out on the semiconductor layer to form the source contact region and the drain contact region, the implanted ions are mainly concentrated in a region with low carrier mobility, so that the ion diffusion distance can be reduced, and the effective channel length of the semiconductor device is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology devices, and more particularly, to a semiconductor device, a manufacturing method of the semiconductor device, and an electronic device. Background Art

[0002] With the development of electronic device manufacturing technology, there are increasingly high requirements for the size of semiconductor devices used in electronic devices. For example, in a display panel, semiconductor switching devices with small size and high carrier mobility can effectively increase the pixel density (Pixels Per Inch, PPI) of the display panel. However, the structural performance of current semiconductor devices still needs to be improved. Summary of the Invention

[0003] In order to overcome the above deficiencies in the prior art, an object of the present application is to provide a semiconductor device, the semiconductor device comprising:

[0004] a substrate;

[0005] a buffer layer located on one side of the substrate;

[0006] a first semiconductor layer located on the side of the buffer layer away from the substrate;

[0007] a second semiconductor layer located on the side of the first semiconductor layer and the buffer layer away from the substrate, the carrier mobility of the second semiconductor layer being less than that of the first semiconductor layer; the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the second semiconductor layer on the substrate;

[0008] a first insulating layer located on the side of the second semiconductor layer away from the substrate;

[0009] a first electrode located on the side of the first insulating layer away from the substrate; the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the first electrode on the substrate.

[0010] In some possible implementation manners, the second semiconductor layer includes a first region, a second region, and a third region. In a first direction parallel to the substrate, the orthographic projection of the first region on the substrate is located between the orthographic projections of the second region and the third region on the substrate; the orthographic projection of the first region on the substrate coincides with the orthographic projection of the first semiconductor layer on the substrate.

[0011] In some possible implementation manners, the buffer layer includes a groove that is recessed from the side away from the substrate toward the side close to the substrate;

[0012] The first semiconductor layer extends from the bottom of the trench and adheres to two opposite sidewalls of the trench in the first direction;

[0013] The second semiconductor layer extends along the first direction from one side outside the trench, through the first semiconductor layer located in the trench, to the other side outside the trench.

[0014] In some possible implementation manners, the buffer layer includes a first buffer layer and a second buffer layer, and the second buffer layer is located between the first buffer layer and the first semiconductor layer; the density of the second buffer layer is greater than that of the first buffer layer.

[0015] In some possible implementation manners, the density of the second buffer layer is 5 g / cm 3 to 7 g / cm 3 .

[0016] In some possible implementation manners, the first buffer layer includes a recessed portion that is recessed from the side away from the substrate toward the side close to the substrate, and the second buffer layer covers the bottom and sidewalls of the recessed portion to form the trench.

[0017] In some possible implementation manners, in the region outside the recessed portion, the thickness range of the first buffer layer is to The thickness range of the second buffer layer is to

[0018] In some possible implementation manners, the orthographic projection of the second buffer layer on the substrate is located within the orthographic projection of the recessed portion on the substrate, and the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the second buffer layer on the substrate.

[0019] In some possible implementation manners, the portions of the second buffer layer and the first semiconductor layer that adhere to the sidewalls of the recessed portion are flush with the opening of the recessed portion on the side away from the substrate.

[0020] In some possible implementation manners, the buffer layer includes a protrusion that protrudes from the side close to the substrate toward the side away from the substrate;

[0021] The first semiconductor layer adheres to the side away from the substrate of the protrusion and two opposite sidewalls of the protrusion in the first direction;

[0022] The second semiconductor layer extends along the first direction from one side of the protrusion to the other side of the protrusion through the first semiconductor layer adhered to the protrusion.

[0023] In some possible implementations, the buffer layer includes a first buffer layer and a second buffer layer. The second buffer layer is located between the first buffer layer and the first semiconductor layer, and the density of the second buffer layer is greater than that of the first buffer layer. Preferably, the density of the second buffer layer is 5 g / cm 3 to 7 g / cm 3 .

[0024] In some possible implementations, the first buffer layer includes a protrusion protruding from the side close to the substrate to the side away from the substrate. The second buffer layer covers the top and side walls of the protrusion to form the protrusion.

[0025] In some possible implementations, in the region other than the protrusion, the thickness range of the first buffer layer is to The thickness range of the second buffer layer is to

[0026] In some possible implementations, the orthographic projection of the protrusion on the substrate is located within the orthographic projection of the second buffer layer on the substrate, and the orthographic projection of the second buffer layer on the substrate is located within the orthographic projection of the first semiconductor layer on the substrate.

[0027] In some possible implementations, the material of the first semiconductor layer includes indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is 2:1 to 5:1;

[0028] The material of the second semiconductor layer includes indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is less than 2:1.

[0029] In some possible implementations, the metal doped in the first semiconductor layer includes at least one of gallium, tin, niobium, and tantalum; the metal doped in the second semiconductor layer includes at least one of gallium and tin.

[0030] In some possible implementations, the thickness range of the first semiconductor layer is to The thickness range of the second semiconductor layer is to

[0031] In some possible implementations, the semiconductor device further includes:

[0032] A third semiconductor layer located between the first semiconductor layer and the buffer layer, and the carrier mobility of the third semiconductor layer is less than that of the first semiconductor layer.

[0033] In some possible implementation manners, the semiconductor device further includes:

[0034] a second insulating layer located on a side of the first electrode and the first insulating layer away from the substrate;

[0035] a second electrode and a third electrode located on a side of the second insulating layer away from the substrate, wherein the second electrode and the third electrode are electrically connected to the second region and the third region respectively through through holes penetrating the second insulating layer and the first insulating layer.

[0036] The present application further provides a manufacturing method of a semiconductor device, the method including:

[0037] providing a substrate;

[0038] forming a buffer layer and a first semiconductor layer on one side of the substrate;

[0039] forming a second semiconductor layer on a side of the first semiconductor layer and the buffer layer away from the substrate, wherein a carrier mobility of the second semiconductor layer is less than a carrier mobility of the first semiconductor layer; a positive projection of the first semiconductor layer on the substrate is located within a positive projection of the second semiconductor layer on the substrate;

[0040] forming a first insulating layer on a side of the second semiconductor layer away from the substrate;

[0041] forming a first electrode on a side of the first insulating layer away from the substrate; a positive projection of the first semiconductor layer on the substrate is located within a positive projection of the first electrode on the substrate;

[0042] performing ion implantation on the second semiconductor layer from a side of the first electrode away from the substrate.

[0043] The present application further provides an electronic device, the electronic device including the semiconductor device provided by the present application.

[0044] Compared with the prior art, the present application has the following beneficial effects:

[0045] The present application provides a semiconductor device, a manufacturing method of a semiconductor device, and an electronic device. By providing two semiconductor layers with different carrier mobilities, the semiconductor layer with a low carrier mobility covers the semiconductor layer with a high carrier mobility, and the semiconductor layer with a high carrier mobility is located within the coverage range of the first electrode. In this way, when ion implantation is performed on the semiconductor layer to form a source contact region and a drain contact region, the implanted ions are mainly concentrated in the region with a low carrier mobility, thereby reducing the ion diffusion distance and ensuring the effective channel length of the semiconductor device. Description of the Drawings

[0046] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following accompanying drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these drawings.

[0047] Figure 1 It is a schematic structural diagram of a semiconductor device in the related art;

[0048] Figure 2 It is a schematic diagram of ion implantation of a semiconductor device in the related art;

[0049] Figure 3 It is one of the schematic structural diagrams of the display panel provided in this embodiment;

[0050] Figure 4 It is another schematic structural diagram of the display panel provided in this embodiment;

[0051] Figure 5 It is the third schematic structural diagram of the display panel provided in this embodiment;

[0052] Figure 6 It is the fourth schematic structural diagram of the display panel provided in this embodiment;

[0053] Figure 7 It is the fifth schematic structural diagram of the display panel provided in this embodiment;

[0054] Figure 8 It is the sixth schematic structural diagram of the display panel provided in this embodiment;

[0055] Figure 9 It is the seventh schematic structural diagram of the display panel provided in this embodiment;

[0056] Figure 10 It is the eighth schematic structural diagram of the display panel provided in this embodiment;

[0057] Figure 11 It is the ninth schematic structural diagram of the display panel provided in this embodiment;

[0058] Figure 12 It is the tenth schematic structural diagram of the display panel provided in this embodiment;

[0059] Figure 13 It is the eleventh schematic structural diagram of the display panel provided in this embodiment;

[0060] Figure 14 It is a schematic flow chart of the steps of the manufacturing method of the display panel provided in this embodiment;

[0061] Figure 15 Schematic diagram of the manufacturing process of the display panel provided in this embodiment.

[0062] Icons: 110 - Substrate; 120 - Buffer layer; 121 - First buffer layer; 122 - Second buffer layer; 1201 - Groove; 1202 - Protrusion; 131 - First semiconductor layer; 132 - Second semiconductor layer; 133 - Third semiconductor layer; 1321 - First region; 1322 - Second region; 1323 - Third region; 140 - First insulating layer; 150 - First electrode; 160 - Second insulating layer; 170 - Second electrode; 180 - Third electrode. Detailed implementation manners

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. Generally, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0064] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0065] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0066] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0067] It should be noted that, without conflict, different features in the embodiments of the present application can be combined with each other.

[0068] Please refer to Figure 1 ,Figure 1 It is a schematic structural diagram of a semiconductor device in the related art. Such a semiconductor device includes a substrate 110', a buffer layer 120' on one side of the substrate 110', a semiconductor layer 130' on the side of the buffer layer 120' away from the substrate 110', a first insulating layer 140' on the side of the semiconductor layer 130' away from the substrate 110', a gate 150' on the side of the first insulating layer 140' away from the substrate 110', a second insulating layer 160' on the side of the gate 150' layer away from the substrate 110', a source electrode 170' and a drain electrode 180' electrically connected to the semiconductor layer 130' from the side of the second insulating layer 160' away from the substrate 110'.

[0069] Among them, please refer to Figure 2 , in the manufacturing process of the above semiconductor layer device, after the gate 150' is formed, the gate 150' serves as a mask, and then ion implantation is performed from one side of the gate 150', so as to form a source contact region and a drain contact region at both ends of the semiconductor layer 130'. However, after the semiconductor layer 130' undergoes ion implantation, the implanted ions will diffuse in the semiconductor layer 130', resulting in an expansion of the conductive region of the semiconductor layer 130' and reducing the effective channel length of the semiconductor device. Especially in some semiconductor devices, in order to reduce the size of the semiconductor device, a semiconductor layer 130' with a higher carrier mobility is used, and the degree of diffusion in the semiconductor layer 130' after ion implantation is greater, increasing the risk of abnormal conduction of the semiconductor device.

[0070] In view of this, this embodiment provides a solution that can suppress the diffusion distance of implanted ions in the semiconductor layer and ensure the effective channel length of the device. The solution provided in this embodiment will be elaborated in detail below.

[0071] Please refer to [[ID=B]]Figure 3 , Figure 3 which is a schematic structural diagram of a semiconductor device provided in this embodiment. The semiconductor device may include a substrate 110, a buffer layer 120, a first semiconductor layer 131, a second semiconductor layer 132, a first insulating layer 140, and a first electrode 150.

[0072] In this embodiment, the substrate 110 may be coated with polyimide (PI). For example, the substrate 110 may be coated with a double-layer polyimide. The thickness of the first layer of polyimide may be 7.5 to 9.5 micrometers (for example, it may be 8.3 micrometers, 8.5 micrometers, or 8.7 micrometers), and the thickness of the second layer of polyimide may be 6.5 micrometers to 8.5 micrometers (for example, it may be 7.3 micrometers, 7.5 micrometers, or 7.7 micrometers).

[0073] The buffer layer 120 is located on one side of the substrate 110. In this embodiment, the material of the buffer layer 120 may include inorganic oxides or metal oxides.

[0074] The first semiconductor layer 131 is located on the side of the buffer layer 120 away from the substrate 110, and the second semiconductor layer 132 is located on the side of the first semiconductor layer 131 away from the substrate 110. In this embodiment, the carrier mobility of the second semiconductor layer 132 is less than that of the first semiconductor layer 131.

[0075] The orthographic projection of the first semiconductor layer 131 on the substrate 110 is located within the orthographic projection of the second semiconductor layer 132 on the substrate 110.

[0076] The first insulating layer 140 is located on the side of the second semiconductor layer 132 away from the substrate 110. In this embodiment, the first insulating layer 140 may be a gate insulating layer (GI).

[0077] The first electrode 150 is located on the side of the first insulating layer 140 away from the substrate 110. In this embodiment, the first electrode 150 may be a gate. The orthographic projection of the first semiconductor layer 131 on the substrate 110 is located within the orthographic projection of the first electrode 150 on the substrate 110.

[0078] Thus, in this embodiment, after the first electrode 150 is formed, when ion implantation is performed on the semiconductor layer, the first electrode 150 can shield the first region 1321 of the first semiconductor layer 131 and the second semiconductor layer 132, so that the implanted ions are mainly concentrated in the second semiconductor layer 132 with a lower carrier mobility, which can reduce the diffusion distance of the implanted ions and ensure the effective channel length of the semiconductor device.

[0079] In some possible implementation manners, please refer to Figure 4 , the second semiconductor layer 132 may include a first region 1321, a second region 1322, and a third region 1323. In the first direction D1 parallel to the substrate 110, the orthographic projection of the first region 1321 on the substrate 110 is located between the orthographic projections of the second region 1322 and the third region 1323 on the substrate 110. The orthographic projection of the first region 1321 on the substrate 110 coincides with the orthographic projection of the first semiconductor layer 131 on the substrate 110, and the orthographic projections of the second region 1322 and the third region 1323 on the substrate 110 do not coincide with the orthographic projection of the first semiconductor layer 131 on the substrate 110.

[0080] That is, in this embodiment, the second semiconductor layer 132 may cover the first semiconductor layer 131, and both ends of the second semiconductor layer 132 in the first direction D1 extend beyond the first semiconductor layer 131. In this way, during the subsequent ion implantation process, ion implantation can be performed only on the second region 1322 and the third region 1323 of the second semiconductor layer 132 that extend beyond the first semiconductor layer 131, thereby avoiding the lateral diffusion of implanted ions in the first semiconductor layer 131 with a large mobility and affecting the channel length.

[0081] Further, in some possible implementation manners, please refer to Figure 3 again, the semiconductor device further includes a second insulating layer 160, a second electrode 170, and a third electrode 180.

[0082] The second insulating layer 160 is located on the side of the first electrode 150 and the first insulating layer 140 away from the substrate 110. In this embodiment, the second insulating layer 160 may include a capacitance insulation layer (CI).

[0083] The second electrode 170 and the third electrode 180 may be located on the side of the second insulating layer 160 away from the substrate 110, and are electrically connected to the second region 1322 and the third region 1323 respectively through through holes penetrating the second insulating layer 160 and the first insulating layer 140. In this embodiment, the second electrode 170 and the third electrode 180 may be a drain electrode and a source electrode respectively.

[0084] In some possible implementation manners, please refer to Figure 5 again, the buffer layer 120 may include a groove 1201 that is recessed from the side away from the substrate 110 toward the side close to the substrate 110.

[0085] Please refer to Figure 6 again, the first semiconductor layer 131 extends from the bottom of the groove 1201 and adheres to two opposite sidewalls of the groove 1201 in the first direction D1.

[0086] The second semiconductor layer 132 extends along the first direction D1 from one side outside the groove 1201, passes through the first semiconductor layer 131 located in the groove 1201, and extends to the other side outside the groove 1201. Among them, please refer to Figure 7 again, in the first direction D1, the second region 1322 and the third region 1323 of the second semiconductor layer 132 may be located on both sides outside the groove 1201.

[0087] Thus, at least a part of the channel region formed by the first semiconductor layer 131 and the second semiconductor layer 132 can extend along the sidewall of the trench 1201 in the thickness direction of the buffer layer 120, so that the effective channel length of the semiconductor device can be increased without increasing the size of the semiconductor device in the first direction D1, thereby improving the pixel density (PPI) of the display panel.

[0088] In some possible implementation manners, please refer to Figure 8 , the buffer layer 120 includes a first buffer layer 121 and a second buffer layer 122, and the second buffer layer 122 is located between the first buffer layer 121 and the first semiconductor layer 131. The density of the second buffer layer 122 is greater than that of the first buffer layer 121. Thus, by disposing the dense second buffer layer 122 between the first buffer layer 121 and the first semiconductor layer 131, the second buffer layer 122 can block the influence of backside impurities such as hydrogen ions in other film layers on one side of the substrate 110 on the first semiconductor layer 131 and the second semiconductor layer 132, and ensure the working performance of the semiconductor device.

[0089] Optionally, in this embodiment, the density of the second buffer layer 122 is 5 g / cm 3 to 7 g / cm 3 , for example, it can be 5.5 g / cm 3 , 6 g / cm 3 or 6.5 g / cm 3 .

[0090] Furthermore, please refer to Figure 9 , the first buffer layer 121 includes a recessed portion that is recessed from the side away from the substrate 110 toward the side close to the substrate 110, and the second buffer layer 122 covers the bottom and sidewalls of the recessed portion to form the trench 1201.

[0091] For example, in this embodiment, since the first buffer layer 121 has a small density and a large thickness, a recessed portion can be etched in the first buffer layer 121 first, and then a second buffer layer 122 with a large density and a small thickness attached to the bottom and sidewalls of the recessed portion can be formed in the recessed portion by deposition.

[0092] Optionally, the first buffer layer 121 may be formed by plasma enhanced chemical vapor deposition (PECVD), and then the second buffer layer 122 may be formed by atomic layer deposition (ALD) with a relatively low film formation rate. It should be noted that the formation methods of the first buffer layer 121 and the second buffer layer 122 described above are only an optional method provided in this embodiment. In this embodiment, other methods may also be used to form the first buffer layer 121 and the second buffer layer 122. For example, both the first buffer layer and the second buffer layer may be formed by plasma enhanced chemical vapor deposition, which is not specifically limited herein.

[0093] Optionally, please refer to Figure 9 , in the region outside the recess, the thickness H1 of the first buffer layer 121 ranges from to For example, it may be or The thickness H2 of the second buffer layer 122 ranges from to For example, it may be or

[0094]

[0095] In some possible implementation manners, please refer to Figure 10 , a part of the second buffer layer 122 and the first semiconductor layer 131 may extend from within the recess of the first buffer layer 121 to outside the recess.

[0096] In some other possible implementation manners, please refer to Figure 8 again, the orthographic projection of the second buffer layer 122 on the substrate 110 is located within the orthographic projection of the recess on the substrate 110, and the orthographic projection of the first semiconductor layer 131 on the substrate 110 is located within the orthographic projection of the second buffer layer 122 on the substrate 110. That is, both the second buffer layer 122 and the first semiconductor layer 131 are only located within the recess of the first buffer layer 121. Preferably, the side of the part of the second buffer layer 122 and the first semiconductor layer 131 attached to the side wall of the recess away from the substrate 110 is flush with the opening of the recess. In this way, the second buffer layer 122 and the first semiconductor layer 131 are deposited as a whole layer and then etched together to form the Figure 8 shown morphology, thereby reducing the manufacturing process of the semiconductor device and improving the manufacturing efficiency.

[0097] In some possible implementations, the material of the first semiconductor layer 131 includes indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is from 2:1 to 5:1. For example, the atomic ratio of indium to zinc can be 2.5:1, 3.5:1, or 4.5:1. The first semiconductor layer 131 can be formed by atomic layer deposition (ALD) or physical vapor deposition (PVD).

[0098] The material of the second semiconductor layer 132 includes indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is less than 2:1. For example, the atomic ratio of indium to zinc can be 1.5:1, 1:1, or 1:2. The second semiconductor layer 132 can be formed by atomic layer deposition or physical vapor deposition.

[0099] Optionally, the metal doped in the first semiconductor layer 131 includes at least one of gallium, tin, niobium, and tantalum; the metal doped in the second semiconductor layer 132 includes at least one of gallium and tin.

[0100] Optionally, the thickness range of the first semiconductor layer 131 is to For example, the thickness of the first semiconductor layer 131 can be or The thickness range of the second semiconductor layer 132 is to For example, the thickness of the second semiconductor layer 132 can be or

[0101]

[0102] In some possible implementations, the material of the first buffer layer 121 can include a stacked structure of silicon oxide (SiOx) and amorphous silicon (a-Si).

[0103] The material of the second buffer layer 122 can include inorganic oxides, including silicon-based oxides. For example, the material of the second buffer layer 122 can include silicon oxide SiOx, and an insulating layer with high density and low hydrogen content (such as hydrogen content less than 5%) is formed by a high-temperature process (≥250°C).

[0104] The material of the second buffer layer 122 can include metal oxides, such as aluminum oxide (Al2O3) or indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is less than 2:1. For example, the atomic ratio of indium to zinc can be 1.5:1, 1:1, or 1:2. The metal doped in the second buffer layer 122 includes gallium or tin.

[0105] In some possible implementations, please refer to Figure 11, the semiconductor device may further include a third semiconductor layer 133.

[0106] The third semiconductor layer 133 is located between the first semiconductor layer 131 and the buffer layer 120, and the carrier mobility of the third semiconductor layer 133 is less than that of the first semiconductor layer 131.

[0107] The material of the third semiconductor layer 133 includes indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is less than 2:1. For example, the atomic ratio of indium to zinc can be 1.5:1, 1:1 or 1:2. The third semiconductor layer 133 can be formed by atomic layer deposition or physical vapor deposition. The thickness range of the third semiconductor layer 133 is to For example, the thickness of the third semiconductor layer 133 can be or

[0108] In this way, the third semiconductor layer 133 can improve the backside impurity (such as hydrogen ions) blocking ability of the semiconductor device from the side of the substrate 110. In addition, by controlling the manufacturing process, multiple semiconductor layers can also be combined into multiple conductive channels to improve the overall carrier mobility of the semiconductor device.

[0109] In some other possible implementation manners, please refer to Figure 12 , the buffer layer 120 may include a protrusion 1202 protruding from the side close to the substrate 110 to the side away from the substrate 110.

[0110] The first semiconductor layer 121 adheres to the side of the protrusion 1202 away from the substrate 110 and the two sidewalls of the protrusion 1202 opposite to each other in the first direction D1. The second semiconductor layer 122 adheres to the first semiconductor layer 121 on the protrusion 1202 and extends from one side of the protrusion 1202 to the other side of the protrusion along the first direction D1.

[0111] In this way, at least a part of the channel region formed by the first semiconductor layer 131 and the second semiconductor layer 132 can extend along the sidewall of the protrusion 1202 in the thickness direction of the buffer layer 120, so that the effective channel length of the semiconductor device can be increased without increasing the size of the semiconductor device in the first direction D1, thereby improving the pixel density (PPI) of the display panel.

[0112] Further, please refer to Figure 13, the buffer layer 120 may include a first buffer layer 121 and a second buffer layer 122, and the second buffer layer 122 is located between the first buffer layer 121 and the first semiconductor layer 131. The density of the second buffer layer 122 is greater than that of the first buffer layer 121. Thus, a dense second buffer layer 122 is provided between the first buffer layer 121 and the first semiconductor layer 131, and the second buffer layer 122 can block the influence of backside impurities such as hydrogen ions in other film layers on one side of the substrate 110 on the first semiconductor layer 131 and the second semiconductor layer 132, ensuring the working performance of the semiconductor device.

[0113] Optionally, in this embodiment, the density of the second buffer layer 122 is 5 g / cm 3 to 7 g / cm 3 , for example, it may be 5.5 g / cm 3 、6 g / cm 3 or 6.5 g / cm 3 .

[0114] Furthermore, please refer to Figure 13 again, the first buffer layer 121 includes a protruding portion protruding from the side close to the substrate 110 to the side away from the substrate 110, and the second buffer layer 122 covers the top and side walls of the protruding portion to form a protrusion 1202.

[0115] Optionally, in the area other than the protruding portion, the thickness range of the first buffer layer 121 is to For example, it may be or The thickness range of the second buffer layer 122 is to For example, it may be or

[0116] In some other possible implementation manners, please refer to Figure 13 again, the orthographic projection of the protruding portion on the substrate 110 is located within the orthographic projection of the second buffer layer 122 on the substrate 110, and the orthographic projection of the second buffer layer 122 on the substrate 110 is located within the orthographic projection of the first semiconductor layer 131 on the substrate 110. That is, both the second buffer layer 122 and the first semiconductor layer 131 are located outside the protruding portion of the first buffer layer 121.

[0117] This embodiment also provides a manufacturing method of a semiconductor device. Please refer to Figure 12 again, the method may include the following steps.

[0118] Step S110, provide a substrate 110.

[0119] Step S120: Form a buffer layer 120 and a first semiconductor layer 131 on one side of the substrate 110.

[0120] Step S130: Form a second semiconductor layer 132 on the side of the first semiconductor layer 131 and the buffer layer 120 away from the substrate 110.

[0121] Among them, the orthographic projection of the first semiconductor layer 131 on the substrate 110 is located within the orthographic projection of the second semiconductor layer 132 on the substrate 110. For example, the carrier mobility of the second semiconductor layer 132 is less than that of the first semiconductor layer 131. The second semiconductor layer 132 includes a first region 1321, a second region 1322, and a third region 1323. In the first direction D1 parallel to the substrate 110, the orthographic projection of the first region 1321 on the substrate 110 is located between the orthographic projections of the second region 1322 and the third region 1323 on the substrate 110. The orthographic projection of the first region 1321 on the substrate 110 coincides with the orthographic projection of the first semiconductor layer 131 on the substrate 110, and the orthographic projections of the second region 1322 and the third region 1323 on the substrate 110 do not coincide with the orthographic projection of the first semiconductor layer 131 on the substrate 110.

[0122] Step S140: Form a first insulating layer 140 on the side of the second semiconductor layer 132 away from the substrate 110.

[0123] Step S150: Form a first electrode 150 on the side of the first insulating layer 140 away from the substrate 110. The orthographic projection of the first semiconductor layer 131 on the substrate 110 is located within the orthographic projection of the first electrode 150 on the substrate 110.

[0124] Step S160: Perform ion implantation on the second semiconductor layer 132 from the side of the first electrode 150 away from the substrate 110.

[0125] In some possible implementation manners, the buffer layer 120 may include a trench 1201 that is recessed from the side away from the substrate 110 toward the side close to the substrate 110. The first semiconductor layer 131 extends from the bottom of the trench 1201 and adheres to the two opposite sidewalls of the trench 1201 in the first direction D1. The second semiconductor layer 132 extends along the first direction D1 from one side of the trench 1201 through the first semiconductor layer 131 located in the trench 1201 to the other side of the trench 1201. Among them, please refer to Figure 7 It should be noted that there seems to be an incorrect tag [[ID=B]] in the original text. It is recommended to check and correct it to ensure the accuracy of the translation. If this is just a placeholder error in the original and not a real tag, the translation remains as above. , in the first direction D1, the second region 1322 and the third region 1323 of the second semiconductor layer 132 may be located on both sides outside the trench 1201.

[0126] Furthermore, the buffer layer 120 includes a first buffer layer 121 and a second buffer layer 122. Specifically, step S120 may include the following sub-steps.

[0127] Step S121, form a first buffer layer 121 on the substrate 110, and form a recessed portion on the first buffer layer 121 that recesses from the side away from the substrate 110 towards the side close to the substrate 110.

[0128] Step S122, sequentially form a second buffer layer 122 and a first semiconductor layer 131 by deposition from the side of the first buffer layer 121 away from the substrate 110, and perform patterned etching on the second buffer layer 122 and the first semiconductor layer 131 to remove the second buffer layer 122 and the first semiconductor layer 131 other than the recess.

[0129] In some other possible implementation manners, the buffer layer 120 may include a protrusion 1202 that protrudes from the side close to the substrate 110 towards the side away from the substrate 110.

[0130] The first semiconductor layer 121 adheres to the side of the protrusion 1202 away from the substrate 110 and the two sidewalls of the protrusion 1202 opposite to each other in the first direction D1. The second semiconductor layer 122 adheres to the first semiconductor layer 121 on the protrusion 1202 and extends from one side of the protrusion 1202 to the other side of the protrusion along the first direction D1.

[0131] Furthermore, the buffer layer 120 includes a first buffer layer 121 and a second buffer layer 122. Specifically, step S120 may include the following sub-steps.

[0132] Step S121, form a first buffer layer 121 on the substrate 110, and etch the first buffer layer 121 to form a protruding portion that protrudes from the side close to the substrate 110 towards the side away from the substrate 110.

[0133] Step S122, sequentially form a second buffer layer 122 covering the protruding portion and a first semiconductor layer 131 covering the second buffer layer 122 by deposition from the side of the first buffer layer 121 away from the substrate 110.

[0134] This embodiment also provides an electronic device, and the electronic device includes the semiconductor device provided in this application.

[0135] Optionally, the electronic device may include a device with a display function. For example, the electronic device may include a display panel, a mobile phone, a tablet computer, a smart wearable device, a television, a laptop computer, a monitor, etc.

[0136] In summary, the present application provides a semiconductor device, a manufacturing method of the semiconductor device, and an electronic device. By providing two semiconductor layers with different carrier mobilities, the semiconductor layer with a low carrier mobility covers the semiconductor layer with a high carrier mobility, and the semiconductor layer with a high carrier mobility is located within the coverage range of the first electrode. In this way, when ion implantation is performed on the semiconductor layer to form a source contact region and a drain contact region, the implanted ions are mainly concentrated in the region with a low carrier mobility, thereby reducing the ion diffusion distance and ensuring the effective channel length of the semiconductor device.

[0137] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0138] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: a substrate; a buffer layer located on one side of the substrate; a first semiconductor layer located on the side of the buffer layer away from the substrate; a second semiconductor layer located on the side of the first semiconductor layer and the buffer layer away from the substrate, the carrier mobility of the second semiconductor layer being less than that of the first semiconductor layer; the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the second semiconductor layer on the substrate; a first insulating layer located on the side of the second semiconductor layer away from the substrate; a first electrode located on the side of the first insulating layer away from the substrate; the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the first electrode on the substrate.

2. The semiconductor device according to claim 1, wherein, The second semiconductor layer includes a first region, a second region, and a third region. In a first direction parallel to the substrate, the orthographic projection of the first region on the substrate is located between the orthographic projections of the second region and the third region on the substrate; the orthographic projection of the first region on the substrate coincides with the orthographic projection of the first semiconductor layer on the substrate.

3. The semiconductor device according to claim 2, wherein The buffer layer includes a trench recessed from the side away from the substrate toward the side close to the substrate; The first semiconductor layer extends from the bottom of the trench and adheres to two opposite sidewalls of the trench in the first direction; The second semiconductor layer extends along the first direction from one side outside the trench, passes through the first semiconductor layer located in the trench, and extends to the other side outside the trench.

4. The semiconductor device according to claim 3, wherein The buffer layer includes a first buffer layer and a second buffer layer. The second buffer layer is located between the first buffer layer and the first semiconductor layer, and the density of the second buffer layer is greater than that of the first buffer layer; Preferably, the density of the second buffer layer is 5 g / cm 3 to 7 g / cm 3 .

5. The semiconductor device according to claim 4, wherein The first buffer layer includes a recess recessed from the side away from the substrate toward the side close to the substrate, and the second buffer layer covers the bottom and sidewalls of the recess to form the trench; Preferably, in the region outside the recessed portion, the thickness range of the first buffer layer is to The thickness range of the second buffer layer is to 6. The semiconductor device according to claim 5, wherein, The orthographic projection of the second buffer layer on the substrate is located within the orthographic projection of the recess on the substrate, and the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the second buffer layer on the substrate; Preferably, the part of the second buffer layer and the first semiconductor layer adhering to the sidewall of the recess away from the substrate is flush with the opening of the recess.

7. The semiconductor device according to claim 2, wherein, The buffer layer includes a protrusion protruding from the side close to the substrate toward the side away from the substrate; The first semiconductor layer adheres to the side away from the substrate of the protrusion and two opposite sidewalls of the protrusion in the first direction; The second semiconductor layer extends along the first direction from one side of the protrusion to the other side of the protrusion through the first semiconductor layer adhering to the protrusion.

8. The semiconductor device according to claim 7, wherein, The buffer layer includes a first buffer layer and a second buffer layer. The second buffer layer is located between the first buffer layer and the first semiconductor layer, and the density of the second buffer layer is greater than that of the first buffer layer; Preferably, the density of the second buffer layer is 5 g / cm 3 to 7 g / cm 3 .

9. The semiconductor device according to claim 8, wherein, The first buffer layer includes a protruding portion protruding from a side close to the substrate toward a side away from the substrate, and the second buffer layer covers the top and side walls of the protruding portion to form the protrusion; Preferably, in the region outside the protruding portion, the thickness range of the first buffer layer is to The thickness range of the second buffer layer is to 10. The semiconductor device according to claim 9, wherein, The orthographic projection of the protruding portion on the substrate is located within the orthographic projection of the second buffer layer on the substrate, and the orthographic projection of the second buffer layer on the substrate is located within the orthographic projection of the first semiconductor layer on the substrate.

11. The semiconductor device according to claim 1, wherein The material of the first semiconductor layer includes indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is from 2:1 to 5:1; the material of the second semiconductor layer includes indium zinc oxide doped with metal, wherein the atomic ratio of indium to zinc is less than 2:1; Preferably, the metal doped in the first semiconductor layer includes at least one of gallium, tin, niobium, and tantalum, and the metal doped in the second semiconductor layer includes at least one of gallium and tin; Preferably, the thickness range of the first semiconductor layer is to The thickness range of the second semiconductor layer is to 12. The semiconductor device according to claim 1, wherein The semiconductor device further includes: A third semiconductor layer located between the first semiconductor layer and the buffer layer, and the carrier mobility of the third semiconductor layer is less than the carrier mobility of the first semiconductor layer.

13. The semiconductor device according to claim 2, wherein, The semiconductor device further includes: A second insulating layer located on a side of the first electrode and the first insulating layer away from the substrate; A second electrode and a third electrode located on a side of the second insulating layer away from the substrate, and the second electrode and the third electrode are electrically connected to the second region and the third region respectively through through-holes penetrating the second insulating layer and the first insulating layer.

14. A method for manufacturing a semiconductor device, characterized in that, The method includes: Providing a substrate; Forming a buffer layer and a first semiconductor layer on one side of the substrate; Forming a second semiconductor layer on a side of the first semiconductor layer and the buffer layer away from the substrate, and the carrier mobility of the second semiconductor layer is less than the carrier mobility of the first semiconductor layer; the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the second semiconductor layer on the substrate; Forming a first insulating layer on a side of the second semiconductor layer away from the substrate; Forming a first electrode on a side of the first insulating layer away from the substrate; the orthographic projection of the first semiconductor layer on the substrate is located within the orthographic projection of the first electrode on the substrate; Performing ion implantation on the second semiconductor layer from a side of the first electrode away from the substrate.

15. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-13.

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