Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a semiconductor substrate on which a silicon carbide epitaxial layer is formed; the source region is formed in the silicon carbide epitaxial layer, and the source region comprises a first source region with a first doping type and a second source region with a second doping type; the connecting region is formed in the silicon carbide epitaxial layer and penetrates through the first source region, and the connecting region has the first doping type; the trench gate structure stretches across the source region and the connecting region, the trench gate structure extends in the first direction and the second direction, and the first direction and the second direction intersect with each other and are parallel to the surface of the silicon carbide epitaxial layer; the shielding region is located at the bottom of the trench gate structure, and the shielding region has a first doping type; and the column region is formed in the silicon carbide epitaxial layer and penetrates through the first source region, and the column region has the first doping type. The trench gate structures extending in different directions are arranged, so that the channel proportion is increased, the drain-source on-resistance of the device is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Silicon Carbide (SiC) is a semiconductor material with excellent properties such as high melting point, high hardness, and high current-carrying capacity, and is widely used in fields such as new energy, power electronics, and radio frequency electronics. The on-resistance and switching losses of SiC MOSFETs are significantly reduced, suitable for higher operating frequencies, and due to their high-temperature operating characteristics, the high-temperature stability is greatly improved.

[0003] SiC MOSFETs include planar SiC MOSFETs and trench SiC MOSFETs. Due to the low channel mobility of planar SiC MOSFETs, trench SiC MOSFETs are regarded as the future development direction. The drain-source on-resistance (Rdson) refers to the resistance between the drain and the source when the MOSFET is in the on state, and this parameter plays a key role in the performance of power MOSFETs, directly affecting the conduction loss and efficiency of the device. Summary of the Invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a semiconductor device on the one hand, and the semiconductor device includes:

[0006] A semiconductor substrate, on which a silicon carbide epitaxial layer is formed;

[0007] A source region, formed in the silicon carbide epitaxial layer, the source region including a first source region with a first doping type and a second source region with a second doping type;

[0008] A connection region, formed in the silicon carbide epitaxial layer and penetrating the first source region, the connection region having a first doping type;

[0009] A trench gate structure, spanning the source region and the connection region, the trench gate structure extending in a first direction and a second direction, the first direction and the second direction intersecting each other and parallel to the surface of the silicon carbide epitaxial layer, the depth of the trench gate structure being greater than the depth of the source region and less than the depth of the connection region;

[0010] A shielding region, located at the bottom of the trench gate structure, the shielding region having a first doping type;

[0011] A column region, formed in the silicon carbide epitaxial layer and penetrating the first source region, the column region having a first doping type.

[0012] In one embodiment, the connection region is formed at an intersection position of a trench gate structure extending along the first direction and a trench gate structure extending along the second direction.

[0013] In one embodiment, the first source region extends along a third direction and a fourth direction, the third direction and the fourth direction intersecting each other and being parallel to the surface of the silicon carbide epitaxial layer.

[0014] In one embodiment, the first direction and the second direction are perpendicular to each other, and the third direction and the fourth direction are perpendicular to each other.

[0015] In one embodiment, the column region is formed at an intersection position of a first source region extending along the third direction and a first source region extending along the fourth direction.

[0016] A second aspect of the embodiments of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0017] Providing a semiconductor substrate, a silicon carbide epitaxial layer being formed on the semiconductor substrate;

[0018] Forming a first source region having a first doping type and a second source region having a second doping type in the silicon carbide epitaxial layer;

[0019] Performing ion implantation of the first doping type on the silicon carbide epitaxial layer to form a column region and a connection region penetrating the first source region;

[0020] Etching the silicon carbide epitaxial layer to form gate trenches spanning the source region and the connection region, the gate trenches extending along a first direction and a second direction, the first direction and the second direction intersecting each other and being parallel to the surface of the silicon carbide epitaxial layer, the depth of the gate trenches being greater than the depth of the source region and less than the depth of the connection region;

[0021] Performing ion implantation of the first doping type on the bottom of the gate trenches to form a shielding region at the bottom of the gate trenches;

[0022] Forming a gate dielectric layer and a gate electrode layer in the gate trenches to obtain a trench gate structure.

[0023] In one embodiment, the connection region is formed at an intersection position of a gate trench extending along the first direction and a gate trench extending along the second direction.

[0024] In one embodiment, the first source region extends along a third direction and a fourth direction, the third direction and the fourth direction intersect with each other and are parallel to the surface of the silicon carbide epitaxial layer, and the third direction and the fourth direction are different from the first direction and the second direction.

[0025] In one embodiment, the first direction and the second direction are perpendicular to each other, and the third direction and the fourth direction are perpendicular to each other.

[0026] In one embodiment, the column region is formed at the intersection position of a first source region extending along the third direction and a first source region extending along the fourth direction.

[0027] A third aspect of an embodiment of the present invention provides an electronic device, and the electronic device includes the semiconductor device as described above.

[0028] According to the semiconductor device provided by the present invention, trench gate structures extending in different directions are provided, which increases the channel ratio, reduces the drain-source on-resistance of the device, and improves the performance of the semiconductor device; a shielding region is provided at the bottom of the trench gate structure, and the shielding region is electrically connected to the column region through a connection region, which can improve the compressive performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The following drawings of the present invention are used as part of the present invention to understand the present invention. The embodiments of the present invention and their descriptions are shown in the drawings to explain the principles of the present invention.

[0030] In the drawings:

[0031] Figure 1 A schematic flowchart of a manufacturing method of a semiconductor device showing a specific embodiment of the present invention is shown;

[0032] Figure 2 A top view of a semiconductor device according to an embodiment of the present invention is shown;

[0033] Figures 3A - 8B A cross-sectional view of a semiconductor device obtained by sequentially implementing each step of a manufacturing method of a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some well-known technical features in the art are not described.

[0035] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0036] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, the first element, component, region, layer or section discussed below may be denoted as the second element, component, region, layer or section without departing from the teachings of the present invention.

[0037] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0039] Next, with reference to Figure 1 , Figure 2 , Figures 3A - 8B a detailed description will be given of the method for manufacturing a semiconductor device according to an embodiment of the present invention. Among them, Figure 1 shows a schematic flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention, Figure 2 shows a top view of a semiconductor device according to an embodiment of the present invention, Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A show a cross-sectional schematic view of a semiconductor device obtained by successively implementing each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention at Figure 2 the A cross-section shown in Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B show a cross-sectional schematic view of a semiconductor device obtained by successively implementing each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention along Figure 2 the B cross-section shown in

[0040] First, step S101 is executed to provide a semiconductor substrate 200, on which a silicon carbide epitaxial layer 201 is formed.

[0041] Among them, the material of the semiconductor substrate 200 may include at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, the semiconductor substrate 200 may further include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), or germanium on insulator (GeOI), etc. Although several examples of materials that can form the semiconductor substrate 200 are described herein, any material that can serve as the semiconductor substrate 200 falls within the spirit and scope of the present invention. In one example, the semiconductor substrate 200 is a silicon carbide substrate.

[0042] A silicon carbide epitaxial layer 201 is formed on the semiconductor substrate 200. Optionally, the silicon carbide substrate and the silicon carbide epitaxial layer 201 may have the same conductivity type. Exemplarily, the silicon carbide substrate and the silicon carbide epitaxial layer 201 may have different doping concentrations. For example, the doping concentration of the silicon carbide epitaxial layer 201 may be lower than that of the silicon carbide substrate. Optionally, the silicon carbide epitaxial layer 201 may serve as the drift region of the semiconductor device. The presence of the drift region can provide the breakdown voltage of the device and act as a buffer, while reducing the parasitic capacitance between the source and drain electrodes.

[0043] Next, step S102 is performed to form source regions in the silicon carbide epitaxial layer 201. The source regions include a first source region 204 having a first doping type and a second source region 203 having a second doping type.

[0044] Exemplarily, first, ion implantation of the second doping type is performed on the silicon carbide epitaxial layer 201 to form a body region 202. Then, heavy ion implantation of the first doping type is performed in the body region 202 to form the first source region 204, as Figure 3B shown; and heavy ion implantation of the second doping type is performed in the body region 201 to form the second source region 203, as Figure 3A shown. After that, an annealing process may be further performed to activate the doping ions and simultaneously repair the lattice structure of the surface of the silicon carbide epitaxial layer damaged during the ion implantation process.

[0045] In one example, the first doping type is P-type and the second doping type is N-type. In this example, the body region 202 has P-type doping ions, the first source region 204 has P-type heavy doping ions, and the second source region 203 has N-type heavy doping ions.

[0046] Exemplarily, referring to Figure 2, the first source region 204 extends along a third direction and a fourth direction, the third direction and the fourth direction intersect with each other and are parallel to the surface of the silicon carbide epitaxial layer. Further, the third direction and the fourth direction are perpendicular to each other, thereby forming a cross-shaped first source region structure.

[0047] Next, step S103 is performed to perform ion implantation of a first doping type on the silicon carbide epitaxial layer 201 to form a column region 205 and a connection region 206 that penetrate the first source region 204.

[0048] Among them, the column region 205 can modulate the internal electric field distribution of the device when the semiconductor device operates in the blocking state, improving the voltage resistance performance of the semiconductor device. The column region 205 penetrates the first source region 204 and is electrically connected to the first source region 204. Further, the column region 205 is formed at the intersection position of the first source region 204 extending along the third direction and the first source region 204 extending along the fourth direction, that is, formed at the center position of the cross-shaped first source region structure, so that the column region 205 is electrically connected to the first source region 204 extending in different directions. In a specific example, the column region 205 has P-type doping ions.

[0049] The connection region 206 has the same doping type as the column region 205, for example, both are P-type doping. The connection region 206 is formed at the position where the gate trench is located, and is used to electrically connect the shielding region 207 formed under the gate trench to the column region 205. Exemplarily, the depth of the connection region 206 is greater than the depth of the gate trench and is close to the depth of the shielding region 207, so as to be electrically connected to the shielding region 207.

[0050] The column region 205 and the connection region 206 can be formed by two ion implantations. For example, first, as Figure 4A , Figure 4B shown, perform the first ion implantation of the first doping type on the silicon carbide epitaxial layer 201 to form the column region 205; then, as Figure 5B shown, perform the second ion implantation of the first doping type on the silicon carbide epitaxial layer 201 again to form the connection region 206. At this time, the connection region is not visible in the A cross-section shown in Figure 5A . Exemplarily, the depth of the column region 205 is greater than the depth of the connection region 206. The ion implantation for the column region 205 is high-energy ion implantation. Forming the column region 205 and the connection region 206 using independent ion implantation processes can facilitate setting the ion implantation parameters. In other embodiments, it is also possible to first perform ion implantation of the connection region 206 and then perform ion implantation of the column region 205.

[0051] Next, step S104 is performed, as Figure 6A , Figure 6BAs shown, the silicon carbide epitaxial layer 201 is etched to form a gate trench that spans the source region and the connection region 206. The gate trench extends in a first direction and a second direction, the first direction and the second direction intersect each other and are parallel to the surface of the silicon carbide epitaxial layer, and the depth of the gate trench is greater than the depth of the source region and less than the depth of the connection region 206. The connection region 206 surrounds the gate trench from the sidewalls and the bottom.

[0052] Specifically, a photoresist layer can be formed on the silicon carbide epitaxial layer 201, and the photoresist layer is exposed and developed to form an etching window that defines the position of the gate trench, and this etching window is located above the connection region. Then, the silicon carbide epitaxial layer 201 is dry-etched using the photoresist layer as a mask, so as to form a gate trench that spans the connection region 206. The dry-etching process includes, but is not limited to, etching processes such as reactive ion etching (RIE), ion beam etching, and plasma etching.

[0053] In an embodiment of the present invention, the gate trench extends in a first direction and a second direction. Compared with the conventional gate trench in a single direction, the channel occupation ratio is increased, and the drain-source on-resistance (Rdson) of the semiconductor device is reduced. In one example, as Figure 2 shown, the first direction and the second direction are perpendicular to each other, so as to form a cross-shaped trench gate structure. Further, the included angles between the first direction and the third direction, and between the second direction and the fourth direction are both 45°, and the intersection point of the gate trench coincides with the intersection point of the first source region.

[0054] Exemplarily, the connection region 206 is formed at the intersection position of the gate trench extending in the first direction, the gate trench extending in the second direction, the first source region 204 extending in the third direction, and the first source region 204 extending in the fourth direction. Among them, the connection region 206 intersects with the gate trenches extending in the first direction and the second direction, that is, the connection region is electrically connected to the shielding regions 207 in two directions; the connection region 206 is electrically connected to the first source regions 204 extending in the third direction and the fourth direction, that is, the connection region 206 is electrically connected to the column regions 205 in two directions. Finally, all the shielding regions 207 and column regions 205 are electrically connected together through the connection region 206, and are uniformly grounded through the column regions 205, improving the compressive performance of the semiconductor device.

[0055] Next, step S105 is executed, as Figure 7A 、 Figure 7BAs shown, ion implantation of the first doping type is performed on the bottom of the gate trench to form a shielding region 207 at the bottom of the gate trench. Due to the curvature effect, the bottom corner of the gate trench is prone to electric field concentration and is likely to cause the gate dielectric layer to fail. The shielding region 207 surrounds the bottom corner of the gate trench, which can avoid the electric field concentration at the bottom corner of the gate trench and prevent the gate dielectric layer from failing. In addition, since the connection region 206 surrounds the gate trench, the shielding region 207 formed at the bottom of the gate trench is electrically connected to the connection region 206 formed below and on both sides of the gate trench.

[0056] Exemplarily, P-type doping ion implantation can be performed on the bottom of the gate trench to form a shielding region. The shielding region 207, the connection region 206, the first source region 204, and the column region 205 are all P-type doped, thereby forming electrical connections with each other.

[0057] Next, step S106 is executed. As Figure 8A 、 Figure 8B shown, a gate dielectric layer 208 and a gate electrode layer 209 are formed in the gate trench to obtain a trench gate structure.

[0058] Specifically, first, a gate dielectric layer 208 covering the bottom and sidewalls of the gate trench is formed. The gate dielectric layer 208 may include conventional dielectric materials such as silicon oxide. Alternatively, the gate dielectric layer 208 may include high-k dielectric materials, such as hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate, and lead zirconate titanate, etc. Then, a gate electrode layer 209 filling the gate trench is formed. In one embodiment, the gate electrode layer 209 is composed of a polysilicon material, or a metal, a metal nitride, a metal silicide, or a similar compound can also be used to form the gate electrode layer 209.

[0059] Next, an isolation dielectric layer 210 is formed above the trench gate structure. Exemplarily, various deposition methods commonly used in the art can be employed to form the isolation dielectric layer 210, which may include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. Exemplarily, the material of the isolation dielectric layer 210 can be an insulating material such as silicon dioxide, fluorocarbon compound, carbon-doped silicon oxide, or silicon carbonitride, etc. Then, the isolation dielectric layer 210 is etched to expose the first source region 204 and the column region 205.

[0060] Finally, a source metal layer 211 connecting the first source region 204 is formed. Since the isolation dielectric layer 210 is formed above the trench gate structure, electrical isolation is formed between the trench gate structure 210 and the source metal layer 211. Exemplarily, the material of the source metal layer 211 can include one or more of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al.

[0061] So far, the process steps implemented by the manufacturing method of the semiconductor device according to the embodiment of the first aspect of the present invention have been completed. It can be understood that the manufacturing method of the semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of the manufacturing method of this embodiment.

[0062] According to the manufacturing method of the semiconductor device provided by the embodiment of the present invention, a trench gate structure extending in different directions is provided, which increases the channel ratio, reduces the drain-source on-resistance of the device, and improves the performance of the semiconductor device; a shielding region is provided at the bottom of the trench gate structure, and the shielding region is electrically connected to the column region through a connection region, which can improve the compressive performance of the semiconductor device.

[0063] An embodiment of the second aspect of the present invention also provides a semiconductor device, which can be prepared by the method in the first embodiment above, but is not limited thereto.

[0064] Next, with reference to Figure 2 and Figure 8A 、 Figure 8B A detailed introduction and description of the semiconductor device of the present invention will be given. It is worth mentioning that, in order to avoid repetition, only a brief description will be made for the same components and structures as those in the first embodiment above, and the specific explanations and descriptions can be referred to the description in the first embodiment.

[0065] Specifically, the semiconductor device of the embodiment of the present invention includes: a semiconductor substrate 200, on which a silicon carbide epitaxial layer 201 is formed; a source region, formed in the silicon carbide epitaxial layer 201, including a first source region 204 having a first doping type and a second source region 203 having a second doping type; a connection region 206, formed in the silicon carbide epitaxial layer 201 and penetrating the first source region 204, and the connection region 206 has a first doping type; a trench gate structure, spanning the source region and the connection region 206, including a gate dielectric layer 208 and a gate electrode layer 209; the trench gate structure extends in a first direction and a second direction, the first direction and the second direction intersect with each other and are parallel to the surface of the silicon carbide epitaxial layer, and the depth of the trench gate structure is greater than the depth of the source region and less than the depth of the connection region 206; a shielding region 207, located at the bottom of the trench gate structure, and the shielding region 207 has a first doping type; a column region 205, formed in the silicon carbide epitaxial layer 201 and penetrating the first source region 204, and the column region 205 has a first doping type.

[0066] Due to the curvature effect, the bottom corner of the trench gate structure is prone to cause electric field concentration and easily lead to the failure of the gate dielectric layer. The shielding region 207 surrounds the bottom corner of the trench gate structure, which can avoid the electric field concentration at the bottom corner of the trench gate structure and prevent the failure of the gate dielectric layer 208. In addition, since the connection region 206 surrounds the trench gate structure, the shielding region 207 formed at the bottom of the trench gate structure is electrically connected to the connection region 206 formed below and on both sides of the trench gate structure.

[0067] Exemplarily, the first source region 204 extends along the third direction and the fourth direction, and the third direction and the fourth direction intersect with each other and are parallel to the surface of the silicon carbide epitaxial layer 201.

[0068] Exemplarily, as Figure 2 shown, the first direction and the second direction are perpendicular to each other, and the third direction and the fourth direction are perpendicular to each other, thereby forming a cross-shaped trench gate structure. In the embodiment of the present invention, the trench gate structure extends along the first direction and the second direction. Compared with the traditional single-direction trench gate structure, the channel ratio is increased, and the drain-source on-resistance of the semiconductor device is reduced.

[0069] Exemplarily, the connection region 206 is formed at the intersection positions of the trench gate structure extending along the first direction, the trench gate structure extending along the second direction, the first source region extending along the third direction, and the first source region extending along the fourth direction. The column region 205 is formed at the intersection position of the first source region 204 extending along the third direction and the first source region 204 extending along the fourth direction. Specifically, the connection region 206 intersects with the trench gate structures extending along the first direction and the second direction, that is, the connection region is electrically connected to the shielding regions 207 in two directions; the connection region 206 is electrically connected to the first source regions 204 extending along the third direction and the fourth direction, that is, the connection region 206 is electrically connected to the column regions 205 in two directions. Finally, all the shielding regions 207 and column regions 205 are electrically connected together through the connection region 206, and are grounded uniformly through the column region 205, improving the compressive performance of the semiconductor device.

[0070] The semiconductor device according to the embodiment of the present invention is provided with trench gate structures extending in different directions, which increases the channel ratio, reduces the drain-source on-resistance of the device, and improves the performance of the semiconductor device; a shielding region is provided at the bottom of the trench gate structure, and the shielding region is electrically connected to the column region through the connection region, which can improve the compressive performance of the semiconductor device.

[0071] In the third aspect of the present invention, an electronic device is further provided, including the aforementioned semiconductor device, and the semiconductor device is prepared according to the aforementioned method.

[0072] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop, netbook, game console, television, VCD, DVD, navigator, digital photo frame, camera, video camera, voice recorder, MP3, MP4, PSP, etc., or can also be any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance due to the use of the above semiconductor device.

[0073] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are only for the purpose of exemplification and illustration, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of protection required by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalent scope.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A semiconductor substrate having a silicon carbide epitaxial layer formed thereon; A source region formed in the silicon carbide epitaxial layer, the source region comprising a first source region having a first doping type and a second source region having a second doping type; a connection region, formed in the silicon carbide epitaxial layer and penetrating the first source region, the connection region having a first doping type; a trench gate structure, spanning the source region and the connection region, the trench gate structure extending along a first direction and a second direction, the first direction and the second direction intersecting each other and parallel to a surface of the silicon carbide epitaxial layer, the depth of the trench gate structure being greater than the depth of the source region and less than the depth of the connection region; A shielding region, located at the bottom of the trench gate structure, the shielding region having a first doping type; A column region is formed in the silicon carbide epitaxial layer and penetrates the first source region, and the column region has a first doping type.

2. The semiconductor device according to claim 1, wherein The connection region is formed at an intersection of a trench gate structure extending along the first direction and a trench gate structure extending along the second direction.

3. The semiconductor device according to claim 1, wherein The first source region extends along a third direction and a fourth direction, the third direction and the fourth direction intersect each other and are parallel to a surface of the silicon carbide epitaxial layer.

4. The semiconductor device according to claim 3, characterized in that The first direction and the second direction are perpendicular to each other, and the third direction and the fourth direction are perpendicular to each other.

5. The semiconductor device according to claim 3, wherein: The stud region is formed at an intersection of a first source region extending along the third direction and a first source region extending along the fourth direction.

6. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a semiconductor substrate, on which a silicon carbide epitaxial layer is formed; forming a first source region having a first doping type and a second source region having a second doping type in the silicon carbide epitaxial layer; Performing ion implantation of the first doping type into the silicon carbide epitaxial layer to form a column region and a connection region penetrating the first source region; Etching the silicon carbide epitaxial layer to form a gate trench spanning the source region and the connection region, wherein the gate trench extends along a first direction and a second direction, the first direction and the second direction intersect each other and are parallel to a surface of the silicon carbide epitaxial layer, and the depth of the gate trench is greater than the depth of the source region and less than the depth of the connection region; Performing ion implantation of the first doping type on the bottom of the gate trench to form a shielding region at the bottom of the gate trench; A gate dielectric layer and a gate electrode layer are formed in the gate trench to form a trench gate structure.

7. The manufacturing method according to claim 6, characterized in that: The connection region is formed at an intersection of a gate trench extending along the first direction and a gate trench extending along the second direction.

8. The manufacturing method according to claim 6, characterized in that: The first source region extends along a third direction and a fourth direction, the third direction and the fourth direction intersect each other and are parallel to a surface of the silicon carbide epitaxial layer.

9. The manufacturing method according to claim 8, characterized in that: The first direction and the second direction are perpendicular to each other, and the third direction and the fourth direction are perpendicular to each other.

10. The manufacturing method according to claim 8, characterized in that: The stud region is formed at an intersection of a first source region extending along the third direction and a first source region extending along the fourth direction.

Images