Semiconductor device

Abstract

This semiconductor device is provided with: a semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side; a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer; and a trench source structure including a source trench formed on the first main surface of the semiconductor layer so as to be deeper than the gate trench at a distance from the gate trench, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, the ratio of the depth of the trench source structure to the depth of the trench gate structure is 1.5 to 4.0; a body region of a second conductivity type formed in a region between the gate trench and the source trench in a surface layer portion of the first main surface of the semiconductor layer; a source region of a first conductivity type formed in a surface layer portion of the body region; and a drain electrode connected to the second main surface of the semiconductor layer.

Description

[0001] This application is a divisional application; the application number of its parent application is "2018800326708", and the invention title is "Semiconductor Device". Technical Field

[0002] The present invention relates to a semiconductor device. Background Art

[0003] A semiconductor device having a gate trench and a source trench is disclosed in Patent Document 1. The gate trench and the source trench are formed at substantially the same depth on the surface of an n-type semiconductor layer. In the surface layer portion of the surface of the semiconductor layer, a p-type body region is formed in a region between the gate trench and the source trench.

[0004] An n+-type source region is formed in the surface layer portion of the p-type body region. A p-type breakdown voltage holding region (deep well region) is formed in a region along the source trench in the semiconductor layer.

[0005] In the gate trench, a gate electrode is buried via a gate insulating layer. A source electrode is buried in the source trench. A drain electrode is connected to the back surface of the semiconductor layer.

[0006] Prior Art Documents

[0007] Patent Documents

[0008] Patent Document 1: WO 2014 / 030589 A1 Summary of the Invention

[0009] Problems to be Solved by the Invention

[0010] As electrical characteristics of a semiconductor device having a MISFET structure including a gate, a source, and a drain, a short-circuit withstand capacity and a feedback capacitance are known. The short-circuit withstand capacity is the time that can withstand a short-circuit current. The short-circuit current is a current flowing between the source and the drain when switching from an on state to an off state. The feedback capacitance is the electrostatic capacitance between the gate and the drain.

[0011] The higher the short-circuit withstand capacity, the higher the reliability of the semiconductor device. In addition, the smaller the feedback capacitance, the higher the switching speed of the semiconductor device. Therefore, by achieving an excellent short-circuit withstand capacity and an excellent feedback capacitance, a semiconductor device that can be used in various situations can be provided.

[0012] However, in a semiconductor device having a structure in which a gate trench and a source trench are formed at substantially the same depth, a p-type deep well region can be formed only in a relatively shallow region of the n-type semiconductor layer.

[0013] In such a structure, it is impossible to sufficiently expand the depletion layer from the boundary region between the semiconductor layer and the deep well region. Therefore, the narrowing of the current path of the short-circuit current caused by the depletion layer becomes insufficient, and the short-circuit withstand cannot be appropriately improved. In addition, since the width of the depletion layer is also small, the feedback capacitance cannot be appropriately reduced.

[0014] One embodiment of the present invention provides a semiconductor device that improves short-circuit withstand and can reduce feedback capacitance.

[0015] Solution to the problem

[0016] One embodiment of the present invention provides a semiconductor device, characterized by comprising: a semiconductor layer of a first conductivity type, having a first main surface on one side and a second main surface on the other side; a trench gate structure including a gate trench formed on the first main surface of the semiconductor layer and a gate electrode buried in the gate trench via a gate insulating layer; a trench source structure including a source trench formed deeper than the gate trench at a distance from the gate trench on the first main surface of the semiconductor layer, a source electrode buried in the source trench, and a well region of a second conductivity type formed in a region along the source trench in the semiconductor layer, and a ratio of a depth of the trench source structure to a depth of the trench gate structure is 1.5 or more and 4.0 or less; a body region of a second conductivity type formed in a region between the gate trench and the source trench in a surface layer portion of the first main surface of the semiconductor layer; a source region of a first conductivity type formed in a surface layer portion of the body region; and a drain electrode connected to the second main surface of the semiconductor layer.

[0017] According to this semiconductor device, the ratio of the depth of the trench source structure to the depth of the trench gate structure is 1.5 or more and 4.0 or less. As a result, the depletion layer can be expanded from the boundary region between the semiconductor layer and the well region toward a region closer to the second main surface side than the bottom wall of the gate trench.

[0018] As a result, the current path of the short-circuit current flowing between the source electrode and the drain electrode can be narrowed. In addition, the feedback capacitance can be inversely reduced by the depletion layer expanded from the boundary region between the semiconductor layer and the well region. Therefore, a semiconductor device that improves short-circuit withstand and can reduce feedback capacitance can be provided.

[0019] One embodiment of the present invention provides a semiconductor device, characterized by comprising: a semiconductor layer of a first conductivity type, having a first main surface on one side and a second main surface on the other side; a trench gate structure, including a gate trench having a first sidewall and a first bottom wall and formed on the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer; a trench source structure, including a source trench having a second sidewall and a second bottom wall and formed at an interval from the gate trench on the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench; a body region of a second conductivity type, formed in a region between the gate trench and the source trench in the surface layer portion of the first main surface of the semiconductor layer; a source region of a first conductivity type, formed in the surface layer portion of the body region; and a drain electrode, connected to the second main surface of the semiconductor layer, wherein the second sidewall of the source trench includes a first wall portion located on the first main surface side of the semiconductor layer with respect to the first bottom wall of the gate trench, and a second wall portion located on the second main surface side of the semiconductor layer with respect to the first bottom wall of the gate trench, and the well region includes a first region formed along the first wall portion of the second sidewall of the source trench, and a second region formed along the second wall portion of the second sidewall of the source trench and having a length greater than that of the first region in the thickness direction of the semiconductor layer.

[0020] According to this semiconductor device, the well region includes a first region formed along the first wall portion of the second sidewall of the source trench, and a second region formed along the second wall portion of the second sidewall of the source trench.

[0021] In the thickness direction of the semiconductor layer, the length of the second region of the well region is greater than the length of the first region of the well region. Thereby, it is possible to expand the depletion layer from the boundary region between the semiconductor layer and the well region toward a region closer to the second main surface side than the first bottom wall of the gate trench.

[0022] As a result, it is possible to narrow the current path of the short-circuit current flowing between the source electrode and the drain electrode. In addition, through the depletion layer expanded from the boundary region between the semiconductor layer and the well region, the feedback capacitance can be inversely reduced. Therefore, it is possible to provide a semiconductor device with improved short-circuit tolerance and reduced feedback capacitance.

[0023] The above or other objects, features, and effects of the present invention will become clearer through the description of the embodiments described below with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1It is a plan view of a semiconductor device showing the first embodiment of the present invention.

[0025] Figure 2 It is a cross-sectional view taken along the Figure 1 II-II line.

[0026] Figure 3 It is a cross-sectional view for explaining the operation of the Figure 1 semiconductor device.

[0027] Figure 4 It is a graph showing the current-voltage characteristics of the Figure 1 semiconductor device.

[0028] Figure 5 It is a graph showing the capacitance-voltage characteristics of the Figure 1 semiconductor device.

[0029] Figure 6 It is a cross-sectional view of a semiconductor device showing the second embodiment of the present invention.

[0030] Figure 7 It is a cross-sectional view of a semiconductor device showing the third embodiment of the present invention.

[0031] Figure 8 It is a cross-sectional view of a semiconductor device showing the fourth embodiment of the present invention.

[0032] Fig. 9 It is a cross-sectional view of a semiconductor device showing the fifth embodiment of the present invention.

[0033] Fig.10 It is a plan view of a semiconductor device showing the sixth embodiment of the present invention.

[0034] Fig.11 It is a plan view of a semiconductor device showing the seventh embodiment of the present invention.

[0035] Fig.12 It is Fig.11 an enlarged view of the region XII shown, and is a diagram for explaining the structure of the first main surface of the SiC semiconductor layer.

[0036] Fig.13 It is a cross-sectional view taken along the Fig.12 XIII-XIII line shown.

[0037] Fig.14 It is a cross-sectional view taken along the Fig.12 XIV-XIV line shown.

[0038] Fig.15 It is a graph showing the relationship between the resistivity of polycrystal and the formation temperature.

[0039] Fig.16 It is a graph for explaining sheet resistance.

[0040] Fig.17A It represents Fig.11 A cross-sectional view showing an example of a method for manufacturing the semiconductor device shown.

[0041] Fig. 17B It represents Fig.17A A cross-sectional view of the subsequent process.

[0042] Fig. 17C It represents Fig. 17B A cross-sectional view of the subsequent process.

[0043] Fig.17D It represents Fig. 17C A cross-sectional view of the subsequent process.

[0044] Fig.17E It represents Fig.17D A cross-sectional view of the subsequent process.

[0045] Fig.17F It represents Fig.17E A cross-sectional view of the subsequent process.

[0046] Figure 17G It represents Fig.17F A cross-sectional view of the subsequent process.

[0047] Fig.17H It represents Figure 17G A cross-sectional view of the subsequent process.

[0048] Fig.17I It represents Fig.17H A cross-sectional view of the subsequent process.

[0049] Fig.17J It represents Fig.17I A cross-sectional view of the subsequent process.

[0050] Figure 17K It represents Fig.17J A cross-sectional view of the subsequent process.

[0051] Figure 17L It represents Figure 17K A cross-sectional view of the subsequent process.

[0052] Fig.18 It is a cross-sectional view of the region corresponding to Fig.13 A cross-sectional view showing the semiconductor device of the eighth embodiment of the present invention.

[0053] Fig.19 It is a cross-sectional view of the region corresponding to Fig.13The cross-sectional view of the corresponding region is the cross-sectional view of the semiconductor device according to the 9th embodiment of the present invention.

[0054] Fig. 20A It shows Fig.19 A cross-sectional view showing an example of the manufacturing method of the semiconductor device shown.

[0055] Fig. 20B It shows Fig. 20A The cross-sectional view of the subsequent process.

[0056] Fig. 20C It shows Fig. 20B The cross-sectional view of the subsequent process.

[0057] Fig.21 It is Fig.12 The enlarged view of the corresponding region, which is the enlarged view of the semiconductor device according to the 10th embodiment of the present invention.

[0058] Fig. 22 It is the cross-sectional view along Fig.21 The line XXII-XXII shown.

[0059] Fig.23 It is Fig.13 The cross-sectional view of the corresponding region, which is the cross-sectional view for explaining the structure of the semiconductor device according to the 11th embodiment of the present invention.

[0060] Fig.24 It is Fig.12 The enlarged view of the corresponding region, which is the enlarged view for explaining the structure of the semiconductor device according to the 12th embodiment of the present invention.

[0061] Fig.25 It is Fig.13 The cross-sectional view of the corresponding region, which is the cross-sectional view for explaining the structure of the semiconductor device according to the 13th embodiment of the present invention.

[0062] Fig.26 It is Fig.13 The cross-sectional view of the corresponding region, which is the cross-sectional view for explaining the structure of the semiconductor device according to the 14th embodiment of the present invention.

[0063] Fig. 27 It is Fig.13 The cross-sectional view of the corresponding region, which is the cross-sectional view for explaining the structure of the semiconductor device according to the 15th embodiment of the present invention.

[0064] Fig.28 It is Fig.13 The cross-sectional view of the corresponding region, which is the cross-sectional view for explaining the structure of the semiconductor device according to the 16th embodiment of the present invention.

[0065] Fig.29is a cross-sectional view of the region corresponding to Fig.13 and is a cross-sectional view for explaining the structure of the semiconductor device according to the 17th embodiment of the present invention.

[0066] Fig.30 is a cross-sectional view of the region corresponding to Fig.13 and is a cross-sectional view for explaining the structure of the semiconductor device according to the 18th embodiment of the present invention.

[0067] Fig.31 is a cross-sectional view of the region corresponding to Fig.13 and is a cross-sectional view for explaining the structure of the semiconductor device according to the 19th embodiment of the present invention.

[0068] Fig.32 is a cross-sectional view of the region corresponding to Fig.13 and is a cross-sectional view for explaining the structure of the semiconductor device according to the 20th embodiment of the present invention.

[0069] Fig.33 is a cross-sectional view of the region corresponding to Fig.13 and is a cross-sectional view for explaining the structure of the semiconductor device according to the 21st embodiment of the present invention.

[0070] Fig.34 is a top view of the semiconductor device according to the 22nd embodiment of the present invention.

[0071] Fig.35 is a bottom view showing the semiconductor device shown in Fig.34 and is a bottom view showing the first exemplary form of the raised portion group.

[0072] Fig.36A is a view showing the second exemplary form of the raised portion group.

[0073] Fig.36B is a view showing the third exemplary form of the raised portion group.

[0074] Fig.36C is a view showing the fourth exemplary form of the raised portion group.

[0075] Fig.36D is a view showing the fifth exemplary form of the raised portion group.

[0076] Fig.37 is an enlarged view of the region XXXVII shown in Fig.34 and is a view in which the structure above the first main surface of the SiC semiconductor layer is removed.

[0077] Fig.38 is a cross-sectional view taken along line XXXVIII-XXXVIII of Fig.37 .

[0078] Fig.39 is a cross-sectional view along Fig.37 the line XXXIX-XXXIX.

[0079] Fig.40 is Fig.39 an enlarged view of the region XL shown in

[0080] Fig.41A is Fig.34 a top view of a semiconductor wafer used in the manufacture of the semiconductor device shown in

[0081] Fig.41B is Fig.41A a bottom view of the semiconductor wafer shown in , which is a view showing the state after the grinding process and the annealing process.

[0082] Fig.42 is for explaining Fig.34 a flowchart of an example of the semiconductor device shown in

[0083] Fig.43A is for explaining Fig.42 a cross-sectional view of the manufacturing method shown in

[0084] Fig.43B is for explaining Fig.43A the subsequent process in

[0085] Fig.43C is for explaining Fig.43B the subsequent process in

[0086] Fig.43D is for explaining Fig.43C the subsequent process in

[0087] Fig.43E is for explaining Fig.43D the subsequent process in

[0088] Fig.43F is for explaining Fig.43E the subsequent process in

[0089] Figure 43G is for explaining Fig.43F the subsequent process in

[0090] Figure 43H is for explaining Figure 43G the subsequent process in

[0091] Fig.43I is for explaining Figure 43H the subsequent process in

[0092] Fig.44 is related to Fig.35 The corresponding bottom view is the bottom view of the semiconductor device according to the 23rd embodiment of the present invention.

[0093] Fig.45 It is Fig.39 The corresponding cross-sectional view is the cross-sectional view of the semiconductor device according to the 24th embodiment of the present invention.

[0094] Fig.46 It is a magnified view of Fig.45 the region XLVI shown.

[0095] Fig.47 It is Fig.39 The corresponding cross-sectional view is the cross-sectional view of the semiconductor device according to the 25th embodiment of the present invention.

[0096] Fig.48 It is Fig.47 a magnified view of the region XLVIII shown.

[0097] Fig.49 It is the top view of the semiconductor device according to the 26th embodiment of the present invention.

[0098] Fig.50 It is Fig.49 the top view of the semiconductor device shown, which is the top view with the resin layer removed.

[0099] Fig.51 It is Fig.50 a magnified view of the region LI shown, which is a diagram for explaining the structure of the first main surface of the SiC semiconductor layer.

[0100] Fig.52 It is a cross-sectional view along Fig.51 the line LII-LII shown, which is a cross-sectional view showing the first exemplary embodiment of the gate trench and the first exemplary embodiment of the source trench.

[0101] Fig.53 It is a cross-sectional view along Fig.51 the line LIII-LIII shown, which is a cross-sectional view showing the first exemplary embodiment of the gate wiring layer.

[0102] Fig.54 It is Fig.52 a magnified view of the region LIV shown.

[0103] Fig.55 It is a cross-sectional view along Fig.50The cross-sectional view of the LV-LV line shown is a cross-sectional view showing the first exemplary embodiment of the active sidewall, the first exemplary embodiment of the outer main surface, the first exemplary embodiment of the sidewall, the first exemplary embodiment of the diode region, the first exemplary embodiment of the outer deep well region, the first exemplary embodiment of the field limiting structure, and the first exemplary embodiment of the anchoring hole.

[0104] Fig.56 is Fig.55 The enlarged view of the region LVI shown is an enlarged view showing the first exemplary embodiment of the active sidewall and the first exemplary embodiment of the outer main surface.

[0105] Fig.57A is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the second exemplary embodiment of the gate trench.

[0106] Fig.57B is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the third exemplary embodiment of the gate trench.

[0107] Fig.57C is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fourth exemplary embodiment of the gate trench.

[0108] Fig.57D is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fifth exemplary embodiment of the gate trench.

[0109] Fig.57E is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the sixth exemplary embodiment of the gate trench.

[0110] Fig.58A is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the second exemplary embodiment of the source trench.

[0111] Fig.58B is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the third exemplary embodiment of the source trench.

[0112] Fig.58C is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fourth exemplary embodiment of the source trench.

[0113] Fig.58D is the same as Fig.54 The cross-sectional view of the corresponding region is a cross-sectional view showing the fifth exemplary embodiment of the source trench.

[0114] Fig.58E is the same as Fig.54A cross-sectional view of the corresponding region, which is a cross-sectional view showing the sixth example of the source electrode trench.

[0115] Fig.58F It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the seventh example of the source electrode trench.

[0116] Figure 58G It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the eighth example of the source electrode trench.

[0117] Figure 58H It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the ninth example of the source electrode trench.

[0118] Fig.58I It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the tenth example of the source electrode trench.

[0119] Fig.58J It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the eleventh example of the source electrode trench.

[0120] Figure 58K It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the twelfth example of the source electrode trench.

[0121] Figure 58L It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the thirteenth example of the source electrode trench.

[0122] Figure 58M It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the fourteenth example of the source electrode trench.

[0123] Figure 58N It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the fifteenth example of the source electrode trench.

[0124] Fig.58O It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the sixteenth example of the source electrode trench.

[0125] Figure 58P It is a cross-sectional view of the region corresponding to Fig.54 A cross-sectional view of the corresponding region, which is a cross-sectional view showing the seventeenth example of the source electrode trench.

[0126] Figure 58Q It is a cross-sectional view of the region corresponding to Fig.54The cross-sectional view of the corresponding area is a cross-sectional view showing the 18th exemplary embodiment of the source trench.

[0127] Fig.59A It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 2nd exemplary embodiment of the active sidewall.

[0128] Fig.59B It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 3rd exemplary embodiment of the active sidewall.

[0129] Fig.59C It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 4th exemplary embodiment of the active sidewall.

[0130] Fig.60A It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 2nd exemplary embodiment of the outer main surface.

[0131] Fig.60B It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 3rd exemplary embodiment of the outer main surface.

[0132] Fig.60C It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 4th exemplary embodiment of the outer main surface.

[0133] Fig.61A It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 2nd exemplary embodiment of the sidewall.

[0134] Fig.61B It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 3rd exemplary embodiment of the sidewall.

[0135] Fig.61C It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 4th exemplary embodiment of the sidewall.

[0136] Fig.61D It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 5th exemplary embodiment of the sidewall.

[0137] Fig.61E It is Fig.56 The enlarged view of the corresponding area is an enlarged view showing the 6th exemplary embodiment of the sidewall.

[0138] Fig.61F It is Fig.56An enlarged view of the corresponding area, which is an enlarged view showing the 7th exemplary embodiment of the side wall.

[0139] Fig.62A It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 2nd exemplary embodiment of the outer deep well region.

[0140] Fig.62B It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 3rd exemplary embodiment of the outer deep well region.

[0141] Fig.62C It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 4th exemplary embodiment of the outer deep well region.

[0142] Fig.63A It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 2nd exemplary embodiment of the field limiting structure.

[0143] Fig.63B It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 3rd exemplary embodiment of the field limiting structure.

[0144] Fig.63C It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 4th exemplary embodiment of the field limiting structure.

[0145] Fig.63D It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 5th exemplary embodiment of the field limiting structure.

[0146] Fig.64A It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 2nd exemplary embodiment of the anchoring hole.

[0147] Fig.64B It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 3rd exemplary embodiment of the anchoring hole.

[0148] Fig.64C It is a cross-sectional view of the area corresponding to Fig.55 and is an enlarged view showing the 4th exemplary embodiment of the anchoring hole.

[0149] Fig.64D It is a plan view of the area corresponding to Fig.50 and is a plan view showing the 5th exemplary embodiment of the anchoring hole.

[0150] Fig.65A It is an enlarged view of the area corresponding to Fig.54 and shows Fig.49 An enlarged view of an example of a method for manufacturing the semiconductor device shown.

[0151] Fig.65B It represents Fig.65A An enlarged view of the subsequent process.

[0152] Fig.65C It represents Fig.65B An enlarged view of the subsequent process.

[0153] Fig.65D It represents Fig.65C An enlarged view of the subsequent process.

[0154] Fig.65E It represents Fig.65D An enlarged view of the subsequent process.

[0155] Fig.65F It represents Fig.65E An enlarged view of the subsequent process.

[0156] Figure 65G It represents Fig.65F An enlarged view of the subsequent process.

[0157] Figure 65H It represents Figure 65G An enlarged view of the subsequent process.

[0158] Figure 65I It represents Figure 65H An enlarged view of the subsequent process.

[0159] Fig.65J It represents Figure 65I An enlarged view of the subsequent process.

[0160] Figure 65K It represents Fig.65J An enlarged view of the subsequent process.

[0161] Figure 65L It represents Figure 65K An enlarged view of the subsequent process.

[0162] Figure 65M It represents Figure 65L An enlarged view of the subsequent process.

[0163] Figure 65N It represents Figure 65M An enlarged view of the subsequent process.

[0164] Fig.65O It represents Figure 65N An enlarged view of the subsequent process.

[0165] Figure 65P It represents Fig.65OEnlarged view of subsequent processes.

[0166] Figure 65Q It represents Figure 65P Enlarged view of subsequent processes.

[0167] Figure 65R It represents Figure 65Q Enlarged view of subsequent processes.

[0168] Figure 65S It represents Figure 65R Enlarged view of subsequent processes.

[0169] Figure 65T It represents Figure 65S Enlarged view of subsequent processes.

[0170] Figure 65U It represents Figure 65T Enlarged view of subsequent processes.

[0171] Figure 65V It represents Figure 65U Enlarged view of subsequent processes.

[0172] Figure 65W It represents Figure 65V Enlarged view of subsequent processes.

[0173] Figure 65X It represents Figure 65W Enlarged view of subsequent processes.

[0174] Figure 65Y It represents Figure 65X Enlarged view of subsequent processes.

[0175] Figure 65Z It represents Figure 65Y Enlarged view of subsequent processes.

[0176] Figure 66A It is a cross-sectional view of the region corresponding to Figure 55 and represents Figure 49 A cross-sectional view showing an example of the manufacturing method of the semiconductor device shown.

[0177] Figure 66B It represents Figure 66A Cross-sectional view of subsequent processes.

[0178] Figure 66C It represents Figure 66B Cross-sectional view of subsequent processes.

[0179] Figure 66D It represents Figure 66C Cross-sectional view of subsequent processes.

[0180] Figure 66E It representsFigure 66D Cross-sectional view of subsequent process

[0181] Figure 66F It represents Figure 66E Cross-sectional view of subsequent process

[0182] Figure 66G It represents Figure 66F Cross-sectional view of subsequent process

[0183] Figure 66H It represents Figure 66G Cross-sectional view of subsequent process

[0184] Figure 66I It represents Figure 66H Cross-sectional view of subsequent process

[0185] Figure 66J It represents Figure 66I Cross-sectional view of subsequent process

[0186] Figure 66K It represents Figure 66J Cross-sectional view of subsequent process

[0187] Figure 66L It represents Figure 66K Cross-sectional view of subsequent process

[0188] Figure 66M It represents Figure 66L Cross-sectional view of subsequent process

[0189] Figure 66N It represents Figure 66M Cross-sectional view of subsequent process

[0190] Figure 66O It represents Figure 66N Cross-sectional view of subsequent process

[0191] Figure 66P It represents Figure 66O Cross-sectional view of subsequent process

[0192] Figure 66Q It represents Figure 66P Cross-sectional view of subsequent process

[0193] Figure 66R It represents Figure 66Q Cross-sectional view of subsequent process

[0194] Figure 66S It represents Figure 66R Cross-sectional view of subsequent process

[0195] Figure 66T It represents Figure 66S Cross-sectional view of subsequent process

[0196] Figure 66U It represents Figure 66T A cross-sectional view of the subsequent process.

[0197] Figure 66V It represents Figure 66U A cross-sectional view of the subsequent process.

[0198] Figure 66W It represents Figure 66V A cross-sectional view of the subsequent process.

[0199] Figure 66X It represents Figure 66W A cross-sectional view of the subsequent process.

[0200] Figure 66Y It represents Figure 66X A cross-sectional view of the subsequent process.

[0201] Figure 66Z It represents Figure 66Y A cross-sectional view of the subsequent process.

[0202] Figure 67 It is related to Figure 51 An enlarged view of the corresponding area, which is an enlarged view of the semiconductor device according to the 27th embodiment of the present invention.

[0203] Figure 68 It is along Figure 67 The cross-sectional view taken along line LXVIII-LXVIII shown.

[0204] Figure 69 It is along Figure 67 The cross-sectional view taken along line LXIX-LXIX shown.

[0205] Figure 70 It is Figure 68 An enlarged view of the area LXX-LXX shown.

[0206] Figure 71 It is a graph showing the leakage current characteristics in the case of using NiSi as the low-resistance electrode layer.

[0207] Figure 72 It is a graph showing the leakage current characteristics in the case of using CoSi 2 as the low-resistance electrode layer.

[0208] Figure 73 It is a graph showing the leakage current characteristics in the case of using TiSi 2 as the low-resistance electrode layer.

[0209] Figure 74A It is related to Figure 70 The enlarged view of the corresponding area, which is used to illustrateFigure 67 An enlarged view of an example of a method for manufacturing the semiconductor device shown

[0210] Figure 74B It shows Figure 74A An enlarged view of the subsequent process

[0211] Figure 74C It shows Figure 74B An enlarged view of the subsequent process

[0212] Figure 74D It shows Figure 74C An enlarged view of the subsequent process

[0213] Figure 74E It shows Figure 74D An enlarged view of the subsequent process

[0214] Figure 74F It shows Figure 74E An enlarged view of the subsequent process

[0215] Figure 74G It shows Figure 74F An enlarged view of the subsequent process

[0216] Figure 75 It is an enlarged view of the region corresponding to Figure 70 and is an enlarged view of the semiconductor device of the 28th embodiment of the present invention

[0217] Figure 76A It is an enlarged view of the region corresponding to Figure 75 and is an enlarged view for explaining Figure 75 An example of a method for manufacturing the semiconductor device shown

[0218] Figure 76B It shows Figure 76A An enlarged view of the subsequent process

[0219] Figure 76C It shows Figure 76B An enlarged view of the subsequent process

[0220] Figure 76D It shows Figure 76C An enlarged view of the subsequent process

[0221] Figure 76E It shows Figure 76D An enlarged view of the subsequent process

[0222] Figure 76F It shows Figure 76E An enlarged view of the subsequent process

[0223] Figure 76G It shows Figure 76FEnlarged view of subsequent processes.

[0224] Figure 77 It is Figure 70 An enlarged view of the corresponding area, and an enlarged view of the semiconductor device of the 29th embodiment of the present invention.

[0225] Figure 78A It is Figure 77 An enlarged view of the corresponding area, and an enlarged view for explaining an example of the manufacturing method of the semiconductor device shown in Figure 77

[0226] Figure 78B It represents Figure 78A An enlarged view of subsequent processes.

[0227] Figure 78C It represents Figure 78B An enlarged view of subsequent processes.

[0228] Figure 78D It represents Figure 78C An enlarged view of subsequent processes.

[0229] Figure 78E It represents Figure 78D An enlarged view of subsequent processes.

[0230] Figure 78F It represents Figure 78E An enlarged view of subsequent processes.

[0231] Figure 79 It is Figure 70 An enlarged view of the corresponding area, and an enlarged view of the semiconductor device of the 30th embodiment of the present invention.

[0232] Figure 80 It is Figure 69 A cross-sectional view of the corresponding area, and a cross-sectional view of the semiconductor device shown in Figure 79

[0233] Figure 81 It is Figure 55 A cross-sectional view of the corresponding area, and a cross-sectional view of the semiconductor device shown in Figure 79

[0234] Figure 82A It is Figure 79 An enlarged view of the corresponding area, and an enlarged view for explaining an example of the manufacturing method of the semiconductor device shown in Figure 79

[0235] Figure 82B It represents Figure 82A An enlarged view of subsequent processes.

[0236] ​​​​Figure 82C It represents Figure 82B an enlarged view of the subsequent process.

[0237] Figure 83 It is a bottom view of the semiconductor device according to the 31st embodiment of the present invention, and is a bottom view showing the first exemplary embodiment of the raised portion group.

[0238] Figure 84A It is a view showing the second exemplary embodiment of the raised portion group.

[0239] Figure 84B It is a view showing the third exemplary embodiment of the raised portion group.

[0240] Figure 84C It is a view showing the fourth exemplary embodiment of the raised portion group.

[0241] Figure 84D It is a view showing the fifth exemplary embodiment of the raised portion group.

[0242] Figure 85 It is a cross-sectional view of the region corresponding to Figure 68 and is a cross-sectional view of the semiconductor device shown in Figure 83 .

[0243] Figure 86 It is a cross-sectional view of the region corresponding to Figure 69 and is a cross-sectional view of the semiconductor device shown in Figure 83 .

[0244] Figure 87 It represents Figure 86 an enlarged view of the region LXXXVII shown.

[0245] Figure 88 It is a cross-sectional view of the region corresponding to Figure 55 and is a cross-sectional view of the semiconductor device shown in Figure 83 .

[0246] Figure 89 It is a bottom view of the region corresponding to Figure 83 and is a bottom view of the semiconductor device according to the 32nd embodiment of the present invention.

[0247] Figure 90 It is a cross-sectional view of the region corresponding to Figure 86 and is a cross-sectional view of the semiconductor device according to the 33rd embodiment of the present invention.

[0248] Figure 91 It is Figure 90 an enlarged view of the region XCI shown.

[0249] Figure 92 It is a cross-sectional view of the region corresponding to Figure 86The corresponding cross-sectional view is a cross-sectional view of the semiconductor device according to the 34th embodiment of the present invention.

[0250] Figure 93 It is a view showing Figure 92 an enlarged view of the region XCIII shown.

[0251] Figure 94 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 35th embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 36th embodiment of the present invention.

[0252] Figure 95 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 37th embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 38th embodiment of the present invention.

[0253] Figure 96 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 39th embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 40th embodiment of the present invention.

[0254] Figure 97 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 41st embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 42nd embodiment of the present invention.

[0255] Figure 98 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 43rd embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 44th embodiment of the present invention.

[0256] Figure 99 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 45th embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 46th embodiment of the present invention.

[0257] Figure 100 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 47th embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 48th embodiment of the present invention.

[0258] Figure 101 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 49th embodiment of the present invention. Figure 55 It is a cross-sectional view of the corresponding region, and is a cross-sectional view of the semiconductor device according to the 50th embodiment of the present invention.

[0259] Figure 102 It is an enlarged view of the corresponding region, and is an enlarged view of the semiconductor device according to the 51st embodiment of the present invention. Figure 51 It is a cross-sectional view taken along the line CIII-CIII shown in

[0260] Figure 103 Figure 102 Figure 102

[0261] Figure 104 is an enlarged view of the region corresponding to Figure 51 and is an enlarged view of a semiconductor device according to the 44th embodiment of the present invention.

[0262] Figure 105 is an enlarged view of the region corresponding to Figure 54 and is an enlarged view of a semiconductor device according to the 45th embodiment of the present invention.

[0263] Figure 106 is a perspective view of a semiconductor package capable of assembling any one of the semiconductor devices according to the 1st to 45th embodiments through a sealing body.

[0264] Figure 107 is a view showing a unit cell of a 4H-SiC single crystal applied in the embodiment of the present invention.

[0265] Figure 108 is a view showing Figure 107 a plan view of a silicon plane of a unit cell of the 4H-SiC single crystal shown. Detailed Embodiments

[0266] Figure 1 is a plan view of a semiconductor device 1 according to the 1st embodiment of the present invention. Figure 2 is a cross-sectional view taken along line II-II of Figure 1 .

[0267] The semiconductor device 1 is a switching device including a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). Referring to Figure 1 and Figure 2 , the semiconductor device 1 has an n-type SiC semiconductor layer 2 including a SiC (silicon carbide) single crystal.

[0268] The SiC semiconductor layer 2 includes a first main surface 3 on one side and a second main surface 4 on the other side. In this embodiment, the SiC semiconductor layer 2 has a stacked structure including a SiC semiconductor substrate 5 including a SiC single crystal and an n-type SiC epitaxial layer 6 including a SiC single crystal. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 5. The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 6.

[0269] A drain electrode 7 is connected to the second main surface 4 of the SiC semiconductor layer 2. The SiC semiconductor substrate 5 is formed as an n+-type drain region. The SiC epitaxial layer 6 is formed as an n-type drain drift region.

[0270] The n-type impurity concentration of the SiC semiconductor substrate 5 is preferably 1.0×1018 cm －3 or more and 1.0×10 21 cm －3 or less. The n-type impurity concentration of the SiC epitaxial layer 6 is preferably 1.0×10 15 cm －3 or more and 1.0×10 17 cm －3 or less. Hereinafter, in this specification, "impurity concentration" means the peak value of the impurity concentration.

[0271] Refer to Figure 1 and Figure 2 , a plurality of trench gate structures 10 and a plurality of trench source structures 11 are formed on the first main surface 3 of the SiC semiconductor layer 2. The trench gate structures 10 and the trench source structures 11 are alternately formed at intervals in an arbitrary first direction X.

[0272] The trench gate structures 10 and the trench source structures 11 are formed in a strip shape extending in a second direction Y orthogonal to the first direction X. Preferably, the first direction X is the [11-20] direction, and the second direction Y is the [1-100] direction.

[0273] A stripe structure including a plurality of trench gate structures 10 and a plurality of trench source structures 11 is formed on the first main surface 3 of the SiC semiconductor layer 2. Preferably, the distance between the trench gate structures 10 and the trench source structures 11 is 0.3 μm or more and 1.0 μm or less in the first direction X.

[0274] Each trench gate structure 10 includes a gate trench 12, a gate insulating layer 13, and a gate electrode layer 14. In Figure 1 , for clarity, the gate electrode layer 14 is shown by hatching.

[0275] The gate trench 12 is formed by digging the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4 side. The gate trench 12 includes a first side wall 15 and a first bottom wall 16.

[0276] The gate insulating layer 13 is formed in a film shape along the first side wall 15, the first bottom wall 16, and the corner portion 17 connecting the first side wall 15 and the first bottom wall 16 of the gate trench 12. The gate insulating layer 13 divides a concave space in the gate trench 12.

[0277] The gate insulating layer 13 may also include silicon oxide. In addition to silicon oxide, the gate insulating layer 13 may also include at least one of impurity-free added silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0278] The gate electrode layer 14 is buried in the gate trench 12 with the gate insulating layer 13 interposed therebetween. More specifically, the gate electrode layer 14 is buried in the concave space defined by the gate insulating layer 13.

[0279] The gate electrode layer 14 may also contain conductive polysilicon. In addition to conductive polysilicon, the gate electrode layer 14 may also contain at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0280] Each trench source structure 11 includes a source trench 18, a barrier formation layer 19, a source electrode layer 20, and a p-type deep well region 21. In Figure 1 the figure, the source electrode layer 20 is shown by hatching for clarity. The deep well region 21 is also referred to as a breakdown voltage holding region.

[0281] The source trench 18 is formed by digging the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4 side. The source trench 18 includes a second sidewall 22 and a second bottom wall 23.

[0282] The second sidewall 22 of the source trench 18 includes a first wall portion 24 and a second wall portion 25. The first wall portion 24 of the source trench 18 is located on the first main surface 3 side of the SiC semiconductor layer 2 with respect to the first bottom wall 16 of the gate trench 12. That is, the first wall portion 24 is the portion that overlaps the gate trench 12 in the lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2.

[0283] The second wall portion 25 of the source trench 18 is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the second bottom wall 23 of the gate trench 12. That is, the second wall portion 25 is the portion of the region that is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the second bottom wall 23 of the gate trench 12 in the source trench 18.

[0284] In the thickness direction of the SiC semiconductor layer 2, the length of the second wall portion 25 of the source trench 18 is greater than the length of the first wall portion 24 of the source trench 18. The second bottom wall 23 of the source trench 18 is located in the region between the first bottom wall 16 of the gate trench 12 and the second main surface 4 of the SiC semiconductor layer 2 in the thickness direction of the SiC semiconductor layer 2.

[0285] In this manner, the second bottom wall 23 of the source trench 18 is located in the SiC epitaxial layer 6. The second bottom wall 23 of the source trench 18 may also be located in the SiC semiconductor substrate 5.

[0286] The barrier formation layer 19 is formed in a film shape along the second sidewall 22, the second bottom wall 23, and the corner portion 26 connecting the second sidewall 22 and the second bottom wall 23 of the source trench 18. The barrier formation layer 19 defines a concave space within the source trench 18.

[0287] The barrier-forming layer 19 is made of a material different from the conductive material of the source electrode layer 20 . The barrier-forming layer 19 has a potential barrier higher than the potential barrier between the source electrode layer 20 and the deep well region 21 .

[0288] A conductive barrier-forming layer may be used as the barrier-forming layer 19. The conductive barrier-forming layer may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0289] An insulating barrier forming layer may also be used as the barrier forming layer 19. The insulating barrier forming layer may also contain at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. Figure 2 , an example in which an insulating barrier-forming layer is formed as the barrier-forming layer 19 is shown.

[0290] More specifically, the barrier-forming layer 19 is silicon oxide. The barrier-forming layer 19 and the gate insulating layer 13 are preferably formed of the same material. In this case, the thickness of the barrier-forming layer 19 and the thickness of the gate insulating layer 13 are preferably the same. When the barrier-forming layer 19 and the gate insulating layer 13 are formed of silicon oxide, the barrier-forming layer 19 and the gate insulating layer 13 can be formed simultaneously by a thermal oxidation process.

[0291] The source electrode layer 20 fills the concave space of the source trench 18 via the barrier forming layer 19. The source electrode layer 20 may include conductive polysilicon. The source electrode layer 20 may be n-type polysilicon to which n-type impurities are added, or p-type polysilicon to which p-type impurities are added.

[0292] The source electrode layer 20 may include at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten, in addition to conductive polysilicon.

[0293] The source electrode layer 20 is formed of the same conductive material as the gate electrode layer 14. In this case, the gate electrode layer 14 and the source electrode layer 20 can be formed simultaneously. Of course, the source electrode layer 20 may be formed of a conductive material different from that of the gate electrode layer 14.

[0294] The deep well region 21 is formed in the region along the source trench 18 in the SiC semiconductor layer 2. The p-type impurity concentration of the deep well region 21 may also be 1.0×10 17 cm －3 Above and 1.0×10 19 cm －3 the following.

[0295] The deep well region 21 is formed in the region of the second side wall 22 of the source trench 18 along the SiC semiconductor layer 2. The deep well region 21 is formed in the region of the second bottom wall 23 of the source trench 18 along the SiC semiconductor layer 2.

[0296] In this manner, the deep well region 21 is continuously formed in the region of the second side wall 22, the corner portion 26, and the second bottom wall 23 of the source trench 18 along the SiC semiconductor layer 2. The deep well region 21 includes a first region 27 and a second region 28 in the portion along the second side wall 22 of the source trench 18.

[0297] The first region 27 of the deep well region 21 is formed along the first wall portion 24 of the second side wall 22 of the source trench 18. The second region 28 of the deep well region 21 is formed along the second wall portion 25 of the second side wall 22 of the source trench 18. In the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is larger than the length of the first region 27 of the deep well region 21.

[0298] The thickness of the portion of the deep well region 21 along the second bottom wall 23 of the source trench 18 may also be equal to or greater than the thickness of the portion of the deep well region 21 along the second side wall 22 of the source trench 18.

[0299] The portion of the deep well region 21 along the second bottom wall 23 of the source trench 18 may also cross the boundary region between the SiC semiconductor substrate 5 and the SiC epitaxial layer 6 and be located within the SiC semiconductor substrate 5.

[0300] In the portion of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18, p-type impurities are implanted in the direction normal to the first main surface 3 of the SiC semiconductor layer 2. On the other hand, in the portion of the SiC semiconductor layer 2 along the second side wall 22 of the source trench 18, p-type impurities are implanted in a state inclined with respect to the first main surface 3 of the SiC semiconductor layer 2.

[0301] Therefore, in the portion of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18, p-type impurities are implanted at a deeper position than in the portion along the second side wall 22 of the source trench 18. As a result, a thickness difference is generated between the portion of the deep well region 21 along the second bottom wall 23 of the source trench 18 and the portion along the second side wall 22 of the source trench 18.

[0302] A p-type body region 30 is formed in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. The body region 30 is formed in the region between the gate trench 12 and the source trench 18. The body region 30 is formed in a strip shape extending along the second direction Y in plan view.

[0303] The body region 30 is exposed from the first sidewall 15 of the gate trench 12 and the second sidewall 22 of the source trench 18. The body region 30 is connected to the first region 27 of the deep well region 21.

[0304] The p-type impurity concentration of the body region 30 may also be 1.0×10 16 cm －3 or more and 1.0×10 19 cm －3 or less. The p-type impurity concentration of the body region 30 may also be substantially equal to the p-type impurity concentration of the deep well region 21. The p-type impurity concentration of the body region 30 may also be higher than the p-type impurity concentration of the deep well region 21.

[0305] An n+-type source region 31 is formed in the surface layer portion of the body region 30. The source region 31 is formed in a region along the first sidewall 15 of the gate trench 12 in the surface layer portion of the body region 30. The source region 31 is exposed from the first sidewall 15 of the gate trench 12.

[0306] The source region 31 may also be formed in a strip shape extending along the second direction Y in a top view. Although not shown, the source region 31 may also include a portion exposed from the second sidewall 22 of the source trench 18.

[0307] The width WS of the source region 31 may also be 0.2 μm or more and 0.6 μm or less (for example, about 0.4 μm). In this mode, the width WS is the width along the first direction X in the source region 31. The n-type impurity concentration of the source region 31 may also be 1.0×10 18 cm －3 or more and 1.0×10 21 cm －3 or less.

[0308] A p+-type contact region 32 is formed in the surface layer portion of the body region 30. The contact region 32 is formed in a region along the second sidewall 22 of the source trench 18 in the surface layer portion of the body region 30. The contact region 32 is exposed from the second sidewall 22 of the source trench 18.

[0309] The contact region 32 may also be connected to the source region 31. The contact region 32 may also be formed in a strip shape extending along the second direction Y in a top view. The contact region 32 may also include a portion exposed from the first sidewall 15 of the adjacent gate trench 12.

[0310] The width WC of the contact region 32 may also be 0.1 μm or more and 0.4 μm or less (for example, about 0.2 μm). In this mode, the width WC is the width along the first direction X in the contact region 32. The p-type impurity concentration of the contact region 32 may also be 1.0×10 18 cm－3 above and 1.0×10 21 cm －3 or less.

[0311] An insulating layer 40 is formed on the first main surface 3 of the SiC semiconductor layer 2. The insulating layer 40 collectively covers a plurality of trench gate structures 10. Contact holes 41 are formed in the insulating layer 40. The contact holes 41 selectively expose the trench source structure 11, the source region 31, and the contact region 32.

[0312] A main surface source electrode 42 is formed on the insulating layer 40. The main surface source electrode 42 enters the contact hole 41 from above the insulating layer 40. The main surface source electrode 42 is electrically connected to the source electrode layer 20, the source region 31, and the contact region 32 within the contact hole 41.

[0313] The main surface source electrode 42 may be formed of the same conductive material as the source electrode layer 20. The main surface source electrode 42 may be formed of a conductive material different from the source electrode layer 20.

[0314] In this mode, the source electrode layer 20 includes n-type polysilicon or p-type polysilicon, and the main surface source electrode 42 includes aluminum or a metal material mainly containing aluminum. The main surface source electrode 42 may also include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten.

[0315] The main surface source electrode 42 may also be constituted by an electrode layer formed integrally with the source electrode layer 20. In this case, the source electrode layer 20 and the main surface source electrode 42 are formed via a common process.

[0316] Hereinafter, the dimensions of the trench gate structure 10 and the dimensions of the trench source structure 11 will be specifically described.

[0317] The trench gate structure 10 has an aspect ratio D1 / W1. The aspect ratio D1 / W1 of the trench gate structure 10 is defined by the ratio of the depth D1 of the trench gate structure 10 to the width W1 of the trench gate structure 10.

[0318] In this mode, the width W1 is the width in the first direction X in the trench gate structure 10. The aspect ratio D1 / W1 of the trench gate structure 10 may also be the aspect ratio of the gate trench 12.

[0319] The aspect ratio D1 / W1 of the trench gate structure 10 may be 0.25 or more and 15.0 or less. The width W1 of the trench gate structure 10 may be 0.2 μm or more and 2.0 μm or less (for example, about 0.4 μm). The depth D1 of the trench gate structure 10 may be 0.5 μm or more and 3.0 μm or less (for example, about 1.0 μm).

[0320] The trench source structure 11 has an aspect ratio D2 / W2. The aspect ratio D2 / W2 of the trench source structure 11 is the ratio of the depth D2 of the trench source structure 11 to the width W2 of the trench source structure 11.

[0321] The width W2 of the trench source structure 11 is the sum of the width WST of the source trench 18, the first width Wα of the deep well region 21, and the second width Wβ of the deep well region 21 (W2 = WST + Wα + Wβ).

[0322] In this manner, the width WST is the width in the source trench 18 along the first direction X. In this manner, the width Wα is the width along the first direction X of a part of the second sidewall 22 on one side of the source trench 18 in the deep well region 21. In this manner, the second width Wβ is the width along the first direction X of a part of the second sidewall 22 on the other side of the source trench 18 in the deep well region 21.

[0323] The aspect ratio D2 / W2 of the trench source structure 11 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 can also be 0.5 or more and 18.0 or less.

[0324] The ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 can also be 1.5 or more and 4.0 or less. By increasing the depth D2 of the trench source structure 11, the breakdown voltage holding effect of the SJ (Super Junction) structure can also be improved.

[0325] The width W2 of the trench source structure 11 can also be 0.6 μm or more and 2.4 μm or less (for example, about 0.8 μm). The depth D2 of the trench source structure 11 can also be 1.5 μm or more and 11 μm or less (for example, about 2.5 μm). The width W2 of the trench source structure 11 can also be equal to the width W1 of the trench gate structure 10. The width W2 of the trench source structure 11 can also be different from the width W1 of the trench gate structure 10.

[0326] In the trench source structure 11, the source trench 18 has an aspect ratio DST / WST. The aspect ratio DST / WST of the source trench 18 is the ratio of the depth DST of the source trench 18 to the width WST of the source trench 18.

[0327] The aspect ratio DST / WST of the source trench 18 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio DST / WST of the source trench 18 can also be 0.5 or more and 18.0 or less.

[0328] The width WST of the source trench 18 may also be 0.2 μm or more and 2.0 μm or less (for example, about 0.4 μm). The width WST of the source trench 18 may also be equal to the width W1 of the gate trench 12 (WST = W1).

[0329] When the width WST of the source trench 18 or the width W1 of the gate trench 12 varies in the depth direction, the width WST and the width W1 are defined as the widths of the opening portions. The depth DST of the source trench 18 may also be 1.0 μm or more and 10 μm or less (for example, about 2.0 μm).

[0330] The ratio of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 (gate trench 12) is preferably 2 or more. The ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 may also exceed 4.0. In this case, attention needs to be paid to the durability of the resist mask used when forming the source trench 18 by the etching method.

[0331] For example, when the depth D1 of the trench gate structure 10 is about 3.0 μm and the ratio DST / D1 exceeds 4, it is assumed that the resist mask approaches the durability limit or exceeds the above durability limit due to etching. If the resist mask exceeds the durability limit, unwanted etching of the SiC semiconductor layer 2 occurs.

[0332] Therefore, the ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 is preferably greater than 1.0 and 4.0 or less. If the ratio DST / D1 is within this range, the source trench 18 can be appropriately formed.

[0333] Figure 3 is a cross-sectional view for explaining Figure 1 the operation of the semiconductor device 1. In Figure 3 , the same reference numerals are assigned to the same structures as Figure 2 those.

[0334] In the semiconductor device 1, a pn junction 45 is formed in the boundary region between the SiC semiconductor layer 2 and the deep well region 21. When the semiconductor device 1 is switched from the on state to the off state, the depletion layer 46 extends from the pn junction 45 toward the SiC semiconductor layer 2. In Figure 3 , the depletion layer 46 is shown by a two-dot chain line.

[0335] The deep well region 21 includes a first region 27 and a second region 28. The first region 27 is formed along the first wall portion 24 of the second side wall 22 of the source trench 18. The second region 28 is formed along the second wall portion 25 of the second side wall 22 of the source trench 18.

[0336] The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 to a region closer to the first main surface 3 than the first bottom wall 16 of the gate trench 12. The depletion layer 46 from the pn junction 45 extends in the SiC semiconductor layer 2 to a region closer to the second main surface 4 than the first bottom wall 16 of the gate trench 12.

[0337] When the semiconductor device 1 is switched from the on state to the off state, the current path of the short-circuit current flowing from the drain electrode 7 toward the source electrode layer 20 is narrowed by the depletion layer 46. Thereby, the time until the semiconductor device 1 is damaged can be delayed.

[0338] In particular, according to the semiconductor device 1, the aspect ratio D2 / W2 of the trench source structure 11 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 is 0.5 or more and 18.0 or less.

[0339] Moreover, the ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 is 1.5 or more and 4.0 or less. In the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is larger than the length of the first region 27 of the deep well region 21.

[0340] Therefore, in the SiC semiconductor layer 2, the ratio of the region occupied by the depletion layer 46 extending in the region on the second main surface 4 side can be reliably increased compared to the ratio of the region occupied by the depletion layer 46 extending in the region on the first main surface 3 side. Thereby, the current path of the short-circuit current can be reliably narrowed in the region on the drain electrode 7 side.

[0341] The depletion layer 46 from the pn junction 45 may also overlap with the first bottom wall 16 of the gate trench 12. The depletion layer 46 on the second region 28 side of the deep well region 21 may also overlap with the first bottom wall 16 of the gate trench 12.

[0342] In this structure, the current path of the short-circuit current can be reliably narrowed in the region on the drain electrode 7 side. Of course, the depletion layer 46 on the first region 27 side of the deep well region 21 may also overlap with the first bottom wall 16 of the gate trench 12.

[0343] In addition, according to the semiconductor device 1, the region occupied by the depletion layer 46 in the SiC semiconductor layer 2 can be increased, so that the feedback capacitance Crss can be inversely reduced. The feedback capacitance Crss is the electrostatic capacitance between the gate electrode layer 14 and the drain electrode 7.

[0344] As described above, according to the semiconductor device 1, the short-circuit withstand is improved and the feedback capacitance Crss can be reduced.

[0345] In addition, according to the semiconductor device 1, a barrier formation layer 19 is formed in the source trench 18. The barrier formation layer 19 has a potential barrier higher than the potential barrier between the deep well region 21 and the source electrode layer 20.

[0346] Therefore, even if the depletion layer 46 extending from the pn junction 45 between the SiC semiconductor layer 2 and the deep well region 21 contacts the inner wall surface of the source trench 18, generation of punch-through can be suppressed. Thereby, leakage current caused by punch-through can be suppressed.

[0347] In the case where the barrier formation layer 19 does not exist, there is a tendency that punch-through can be observed significantly at the corner portion 26 of the source trench 18. This is because the depletion layer 46 further extends along the second bottom wall 23 of the source trench 18 from the second side wall 22 of the source trench 18.

[0348] Here, in the semiconductor device 1, the inner wall surface of the source trench 18 including the corner portion 26 is covered with the barrier formation layer 19. Thereby, generation of punch-through in the source trench 18 can be effectively suppressed.

[0349] According to the semiconductor device 1, from the viewpoint of the design of the short-circuit withstand capacity and the feedback capacitance Crss, the depletion layer 46 is formed in a relatively wide region in the SiC semiconductor layer 2, but the leakage current caused by the depletion layer 46 can be appropriately suppressed by the barrier formation layer 19.

[0350] Figure 4 It represents Figure 1 a graph showing the drain current-drain voltage characteristics of the semiconductor device 1. In Figure 4 it, the vertical axis represents the drain current ID [A / cm 2 , and the horizontal axis represents the drain voltage VD [V]. The drain current ID is the current (short-circuit current) flowing between the drain electrode 7 and the source electrode layer 20.

[0351] Figure 4 Curves L1 and L2 are shown in it. Both the curves L1 and L2 are obtained by simulation. The curves L1 and L2 represent the change in the drain current ID when a predetermined range of the drain voltage VD is applied to the drain electrode 7. The drain voltage VD varies in the range between 0 V and 1000 V.

[0352] The curve L1 represents the drain current-drain voltage characteristics of the semiconductor device of the reference example. The curve L2 represents the drain current-drain voltage characteristics of the semiconductor device 1. The semiconductor device of the reference example has the same structure as the semiconductor device 1 except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0353] Referring to curve L1, in the semiconductor device of the reference example, when the drain voltage VD exceeds 200V, the drain current ID exceeds 15000A / cm 2 On the other hand, referring to curve L2, in the semiconductor device 1, in the range where the drain voltage VD is between 0V and 1000V, the drain current ID is less than 15000A / cm 2 .

[0354] In the semiconductor device 1, in the range where the drain voltage VD is 400V or more and 1000V or less, the drain current ID is 10000A / cm 2 or more and less than 15000A / cm 2 .

[0355] When observing that the drain voltage VD is 600V, the drain current ID of the semiconductor device 1 is reduced by about 45% compared to the drain current ID of the semiconductor device of the reference example.

[0356] Based on this simulation result, it can be confirmed that by forming the deep well region 21 along the source trench 18 deeper than the gate trench 12, the short-circuit tolerance can be significantly improved.

[0357] Figure 5 is a graph showing Figure 1 the feedback capacitance-drain voltage characteristics of the semiconductor device 1. In Figure 5 , the vertical axis represents the feedback capacitance Crss [F / cm 2 , and the horizontal axis represents the drain voltage VD [V].[[]END]]

[0358] In Figure 5 , curve L3 and curve L4 are shown. Both curve L3 and curve L4 are obtained by simulation. Curve L3 and curve L4 represent the change in the feedback capacitance Crss when a predetermined range of drain voltage VD is applied to the drain electrode 7. The drain voltage VD varies within the range of 0V to 1000V.

[0359] Curve L3 represents the feedback capacitance-drain voltage characteristics of the semiconductor device of the reference example. Curve L4 represents the feedback capacitance-drain voltage characteristics of the semiconductor device 1. The semiconductor device of the reference example has the same structure as the semiconductor device 1 except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0360] Referring to curve L3, in the semiconductor device of the reference example, in the range where the drain voltage VD is from 1V to 10V, the feedback capacitance Crss slowly decreases. In the semiconductor device of the reference example, in the range of the drain voltage VD from 1V to 10V, the reduction rate of the feedback capacitance Crss is about 25%.

[0361] On the other hand, in the semiconductor device 1, in the range where the drain voltage VD is from 1 V to 10 V, the feedback capacitance Crss decreases sharply. When observing the drain voltage VD of 10 V, the feedback capacitance Crss of the semiconductor device 1 is reduced by about 95% compared with that of the semiconductor device in the reference example. In the semiconductor device 1, in the range of the drain voltage VD from 1 V to 10 V, the reduction rate of the feedback capacitance Crss is 95% or more and 99% or less.

[0362] According to this simulation result, it can be confirmed that by forming the deep well region 21 along the source trench 18 deeper than the gate trench 12, the feedback capacitance Crss can be significantly reduced. That is, it can be confirmed that by reducing the feedback capacitance Crss, the switching speed can be significantly increased.

[0363] Figure 6 FIG. is a cross-sectional view showing a semiconductor device 51 according to the second embodiment of the present invention. Hereinafter, the structures corresponding to those described for the semiconductor device 1 are denoted by the same reference numerals and the description thereof is omitted.

[0364] Refer to Figure 6 , the source region 31 is exposed from the first sidewall 15 of the gate trench 12 and the second sidewall 22 of the source trench 18. The contact region 32 is formed in the deep well region 21 in a region along the second bottom wall 23 of the source trench 18. The contact region 32 is exposed from the second bottom wall 23 of the source trench 18.

[0365] The contact region 32 may cover the entire second bottom wall 23 of the source trench. The p-type impurity concentration of the contact region 32 is larger than the p-type impurity concentration of the deep well region 21.

[0366] In Figure 6 , an example in which the barrier formation layer 19 is composed of a conductive barrier formation layer is shown. The barrier formation layer 19 is formed along the inner wall surface of the source trench 18, and the contact region 32 is selectively exposed from the second bottom wall 23 of the source trench 18.

[0367] More specifically, the barrier formation layer 19 includes a first portion 52 and a second portion 53. The first portion 52 of the barrier formation layer 19 covers the second sidewall 22 of the source trench 18. The second portion 53 of the barrier formation layer 19 locally covers the second bottom wall 23 of the source trench 18.

[0368] The second portion 53 of the barrier formation layer 19 is connected to the first portion 52 of the barrier formation layer 19. The second portion 53 of the barrier formation layer 19 extends along the second bottom wall 23 from the corner 26 of the source trench 18.

[0369] The second part 53 of the barrier forming layer 19 exposes the central portion of the second bottom wall 23 of the source trench 18. The second part 53 of the barrier forming layer 19 may also be formed as a continuous (ring-shaped) shape in a plan view.

[0370] As described above, according to the semiconductor device 51, the same effects as those described for the semiconductor device 1 can be achieved. In addition, according to the semiconductor device 51, even if the depletion layer 46 extends from the corner portion 26 of the source trench 18 along the second bottom wall 23, the distance for the depletion layer 46 to reach the source electrode layer 20 can be obtained by the barrier forming layer 19. Accordingly, generation of punch-through can be suppressed near the corner portion 26 of the source trench 18.

[0371] Figure 7 FIG. is a cross-sectional view showing a semiconductor device 61 according to a third embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to those described for the semiconductor device 51, and the description thereof is omitted.

[0372] An exposed portion 62 for selectively exposing the second bottom wall 23 of the source trench 18 is formed in the deep well region 21. More specifically, the second region 28 of the deep well region 21 is formed along the corner portion 26 of the source trench 18 so as to expose the central portion of the second bottom wall 23 of the source trench 18. The second region 28 of the deep well region 21 may also be formed as a continuous (ring-shaped) shape in a plan view.

[0373] In this embodiment, the contact region 32 is not formed. The contact region 32 may also be formed in a region along the second side wall 22 of the source trench 18 in the surface layer portion of the main body region 30.

[0374] A heterojunction portion is formed between the source electrode layer 20 and the SiC semiconductor layer 2 in the exposed portion 62 of the deep well region 21. Accordingly, a heterojunction diode 63 having the source electrode layer 20 as an anode and the SiC semiconductor layer 2 as a cathode is formed.

[0375] The source electrode layer 20 may also include conductive polysilicon. Of course, as long as the heterojunction diode 63 can be formed, the source electrode layer 20 may include a conductive material other than conductive polysilicon.

[0376] A main body diode 64 is formed at the pn junction between the SiC semiconductor layer 2 and the main body region 30. The junction barrier of the heterojunction diode 63 is smaller than the diffusion potential of the main body diode 64. The junction barrier of the heterojunction diode 63 may also be 1.0 eV or more and 1.5 eV or less. The diffusion potential of the main body diode 64 may also be 2.8 eV or more and 3.2 eV or less.

[0377] As described above, according to the semiconductor device 61, the same effects as those described for the semiconductor device 51 can be achieved. Further, in the semiconductor device 61, when a reverse bias voltage is applied, current can preferentially flow into the heterojunction diode 63. As a result, the expansion of SiC crystal defects in the SiC semiconductor layer 2 can be suppressed. Consequently, an improvement in short-circuit withstand voltage and a reduction in the feedback capacitance Crss can be achieved, and an increase in on-resistance can be suppressed.

[0378] Figure 8 FIG. 4 is a cross-sectional view showing a semiconductor device 71 according to a fourth embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to those described for the semiconductor device 51, and the description thereof is omitted.

[0379] The barrier formation layer 19 has a stacked structure including a plurality of barrier formation layers formed along the inner wall of the source trench 18. In this embodiment, the barrier formation layer 19 has a stacked structure including an insulating barrier formation layer 72 and a conductive barrier formation layer 73 stacked in order from the inner wall of the source trench 18.

[0380] The insulating barrier formation layer 72 is formed in a film shape along the inner wall surface of the source trench 18. The insulating barrier formation layer 72 selectively exposes the contact region 32 from the second bottom wall 23 of the source trench 18.

[0381] More specifically, the insulating barrier formation layer 72 includes a first portion 74 and a second portion 75. The first portion 74 covers the second side wall 22 of the source trench 18. The second portion 75 selectively covers the second bottom wall 23 of the source trench 18.

[0382] The second portion 75 is connected to the first portion 74. The second portion 75 extends along the second bottom wall 23 from the corner portion 26 of the source trench 18 so as to expose the central portion of the second bottom wall 23 of the source trench 18.

[0383] The insulating barrier formation layer 72 may include at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0384] The conductive barrier formation layer 73 is formed in a film shape along the insulating barrier formation layer 72 so as to selectively expose the contact region 32 from the second bottom wall 23 of the source trench 18. The conductive barrier formation layer 73 contains a conductive material different from that of the source electrode layer 20.

[0385] The conductive barrier formation layer 73 may be formed of the same conductive material as that of the gate electrode layer 14. The conductive barrier formation layer 73 may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0386] As described above, according to the semiconductor device 71, the same effects as those described for the semiconductor device 51 can be achieved. In addition, in the semiconductor device 71, the barrier formation layer 19 has a stacked structure including an insulating barrier formation layer 72 and a conductive barrier formation layer 73. Thus, the generation of punch-through can be suppressed by these two layers, i.e., the insulating barrier formation layer 72 and the conductive barrier formation layer 73.

[0387] If the conductive material of the conductive barrier formation layer 73 is the same as that of the gate electrode layer 14, the gate electrode layer 14 and the conductive barrier formation layer 73 can be formed by the same process. Therefore, an increase in man-hours can be suppressed.

[0388] Figure 9 FIG. is a cross-sectional view showing a semiconductor device 81 according to a fifth embodiment of the present invention. Hereinafter, the structures corresponding to those described for the semiconductor device 1 will be denoted by the same reference numerals and the description thereof will be omitted.

[0389] The barrier formation layer 19 includes a first portion 82 and a second portion 83. The first portion 82 of the barrier formation layer 19 covers the second sidewall 22 of the source trench 18. The second portion 83 of the barrier formation layer 19 covers the second bottom wall 23 of the source trench 18.

[0390] The first portion 82 of the barrier formation layer 19 selectively has a sidewall contact hole 84 that exposes the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. The first portion 82 covers the first wall portion 24 of the source trench 18 and exposes the second wall portion 25.

[0391] The first portion 82 may be formed to cross the boundary region between the SiC semiconductor layer 2 and the body region 30. In the first portion 82, the end portion on the second main surface 4 side may be formed in a region deeper than the bottom of the body region 30.

[0392] In the first portion 82, the end portion on the second main surface 4 side may be formed in a region shallower than the bottom of the body region 30. In the first portion 82, the end portion on the second main surface 4 side may be formed in a region between the bottom of the body region 30 and the bottom of the contact region 32. In the above cases, the source electrode layer 20 is connected to at least the body region 30 within the source trench 18.

[0393] In the first portion 82, the end portion on the second main surface 4 side may be formed in a region between the first main surface 3 of the SiC semiconductor layer 2 and the bottom of the contact region 32. The barrier formation layer 19 may have no first portion 82 and only the second portion 83. In the above cases, the source electrode layer 20 is connected to the body region 30 and the contact region 32 within the source trench 18.

[0394] The second part 83 of the barrier forming layer 19 is formed at intervals from the first part 82 of the barrier forming layer 19. The second part 83 is separated from the first part 82. The second part 83 may also cover the corner 26 of the source trench 18.

[0395] The second part 83 may also expose the corner 26 of the source trench 18. The second part 83 may also cover the corner 26 of the source trench 18 and may also cover a part of the second sidewall 22 of the source trench 18.

[0396] The source electrode layer 20 forms a Schottky junction within the source trench 18 and between the SiC semiconductor layers 2. Thus, a Schottky barrier diode 85 is formed with the source electrode layer 20 as the anode and the SiC semiconductor layer 2 as the cathode.

[0397] The source electrode layer 20 may also be formed of the same conductive material as the main surface source electrode 42. The source electrode layer 20 and the main surface source electrode 42 may also be formed of aluminum or a metal material containing aluminum as the main component.

[0398] The source electrode layer 20 and the main surface source electrode 42 may also contain at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, or tungsten. In this case, the gate electrode layer 14 is preferably formed of polysilicon (n-type polysilicon or p-type polysilicon).

[0399] The p-type deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the second bottom wall 23 of the source trench 18. The deep well region 21 may also be continuously formed in the SiC semiconductor layer 2 in a region along the second sidewall 22 and the corner 26 of the source trench 18 so that the source electrode layer 20 is exposed from the second sidewall 22 of the source trench 18.

[0400] That is, the deep well region 21 covers the second bottom wall 23 of the source trench 18. In addition, the deep well region 21 covers the corner 26 connecting the second sidewall 22 and the second bottom wall 23 of the source trench 18. The deep well region 21 may also expose substantially the entire region of the second sidewall 22 of the source trench 18 in the SiC semiconductor layer 2.

[0401] The deep well region 21 extends from the second bottom wall 23 of the source trench 18 in a lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2. Thus, the deep well region 21 faces the main body region 30 across a part of the SiC semiconductor layer 2 in the normal direction of the first main surface 3 of the SiC semiconductor layer 2.

[0402] More specifically, in the normal direction of the first main surface 3 of the SiC semiconductor layer 2, the source electrode layer 20 forms a Schottky junction at a depth position between the main body region 30 and the deep well region 21 and between the source electrode layer 20 and the SiC semiconductor layer 2.

[0403] More specifically, in the normal direction of the first main surface 3 of the SiC semiconductor layer 2, the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 in a region of the SiC semiconductor layer 2 sandwiched between the main region 30 and the deep well region 21.

[0404] The width W2 of the trench source structure 11 may also be consistent with the width WST of the source trench 18. That is, both the first width Wα and the second width Wβ of the deep well region 21 may be zero.

[0405] As described above, according to the semiconductor device 81, the same effects as those described for the semiconductor device 1 can be achieved. In addition, in the semiconductor device 81, when a reverse bias voltage is applied, current can preferentially flow into the Schottky barrier diode 85. As a result, the expansion of SiC crystal defects in the SiC semiconductor layer 2 can be suppressed. As a result, an improvement in short-circuit withstand capacity, a reduction in the feedback capacitance Crss, and an increase in the on-resistance can be suppressed.

[0406] In this embodiment, an example in which the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 within the sidewall contact hole 84 of the barrier formation layer 19 has been described. However, a method in which the barrier formation layer 19 (the first portion 82 and the second portion 83) is not formed may also be employed.

[0407] Figure 10 It is a plan view of the semiconductor device 91 according to the sixth embodiment of the present invention. Hereinafter, the structures corresponding to those of the semiconductor device 1 will be denoted by the same reference numerals and description thereof will be omitted.

[0408] Refer to Figure 10 , in this embodiment, the trench gate structure 10 is formed in a lattice shape in plan view. The trench source structure 11 may also be formed within the region surrounded by the trench gate structure 10.

[0409] The source region 31 may also be formed along the periphery of the trench gate structure 10. The contact region 32 may also be formed along the periphery of the trench source structure 11.

[0410] As described above, according to the semiconductor device 91, the same effects as those described for the semiconductor device 1 can also be achieved. In addition, according to the semiconductor device 91, the density of the current flowing through the SiC semiconductor layer 2 can also be increased.

[0411] The structure of the semiconductor device 91 can also be applied to the above-described embodiments. That is, the structure in which the trench gate structure 10 is formed in a lattice shape in plan view and the trench source structure 11 is formed within the region surrounded by the trench gate structure 10 can also be applied to the above-described embodiments.

[0412] The first to sixth embodiments of the present invention have been described, but the first to sixth embodiments of the present invention can also be implemented in other ways.

[0413] In the above-described first to sixth embodiments, the barrier formation layer 19 may also selectively expose the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. For example, the barrier formation layer 19 may also expose at least one of the contact region 32, the source region 31, and the body region 30 within the source trench 18.

[0414] In the above-described first to sixth embodiments, a configuration in which the barrier formation layer 19 is omitted may also be employed.

[0415] In the above-described first to sixth embodiments, the gate trench 12 may also be formed in a tapered shape in which the area of the first bottom wall 16 is smaller than the opening area in a cross-sectional view.

[0416] In the above-described first to sixth embodiments, the first bottom wall 16 of the gate trench 12 may also be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The first bottom wall 16 of the gate trench 12 may also be formed in a convexly curved shape from the first sidewall 15 toward the second main surface 4 of the SiC semiconductor layer 2.

[0417] In the above-described first to sixth embodiments, the source trench 18 may also be formed in a tapered shape in which the area of the second bottom wall 23 is smaller than the opening area in a cross-sectional view.

[0418] In the above-described first to sixth embodiments, the second bottom wall 23 of the source trench 18 may also be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The second bottom wall 23 of the source trench 18 may also be formed in a convexly curved shape from the second sidewall 22 toward the outside.

[0419] In the above-described first to sixth embodiments, an Si (silicon) semiconductor layer (2) made of Si may also be used instead of the SiC semiconductor layer 2 made of a single crystal of SiC. That is, the Si semiconductor layer (2) may also have a stacked structure including an Si semiconductor substrate (5) made of Si and an Si epitaxial layer (6) made of Si.

[0420] In the above-described first to sixth embodiments, a configuration in which the conductivity type of each semiconductor part is inverted may also be employed. That is, a p-type part may also be formed as an n-type, and an n-type part may also be formed as a p-type.

[0421] In the above-described first to sixth embodiments, a p+-type SiC semiconductor substrate (5) may be used instead of the n+-type SiC semiconductor substrate 5. According to this configuration, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of a MISFET.

[0422] In this case, the "source" of the MISFET is replaced with the "emitter" of the IGBT. In addition, the "drain" of the MISFET is replaced with the "collector" of the IGBT. When an IGBT is used instead of a MISFET, the same effects as those described in the above embodiments can also be achieved.

[0423] Figure 11 FIG. is a plan view showing a semiconductor device 101 according to a seventh embodiment of the present invention.

[0424] Refer to Figure 11 , the semiconductor device 101 includes a SiC semiconductor layer 102 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may also contain a 4H-SiC single crystal.

[0425] The 4H-SiC single crystal has an inclination angle of 10° or less with respect to the [11-20] direction from the (0001) plane. The inclination angle may be 0° or more and 4° or less. The inclination angle may be greater than 0° and less than 4°. Typically, the inclination angle is set to 2° or 4°, more specifically, in the range of 2° ± 0.2° or 4° ± 0.4°.

[0426] In this embodiment, the SiC semiconductor layer 102 is formed in a rectangular parallelepiped shape. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104.

[0427] The first main surface 103 and the second main surface 104 are formed in a quadrilateral shape in a plan view (hereinafter simply referred to as "plan view") observed from the above normal direction. The side surface 105A is opposed to the side surface 105C. The side surface 105B is opposed to the side surface 105D.

[0428] The side surfaces 105A to 105D extend in a plane along the normal directions of the first main surface 103 and the second main surface 104, respectively. The lengths of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0429] An active region 106 and an outer region 107 are defined in the SiC semiconductor layer 102. The active region 106 is a region where a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106.

[0430] The active region 106 is defined in the central portion of the SiC semiconductor layer 102 at intervals from the side surfaces 105A to 105D of the SiC semiconductor layer 102 toward the inner region of the SiC semiconductor layer 102 when viewed from above. The active region 106 is defined to have a quadrilateral shape with four sides parallel to the four side surfaces 105A to 105D of the SiC semiconductor layer 102 when viewed from above.

[0431] The outer region 107 is defined in the region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. The outer region 107 is defined to surround the active region 106 in a continuous (quadrilateral ring shape) when viewed from above.

[0432] A gate pad 108, gate fingers 109, and a source pad 110 are formed on the first main surface 103 of the SiC semiconductor layer 102 as the first main surface electrodes. In Figure 11 order to clarify, the gate pad 108, gate fingers 109, and source pad 110 are shown by hatching. The gate pad 108, gate fingers 109, and source pad 110 may also contain aluminum or copper.

[0433] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 when viewed from above. The gate pad 108 is formed in the central region of the side surface 105A of the SiC semiconductor layer 102 when viewed from above. The gate pad 108 may also be formed along a line connecting any two corner portions among the four side surfaces 105A to 105D of the SiC semiconductor layer 102 when viewed from above.

[0434] The gate pad 108 is formed in a quadrilateral shape when viewed from above. The gate pad 108 extends from the outer region 107 into the active region 106 in such a way as to cross the boundary region between the outer region 107 and the active region 106 when viewed from above.

[0435] The gate fingers 109 are formed in the outer region 107. The gate fingers 109 extend from the gate pad 108 and extend in a strip shape in the outer region 107. In this way, the gate fingers 109 are formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to divide the active region 106 from three directions.

[0436] The source pad 110 is formed in the active region 106 with a space from the gate pad 108 and the gate fingers 109. The source pad 110 is formed in a concave shape in a top view so as to cover the concave region defined by the gate pad 108 and the gate fingers 109.

[0437] A gate voltage is applied to the gate pad 108 and the gate fingers 109. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, GND voltage).

[0438] Figure 12 is Figure 11 An enlarged view of the region XII shown is an enlarged view for explaining the structure of the first main surface 103 of the SiC semiconductor layer 102. Figure 13 is along Figure 12 A cross-sectional view taken along line XIII-XIII shown. Figure 14 is along Figure 12 A cross-sectional view taken along line XIV-XIV shown.

[0439] Refer to Figures 12 - 14 , in this mode, the SiC semiconductor layer 102 has a stacked structure including an n+-type SiC semiconductor substrate 111 and an n-type SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 111.

[0440] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 may be a ground surface. The second main surface 104 of the SiC semiconductor layer 102 may have ground processing marks.

[0441] The thickness of the SiC semiconductor substrate 111 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 111 may be 5 μm or more. The thickness of the SiC semiconductor substrate 111 may be 25 μm or more. The thickness of the SiC semiconductor substrate 111 may be 50 μm or more. The thickness of the SiC semiconductor substrate 111 may be 100 μm or more.

[0442] The thickness of the SiC semiconductor substrate 111 may be 700 μm or less. The thickness of the SiC semiconductor substrate 111 may be 500 μm or less. The thickness of the SiC semiconductor substrate 111 may be 400 μm or more. The thickness of the SiC semiconductor substrate 111 may be 300 μm or less.

[0443] The thickness of the SiC semiconductor substrate 111 may also be 250 μm or less. The thickness of the SiC semiconductor substrate 111 may also be 200 μm or less. The thickness of the SiC semiconductor substrate 111 may also be 150 μm or less. The thickness of the SiC semiconductor substrate 111 may also be 100 μm or less.

[0444] The thickness of the SiC semiconductor substrate 111 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 111, it is possible to reduce the resistance value by shortening the current path.

[0445] The thickness of the SiC epitaxial layer 112 may also be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 112 may also be 5 μm or more. The thickness of the SiC epitaxial layer 112 may also be 10 μm or more.

[0446] The thickness of the SiC epitaxial layer 112 may also be 50 μm or less. The thickness of the SiC epitaxial layer 112 may also be 40 μm or less. The thickness of the SiC epitaxial layer 112 may also be 30 μm or less.

[0447] The thickness of the SiC epitaxial layer 112 may also be 20 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 10 μm or less.

[0448] The n-type impurity concentration of the SiC epitaxial layer 112 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 111. More specifically, the n-type impurity concentration of the SiC epitaxial layer 112 is less than the n-type impurity concentration of the SiC semiconductor substrate 111.

[0449] The n-type impurity concentration of the SiC semiconductor substrate 111 may also be 1.0×10 18 cm －3 or more and 1.0×10 21 cm －3 or less. The n-type impurity concentration of the SiC epitaxial layer 112 may also be 1.0×10 15 cm －3 or more and 1.0×10 18 cm －3 or less. In this mode, the SiC epitaxial layer 112 has a plurality of regions, and the plurality of regions have different n-type impurity concentrations along the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0450] More specifically, the SiC epitaxial layer 112 includes a high-concentration region 112a with a relatively high n-type impurity concentration and a low-concentration region 112b with a lower n-type impurity concentration than the high-concentration region 112a. The high-concentration region 112a is formed in a region on the side of the first main surface 103. The low-concentration region 112b is formed in a region on the side of the SiC semiconductor substrate 111 relative to the high-concentration region 112a.

[0451] The n-type impurity concentration of the high-concentration region 112a may also be 1×10 16 cm －3 or more and 1×10 18 cm －3 or less. The n-type impurity concentration of the low-concentration region 112b may also be 1×10 15 cm －3 or more and 1×10 16 cm− or less. The thickness of the high-concentration region 112a is equal to or less than the thickness of the low-concentration region 112b. More specifically, the thickness of the high-concentration region 112a is less than the thickness of the low-concentration region 112b.

[0452] A drain pad 113 as a second main surface electrode is connected to the second main surface 104 of the SiC semiconductor layer 102. When off, the maximum voltage that can be applied between the source pad 110 and the drain pad 113 may also be 1000 V or more and 10000 V or less.

[0453] The SiC semiconductor substrate 111 is formed as a drain region 114 of the MISFET. The SiC epitaxial layer 112 is formed as a drift region 115 of the MISFET.

[0454] In the active region 106, a p-type body region 116 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 116 may also be 1×10 17 cm －3 or more and 1×10 20 cm －3 or less. The active region 106 is defined by the body region 116.

[0455] In the active region 106, a plurality of gate trenches 121 are formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 121 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 121 are formed in a band shape extending along a second direction Y intersecting the first direction X.

[0456] More specifically, the first direction X is along the sides 105B and 105D of the SiC semiconductor layer 102. The second direction Y is a direction orthogonal to the first direction X. The second direction Y is also along the sides 105A and 105C of the SiC semiconductor layer 102.

[0457] The plurality of gate trenches 121 are formed in a striped shape in plan view. In this manner, each gate trench 121 extends in a band shape from the peripheral portion on one side (the side 105B side) to the peripheral portion on the other side (the side 105D side) of the first main surface 103 of the SiC semiconductor layer 102 in plan view.

[0458] Each gate trench 121 crosses the intermediate portion between the peripheral portion on one side and the peripheral portion on the other side of the first main surface 103 in plan view. One end portion of each gate trench 121 is located at the peripheral portion on one side of the first main surface 103 of the SiC semiconductor layer 102. The other end portion of each gate trench 121 is located at the peripheral portion on the other side of the first main surface 103 of the SiC semiconductor layer 102.

[0459] The first direction X can also be set to the [11 - 20] direction ([ - 1 - 120] direction). In this case, each gate trench 121 can also extend along the [11 - 20] direction. The first direction X can also be set to the [ - 1100] direction ([1 - 100] direction) orthogonal to the [11 - 20] direction. In this case, each gate trench 121 can also extend along the [ - 1100] direction ([1 - 100] direction).

[0460] Each gate trench 121 has a length on the order of millimeters (a length of 1 mm or more). In Figure 14 the shown cross section, the length of the gate trench 121 is the length from the end portion on the side of the connection portion of the gate trench 121 and the gate finger 109 to the end portion on the opposite side.

[0461] The length of each gate trench 121 can also be 0.5 mm or more. In this manner, the length of each gate trench 121 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total extension of one or more gate trenches 121 per unit area can also be 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less.

[0462] Each gate trench 121 integrally includes an active trench portion 121a and a contact trench portion 121b. The active trench portion 121a is the portion where the gate trench 121 is formed in the active region 106. The contact trench portion 121b is the portion where the gate trench 121 extends from the active trench portion 121a to the outer region 107.

[0463] Each gate trench 121 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each gate trench 121 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each gate trench 121 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0464] In the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the depth of the gate trench 121 may also be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the gate trench 121 is preferably 0.5 μm or more and 1.0 μm or less.

[0465] The width of the gate trench 121 in the first direction may also be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). The width of the gate trench 121 in the first direction is preferably 0.1 μm or more and 0.5 μm or less.

[0466] Refer to Figure 13 and Figure 14 , the opening edge portion 124 of each gate trench 121 includes a bent portion 125 that bends inward toward the gate trench 121. The opening edge portion 124 of the gate trench 121 is the corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the side wall of the gate trench 121.

[0467] The electric field of the gate trench 121 with respect to the opening edge portion 124 is dispersed along the bent portion 125. Thereby, the electric field concentration of the gate trench 121 with respect to the opening edge portion 124 can be alleviated.

[0468] In the surface layer portion of the body region 116, an n+-type source region 126 is formed in the region along the side wall of the gate trench 121. The n-type impurity concentration of the source region 126 may also be 1.0×10 18 cm －3 or more and 1.0×10 21 cm －3 or less.

[0469] The source region 126 is formed in a plurality along the side wall on one side and the side wall on the other side of the gate trench 121 in the first direction X. The plurality of source regions 126 are each formed in a strip shape extending along the second direction Y. The plurality of source regions 126 are formed in a striped shape in a top view.

[0470] In each gate trench 121, a gate insulating layer 131 and a gate electrode layer 132 are formed. For the sake of clarity, in Figure 12 , the gate insulating layer 131 and the gate electrode layer 132 are shown by hatching.

[0471] The gate insulating layer 131 may also include silicon oxide. The gate insulating layer 131 may also include other insulating films such as silicon nitride. The gate insulating layer 131 is formed in a film shape along the inner wall surface of the gate trench 121 in such a manner as to divide a concave space within the gate trench 121.

[0472] The gate insulating layer 131 includes a first region 131a, a second region 131b, and a third region 131c. The first region 131a is formed along the sidewall of the gate trench 121. The second region 131b is formed along the bottom wall of the gate trench 121. The third region 131c is formed along the first main surface 103 of the SiC semiconductor layer 102.

[0473] The thickness T1 of the first region 131a is smaller than the thickness T2 of the second region 131b and the thickness T3 of the third region 131c. The ratio T2 / T1 of the thickness T2 of the second region 131b to the thickness T1 of the first region 131a may also be 2 or more and 5 or less. The ratio T3 / T1 of the thickness T3 of the third region 131c to the thickness T1 of the first region 131a may also be 2 or more and 5 or less.

[0474] The thickness T1 of the first region 131a may also be 0.01 μm or more and 0.2 μm or less. The thickness T2 of the second region 131b may also be 0.05 μm or more and 0.5 μm or less. The thickness T3 of the third region 131c may also be 0.05 μm or more and 0.5 μm or less.

[0475] By forming the first region 131a of the gate insulating layer 131 thinly, it is possible to suppress an increase in carriers induced in the region near the sidewall of the gate trench 121 in the body region 116. As a result, an increase in channel resistance can be suppressed. By forming the second region 131b of the gate insulating layer 131 thickly, it is possible to alleviate the electric field concentration of the gate trench 121 with respect to the bottom wall.

[0476] By forming the third region 131c of the gate insulating layer 131 thickly, the breakdown voltage of the gate insulating layer 131 near the opening edge portion 124 of the gate trench 121 can be increased. In addition, by forming the third region 131c thickly, it is possible to suppress the disappearance of the third region 131c due to the etching method.

[0477] As a result, it is possible to suppress the case where the first region 131a is removed by the etching method due to the disappearance of the third region 131c. As a result, the gate electrode layer 132 can be properly opposed to the SiC semiconductor layer 102 with the gate insulating layer 131 interposed therebetween.

[0478] The gate electrode layer 132 is embedded in the gate trench 121 via the gate insulating layer 131. More specifically, the gate electrode layer 132 is embedded in the gate trench 121 so as to fill a concave space defined by the gate insulating layer 131. The gate electrode layer 132 is controlled by a gate voltage.

[0479] Reference Figure 13 as well as Figure 14 The gate electrode layer 132 is formed in a wall shape extending in a normal direction of the first main surface 103 of the SiC semiconductor layer 102 in a cross-sectional view, perpendicular to the extending direction of the gate trench 121 .

[0480] The gate electrode layer 132 has an upper end portion located on the opening side of the gate trench 121. The upper end portion of the gate electrode layer 132 is formed in a curved shape recessed toward the bottom wall of the gate trench 121.

[0481] The cross-sectional area of ​​the gate electrode layer 132 (the cross-sectional area perpendicular to the direction in which the gate trench 121 extends) may be 0.05 μm 2 Above and 0.5μm 2 The cross-sectional area of ​​the gate electrode layer 132 is defined by the product of the depth of the gate electrode layer 132 and the width of the gate electrode layer 132 .

[0482] The depth of the gate electrode layer 132 is the distance from the upper end to the lower end of the gate electrode layer 132. The width of the gate electrode layer 132 is the width of the groove at the middle position between the upper end and the lower end of the gate electrode layer 132. When the upper end is a curved surface (in this embodiment, a curved shape that is concave toward the lower side), the position of the upper end of the gate electrode layer 132 becomes the middle position of the upper surface of the gate electrode layer 132 in the depth direction.

[0483] The gate electrode layer 132 includes p-type polysilicon to which p-type impurities are added. The p-type impurities may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0484] The p-type impurity concentration of the gate electrode layer 132 is equal to or higher than the p-type impurity concentration of the body region 116 . More specifically, the p-type impurity concentration of the gate electrode layer 132 is higher than the p-type impurity concentration of the body region 116 .

[0485] The p-type impurity concentration of the gate electrode layer 132 may also be 1×10 18 cm －3 Above and 1×10 22 cm －3 The sheet resistance of the gate electrode layer 132 may be 10Ω / □ or more and 500Ω / □ or less (about 200Ω / □ in this embodiment).

[0486] Refer to Figure 14 , a gate wiring layer 133 is formed in the outer region 107. The gate wiring layer 133 is electrically connected to the gate pad 108 and the gate fingers 109.

[0487] The gate wiring layer 133 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 133 is formed on the third region 131c of the gate insulating layer 131.

[0488] In this manner, the gate wiring layer 133 is formed along the gate fingers 109. The gate wiring layer 133 is formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 in such a way as to divide the active region 106 from three directions.

[0489] The gate wiring layer 133 is connected to the gate electrode layer 132 exposed from the contact trench portion 121b of each gate trench 121. In this manner, the gate wiring layer 133 is formed by the lead-out portion led out from the gate electrode layer 132 above the first main surface 103 of the SiC semiconductor layer 102. The upper end portion of the gate wiring layer 133 is connected to the upper end portion of the gate electrode layer 132.

[0490] Refer to Figure 13 , a low-resistance electrode layer 134 is formed on the gate electrode layer 132. The low-resistance electrode layer 134 covers the upper end portion of the gate electrode layer 132 in the gate trench 121.

[0491] The low-resistance electrode layer 134 contains a conductive material having a sheet resistance smaller than that of the gate electrode layer 132. The sheet resistance of the low-resistance electrode layer 134 may be 0.01 Ω / sq or more and 10 Ω / sq or less.

[0492] The current supplied into the gate trench 121 flows in the low-resistance electrode layer 134 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 132. Thus, it is possible to quickly move the entire gate electrode layer 132 (the entire region of the active region 106) from the off state to the on state, and therefore it is possible to suppress the delay of the switching response.

[0493] In particular, in the case of the gate trench 121 having a length on the order of millimeters, it takes time for the current to be transmitted, but according to the low-resistance electrode layer 134, it is possible to appropriately suppress the delay of the switching response. That is, the low-resistance electrode layer 134 is formed in the gate trench 121 as a current diffusion electrode layer for diffusing the current.

[0494] In addition, if the miniaturization of the cell structure progresses, the width, depth, cross-sectional area, etc. of the gate electrode layer 132 become smaller, and therefore there is a concern about the delay of the switching response caused by the increase in the resistance in the gate trench 121.

[0495] However, according to the low-resistance electrode layer 134, the entire gate electrode layer 132 can be quickly moved from the off state to the on state, so that the delay of the switching response caused by miniaturization can be appropriately suppressed.

[0496] The low-resistance electrode layer 134 is formed in a film shape. The low-resistance electrode layer 134 has a connection portion 134a that contacts the upper end portion of the gate electrode layer 132 and a non-connection portion 134b opposite thereto. The connection portion 134a and the non-connection portion 134b of the low-resistance electrode layer 134 may also be formed in a curved shape imitating the upper end portion of the gate electrode layer 132. The connection portion 134a and the non-connection portion 134b of the low-resistance electrode layer 134 can adopt various forms.

[0497] The entire connection portion 134a of the low-resistance electrode layer 134 may also be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connection portion 134a of the low-resistance electrode layer 134 may also be located below the first main surface 103 of the SiC semiconductor layer 102.

[0498] The connection portion 134a of the low-resistance electrode layer 134 may also include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 134a of the low-resistance electrode layer 134 may also include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0499] For example, the central portion of the connection portion 134a of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connection portion 134a of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0500] The entire non-connection portion 134b of the low-resistance electrode layer 134 may also be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connection portion 134b of the low-resistance electrode layer 134 may also be located below the first main surface 103 of the SiC semiconductor layer 102.

[0501] The non-connection portion 134b of the low-resistance electrode layer 134 may also include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connection portion 134b of the low-resistance electrode layer 134 may also include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0502] For example, the central portion of the non-connected portion 134b of the low-resistance electrode layer 134 may also be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connected portion 134b of the low-resistance electrode layer 134 may also be located above the first main surface 103 of the SiC semiconductor layer 102.

[0503] The low-resistance electrode layer 134 has an edge portion 134c that abuts against the gate insulating layer 131. The edge portion 134c of the low-resistance electrode layer 134 abuts against the corner portion connecting the first region 131a and the second region 131b in the gate insulating layer 131.

[0504] The edge portion 134c of the low-resistance electrode layer 134 is formed in a region on the side of the first main surface 103 of the SiC semiconductor layer 102 with respect to the bottom of the source region 126. That is, the edge portion 134c of the low-resistance electrode layer 134 is formed in a region closer to the first main surface 103 of the SiC semiconductor layer 102 than the boundary region between the body region 116 and the source region 126.

[0505] Therefore, the edge portion 134c of the low-resistance electrode layer 134 faces the source region 126 with the gate insulating layer 131 interposed therebetween. The edge portion 134c of the low-resistance electrode layer 134 does not face the body region 116 with the gate insulating layer 131 interposed therebetween.

[0506] Thereby, it is possible to suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the body region 116 of the gate insulating layer 131. The current path can be formed by an undesired diffusion of the electrode material of the low-resistance electrode layer 134 with respect to the gate insulating layer 131.

[0507] In particular, a design in which the edge portion 134c of the low-resistance electrode layer 134 is connected to the third region 131c (the corner portion of the gate insulating layer 131) of the relatively thick gate insulating layer 131 is effective in reducing the risk of forming a current path.

[0508] In the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the thickness TR of the low-resistance electrode layer 134 is equal to or less than the thickness TG of the gate electrode layer 132 (TR ≤ TG). The thickness TR of the low-resistance electrode layer 134 is preferably less than the thickness TG of the gate electrode layer 132 (TR < TG). More specifically, the thickness TR of the low-resistance electrode layer 134 is preferably equal to or less than half of the thickness TG of the gate electrode layer 132 (TR ≤ TG / 2).

[0509] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 134 to the thickness TG of the gate electrode layer 132 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 132 may be 0.5 μm or more and 3 μm or less. The thickness TR of the low-resistance electrode layer 134 may be 0.01 μm or more and 3 μm or less.

[0510] Refer to Figure 14 , in this mode, the low-resistance electrode layer 134 also covers the upper end portion of the gate wiring layer 133. The portion of the low-resistance electrode layer 134 covering the upper end portion of the gate wiring layer 133 and the portion of the low-resistance electrode layer 134 covering the upper end portion of the gate electrode layer 132 are integrally formed. Thus, the low-resistance electrode layer 134 covers the entire region of the gate electrode layer 132 and the entire region of the gate wiring layer 133.

[0511] Therefore, the current supplied from the gate pad 108 and the gate fingers 109 to the gate wiring layer 133 flows in the low-resistance electrode layer 134 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 132 and the gate wiring layer 133.

[0512] Thus, the entire gate electrode layer 132 (the entire region of the active region 106) can be quickly moved from the off state to the on state via the gate wiring layer 133, thereby suppressing the delay of the switching response.

[0513] In particular, in the case of the gate trench 121 having a length on the order of millimeters, the delay of the switching response can be appropriately suppressed by the low-resistance electrode layer 134 covering the upper end portion of the gate wiring layer 133.

[0514] The low-resistance electrode layer 134 includes a polycrystalline layer. The polycrystalline layer is formed by siliciding a part of the surface layer portion of the gate electrode layer 132 with a metal material. More specifically, the polycrystalline layer is composed of a p-type polycrystalline layer containing p-type impurities added to the gate electrode layer 132 (p-type polysilicon).

[0515] In this mode, the polycrystalline layer has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less. More specifically, the polycrystalline layer contains at least one of TiSi, TiSi 2 , NiSi, CoSi, CoSi 2 , MoSi 2 or WSi 2 .

[0516] When a low-resistance electrode layer 134 is formed over p-type polysilicon, the sheet resistance within the gate trench 121 is equal to or less than the sheet resistance of the gate electrode layer 132 (p-type polysilicon) alone. The sheet resistance within the gate trench 121 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with an n-type impurity.

[0517] The sheet resistance within the gate trench 121 is approximately the same as the sheet resistance of the low-resistance electrode layer 134. That is, the sheet resistance within the gate trench 121 can also be 0.01 Ω / sq or more and 10 Ω / sq or less. The sheet resistance within the gate trench 121 is preferably less than 10 Ω / sq.

[0518] Figure 15 Shows the results of investigating the resistivity of the polycrystalline layer. Figure 15 Is a graph showing the relationship between the resistivity of the polycrystal and the formation temperature. In Figure 15 it, the vertical axis represents the resistivity [μΩ·cm], and the horizontal axis represents the formation temperature [°C] of the polycrystal.

[0519] Refer to Figure 15 , the resistivity decreases in the order of MoSi 2 , WSi 2 , NiSi, CoSi 2 , TiSi 2 . Therefore, the priority of the material used as the polycrystalline layer decreases in the order of MoSi 2 , WSi 2 , NiSi, CoSi 2 , TiSi 2 .

[0520] In particular, NiSi, CoSi 2 and TiSi 2 in the above are suitable as the polycrystalline layer for forming the low-resistance electrode layer 134 because their resistivity values and temperature dependencies are relatively small.

[0521] Also, based on the verification results of the inventors, when TiSi2 is used as the material for the low-resistance electrode layer 134, an increase in the leakage current between the gate and the source is observed when a low electric field is applied. In contrast, when CoSi 2 is used, no increase in the leakage current between the gate and the source is found when a low electric field is applied. Considering that NiSi has problems with heat resistance compared to CoSi 2 , CoSi 2 is most preferably used as the polycrystalline layer for forming the low-resistance electrode layer 134.

[0522] Refer to Figure 12 and Figure 13, in the active region 106, a plurality of source trenches 141 are formed on the first main surface 103 of the SiC semiconductor layer 102. Each source trench 141 is formed in a region between two adjacent gate trenches 121.

[0523] The plurality of source trenches 141 are each formed in a strip shape extending along the second direction Y. The plurality of source trenches 141 are formed in a stripe shape in a plan view. In the first direction X, the distance between the central portions of adjacent source trenches 141 may be 1.5 μm or more and 3 μm or less.

[0524] Each source trench 141 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each source trench 141 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each source trench 141 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0525] The depth of the source trench 141 is substantially equal to the depth of the gate trench 121. The depth of the source trench 141 may also be equal to or greater than the depth of the gate trench 121. In the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the depth of the source trench 141 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0526] The width of the source trench 141 in the first direction may also be substantially equal to the width of the gate trench 121 in the first direction. The width of the source trench 141 in the first direction may also be equal to or greater than the width of the gate trench 121 in the first direction. The width of the source trench 141 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

[0527] The opening edge portion 142 of each source trench 141 includes a bent portion 143 that bends inward toward the source trench 141. The opening edge portion 142 of the source trench 141 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the side wall of the source trench 141.

[0528] The electric field with respect to the opening edge portion 142 of the source trench 141 is dispersed along the bent portion 143. Thereby, the electric field concentration with respect to the opening edge portion 142 of the source trench 141 can be alleviated.

[0529] In the SiC semiconductor layer 102, a p+-type contact region 144 is formed in a region along the side wall of the source trench 141. The p-type impurity concentration of the contact region 144 may also be 1.0×10 18 cm －3 or more and 1.0×10 21 cm －3As described below, a plurality of contact regions 144 are formed on the side surfaces of one side and the other side of a source trench 141.

[0530] The plurality of contact regions 144 are formed at intervals in the second direction Y. The plurality of contact regions 144 are formed at intervals in the first direction X from the gate trench 121.

[0531] In the SiC semiconductor layer 102, a p-type deep well region 145 is formed in a region along the inner wall of the source trench 141. The deep well region 145 is also referred to as a breakdown voltage holding region. The deep well region 145 is formed in a strip shape extending along the source trench 141. The deep well region 145 extends along the inner wall of the source trench 141.

[0532] Refer to Figure 12 and Figure 14 , more specifically, the deep well region 145 extends along the side wall of the source trench 141, passes through the edge portion and covers the bottom wall of the source trench 141. The deep well region 145 is connected to the main body region 116 at the side wall of the source trench 141.

[0533] The deep well region 145 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 121. The deep well region 145 is formed in a high-concentration region 112a of the SiC epitaxial layer 112.

[0534] The p-type impurity concentration of the deep well region 145 may be substantially equal to the p-type impurity concentration of the main body region 116. The p-type impurity concentration of the deep well region 145 may exceed the p-type impurity concentration of the main body region 116. The p-type impurity concentration of the deep well region 145 may be less than the p-type impurity concentration of the main body region 116.

[0535] The p-type impurity concentration of the deep well region 145 may also be equal to or less than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the deep well region 145 may be less than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the deep well region 21 may also be 1.0×10 17 cm －3 or more and 1.0×10 19 cm －3 or less.

[0536] Refer to Figure 12 and Figure 14 , a p-type peripheral deep well region 148 is formed in the outer region 107. The peripheral deep well region 148 is electrically connected to the deep well region 145.

[0537] The peripheral deep well region 148 is configured to have the same potential as the deep well region 145. In this manner, the peripheral deep well region 148 and the deep well region 145 are integrally formed.

[0538] More specifically, the peripheral deep well region 148 extends in a band shape along the periphery of the active region 106 in the outer region 107. More specifically, the peripheral deep well region 148 is formed to surround the active region 106 without discontinuities (quadrilateral ring shape in this case).

[0539] The peripheral deep well region 148 is formed in a region on the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 along the outer region 107 and on the inner wall of the contact groove portion 121b of the gate trench 121. The peripheral deep well region 148 extends along the side wall of the contact groove portion 121b, passes through the edge portion, and covers the bottom wall of the contact groove portion 121b.

[0540] The peripheral deep well region 148 overlaps with the gate wiring layer 133 in a plan view. That is, the peripheral deep well region 148 faces the gate wiring layer 133 with the gate insulating layer 131 (the third region 131c) interposed therebetween.

[0541] The peripheral deep well region 148 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the contact groove portion 121b of the gate trench 121. The peripheral deep well region 148 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0542] The peripheral deep well region 148 includes a lead-out portion 148a that leads out from the outer region 107 to the peripheral portion of the active region 106 in a plan view. The lead-out portion 148a of the peripheral deep well region 148 covers the end portion on the outer region 107 side of the source trench 141 in a plan view.

[0543] The lead-out portion 148a of the peripheral deep well region 148 covers the inner wall of the active trench portion 121a at the peripheral portion of the active region 106. The lead-out portion 148a of the peripheral deep well region 148 extends along the side wall of the active trench portion 121a, passes through the edge portion, and covers the bottom wall of the active trench portion 121a. The lead-out portion 148a of the peripheral deep well region 148 is connected to the deep well region 145 in the active region 106.

[0544] The lead-out portion 148a of the peripheral deep well region 148 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the active trench portion 121a of the gate trench 121. The lead-out portion 148a of the peripheral deep well region 148 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0545] The p-type impurity concentration of the peripheral deep well region 148 may be approximately equal to the p-type impurity concentration of the main body region 116. The p-type impurity concentration of the peripheral deep well region 148 may exceed the p-type impurity concentration of the main body region 116. The p-type impurity concentration of the peripheral deep well region 148 may be less than the p-type impurity concentration of the main body region 116.

[0546] The p-type impurity concentration in the peripheral deep well region 148 may also be substantially equal to the p-type impurity concentration in the deep well region 145. The p-type impurity concentration in the peripheral deep well region 148 may also exceed the p-type impurity concentration in the deep well region 145. The p-type impurity concentration in the peripheral deep well region 148 may also be less than the p-type impurity concentration in the deep well region 145.

[0547] The p-type impurity concentration in the peripheral deep well region 148 may also be below the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the peripheral deep well region 148 may also be less than the p-type impurity concentration in the contact region 144. The p-type impurity concentration in the peripheral deep well region 148 may also be 1.0×10 17 cm －3 or more and 1.0×10 19 cm －3 or less.

[0548] A source insulating layer 146 and a source electrode layer 147 are formed in each source trench 141. For clarity, in Figure 12 , the source insulating layer 146 and the source electrode layer 147 are shown by hatching.

[0549] The source insulating layer 146 may also contain silicon oxide. The source insulating layer 146 is formed in a film shape along the inner wall surface of the source trench 141 so as to divide a concave space in the source trench 141.

[0550] The source insulating layer 146 includes a first region 146a and a second region 146b. The first region 146a is formed along the side wall of the source trench 141. The second region 146b is formed along the bottom wall of the source trench 141. The thickness T11 of the first region 146a is smaller than the thickness T12 of the second region 146b.

[0551] The ratio T12 / T11 of the thickness T12 of the second region 146b to the thickness T11 of the first region 146a may also be 2 or more and 5 or less. The thickness T11 of the first region 146a may also be 0.01 μm or more and 0.2 μm or less. The thickness T12 of the second region 146b may also be 0.05 μm or more and 0.5 μm or less.

[0552] The thickness T11 of the first region 146a may also be substantially equal to the thickness T1 of the first region 131a of the gate insulating layer 131. The thickness T12 of the second region 146b may also be substantially equal to the thickness T2 of the second region 131b of the gate insulating layer 131.

[0553] The source insulating layer 146 exposes the opening edge portion 142 of the source trench 141 . More specifically, the source insulating layer 146 exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141 .

[0554] More specifically, the first region 146 a of the source insulating layer 146 has an upper end portion located on the opening side of the source trench 141 . The upper end portion of the first region 146 a is formed below the first main surface 103 of the SiC semiconductor layer 102 .

[0555] The upper end of the first region 146a exposes the side wall of the source trench 141 on the opening side of the source trench 141. Thus, the first region 146a exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141.

[0556] The source electrode layer 147 is embedded in the source trench 141 via the source insulating layer 146. More specifically, the source electrode layer 147 is embedded in the source trench 141 so as to fill the concave space defined by the source insulating layer 146. The source electrode layer 147 is controlled by a source voltage.

[0557] The source electrode layer 147 has an upper end portion located on the opening side of the source trench 141. The upper end portion of the source electrode layer 147 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end portion of the source electrode layer 147 may be formed on the same surface as the upper end portion of the source insulating layer 146.

[0558] The upper end of the source electrode layer 147 may protrude further upward than the upper end of the source insulating layer 146. The upper end of the source electrode layer 147 may be located below the upper end of the source insulating layer 146. The thickness of the source electrode layer 147 may be greater than or equal to 0.5 μm and less than or equal to 10 μm (eg, about 1 μm).

[0559] The source electrode layer 147 preferably includes polysilicon having properties close to those of SiC. This can reduce stress generated in the SiC semiconductor layer 102. The source electrode layer 147 preferably includes p-type polysilicon to which p-type impurities are added. In this case, the source electrode layer 147 can be formed simultaneously with the gate electrode layer 132.

[0560] The p-type impurity concentration of the source electrode layer 147 is greater than or equal to the p-type impurity concentration of the body region 116. More specifically, the p-type impurity concentration of the source electrode layer 147 is greater than the p-type impurity concentration of the body region 116. The p-type impurity of the source electrode layer 147 may also include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

[0561] The p-type impurity concentration of the source electrode layer 147 may also be 1×10 18 cm －3 or more and 1×10 22 cm －3 or less. The sheet resistance of the source electrode layer 147 may also be 10 Ω / sq or more and 500 Ω / sq or less (about 200 Ω / sq in this embodiment).

[0562] The p-type impurity concentration of the source electrode layer 147 may be substantially equal to the p-type impurity concentration of the gate electrode layer 132. The sheet resistance of the source electrode layer 147 may be substantially equal to the sheet resistance of the gate electrode layer 132.

[0563] The source electrode layer 147 may include n-type polysilicon instead of p-type polysilicon. The source electrode layer 147 may include at least one of tungsten, aluminum, copper, aluminum alloy, or copper alloy instead of p-type polysilicon.

[0564] Thus, the semiconductor device 101 has a trench gate structure 151 and a trench source structure 152. The trench gate structure 151 includes a gate trench 121, a gate insulating layer 131, a gate electrode layer 132, and a low-resistance electrode layer 134. The trench source structure 152 includes a source trench 141, a source insulating layer 146, and a source electrode layer 147.

[0565] Referring to Figure 13 and Figure 14 , an interlayer insulating layer 153 is formed over the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 covers the trench gate structure 151 in the active region 106 and the gate wiring layer 133 in the outer region 107.

[0566] The interlayer insulating layer 153 may include silicon oxide or silicon nitride. A gate contact hole 154 and a source contact hole 155 are formed in the interlayer insulating layer 153.

[0567] The gate contact hole 154 exposes the gate wiring layer 133 (low-resistance electrode layer 134) in the outer region 107. The source contact hole 155 exposes the source region 126, the contact region 144, and the trench source structure 152 in the active region 106. A gate pad 108, gate fingers 109, and a source pad 110 are formed over the interlayer insulating layer 153.

[0568] The gate fingers 109 enter the gate contact hole 154 from over the interlayer insulating layer 153. The gate fingers 109 are electrically connected to the low-resistance electrode layer 134 within the gate contact hole 154. Thus, an electrical signal from the gate pad 108 is transmitted to the gate electrode layer 132 via the low-resistance electrode layer 134 having a relatively low resistance value.

[0569] The source pad 110 enters the source contact hole 155 from above the interlayer insulating layer 153. The source pad 110 is electrically connected to the source region 126, the contact region 144, and the source electrode layer 147 within the source contact hole 155. The source electrode layer 147 can also be formed using a partial region of the source pad 110.

[0570] Figure 16 is a graph for explaining sheet resistance. In Figure 16 it, the vertical axis represents the sheet resistance [Ω / □], and the horizontal axis represents the item. In Figure 16 it, the first bar graph L1, the second bar graph L2, and the third bar graph L3 are shown.

[0571] The first bar graph L1 represents the sheet resistance of n-type polysilicon. The second bar graph L2 represents the sheet resistance of p-type polysilicon. The third bar graph L3 represents the sheet resistance in the case where a low-resistance electrode layer 134 is formed on p-type polysilicon. The low-resistance electrode layer 134 includes TiSi 2 (p-type titanium silicide) here.

[0572] Referring to the first bar graph L1, the sheet resistance of n-type polysilicon is 10 Ω / □. Referring to the second bar graph L2, the sheet resistance of p-type polysilicon is 200 Ω / □. Referring to the third bar graph L3, the sheet resistance in the case where a low-resistance electrode layer 134 is formed on p-type polysilicon is 2 Ω / □.

[0573] p-type polysilicon has a work function different from that of n-type polysilicon. By simply burying p-type polysilicon in the gate trench 121, the gate threshold voltage Vth can be increased by about 1 V.

[0574] However, p-type polysilicon has a sheet resistance that is dozens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material of the gate electrode layer 132, the energy loss increases significantly along with the increase of the parasitic resistance (hereinafter simply referred to as "gate resistance") in the gate trench 121.

[0575] In contrast, in the structure with the low-resistance electrode layer 134 on p-type polysilicon, compared with the case where the low-resistance electrode layer 134 is not formed, the sheet resistance can be reduced to less than 1 / 100. In the structure with the low-resistance electrode layer 134, compared with the gate electrode layer 132 including n-type polysilicon, the sheet resistance can be reduced to less than 1 / 5.

[0576] As described above, according to the semiconductor device 101, the trench gate structure 151 is formed in which the gate electrode layer 132 is buried in the gate trench 121 via the gate insulating layer 131. In the trench gate structure 151, the gate electrode layer 132 is covered by the low resistance electrode layer 134 in a limited space called the gate trench 121.

[0577] The gate electrode layer 132 includes p-type polysilicon. This can increase the gate threshold voltage Vth. The low-resistance electrode layer 134 includes a conductive material having a sheet resistance lower than that of p-type polysilicon.

[0578] This can reduce gate resistance and, as a result, can effectively diffuse current along the trench gate structure 151 , thereby reducing switching delay.

[0579] In particular, the structure in which the gate electrode layer 132 is covered by the low resistance electrode layer 134 does not need to increase the p-type impurity concentration in the body region 116. Therefore, it is possible to increase the gate threshold voltage Vth while preventing an increase in channel resistance.

[0580] Furthermore, according to the semiconductor device 101, the gate wiring layer 133 is covered with the low-resistance electrode layer 134 in the outer region 107. This also enables the gate resistance of the gate wiring layer 133 to be reduced.

[0581] In particular, in a structure in which the gate electrode layer 132 and the gate wiring layer 133 are covered by the low-resistance electrode layer 134, the current can be efficiently diffused along the trench gate structure 151. Therefore, the switching delay can be appropriately shortened.

[0582] Figures 17A - 17L Yes means Figure 11 A cross-sectional view of an example of a method for manufacturing a semiconductor device 101 is shown. Figures 17A - 17L is with Figure 12 The corresponding section view.

[0583] Reference Figure 17A First, an n+ type SiC semiconductor substrate 111 is prepared. Next, a SiC epitaxial layer 112 is formed on the main surface of the SiC semiconductor substrate 111. The SiC epitaxial layer 112 is formed by growing SiC on the main surface of the SiC semiconductor substrate 111 by an epitaxial growth method.

[0584] In this embodiment, the SiC epitaxial layer 112 having the high concentration region 112 a and the low concentration region 112 b is formed. Thus, the SiC semiconductor layer 102 including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112 is formed.

[0585] Next, a p-type body region 116 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The body region 116 is formed by introducing a p-type impurity into the first main surface 103 of the SiC semiconductor layer 102.

[0586] The body region 116 can also be formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 by an ion implantation method via an ion implantation mask (not shown). The active region 106 is defined by the body region 116.

[0587] Next, referring to Figure 17B , an n+-type source region 126 is formed in the surface layer portion of the body region 116. The source region 126 is formed by introducing an n-type impurity into the surface layer portion of the body region 116. The source region 126 can also be formed in the surface layer portion of the body region 116 by an ion implantation method via the ion implantation mask 161.

[0588] Next, referring to Figure 17C , a p+-type contact region 144 is formed in the surface layer portion of the body region 116. The contact region 144 is formed by introducing a p-type impurity into the surface layer portion of the body region 116. The contact region 144 can also be formed in the surface layer portion of the body region 116 by an ion implantation method via the ion implantation mask 162.

[0589] Next, referring to Figure 17D , a mask 163 having a predetermined pattern is formed on the first main surface 103 of the SiC semiconductor layer 102. The mask 163 has a plurality of openings 164 that expose regions where the gate trench 121 and the source trench 141 need to be formed.

[0590] Next, unnecessary portions of the SiC semiconductor layer 102 are removed. The unnecessary portions of the SiC semiconductor layer 102 can also be removed by an etching method (e.g., wet etching method) via the mask 163. Thereby, the gate trench 121 and the source trench 141 are formed. Then, the mask 163 is removed.

[0591] Next, a deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the inner wall of the source trench 141. The deep well region 145 can also be formed in the SiC semiconductor layer 102 by an ion implantation method via an ion implantation mask (not shown).

[0592] In addition, in the outer region 107, a peripheral deep well region 148 is formed in a region along the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 and the inner wall of the contact trench portion 121b of the gate trench 121. In this process, a peripheral deep well region 148 including a lead-out portion 148a leading from the outer region 107 to the peripheral portion of the active region 106 is formed.

[0593] The peripheral deep well region 148 can also be formed in the SiC semiconductor layer 102 by an ion implantation method via an ion implantation mask (not shown). Part or all of the peripheral deep well region 148 can also be formed simultaneously with the deep well region 145 using the formation process of the deep well region 145. Part of the peripheral deep well region 148 can also be formed simultaneously with the main region 116 using the formation process of the main region 116.

[0594] Next, referring to Figure 17E , an annealing process is performed on the SiC semiconductor layer 102. The annealing process can also be a high-temperature hydrogen annealing process. The annealing temperature can also be 1400 °C or higher.

[0595] As a result, a bent portion 125 is formed at the opening edge portion 124 of the gate trench 121. In addition, a bent portion 143 is formed at the opening edge portion 142 of the source trench 141.

[0596] Next, referring to Figure 17F , a base insulating layer 165 that serves as a base for the gate insulating layer 131 and the source insulating layer 146 is formed so as to cover the first main surface 103 of the SiC semiconductor layer 102. The base insulating layer 165 can also be formed by a CVD (chemical vapor deposition) method. The base insulating layer 165 can also contain silicon oxide.

[0597] In this process, in the base insulating layer 165, portions covering the side walls of the gate trench 121 and portions covering the side walls of the source trench 141 are formed thinner than other portions.

[0598] The base insulating layer 165 in such a manner is formed by adjusting predetermined conditions such as gas flow rate, gas type, gas ratio, gas supply time, etc. using the CVD method. The base insulating layer 165 can also be formed by an oxidation treatment method instead of the CVD method. The oxidation treatment method can also be a thermal oxidation treatment method or a wet oxidation treatment method.

[0599] Next, referring to Figure 17G , a base conductor layer 166 that serves as a base for the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 is formed on the first main surface 103 of the SiC semiconductor layer 102.

[0600] The base conductor layer 166 can also contain p-type polysilicon doped with a p-type impurity. The base conductor layer 166 can also be formed by a CVD method. The CVD method can also be an LP-CVD (Low Pressure-CVD) method.

[0601] Next, referring to Figure 17H, the unnecessary portions of the base conductor layer 166 are removed. The unnecessary portions of the base conductor layer 166 are removed by an etching method (e.g., wet etching method) through a mask (not shown) having a predetermined pattern.

[0602] This mask (not shown) covers the region where the gate wiring layer 133 should be formed. The unnecessary portions of the base conductor layer 166 are removed at least until the portion covering the first main surface 103 of the SiC semiconductor layer 102 is exposed on the base insulating layer 165. Thus, the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 are formed.

[0603] When the source electrode layer 147 is made of an electrode material different from that of the gate electrode layer 132, the electrode material of the source electrode layer 147 is separately subjected to the same process as Figures 17G - 17H to form the source electrode layer 147. When the source electrode layer 147 is formed using a part of the source pad 110, the source electrode layer 147 is formed when the source pad 110 is formed.

[0604] Next, referring to Figure 17I , a metal material layer 167 is formed on the gate electrode layer 132. In this manner, the metal material layer 167 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover the gate electrode layer 132 and the source electrode layer 147 together.

[0605] The metal material layer 167 contains a metal material that can be polycrystallized between p-type polysilicons. The metal material layer 167 may also contain at least one of Mo, W, Ni, Co, or Ti.

[0606] Next, a p-type polycrystalline layer is formed on the surface layer portion of the gate electrode layer 132 and the surface layer portion of the gate wiring layer 133. In this manner, a p-type polycrystalline layer is also formed on the surface layer portion of the source electrode layer 147.

[0607] The p-type polycrystalline layer is formed by polycrystallizing the surface layer portion of the gate electrode layer 132, the surface layer portion of the gate wiring layer 133, and the surface layer portion of the source electrode layer 147 by heat treatment of the metal material layer 167. The heat treatment of the metal material layer 167 may also be the RTA (Rapid Thermal Annealing) method.

[0608] Thus, corresponding to the metal material of the metal material layer 167, there is formed a layer containing TiSi, TiSi 2 , NiSi, CoSi, CoSi 2 , MoSi 2 or WSi 2A p-type polycrystal of at least one of them. A low-resistance electrode layer 134 is formed from the p-type polycrystalline layer.

[0609] Next, referring to Figure 17J , unreacted portions in the metal material layer 167 that are not bonded to the p-type polysilicon are removed. The unreacted portions of the metal material layer 167 can also be removed by an etching method (e.g., a wet etching method).

[0610] When the low-resistance electrode layer 134 (p-type polycrystal) contains at least one of TiSi or CoSi, after removing the unreacted portions of the metal material layer 167, heat treatment can be performed on the low-resistance electrode layer 134 as needed.

[0611] The heat treatment for the low-resistance electrode layer 134 can also be the RTA method. Thereby, TiSi is modified to TiSi 2 , CoSi is modified to CoSi 2 , and thus low resistance can be achieved.

[0612] Next, referring to Figure 17K , an interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover the trench gate structure 151 and the gate wiring layer 133. The interlayer insulating layer 153 contains silicon oxide or silicon nitride. The interlayer insulating layer 153 can also be formed by CVD method.

[0613] Next, a mask 168 having a predetermined pattern is formed on the interlayer insulating layer 153. The mask 168 has a plurality of openings 169 that expose regions where the gate contact hole 154 and the source contact hole 155 need to be formed.

[0614] Next, unnecessary portions of the interlayer insulating layer 153 are removed. The unnecessary portions of the interlayer insulating layer 153 can also be removed by an etching method (e.g., a dry etching method) via the mask 168. Thereby, the gate contact hole 154 and the source contact hole 155 are formed.

[0615] Next, referring to Figure 17L , the gate pad 108, the gate fingers 109, and the source pad 110 are formed on the interlayer insulating layer 153. The gate pad 108, the gate fingers 109, and the source pad 110 are formed using a mask (not shown) having a predetermined pattern. In addition, the drain pad 113 is formed on the second main surface 104 of the SiC semiconductor layer 102. Through the processes including the above processes, the semiconductor device 101 is manufactured.

[0616] Figure 18 is related to Figure 13A cross-sectional view of the corresponding region is a cross-sectional view showing the semiconductor device 171 of the eighth embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to those described for the semiconductor device 101, and the description thereof is omitted.

[0617] Refer to Figure 18 , in the semiconductor device 171, the gate insulating layer 131 includes a bulging portion 172 that bulges toward the inside of the gate trench 121 at the opening edge portion 124 of the gate trench 121. The bulging portion 172 is formed at the corner portion connecting the first region 131a and the third region 131c of the gate insulating layer 131.

[0618] The bulging portion 172 extends inwardly of the gate trench 121 in a curved shape. The bulging portion 172 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0619] The upper end portion of the gate electrode layer 132 has a constricted portion that is recessed along the bulging portion 172 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end portion) of the gate electrode layer 132. In this manner, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 172 of the gate insulating layer 131.

[0620] In the above Figure 17F process, the shape of the bulging portion 172 of the gate insulating layer 131 is also considered, and the bulging portion 172 of the gate insulating layer 131 is formed by setting predetermined conditions (gas flow rate, gas type, gas ratio, gas supply time, etc.) of the CVD method.

[0621] As described above, according to the semiconductor device 171, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 172 of the gate insulating layer 131. Thereby, it is possible to appropriately suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0622] In addition, according to the semiconductor device 171, the opening edge portion 124 of the gate trench 121 has a bent portion 125, and in addition, a bulging portion 172 is formed at the opening edge portion 124 of the gate trench 121. Thereby, it is possible to further improve the breakdown voltage of the gate insulating layer 131 at the opening edge portion 124 of the gate trench 121.

[0623] Figure 19 Is a cross-sectional view of the corresponding region, and is a cross-sectional view showing the semiconductor device 181 of the ninth embodiment of the present invention. Hereinafter, the same reference numerals are given to the structures corresponding to those described for the semiconductor device 101, and the description thereof is omitted. Figure 13

[0624] Figure 19 Refer to Figure 19, in the semiconductor device 181, the opening edge portion 124 of the gate trench 121 has an inclined portion 182 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the side wall of the gate trench 121.

[0625] According to the inclined portion 182 of the gate trench 121, the electric field can be dispersed along the inclined portion 182, so that the electric field concentration with respect to the opening edge portion 124 of the gate trench 121 can be alleviated.

[0626] The gate insulating layer 131 includes a bulging portion 183 that bulges toward the inside of the gate trench 121 in the inclined portion 182 of the gate trench 121. The bulging portion 183 is formed at the corner of the gate insulating layer 131 that connects the first region 131a and the third region 131c.

[0627] The bulging portion 183 protrudes inward of the gate trench 121 in a curved shape. The bulging portion 183 narrows the opening of the gate trench 121 at the opening edge portion 124 of the gate trench 121.

[0628] The upper end portion of the gate electrode layer 132 has a constricted portion that is recessed along the bulging portion 183 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end portion) of the gate electrode layer 132. In this manner, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 183 of the gate insulating layer 131.

[0629] The opening edge portion 142 of the source trench 141 has an inclined portion 184 that slopes downward from the first main surface 103 of the SiC semiconductor layer 102 toward the side wall of the source trench 141. According to the inclined portion 184 of the source trench 141, since the electric field can be dispersed along the inclined portion 184, the electric field concentration with respect to the opening edge portion 142 of the source trench 141.

[0630] Figures It represents ​ A cross-sectional view showing an example of the manufacturing method of the semiconductor device 181 shown.

[0631] First, referring to ​ , prepare the SiC semiconductor layer 102 having the gate trench 121 and the source trench 141 formed on the first main surface 103 through the process of ​ .

[0632] Next, referring to ​ , a thermal oxidation treatment is performed on the first main surface 103 of the SiC semiconductor layer 102, and a sacrificial oxide film 185 is formed. In this process, oxidation starts uniformly from both the first main surface 103 of the SiC semiconductor layer 102 and the side wall of the gate trench 121.

[0633] The oxide film advancing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film advancing from the side wall of the gate trench 121 are integrated at the opening edge portion 124 of the gate trench 121.

[0634] Through the integration of these oxide films, the oxidation of the opening edge portion 124 of the gate trench 121 is accelerated. And an inclined portion 182 is formed below the oxide film integrated at the opening edge portion 124 of the gate trench 121.

[0635] The oxide film advancing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film advancing from the side wall of the source trench 141 are integrated at the opening edge portion 142 of the source trench 141.

[0636] Through the integration of these oxide films, the oxidation of the opening edge portion 142 of the source trench 141 is accelerated. And an inclined portion 184 is formed below the oxide film integrated at the opening edge portion 142 of the source trench 141.

[0637] Next, referring to ​ , the sacrificial oxide film 185 is removed. The sacrificial oxide film 185 can also be removed by an etching method (for example, a wet etching method). Then, the processes of ​ are performed in sequence.

[0638] In ​ 's process, the shape of the bulging portion 183 of the gate insulating layer 131 is also considered, and the bulging portion 183 of the gate insulating layer 131 is formed by setting predetermined conditions (gas flow rate, gas type, gas ratio, gas supply time, etc.) of the CVD method. Through the process including the above processes, the semiconductor device 181 is manufactured.

[0639] As described above, according to the semiconductor device 181, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 183 of the gate insulating layer 131. Thus, it is possible to appropriately suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0640] In addition, according to the semiconductor device 181, the opening edge portion 124 of the gate trench 121 has the inclined portion 182, and in addition, a bulging portion 183 is formed at the opening edge portion 124 of the gate trench 121. Thus, it is possible to further improve the breakdown voltage of the gate insulating layer 131 at the opening edge portion 124 of the gate trench 121.

[0641] In the present embodiment, an example of the manner of forming the gate insulating layer 131 having the bulging portion 183 in the semiconductor device 181 has been described. However, it is also possible to form the gate insulating layer 131 without the bulging portion 183 in the semiconductor device 181.

[0642] ​ is an enlarged view of the region corresponding to ​ and is an enlarged view showing the semiconductor device 191 of the 10th embodiment of the present invention. ​ is a cross-sectional view taken along the line XXII-XXII shown in ​ . Hereinafter, the structures corresponding to the structures described for the semiconductor device 101 are denoted by the same reference numerals and the description thereof is omitted.

[0643] Referring to ​ and ​ , in the semiconductor device 191, an outer gate trench 192 is formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 107. The outer gate trench 192 extends in a band shape in the outer region 107.

[0644] The outer gate trench 192 is formed in a region directly below the gate finger 109 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 192 extends along the gate finger 109.

[0645] More specifically, the outer gate trench 192 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to divide the active region 106 from three directions. The outer gate trench 192 may also be formed in a continuous shape (e.g., a quadrilateral ring shape) surrounding the active region 106.

[0646] The outer gate trench 192 communicates with the contact trench portion 121b of each gate trench 121. Thus, the outer gate trench 192 and the gate trench 121 are formed by one trench.

[0647] A gate wiring layer 133 is buried in the outer gate trench 192. The gate wiring layer 133 is connected to the gate electrode layer 132 at the communication portion of the outer gate trench 192 and the contact trench portion 121b.

[0648] In this manner, the low-resistance electrode layer 134 covers the upper end portion of the gate wiring layer 133 in the outer gate trench 192. Therefore, the low-resistance electrode layer 134 covering the gate electrode layer 132 and the low-resistance electrode layer 134 covering the gate wiring layer 133 are both located in one trench.

[0649] In this manner, the peripheral deep well region 148 covers the inner wall of the outer gate trench 192 in the outer region 107. The peripheral deep well region 148 extends along the side wall of the outer gate trench 192 and passes through the edge portion to reach the bottom wall of the outer gate trench 192.

[0650] That is, the peripheral deep well region 148 is a part along the inner wall of the outer gate trench 192, and is opposed to the gate wiring layer 133 with the gate insulating layer 131 therebetween. Further, the peripheral deep well region 148 is a part along the inner wall of the gate trench 121, and is opposed to the gate electrode layer 132 with the gate insulating layer 131 therebetween.

[0651] As described above, according to the semiconductor device 191, the same effects as those described for the semiconductor device 101 can also be achieved. Further, according to the semiconductor device 191, it is not necessary to lead out the gate wiring layer 133 onto the first main surface 103 of the SiC semiconductor layer 102.

[0652] Thereby, at the opening edge portions of the gate trench 121 and the outer gate trench 192, it is possible to suppress the gate wiring layer 133 from being opposed to the SiC semiconductor layer 102 with the gate insulating layer 131 therebetween. As a result, it is possible to suppress the electric field concentration at the opening edge portion of the gate trench 121.

[0653] ​ is a cross-sectional view of a region corresponding to Figure 13 and is a cross-sectional view for explaining the structure of the semiconductor device 201 according to the eleventh embodiment of the present invention. Hereinafter, the structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and the description thereof is omitted.

[0654] Referring to Figure 23 , in the semiconductor device 201, each source trench 141 is formed deeper than the gate trench 121. Therefore, the bottom wall of each source trench 141 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom of the gate trench 121. More specifically, the bottom wall of each source trench 141 is located in the high-concentration region 112a of the SiC epitaxial layer 112.

[0655] The ratio of the depth of the source trench 141 to the depth of the gate trench 121 may be 1.5 or more. The ratio of the depth of the source trench 141 to the depth of the gate trench 121 is preferably 2 or more.

[0656] The depth of the gate trench 121 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the source trench 141 may be 0.75 μm or more and 10 μm or less (for example, about 2 μm).

[0657] Similar to the case of the semiconductor device 101, the deep well region 145 extends along the inner wall of the source trench 141 and has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0658] As described above, according to the semiconductor device 201, the same effects as those described for the semiconductor device 101 can also be achieved.

[0659] Figure 24 is a plan view of a region corresponding to Figure 12 and is a plan view for explaining the structure of the semiconductor device 211 according to the 12th embodiment of the present invention. Hereinafter, the structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and the description thereof is omitted.

[0660] Referring to Figure 24 , in this embodiment, the gate trench 121 is formed in a lattice shape integrally including a plurality of gate trenches 121 extending in the first direction X and a plurality of gate trenches 121 extending in the second direction Y in a plan view.

[0661] On the first main surface 103 of the SiC semiconductor layer 102, a plurality of unit regions 212 are divided in a row and column manner by the gate trenches 121. Each unit region 212 is formed in a quadrilateral shape in a plan view. Source trenches 141 are respectively formed in the plurality of unit regions 212. The source trenches 141 may also be formed in a quadrilateral shape in a plan view.

[0662] Along Figure 24 the cross-sectional view taken along line XIII-XIII is substantially the same as the cross-sectional view shown in Figure 13 . The cross-sectional view taken along line XIV-XIV along Figure 24 is substantially the same as the cross-sectional view shown in Figure 14 .

[0663] As described above, according to the semiconductor device 211, the same effects as those described for the semiconductor device 101 can also be achieved. The gate trench 121 having a lattice-shaped structure instead of a striped shape can also be applied to other embodiments.

[0664] Figure 25 is a cross-sectional view of a region corresponding to Figure 13 and is a plan view for explaining the structure of the semiconductor device 221 according to the 13th embodiment of the present invention. Hereinafter, the structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and the description thereof is omitted.

[0665] Referring to Figure 25 , in the semiconductor device 221, the SiC semiconductor layer 102 includes a p+-type SiC semiconductor substrate 222 instead of the n+-type SiC semiconductor substrate 111. The p+-type SiC semiconductor substrate 222 is formed as a collector region of an IGBT (Insulated Gate Bipolar Transistor).

[0666] In the description of the semiconductor device 101, the "source" of the MISFET is replaced with the "emitter" of the IGBT, and the "drain" of the MISFET is replaced with the "collector" of the IGBT, and this is applied to the description of the semiconductor device 221.

[0667] That is, the source pad 110 and the source region 126 are respectively replaced with the emitter pad (110) and the emitter region (126). Further, the drain pad 113 and the drain region 114 are respectively replaced with the collector electrode layer (113) and the collector region (114).

[0668] As described above, according to the semiconductor device 221, the same effects as those described for the semiconductor device 101 can also be achieved.

[0669] Figure 26 It is Figure 13 A cross-sectional view of a corresponding region, and it is a cross-sectional view for explaining the structure of the semiconductor device 231 according to the 14th embodiment of the present invention. Hereinafter, for the structure corresponding to the structure described for the semiconductor device 101, the same reference numerals are given and the description is omitted.

[0670] Refer to Figure 26 , the contact region 144 is formed in a region along the bottom wall of the source trench 141 within the deep well region 145. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0671] The source insulating layer 146 is formed along the inner wall surface of the source trench 141 in such a manner that the contact region 144 is selectively exposed from the bottom wall of the source trench 141.

[0672] More specifically, the source insulating layer 146 includes a first portion 232 and a second portion 233. The first portion 232 covers the side wall of the source trench 141. The second portion 233 locally covers the bottom wall of the source trench 141.

[0673] The second portion 233 is connected to the first portion 232. The second portion 233 extends along the bottom wall from the corner of the source trench 141 in such a manner that the central portion of the bottom wall of the source trench 141 is exposed. The second portion 233 may be formed to be continuous (annular) in a plan view.

[0674] As described above, according to the semiconductor device 231, the same effects as those described for the semiconductor device 101 can be achieved. Further, according to the semiconductor device 231, a pn junction is formed in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0675] Even if the depletion layer extends from the pn junction along the bottom wall from the corner of the source trench 141, the distance at which the depletion layer reaches the source electrode layer 147 can be obtained through the source insulating layer 146. Thus, near the corner of the source trench 141, generation of punch-through can be suppressed.

[0676] Figure 27 is a cross-sectional view of a region corresponding to Figure 13 and is a cross-sectional view for explaining the structure of the semiconductor device 241 according to the 15th embodiment of the present invention. Hereinafter, for the structures corresponding to those described for the semiconductor device 101, the same reference numerals are given and the description is omitted.

[0677] Refer to Figure 27 , in the deep well region 145, an exposed portion 242 for selectively exposing the bottom wall of the source trench 141 is formed. The exposed portion 242 exposes the central portion of the bottom wall of the source trench 141.

[0678] In this embodiment, the source insulating layer 146 includes a first portion 243 and a second portion 244. The first portion 243 covers the side wall of the source trench 141. The second portion 244 locally covers the bottom wall of the source trench 141.

[0679] The second portion 244 is connected to the first portion 243. The second portion 244 extends along the bottom wall from the corner of the source trench 141 so as to expose the central portion of the bottom wall of the source trench 141. The second portion 244 may also be formed to be continuous (ring-shaped) in plan view.

[0680] The source electrode layer 147 forms a heterojunction portion in the exposed portion 242 of the deep well region 145 and between the SiC semiconductor layer 102. Thus, a heterojunction diode 245 having the source electrode layer 147 as an anode and the SiC semiconductor layer 102 as a cathode is formed. The source electrode layer 147 may contain a conductive material other than polysilicon as long as the heterojunction diode 245 can be formed.

[0681] A body diode 246 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116. The junction barrier of the heterojunction diode 245 is smaller than the diffusion potential of the body diode 246.

[0682] The junction barrier of the heterojunction diode 245 may be 1.0 eV or more and 1.5 eV or less. The diffusion potential of the body diode 246 may be 2.8 eV or more and 3.2 eV or less.

[0683] As described above, according to the semiconductor device 241, the same effects as those described for the semiconductor device 101 can be achieved. In addition, in the semiconductor device 241, when a reverse bias voltage is applied, current can preferentially flow into the heterojunction diode 245.

[0684] Thereby, the expansion of crystal defects of SiC in the SiC semiconductor layer 102 can be suppressed. As a result, an improvement in short-circuit withstand capacity and a reduction in the feedback capacitance Crss can be achieved, and an increase in the on-resistance can be suppressed.

[0685] Figure 28 is a cross-sectional view of a region corresponding to Figure 13 and is a cross-sectional view for explaining the structure of the semiconductor device 251 according to the 16th embodiment of the present invention. Hereinafter, the structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals and the description thereof is omitted.

[0686] Refer to Figure 28 , the contact region 144 is formed in a region along the bottom wall of the source trench 141 within the deep well region 145. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0687] The source insulating layer 146 has a stacked structure including a plurality of barrier forming layers formed along the inner wall of the source trench 141. In this embodiment, the source insulating layer 146 has a stacked structure including an insulating barrier forming layer 252 and a conductive barrier forming layer 253 stacked in this order from the inner wall of the source trench 141.

[0688] The insulating barrier forming layer 252 may contain at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0689] The insulating barrier forming layer 252 is formed in a film shape along the inner wall surface of the source trench 141 in such a manner that the contact region 144 is selectively exposed from the bottom wall of the source trench 141.

[0690] More specifically, the insulating barrier forming layer 252 includes a first portion 254 and a second portion 255. The first portion 254 covers the side wall of the source trench 141. The second portion 255 selectively covers the bottom wall of the source trench 141.

[0691] The second portion 255 is connected to the first portion 254. The second portion 255 extends along the bottom wall from the corner of the source trench 141 in such a manner that the central portion of the bottom wall of the source trench 141 is exposed.

[0692] The conductive barrier forming layer 253 may also include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier forming layer 253 includes a conductive material different from that of the source electrode layer 147.

[0693] The conductive barrier forming layer 253 is formed in a film shape along the insulating barrier forming layer 252 in such a manner that the contact region 144 is selectively exposed from the bottom wall of the source trench 141.

[0694] Instead of the conductive barrier forming layer 253, the source insulating layer 146 may also include an insulating barrier forming layer made of an insulating material different from that of the insulating barrier forming layer 252. Instead of the conductive barrier forming layer 253, the source insulating layer 146 may also include an insulating barrier forming layer made of the same insulating material as that of the insulating barrier forming layer 252.

[0695] As described above, according to the semiconductor device 251, the same effects as those described for the semiconductor device 101 can be achieved. In addition, in the semiconductor device 251, the source insulating layer 146 has a stacked structure including the insulating barrier forming layer 252 and the conductive barrier forming layer 253. Thus, the generation of punch-through can be suppressed by using these two layers, i.e., the insulating barrier forming layer 252 and the conductive barrier forming layer 253.

[0696] Figure 29 is a cross-sectional view of a corresponding region, and is a cross-sectional view for explaining the structure of the semiconductor device 261 according to the 17th embodiment of the present invention. Hereinafter, for the structures corresponding to those described for the semiconductor device 101, the same reference numerals are given and the description is omitted. Figure 13

[0697] Figure 29 Refer to In, the contact region 144 is formed in a region along the bottom wall of the source trench 141 within the deep well region 145. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0698] The source insulating layer 146 includes a first portion 262 and a second portion 263. The first portion 262 covers the side wall of the source trench 141. The second portion 263 covers the bottom wall of the source trench 141.

[0699] The first portion 262 selectively has a side wall contact hole 264 that exposes the SiC semiconductor layer 102 from the side wall of the source trench 141. The first portion 262 may also be formed to cross the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0700] ​The end portion on the lower side of the first part 262 (the end portion on the bottom wall side of the source trench 141) may also be located on the bottom wall side of the source trench 141 with respect to the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 within the source trench 141.

[0701] The end portion on the lower side of the first part 262 may also be located on the first main surface 103 side with respect to the bottom of the body region 116. The end portion on the lower side of the first part 262 may also be formed in the region between the bottom of the body region 116 and the bottom of the source region 126. In the above cases, the source electrode layer 147 is connected to at least the body region 116 within the source trench 141.

[0702] The end portion on the lower side of the first part 262 may also be formed in the region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may also have only the second part 263 without the first part 262. In the above cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 within the source trench 141.

[0703] The second part 263 of the source insulating layer 146 is formed at an interval from the first part 262 of the source insulating layer 146. That is, the second part 263 is separated from the first part 262. The second part 263 may also cover the corner portion of the source trench 141.

[0704] The second part 263 may also expose the corner portion of the source trench 141. The second part 263 may also cover the corner portion of the source trench 141 and a part of the side wall of the source trench 141.

[0705] A Schottky junction is formed between the source electrode layer 147 within the source trench 141 and the SiC semiconductor layer 102 (drift region 115). Thus, a Schottky barrier diode 265 with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode is formed.

[0706] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in the region along the bottom wall of the source trench 141. In this manner, the deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112. The entire region of the deep well region 145 is formed in the high concentration region 112a.

[0707] The deep well region 145 may also be continuously formed in the SiC semiconductor layer 102 in the region along the side wall and the corner portion of the source trench 141 in such a manner that the source electrode layer 147 is exposed from the side wall of the source trench 141.

[0708] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the connecting side wall of the source trench 141 and the corner portion of the bottom wall. The deep well region 145 may also expose substantially the entire region of the side wall of the source trench 141 in the SiC semiconductor layer 102.

[0709] The deep well region 145 is led out from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. Thus, the deep well region 145 faces the body region 116 across a partial region of the SiC semiconductor layer 102 (drift region 115) in the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0710] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a depth position between the body region 116 and the deep well region 145 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0711] Even more specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a region in the SiC semiconductor layer 102 that is sandwiched between the body region 116 and the deep well region 145 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0712] The source electrode layer 147 may also have a stacked structure including a plurality of electrode layers. The source electrode layer 147 may also include a first electrode layer and a second electrode layer stacked in sequence from the SiC semiconductor layer 102 side.

[0713] The first electrode layer may also be a barrier electrode layer including a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may also have a stacked structure in which a Ti (titanium) film and a TiN (titanium nitride) film are stacked in sequence from the SiC semiconductor layer 102 side. The first electrode layer may also have a single-layer structure composed of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may contain aluminum or tungsten.

[0714] As described above, according to the semiconductor device 261, the same effects as those described for the semiconductor device 101 can be achieved. In addition, in the semiconductor device 261, when a reverse bias voltage is applied, current can preferentially flow into the Schottky barrier diode 265.

[0715] Thereby, the expansion of crystal defects of SiC in the SiC semiconductor layer 102 can be suppressed. As a result, an improvement in short-circuit withstand capacity, a reduction in the feedback capacitance Crss, and an increase in the on-resistance can be suppressed.

[0716] In this manner, an example in which a Schottky junction is formed between the source electrode layer 147 within the sidewall contact hole 264 of the source insulating layer 146 and the SiC semiconductor layer 102 has been described. However, a mode in which the source insulating layer 146 (the first part 262 and the second part 263) is not formed may also be employed.

[0717] Figure 30 is a cross-sectional view of a region corresponding to Figure 13 and is a cross-sectional view for explaining the structure of the semiconductor device 271 according to the 18th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 201, the same reference numerals are given and the description is omitted.

[0718] Refer to Figure 30 , the contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141. The source insulating layer 146 is formed along the inner wall surface of the source trench 141 in such a manner that the contact region 144 is selectively exposed from the bottom wall of the source trench 141.

[0719] More specifically, the source insulating layer 146 includes a first part 272 and a second part 273. The first part 272 covers the sidewall of the source trench 141. The second part 273 locally covers the bottom wall of the source trench 141.

[0720] The second part 273 is connected to the first part 272. The second part 273 extends along the bottom wall from the corner of the source trench 141 in such a manner that the central portion of the bottom wall of the source trench 141 is exposed. The second part 273 may also be formed to be continuous (ring-shaped) in plan view.

[0721] As described above, according to the semiconductor device 271, the same effects as those described for the semiconductor device 201 can be achieved. In addition, according to the semiconductor device 271, a pn junction is formed in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0722] Even if the depletion layer extends from the corner of the source trench 141 along the bottom wall from this pn junction, the distance at which the depletion layer reaches the source electrode layer 147 can be obtained through the source insulating layer 146. Thus, generation of punch-through can be suppressed in the vicinity of the corner of the source trench 141.

[0723] Figure 31 is a cross-sectional view of a region corresponding to Figure 13 and is a cross-sectional view for explaining the structure of the semiconductor device 281 according to the 19th embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 201, the same reference numerals are given and the description is omitted.

[0724] Reference Figure 31 An exposed portion 282 for selectively exposing the bottom wall of the source trench 141 is formed in the deep well region 145. The exposed portion 282 exposes the central portion of the bottom wall of the source trench 141.

[0725] In this embodiment, the source insulating layer 146 includes a first portion 283 and a second portion 284 . The first portion 283 covers the sidewalls of the source trench 141 , and the second portion 284 partially covers the bottom wall of the source trench 141 .

[0726] The second portion 284 is connected to the first portion 283. The second portion 284 extends from a corner portion of the source trench 141 along the bottom wall so as to expose the center portion of the bottom wall of the source trench 141. The second portion 284 may be formed in a shape without discontinuities (ring shape) in a plan view.

[0727] The source electrode layer 147 forms a heterojunction portion between the exposed portion 282 of the deep well region 145 and the SiC semiconductor layer 102. Thus, a heterojunction diode 285 is formed with the source electrode layer 147 as an anode and the SiC semiconductor layer 102 as a cathode. The source electrode layer 147 may include a conductive material other than polysilicon as long as the heterojunction diode 285 can be formed.

[0728] A body diode 286 is formed at a pn junction between the SiC semiconductor layer 102 and the body region 116 . The junction barrier of the heterojunction diode 285 is smaller than the diffusion potential of the body diode 286 .

[0729] The junction barrier of the heterojunction diode 285 may be 1.0 eV to 1.5 eV. The diffusion potential of the body diode 286 may be 2.8 eV to 3.2 eV.

[0730] As described above, the semiconductor device 281 can achieve the same effects as those described for the semiconductor device 201. In addition, in the semiconductor device 281, when a reverse bias voltage is applied, current can flow preferentially into the heterojunction diode 285.

[0731] This can suppress the expansion of SiC crystal defects in the SiC semiconductor layer 102. As a result, the short-circuit withstand capability can be improved and the feedback capacitance Crss can be reduced, and an increase in the on-resistance can be suppressed.

[0732] Figure 32 is with Figure 13 The cross-sectional views of the corresponding regions are used to describe the structure of the semiconductor device 291 according to the 20th embodiment of the present invention. Hereinafter, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals and description thereof is omitted.

[0733] Refer to Figure 32 ,the contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0734] The source insulating layer 146 has a stacked structure including a plurality of barrier forming layers formed along the inner wall of the source trench 141. In this manner, the source insulating layer 146 has a stacked structure including an insulating barrier forming layer 292 and a conductive barrier forming layer 293 stacked in sequence from the inner wall of the source trench 141.

[0735] The insulating barrier forming layer 292 may also contain at least one of impurity-free added silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0736] The insulating barrier forming layer 292 is formed in a film shape along the inner wall surface of the source trench 141 in such a manner that the contact region 144 is selectively exposed from the bottom wall of the source trench 141.

[0737] More specifically, the insulating barrier forming layer 292 includes a first portion 294 and a second portion 295. The first portion 294 covers the side wall of the source trench 141. The second portion 295 selectively covers the bottom wall of the source trench 141.

[0738] The second portion 295 is connected to the first portion 294. The second portion 295 extends along the bottom wall from the corner of the source trench 141 in such a manner that the central portion of the bottom wall of the source trench 141 is exposed.

[0739] The conductive barrier forming layer 293 may also contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier forming layer 293 contains a conductive material different from the conductive material of the source electrode layer 147.

[0740] The conductive barrier forming layer 293 is formed in a film shape along the insulating barrier forming layer 292 in such a manner that the contact region 144 is selectively exposed from the bottom wall of the source trench 141.

[0741] As described above, according to the semiconductor device 291, the same effects as those described for the semiconductor device 201 can be achieved. In addition, in the semiconductor device 291, the source insulating layer 146 has a stacked structure including an insulating barrier forming layer 292 and a conductive barrier forming layer 293. Thus, the generation of punch-through can be suppressed by these two layers, namely, the insulating barrier forming layer 292 and the conductive barrier forming layer 293.

[0742] Figure 33 is related to Figure 13A cross-sectional view of the corresponding region is a cross-sectional view for explaining the structure of the semiconductor device 301 according to the 21st embodiment of the present invention. Hereinafter, for the structures corresponding to those described for the semiconductor device 201, the same reference numerals are assigned and the description is omitted.

[0743] Refer to Figure 33 , the contact region 144 is formed in the deep well region 145 in a region along the bottom wall of the source trench 141. The contact region 144 is exposed from the bottom wall of the source trench 141.

[0744] The source insulating layer 146 includes a first portion 302 and a second portion 303. The first portion 302 covers the side walls of the source trench 141. The second portion 303 covers the bottom wall of the source trench 141.

[0745] The first portion 302 selectively has a sidewall contact hole 304 that exposes the SiC semiconductor layer 102 from the side walls of the source trench 141. The first portion 302 may also be formed to cross the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0746] The lower end (the end on the source trench 141 side) of the first portion 302 may be located on the bottom wall side of the source trench 141 with respect to the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 in the source trench 141.

[0747] The lower end of the first portion 302 may be located on the first main surface 103 side with respect to the bottom of the body region 116. The lower end of the first portion 302 may also be formed in a region between the bottom of the body region 116 and the bottom of the source region 126. In the above cases, the source electrode layer 147 is connected to at least the body region 116 in the source trench 141.

[0748] The lower end of the first portion 302 may also be formed in a region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may also have only the second portion 303 without the first portion 302. In the above cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 in the source trench 141.

[0749] The second portion 303 of the source insulating layer 146 is formed at an interval from the first portion 302 of the source insulating layer 146. That is, the second portion 303 is separated from the first portion 302. The second portion 303 may also cover the corners of the source trench 141.

[0750] The second part 303 may also expose the corners of the source trench 141. The second part 303 may also cover the corners of the source trench 141 and may also cover a part of the sidewalls of the source trench 141.

[0751] The source electrode layer 147 forms a Schottky junction within the source trench 141 and between the SiC semiconductor layer 102 (drift region 115). Thus, a Schottky barrier diode 305 is formed with the source electrode layer 147 as the anode and the SiC semiconductor layer 102 as the cathode.

[0752] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the bottom wall of the source trench 141. In this manner, the deep well region 145 is formed in the high-concentration region 112a of the SiC epitaxial layer 112. The entire region of the deep well region 145 is formed in the high-concentration region 112a.

[0753] The deep well region 145 may be continuously formed in the SiC semiconductor layer 102 in a region along the sidewalls and corners of the source trench 141 in such a manner that the source electrode layer 147 is exposed from the sidewalls of the source trench 141.

[0754] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the corners connecting the sidewalls and the bottom wall of the source trench 141. The deep well region 145 may also expose substantially the entire region of the sidewalls of the source trench 141 in the SiC semiconductor layer 102.

[0755] The deep well region 145 is led out from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. Thus, the deep well region 145 faces the main region 116 with a part of the SiC semiconductor layer 102 (drift region 115) interposed therebetween in the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0756] The deep well region 145 is led out from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. Thus, the deep well region 145 faces the main region 116 with a part of the SiC semiconductor layer 102 (drift region 115) interposed therebetween in the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0757] More specifically, the source electrode layer 147 forms a Schottky junction at a depth position between the main region 116 and the deep well region 145 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102 and between the SiC semiconductor layer 102 (drift region 115).

[0758] More specifically, the source electrode layer 147 forms a Schottky junction in the normal direction of the first main surface 103 of the SiC semiconductor layer 102, in a region where the SiC semiconductor layer 102 is sandwiched between the main region 116 and the deep well region 145, and between the SiC semiconductor layer 102 (drift region 115).

[0759] The source electrode layer 147 may also have a stacked structure including a plurality of electrode layers. The source electrode layer 147 may also include, in order from the SiC semiconductor layer 102 side, a stacked first electrode layer and second electrode layer.

[0760] The first electrode layer may also be a barrier electrode layer including a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may also have a stacked structure in which a Ti (titanium) film and a TiN (titanium nitride) film are stacked in order from the SiC semiconductor layer 102 side. The first electrode layer may also have a single-layer structure composed of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may also include aluminum or tungsten.

[0761] As described above, according to the semiconductor device 301, the same effects as those described for the semiconductor device 201 can be achieved. In addition, in the semiconductor device 301, when a reverse bias voltage is applied, current can preferentially flow into the Schottky barrier diode 305.

[0762] Thereby, the expansion of crystal defects of SiC in the SiC semiconductor layer 102 can be suppressed. As a result, an improvement in short-circuit withstand capacity, a reduction in the feedback capacitance Crss, and an increase in the on-resistance can be achieved.

[0763] In this embodiment, an example in which a Schottky junction is formed between the source electrode layer 147 in the sidewall contact hole 264 of the source insulating layer 146 and the SiC semiconductor layer 102 has been described. However, a method in which the source insulating layer 146 (the first part 302 and the second part 303) is not formed may also be adopted.

[0764] The 7th to 21st embodiments of the present invention have been described, but the 7th to 21st embodiments of the present invention can also be implemented in other ways.

[0765] In the above-described 7th to 21st embodiments, an example in which the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed by the epitaxial growth method has been described. However, the SiC epitaxial layer 112 can also be formed by the following process.

[0766] First, an SiC epitaxial layer 112 with a relatively low n-type impurity concentration is formed by epitaxial growth. Next, n-type impurities are introduced into the surface portion of the SiC epitaxial layer 112 by ion implantation. Thus, an SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b is formed.

[0767] In the above-described 7th to 21st embodiments, an example in which the SiC semiconductor layer 102 has a stacked structure including an SiC semiconductor substrate 111 and an SiC epitaxial layer 112 has been described. However, the SiC semiconductor layer 102 may have a single-layer structure composed of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may also have a single-layer structure composed of the SiC epitaxial layer 112.

[0768] In the above-described 7th to 21st embodiments, a structure in which the conductivity type of each semiconductor part is inverted may also be adopted. That is, the p-type part may be n-type, and the n-type part may be p-type.

[0769] In the above-described 7th to 21st embodiments, an example in which a gate electrode layer 132 and a gate wiring layer 133 including p-type polysilicon doped with p-type impurities are formed has been described. However, when an increase in the gate threshold voltage Vth is not emphasized, the gate electrode layer 132 and the gate wiring layer 133 may include n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0770] The low-resistance electrode layer 134 may also be formed by siliciding a part of the surface portion of the gate electrode layer 132 (n-type polysilicon) using a metal material. That is, the low-resistance electrode layer 134 may also include n-type polycrystal. In the case of this structure, a reduction in gate resistance can be achieved.

[0771] In the above-described 7th to 21st embodiments, the structure of the semiconductor device 221 may also be adopted. That is, in the above-described 7th to 21st embodiments, a p+-type SiC semiconductor substrate 222 may be used instead of the n+-type SiC semiconductor substrate 111. In this case, in the description of the 7th to 13th embodiments above, "source" is replaced with "emitter" and "drain" is replaced with "collector".

[0772] Figure 34 It is a top view of a semiconductor device 311 showing the 22nd embodiment of the present invention. Figure 35 is Figure 34 a bottom view of the semiconductor device 311 shown below. Hereinafter, for the structures corresponding to the structures described for the semiconductor device 101, the same reference numerals will be used for description.

[0773] Refer toFigure 34 , the semiconductor device 311 includes a SiC semiconductor layer 102 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may also contain a 4H-SiC single crystal.

[0774] The 4H-SiC single crystal has a tilt angle that is inclined from the

[0001] plane by an angle within 10° with respect to the [11-20] direction. The tilt angle may also be 0° or more and 4° or less. The tilt angle may also be greater than 0° and less than 4°. Typically, the tilt angle is set in the range of 2° or 4°, and more specifically, in the range of 2° ± 0.2° or 4° ± 0.4°.

[0775] In this embodiment, the SiC semiconductor layer 102 is formed in a rectangular plate shape. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrilateral shape (a rectangular shape in this embodiment) when viewed from above in the normal direction (hereinafter simply referred to as "viewed from above").

[0776] The side surface 105A is opposed to the side surface 105C. The side surface 105B is opposed to the side surface 105D. The four side surfaces 105A to 105D extend in a plane along the normal direction of the first main surface 103 and the second main surface 104, respectively. The length of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less), respectively.

[0777] In the SiC semiconductor layer 102, an active region 106 and an outer region 107 are set. The active region 106 is a region where a vertical MISFET is formed. The outer region 107 is a region outside the active region 106.

[0778] The active region 106 is set in the central portion of the SiC semiconductor layer 102 with a space from the side surfaces 105A to 105D of the SiC semiconductor layer 102 inward in a plan view. The active region 106 is set to have a quadrilateral shape (a rectangular shape in this embodiment) with four sides parallel to the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0779] The outer region 107 is set in the region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the periphery of the active region 106. The outer region 107 is set to surround the active region 106 without interruption (quadrilateral ring shape) in a plan view.

[0780] Above the first main surface 103 of the SiC semiconductor layer 102, a gate pad 108, gate fingers 109, and a source pad 110 are formed. The gate pad 108, the gate fingers 109, and the source pad 110 may also contain aluminum and / or copper.

[0781] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 is formed in the central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 may also be formed at the corner connecting any two of the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0782] The gate pad 108 is formed in a quadrilateral shape in a plan view. The gate pad 108 is led out from the outer region 107 into the active region 106 in a manner that crosses the boundary region between the outer region 107 and the active region 106.

[0783] The gate fingers 109 include outer gate fingers 109A and inner gate fingers 109B. The outer gate fingers 109A are led out from the gate pad 108 to the outer region 107. The outer gate fingers 109A extend in a strip shape in the outer region 107.

[0784] In this manner, the outer gate fingers 109A may also be formed along the three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 in a manner that divides the active region 106 from three directions.

[0785] The inner gate fingers 109B are led out from the gate pad 108 to the active region 106. The inner gate fingers 109B extend in a strip shape in the active region 106. The inner gate fingers 109B extend from the side surface 105A side toward the side surface 105C side.

[0786] The source pad 110 is formed in the active region 106 at an interval from the gate pad 108 and the gate fingers 109. The source pad 110 is formed in a C shape (an inverted C shape in Figure 34 ) in a plan view so as to cover the C-shaped (inverted C-shaped in Figure 34 ) region divided by the gate pad 108 and the gate fingers 109.

[0787] A gate voltage is applied to the gate pad 108 and the gate fingers 109. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 110. The source voltage may also be a reference voltage (for example, GND voltage).

[0788] Above the first main surface 103 of the SiC semiconductor layer 102 (more specifically, above the interlayer insulating layer 153), a resin layer 312 is formed. In Figure 34 For clarity, the resin layer 312 is shown by hatching. The resin layer 312 covers the gate pad 108, the gate fingers 109, and the source pad 110.

[0789] The resin layer 312 may also contain a negative or positive photosensitive resin. In this manner, the resin layer 312 contains polybenzoxazole as an example of a positive photosensitive resin. The resin layer 312 may also contain polyimide as an example of a negative photosensitive resin.

[0790] The peripheral portion of the resin layer 312 is formed at a distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 toward the inner region. Thus, the peripheral portion of the resin layer 312 exposes the first main surface 103 of the SiC semiconductor layer 102. More specifically, the peripheral portion of the resin layer 312 exposes the interlayer insulating layer 153.

[0791] A gate pad opening 313 and a source pad opening 314 are formed in the resin layer 312. The gate pad opening 313 exposes the gate pad 108. The source pad opening 314 exposes the source pad 110.

[0792] Referring to Figure 35 and Figure 35 In the enlarged views of, a bump group 316 including a plurality of bumps 315 is formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of bumps 315 are portions that protrude along the normal direction of the second main surface 104 of the SiC semiconductor layer 102 on the second main surface 104 of the SiC semiconductor layer 102.

[0793] The plurality of bumps 315 are formed at intervals in an arbitrary first direction X and a second direction Y intersecting the first direction X. The first direction X is one direction in the plane direction of the first main surface 103 of the SiC semiconductor layer 102.

[0794] In this manner, the first direction X is set to a direction parallel to the side surfaces 105B and 105D of the SiC semiconductor layer 102. More specifically, the second direction Y is a direction orthogonal to the first direction X. That is, in this manner, the second direction Y is set to a direction parallel to the side surfaces 105A and 105C of the SiC semiconductor layer 102.

[0795] The bump group 316 has a first portion 317 in which some of the plurality of bumps 315 overlap in the first direction X when viewed in the first direction when viewed from the first direction X.

[0796] In addition, the raised portion group 316 has a second portion 318 that is formed such that several of the plurality of raised portions 315 depart from the first portion 317 and overlap in the first direction X when viewed in the first direction.

[0797] The plurality of raised portions 315 are continuously formed along the first direction X. More specifically, the plurality of raised portions 315 have a distribution pattern that is spaced apart along the first direction X and the second direction Y.

[0798] The plurality of raised portions 315 maintain this distribution pattern and are continuously formed along the first direction X. In this manner, the plurality of raised portions 315 are formed from the periphery on one side surface 105A side of the SiC semiconductor layer 102 to the periphery on the other side surface 105C side in a plan view.

[0799] In the raised portion group 316, the distances between the plurality of raised portions 315 formed at intervals in the first direction X may also be different from each other. The distances between the plurality of raised portions 315 formed at intervals in the second direction Y in the raised portion group 316 may also be different from each other.

[0800] The plurality of raised portions 315 are each formed with an uneven shape, size, and thickness. The thickness of the raised portion 315 is the distance from the base to the top (front end portion) of the raised portion 315 in the normal direction of the second main surface 104 of the SiC semiconductor layer 102.

[0801] The plurality of raised portions 315 may each have a size greater than 0 μm and 10 μm or less. Each raised portion 315 may have a thickness of 500 nm or less (for example, 1 nm or more and 250 nm or less).

[0802] The raised portion group 316 is formed on the second main surface 104 of the SiC semiconductor layer 102 in a range narrower than the widths of the side surfaces 105A to 105D (in this manner, the side surfaces 105A and 105C) of the SiC semiconductor layer 102.

[0803] The raised portion group 316 is formed, for example, in a range of 1 / 1000 or more and 1 / 5 or less of the widths of the side surfaces 105A to 105D (in this manner, the side surfaces 105A and 105C) of the SiC semiconductor layer 102.

[0804] The raised portion group 316 may also be formed in a range of 1 / 200 or more and 1 / 10 or less of the widths of the side surfaces 105A to 105D (in this manner, the side surfaces 105A and 105C) of the SiC semiconductor layer 102.

[0805] The raised portion group 316 may also be formed in the range of 10 μm or more and 200 μm or less in the second direction Y. The raised portion group 316 may also be formed in the range of 50 μm or more and 150 μm or less in the second direction Y. The raised portion group 316 may also be formed in the range of 80 μm or more and 120 μm or less in the second direction Y.

[0806] The raised portion group 316 has a layout in which a plurality of raised portions 315 overlap in the first direction X when viewed in the first direction from the first direction X. Thus, the raised portion group 316 forms a raised portion group region 319 extending in a strip shape in the first direction X by a collective pattern of a plurality of raised portions 315 continuously distributed in the first direction X.

[0807] In other words, the raised portion group region 319 includes a plurality of raised portions 315 (raised portion group 316) formed in a strip-shaped region extending in the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0808] On the second main surface 104 of the SiC semiconductor layer 102, a plurality of raised portion groups 316 (raised portion group regions 319) having such a form are formed at intervals in the second direction Y.

[0809] That is, the distribution pattern of the plurality of raised portions 315 is intermittently formed when viewed in the second direction from the second direction Y. The distance between the plurality of raised portion groups 316 may also have a value of 1% or more and 25% or less of the range in which the raised portion group 316 is formed.

[0810] In the second direction Y, the distance between the plurality of adjacent raised portion groups 316 may also be 100 μm or less. The distance between the plurality of raised portion groups 316 may also be 5 μm or more and 50 μm or less. The distance between the plurality of raised portion groups 316 may also be 20 μm or less.

[0811] The first direction X may also be set to the [11 - 20] direction, and the second direction Y may also be set to the [1 - 100] direction. That is, the raised portion group 316 may also form a strip-shaped raised portion group region 319 extending substantially parallel or parallel to the [11 - 20] direction, and a plurality of them are formed at intervals along the [1 - 100] direction.

[0812] The first direction X may also be set to the [1 - 100] direction, and the second direction Y may also be set to the [11 - 20] direction. That is, the raised portion group 316 may also form a strip-shaped raised portion group region 319 extending substantially parallel or parallel to the [1 - 100] direction, and a plurality of them are formed at intervals along the [11 - 20] direction.

[0813] In the region between the groups of projections 316 adjacent to each other in the second main surface 104 of the SiC semiconductor layer 102 in the second direction Y, a space 320 is demarcated in which there is no distribution pattern formed by a plurality of projections 315.

[0814] The space 320 is divided by the groups of projections 316 (projection group regions 319) adjacent to each other into strips extending parallel to the first direction X. Thus, on the second main surface 104 of the SiC semiconductor layer 102, a striped pattern is formed in which the groups of projections 316 and the space 320 are alternately formed in the second direction Y.

[0815] A plurality of grooves 321 are formed in the second main surface 104 of the SiC semiconductor layer 102. In Figure 35 and Figure 35 the enlarged view, the grooves 321 are shown by lines. The grooves 321 are formed in the groups of projections 316 and the space 320.

[0816] The plurality of grooves 321 include grinding marks generated by grinding the second wafer main surface 333 of a SiC semiconductor wafer 331 described later. Therefore, the direction in which the grooves 321 extend varies depending on the position where the SiC semiconductor layer 102 is cut out from the SiC semiconductor wafer 331.

[0817] The grooves 321 may extend substantially parallel or parallel to each group of projections 316. The grooves 321 may also include portions that cross the groups of projections 316. The grooves 321 may extend in a direction that crosses or is orthogonal to each group of projections 316. The grooves 321 may extend linearly or in an arc shape.

[0818] Several of the plurality of projections 315 included in each group of projections 316 are formed at intervals along the grooves 321. That is, each group of projections 316 includes a third portion 322 in which several of the plurality of projections 315 are formed at intervals along the grooves 321 in a top view.

[0819] Each group of projections 316 is formed, for example, by an annealing treatment method. The plurality of projections 315 may also be laser processing marks formed by a laser annealing treatment method.

[0820] The plurality of projections 315 (the third portion 322 of the projection group 316) along the grooves 321 may also be formed by an annealing treatment method for the unevenness demarcated by the grooves 321 in the second main surface 104 of the SiC semiconductor layer 102 (the second wafer main surface 333 of the SiC semiconductor wafer 331).

[0821] As Figures 36A to 36D shown, each group of projections 316 can be formed in various ways by adjusting the annealing treatment conditions (here, the laser annealing treatment conditions).

[0822] Figure 36A This is a diagram showing the second exemplary form of each raised portion group 316.

[0823] As Figure 36A shown, the raised portion group 316 may also include a convex curved raised portion 315 that extends in the first direction X in a plan view and protrudes in the second direction Y (toward the side 105B side in Figure 36A ). The raised portion 315 may also be formed by a plurality of overlapping raised portions 315.

[0824] The distance between the two points with the maximum distance in the raised portion 315 may also be 1 μm or more and 200 μm or less (about 50 μm in this exemplary form). In the first direction X, the distance between a plurality of adjacent raised portions 315 is set to a value of 10% or more of the size of the raised portion 315. The plurality of raised portions 315 are formed by staggering the laser irradiation positions adjacent to each other in the first direction X.

[0825] Figure 36B This is a diagram showing the third exemplary form of the raised portion group 316.

[0826] As Figure 36B shown, the raised portion group 316 may also include a concave curved raised portion 315 that extends in the second direction Y in a plan view and is recessed in the first direction X. The raised portion 315 may also be formed by a plurality of overlapping raised portions 315.

[0827] The distance between the two points with the maximum distance in each raised portion 315 may also be 1 μm or more and 200 μm or less (about 50 μm in this exemplary form). The plurality of raised portions 315 are formed by overlapping the laser irradiation positions adjacent to each other within a range of 50% or more and 70% or less.

[0828] Figure 36C This is a diagram showing the fourth exemplary form of the raised portion group 316.

[0829] As Figure 36C shown, the raised portion group 316 may also include a linear raised portion 315 that extends in the second direction Y in a plan view and is recessed in the first direction X. The raised portion 315 may also have a protruding portion that protrudes in the first direction X. The raised portion 315 may also be formed by a plurality of overlapping raised portions 315.

[0830] The distance between the two points with the maximum distance in the raised portion 315 may also be 1 μm or more and 200 μm or less (about 50 μm in this exemplary form). The plurality of raised portions 315 are formed by overlapping the laser irradiation positions adjacent to each other within a range of 70% or more and 90% or less.

[0831] Figure 36DThis is a diagram showing the fifth exemplary embodiment of the raised portion group 316.

[0832] As Figure 36D shown, the raised portion group 316 may also have a layout in which raised portion rows including a plurality of raised portions 315 arranged at intervals along the second direction Y are formed at intervals along the first direction X.

[0833] The distance between the two points with the farthest distance among the raised portions 315 may also be 1 μm or more and 200 μm or less (about 5 μm in this exemplary embodiment). The plurality of raised portions 315 are formed by overlapping the laser irradiation positions adjacent to each other within a range of 90% or more and less than 100%.

[0834] Figure 37 This is Figure 34 an enlarged view of the region XXXVII shown in the figure, and is a diagram in which the structure above the first main surface 103 of the SiC semiconductor layer 102 is removed. Figure 38 This is Figure 37 a cross-sectional view taken along line XXXVIII-XXXVIII. Figure 39 This is Figure 37 a cross-sectional view taken along line XXXIX-XXXIX. Figure 40 This is Figure 39 an enlarged view of the region XL shown in the figure.

[0835] Referring to Figures 37 to 39 , the semiconductor device 311 has the same planar structure and cross-sectional structure as the semiconductor device 101, except that the raised portion group 316 is formed on the second main surface 104 of the SiC semiconductor layer 102.

[0836] Referring to Figure 40 , the raised portion group 316 (a plurality of raised portions 315) and the groove 321 are formed in the SiC semiconductor substrate 111. A modified layer 323 in which a part of the SiC of the SiC semiconductor layer 102 (SiC semiconductor substrate 111) is modified to other properties is formed in the surface layer portion of the second main surface 104 of the SiC semiconductor layer 102. The modified layer 323 is formed by an annealing treatment method for the second main surface 104 of the SiC semiconductor layer 102.

[0837] The modified layer 323 contains Si atoms and C atoms. More specifically, the modified layer 323 has a carbon density lower than that of the region outside the modified layer 323 in the SiC semiconductor layer 102 (SiC semiconductor substrate 111).

[0838] In addition, the modified layer 323 has a silicon density higher than the carbon density. That is, the modified layer 323 includes a Si modified layer in which the SiC of the SiC semiconductor layer 102 (SiC semiconductor substrate 111) is modified to Si. The Si modified layer may also be a Si amorphous layer.

[0839] The modified layer 323 may also include lattice defects caused by the modification of SiC. That is, the modified layer 323 may also include a lattice defect region having a defect energy level introduced due to the modification of SiC.

[0840] In this manner, the modified layer 323 is formed in a region along the bump group 316 on the surface layer portion of the second main surface 104 of the SiC semiconductor layer 102. Thus, in each bump group 316, a plurality of bumps 315 are formed by the modified layer 323.

[0841] In this manner, the modified layer 323 further extends from the bump group 316 toward the space 320. That is, the annealing treatment method for the second main surface 104 of the SiC semiconductor layer 102 reaches the space 320.

[0842] The thickness of the portion along the bump group 316 in the modified layer 323 becomes greater than or equal to the thickness of the portion along the space 320 in the modified layer 323 due to the presence of the bumps 315. More specifically, the thickness of the portion along the bump group 316 in the modified layer 323 is greater than the thickness of the portion along the space 320 in the modified layer 323.

[0843] The thickness of the modified layer 323 may be 1 nm or more and 1000 nm or less. The thickness Ta of the region in the modified layer 323 where the bumps 315 are formed may be 50 nm or more and 1000 nm or less. The thickness Tb of the region outside the bumps 315 in the modified layer 323 may be 1 nm or more and 300 nm or less.

[0844] The thickness Ta may be 50 nm or more and 100 nm or less. The thickness Ta may be 100 nm or more and 150 nm or less. The thickness Ta may be 150 nm or more and 200 nm or less. The thickness Ta may be 200 nm or more and 250 nm or less.

[0845] The thickness Ta may be 250 nm or more and 300 nm or less. The thickness Ta may be 300 nm or more and 350 nm or less. The thickness Ta may be 350 nm or more and 400 nm or less. The thickness Ta may be 400 nm or more and 450 nm or less. The thickness Ta may be 450 nm or more and 500 nm or less.

[0846] The thickness Ta may be 500 nm or more and 600 nm or less. The thickness Ta may be 600 nm or more and 700 nm or less. The thickness Ta may be 700 nm or more and 800 nm or less. The thickness Ta may be 800 nm or more and 900 nm or less. The thickness Ta may be 900 nm or more and 1000 nm or less.

[0847] The thickness Tb can also be 1 nm or more and 10 nm or less. The thickness Tb can also be 10 nm or more and 50 nm or less. The thickness Tb can also be 50 nm or more and 100 nm or less.

[0848] The thickness Tb can also be 100 nm or more and 150 nm or less. The thickness Tb can also be 150 nm or more and 200 nm or less. The thickness Tb can also be 200 nm or more and 250 nm or less. The thickness Tb can also be 250 nm or more and 300 nm or less.

[0849] The thickness Tb can also be 1 / 2 or less, 1 / 3 or less, 1 / 4 or less, 1 / 5 or less, 1 / 6 or less, 1 / 7 or less, 1 / 8 or less, 1 / 9 or less, 1 / 10 or less, 1 / 11 or less, 1 / 12 or less, 1 / 13 or less, 1 / 14 or less, 1 / 15 or less, 1 / 16 or less, 1 / 17 or less, 1 / 18 or less, 1 / 19 or less, or 1 / 20 or less of the thickness Ta.

[0850] The resistance value of the second main surface 104 in the case where the raised portion group 316 does not exist on the second main surface 104 of the SiC semiconductor layer 102 is larger than the resistance value of the second main surface 104 in the case where the raised portion group 316 exists on the second main surface 104 of the SiC semiconductor layer 102.

[0851] That is, as an electrical property, the plurality of raised portion groups 316 have a resistance value equal to or less than the resistance value of a single SiC crystal. More specifically, the plurality of raised portion groups 316 have a resistance value smaller than the resistance value of a single SiC crystal.

[0852] In addition, the plurality of raised portion groups 316 have a resistance value equal to or less than the resistance value of the space 320. More specifically, the plurality of raised portion groups 316 have a resistance value smaller than the resistance value of the space 320.

[0853] The resistance value of the raised portion group 316 is reduced by the modified layer 323. That is, the resistance value of the raised portion group 316 becomes equal to or less than the resistance value of a SiC single crystal due to the modified layer 323 obtained by modifying the properties of SiC. In addition, the resistance value of the space 320 is also reduced by the modified layer 323.

[0854] In this mode, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the raised portion group 316 on the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the plurality of raised portion groups 316 together.

[0855] The drain pad 113 is formed in a film shape by imitating the outer surface of the protrusion group 316 (the outer surfaces of the plurality of protrusions 315) and the inner surface of the groove 321. Thus, on the outer surface of the drain pad 113, a protrusion 113a that bulges in a direction away from the second main surface 104 is formed at a portion covering the protrusion group 316 (the plurality of protrusions 315). In addition, at a portion of the outer surface of the drain pad 113 covering the groove 321, a recess 113b that is recessed toward the second main surface 104 is formed.

[0856] The drain pad 113 forms an ohmic contact between the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the protrusion group 316.

[0857] More specifically, the drain pad 113 forms an ohmic contact with the plurality of protrusion groups 316. In addition, in this manner, the drain pad 113 also forms an ohmic contact with the space 320.

[0858] The drain pad 113 has a stacked structure including a plurality of electrode layers stacked on the second main surface 104 of the SiC semiconductor layer 102. In this manner, the drain pad 113 has a four-layer structure including a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 that are sequentially stacked from the second main surface 104 of the SiC semiconductor layer 102.

[0859] The Ti layer 324, the Ni layer 325, the Au layer 326, and the Ag layer 327 are each formed in a film shape by imitating the outer surface of the protrusion group 316 (the outer surfaces of the plurality of protrusions 315) and the inner surface of the groove 321. The protrusion 113a and the recess 113b of the drain pad 113 are formed on the outer surface of the Ag layer 327.

[0860] The Ti layer 324 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ti layer 324 covers the plurality of protrusion groups 316 together and forms an ohmic contact between the second main surface 104 of the SiC semiconductor layer 102. In this manner, the Ti layer 324 also forms an ohmic contact with the space 320.

[0861] The Ni layer 325 covers substantially the entire region or the entire region of the Ti layer 324. The Au layer 326 covers substantially the entire region or the entire region of the Ni layer 325. The Ag layer 327 covers substantially the entire region or the entire region of the Au layer 326.

[0862] The thickness of the Ti layer 324 may be 0.01 μm or more and 5 μm or less (for example, about 0.07 μm). The thickness of the Ni layer 325 may be 0.1 μm or more and 40 μm or less (for example, about 1.2 μm).

[0863] The thickness of the Au layer 326 may be 0.1 μm or more and 40 μm or less (for example, about 0.07 μm). The thickness of the Ag layer 327 may also be 0.1 μm or more and 40 μm or less (for example, about 0.3 μm). Of course, the drain pad 113 may also have a single-layer structure composed of the Ti layer 324, the Ni layer 325, the Au layer 326, or the Ag layer 327.

[0864] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without passing through a silicide layer containing a silicide as a main component. The drain pad 113 forms an ohmic contact with each group of protrusions 316 without passing through a silicide layer containing a silicide as a main component.

[0865] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without passing through a carbon layer containing carbon as a main component. The drain pad 113 forms an ohmic contact with each group of protrusions 316 without passing through a carbon layer containing carbon as a main component.

[0866] The drain pad 113 does not include a region formed in a layered form of a material containing a silicide as a main component. In addition, the drain pad 113 does not include a region formed in a layered form of a material containing carbon as a main component.

[0867] Figure 41A It represents Figure 34 A top view of the SiC semiconductor wafer 331 used in the manufacture of the semiconductor device 311 shown. Figure 41B It is Figure 41A A bottom view of the SiC semiconductor wafer 331 shown, and is a view showing a state after a grinding process and an annealing process with respect to the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0868] Refer to Figure 41A and Figure 41B , the SiC semiconductor wafer 331 is composed of a plate-like SiC single crystal formed in a disk shape. The SiC semiconductor wafer 331 serves as a base for the SiC semiconductor substrate 111.

[0869] The SiC semiconductor wafer 331 has a first wafer main surface 332 on one side, a second wafer main surface 333 on the other side, and a wafer side surface 334 connecting the first wafer main surface 332 and the second wafer main surface 333.

[0870] The SiC semiconductor wafer 331 may also contain a 4H-SiC single crystal. The first wafer main surface 332 of the SiC semiconductor wafer 331 has an inclination angle within 10° from the (0001) plane with respect to the [11-20] direction.

[0871] The declination angle can also be 0° or more and 4° or less. The declination angle can also be greater than 0° and less than 4°. Typically, the declination angle is set within the range of 2° or 4°. More specifically, it is set within the range of 2° ± 0.2° or 4° ± 0.4°.

[0872] On the wafer side surface 334 of the SiC semiconductor wafer 331, one or more (in this case, one) orientation planes 335 indicating the crystal orientation are formed. The orientation plane 335 is a cut portion formed on the periphery of the SiC semiconductor wafer 331. In this case, the orientation plane 335 extends linearly along the [11 - 20] direction.

[0873] The first wafer main surface 332 is an element formation surface on which MISFETs are formed. A plurality of device formation regions 336 corresponding to the semiconductor device 311 are set on the first wafer main surface 332.

[0874] In this case, the plurality of device formation regions 336 are arranged in a row and column pattern along the [11 - 20] direction ([ - 1 - 120] direction) and the [ - 1100] direction ([1 - 100] direction).

[0875] The lattice - shaped regions that divide the plurality of device formation regions 336 are scribe lines 337. The semiconductor device 311 is cut out by cutting the SiC semiconductor wafer 331 along the periphery of the plurality of device formation regions 336 (scribe lines 337).

[0876] Refer to Figure 41B , in the state after the polishing process and annealing treatment with respect to the second wafer main surface 333 of the SiC semiconductor wafer 331, a plurality of raised portion groups 316 and a plurality of polishing marks 338 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0877] The plurality of raised portion groups 316 are formed in a stripe shape that is substantially parallel or parallel to the orientation plane 335. The plurality of raised portion groups 316 can also be formed in a stripe shape that intersects or is orthogonal to the orientation plane 335.

[0878] The plurality of polishing marks 338 each extend in an arc shape from the central portion of the SiC semiconductor wafer 331 toward the peripheral portion. The plurality of polishing marks 338 substantially include polishing marks 338 that intersect the [11 - 20] direction and the [1 - 100] direction.

[0879] In addition, the plurality of polishing marks 338 include polishing marks 338 that extend substantially parallel or parallel to the [11 - 20] direction or the [1 - 100] direction at a portion where the tangent of the arc is along the [11 - 20] direction or the [1 - 100] direction. The groove 321 formed on the second main surface 104 of the SiC semiconductor layer 102 can also be formed by a part of the polishing marks 338.

[0880] Figure 42 is a flowchart showing an example of a method for manufacturing the semiconductor device 311 shown Figure 34 below. Figures 43A to 43I is applicable to an explanatory Figure 34 cross-sectional view of the method for manufacturing the semiconductor device 311 shown

[0881] In the method for manufacturing the semiconductor device 311, before the step of forming the drain pad 113 in the method for manufacturing the semiconductor device 101 (see Figure 17L ), a processing step of the second main surface 333 of the wafer is performed. The processing step of the second main surface 333 of the wafer may also be performed after the steps of forming the gate pad 108, the gate fingers 109, and the source pad 110.

[0882] See Figure 43A , first, perform the Figures 17A to 17L step to prepare the SiC semiconductor wafer 331 on which the MISFET is fabricated on the first main surface 332. The second main surface 333 of the SiC semiconductor wafer 331 is in an untreated state.

[0883] Next, see Figure 43B , grind the second main surface 333 of the SiC semiconductor wafer 331 ( Figure 42 step S1). In this step, the second main surface 333 of the SiC semiconductor wafer 331 is ground using abrasive grains having a particle size of 500 or more.

[0884] The particle size of the abrasive grains is preferably 1000 or more and 5000 or less. As a result, a plurality of grinding marks 338 are formed on the second main surface 333 of the SiC semiconductor wafer 331 (also see Figure 41B simultaneously). In addition, as a result, while the second main surface 333 of the SiC semiconductor wafer 331 is planarized, the SiC semiconductor wafer 331 becomes thinner.

[0885] Next, see Figure 43C , a metal layer 341 is formed on the second main surface 333 of the SiC semiconductor wafer 331 ( Figure 42 step S2). In this method, the metal layer 341 is composed of a Ni layer. The Ni layer may also be formed by sputtering. The thickness of the Ni layer may be or more and or less.

[0886] Next, see Figure 43D , perform an annealing treatment on the second main surface 333 of the SiC semiconductor wafer 331 ( Figure 42Step S3). In this process, a laser annealing treatment method, which is an example of an annealing treatment method, is implemented.

[0887] In the laser annealing treatment method, a pulsed laser having a laser diameter of 50 μm or more and 200 μm (for example, about 100 μm) is used. The pulsed laser is a UV laser having a wavelength in the ultraviolet region. The energy of the pulsed laser can also be 1.0 J / cm 2 or more and 4.0 J / cm 2 or less (for example, about 3.0 J / cm 2 or so).

[0888] The pulsed laser enters the second main surface 333 of the SiC semiconductor wafer 331 through the metal layer 341. In this manner, the pulsed laser enters the second main surface 333 of the SiC semiconductor wafer 331 while moving the irradiation position along the orientation plane 335.

[0889] On the second main surface 333 of the SiC semiconductor wafer 331 and in the region where the pulsed laser enters, one or more protrusions 315 are formed on the second main surface 333 of the SiC semiconductor wafer 331.

[0890] In addition, on the second main surface 333 of the SiC semiconductor wafer 331 and in the region where the pulsed laser enters, a modified layer 323 in which the SiC of the SiC semiconductor wafer 331 is modified to other properties is formed. More specifically, the SiC of the SiC semiconductor wafer 331 is modified to Si by heating to cause C atoms to detach from and / or sublime from the SiC.

[0891] Thereby, a modified layer 323 including an Si modified layer is formed. The modified layer 323 may also include a silicon amorphous layer. The modified layer 323 may also include C atoms. One or more protrusions 315 formed on the second main surface 333 may also be formed of the modified layer 323.

[0892] Moreover, the pulsed laser continuously enters in the direction along the orientation plane 335, and a plurality of protrusions 315 are formed along the orientation plane 335. Thereby, a protrusion group 316 including a plurality of protrusions 315 and extending in the [11-20] direction is formed on the second main surface 333 of the SiC semiconductor wafer 331.

[0893] When one protrusion group 316 is formed, the irradiation position of the pulsed laser moves in the [1-100] direction. Then, the pulsed laser enters the second main surface 333 of the SiC semiconductor wafer 331 again while moving the irradiation position along the orientation plane 335.

[0894] Thus, another set of raised portions 316 that extends substantially parallel or parallel to one set of raised portions 316 is formed on the second main surface 333 of the SiC semiconductor wafer 331.

[0895] In the laser annealing treatment method, such a process is repeated until a plurality of sets of raised portions 316 are formed over substantially the entire area or the entire area of the second main surface 333 of the SiC semiconductor wafer 331 (also refer to Figure 41B ).

[0896] In this method, the metal layer 341 that has undergone the laser annealing treatment method has a laminated structure including a carbon layer 342, a NiSi (nickel silicide) layer 343, and a Ni layer 344 laminated in sequence from the second main surface 333 side of the SiC semiconductor wafer 331.

[0897] That is, the laser annealing treatment method includes a process of reacting the metal layer 341 with the SiC semiconductor wafer 331 to form silicide. More specifically, the laser annealing treatment method includes a process of forming the NiSi layer 343.

[0898] In the laser annealing treatment method, in addition to the NiSi layer 343, a carbon layer 342 containing C atoms is also formed as a by-product within the metal layer 341. The carbon layer 342 is formed by the precipitation of C atoms constituting SiC.

[0899] In the metal layer 341, the carbon layer 342 and the NiSi layer 343 can become the starting points for peeling. That is, although the metal layer 341 can be used as the drain pad 113 as it is, there are problems of poor connection and an increase in resistance value due to the poor connection in the metal layer 341. Therefore, it is preferable to form a metal layer different from the preferred metal layer 341 as the drain pad 113.

[0900] The temperature given to the metal layer 341 with the formation of the NiSi layer 343 is above the melting point of the gate pad 108, the gate fingers 109, and the source pad 110 (for example, 1000° or higher).

[0901] According to the laser annealing treatment method, the temperature of the second main surface 333 of the SiC semiconductor wafer 331 can be locally increased, so it is not necessary to heat the gate pad 108, the gate fingers 109, and the source pad 110. Therefore, melting of the gate pad 108, the gate fingers 109, and the source pad 110 can be appropriately suppressed.

[0902] Next, refer to Figure 43E , and perform the removal process of the metal layer 341. The removal process of the metal layer 341 is carried out until the second main surface 333 of the SiC semiconductor wafer 331 is exposed.

[0903] In this process, first, the NiSi layer 343 and the Ni layer 344 in the metal layer 341 are removed ( Figure 42 step S4). The NiSi layer 343 and the Ni layer 344 can also be removed by a wet etching method.

[0904] Next, referring to Figure 43F , the carbon layer 342 in the metal layer 341 is removed ( Figure 42 step S5). The carbon layer 342 can also be removed by a dry etching method.

[0905] Next, referring to Figure 43G , the residues of the NiSi layer 343 and the Ni layer 344 attached to the second main wafer surface 333 of the SiC semiconductor wafer 331 are removed ( Figure 42 step S6). The NiSi layer 343 and the Ni layer 344 can also be removed by a wet etching method.

[0906] Next, referring to Figure 43H , the residue of the carbon layer 342 attached to the second main wafer surface 333 of the SiC semiconductor wafer 331 is removed ( Figure 42 step S7). The carbon layer 342 can also be removed by a dry etching method.

[0907] Next, the native oxide film is removed from the second main wafer surface 333 of the SiC semiconductor wafer 331 ( Figure 42 step S8). The native oxide film can also be removed by a wet etching method.

[0908] In this way, in this method, the removal process of the Ni-containing layer (NiSi layer 343 and Ni layer 344) and the removal process of the carbon-containing layer (carbon layer 342) are repeated twice.

[0909] Thereby, the metal layer 341 can be appropriately removed. In addition, after the removal process of the metal layer 341, the second main wafer surface 333 of the SiC semiconductor wafer 331 whose resistance value has been reduced by laser annealing treatment is appropriately exposed.

[0910] Next, referring to Figure 43I , a drain pad 113 is formed on the second main wafer surface 333 of the SiC semiconductor wafer 331 ( Figure 42 step S9).

[0911] This process includes the process of sequentially forming a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 on the second main wafer surface 333 of the SiC semiconductor wafer 331. The Ti layer 324, the Ni layer 325, the Au layer 326, and the Ag layer 327 can all be formed by a sputtering method.

[0912] In the drain pad 113, the Ti layer 324 is directly connected to the second main surface 333 of the SiC semiconductor wafer 331. The Ti layer 324 also covers a plurality of groups of protrusions 316, and an ohmic contact is formed between the plurality of groups of protrusions 316 and between the plurality of spaces 320.

[0913] Next, the SiC semiconductor wafer 331 is cut along the periphery (cutting line 337) of the plurality of device formation regions 336. Thereby, a plurality of semiconductor devices 311 are cut out from the SiC semiconductor wafer 331. Through the process including the above processes, the semiconductor device 311 is manufactured.

[0914] As described above, according to the semiconductor device 311, the same effects as those described for the semiconductor device 101 can be achieved. In addition, the semiconductor device 311 can increase the connection area of the drain pad 113 with respect to the second main surface 104 of the SiC semiconductor layer 102 through the group of protrusions 316. Thereby, the electrical characteristics can be improved.

[0915] More specifically, an ohmic contact is formed between the drain pad 113 and the group of protrusions 316. Thereby, good ohmic characteristics can be obtained between the SiC semiconductor layer 102 and the drain pad 113, and thus the electrical characteristics can be improved.

[0916] In addition, according to the semiconductor device 311, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. More specifically, an ohmic contact is formed between the drain pad 113 and the group of protrusions 316 without passing through a carbon layer. In addition, an ohmic contact is formed between the drain pad 113 and the group of protrusions 316 without passing through a silicide layer.

[0917] The carbon layer and the silicide layer are likely to be the starting points of peeling. Therefore, with the structure in which the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102, it is possible to appropriately suppress connection failure or an increase in the resistance value caused by connection failure.

[0918] Figure 44 Is corresponding to Figure 35 The corresponding bottom view is a bottom view showing the semiconductor device 351 according to the 23rd embodiment of the present invention. Hereinafter, the structures corresponding to the structures described for the semiconductor device 311 are denoted by the same reference numerals and the description thereof is omitted.

[0919] Refer to Figure 44 , the semiconductor device 351 has a plurality of groups of protrusions 316 including a first group of protrusions 316A and a second group of protrusions 316B.

[0920] The first raised portion group 316A includes a plurality of first raised portions 315A formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of first raised portions 315A are portions that protrude in the normal direction of the second main surface 104 of the SiC semiconductor layer 102 along the second main surface 104 of the SiC semiconductor layer 102.

[0921] The plurality of first raised portions 315A are formed at intervals from each other along the first direction X and the second direction Y that intersects the first direction X. The first raised portion 315A has a first portion 317A, which is a portion where several of the plurality of first raised portions 315A overlap in the first direction X when viewed in the first direction from the first direction X.

[0922] In addition, the first raised portion 315A has a second portion 318A, which is a portion where several of the plurality of first raised portions 315A are separated from the first portion 317A and overlap in the first direction X when viewed in the first direction.

[0923] The plurality of first raised portions 315A are formed continuously along the first direction X. More specifically, the plurality of first raised portions 315A have a distribution pattern that is distributed at intervals along the first direction X and the second direction Y.

[0924] The plurality of first raised portions 315A maintain this distribution pattern and are formed continuously along the first direction X. In this manner, the distribution pattern of the plurality of first raised portions 315A is formed from the peripheral edge on one side surface 105A side to the peripheral edge on the other side surface 105C side of the SiC semiconductor layer 102 in a plan view.

[0925] When viewed from the first direction X, the first raised portion group 316A has a layout in which a plurality of raised portions 315 overlap in the first direction X. Thus, the first raised portion group 316A is formed by a collective pattern of a plurality of raised portions 315 that are continuously distributed along the first direction X to form a first raised portion group region 319A that extends in a band shape along the first direction X.

[0926] In other words, the first raised portion group region 319A includes a plurality of first raised portions 315A (first raised portion group 316A) formed in a band-shaped region that extends along the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0927] The second raised portion group 316B includes a plurality of second raised portions 315B formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of second raised portions 315B are portions that protrude in the normal direction of the second main surface 104 of the SiC semiconductor layer 102 along the second main surface 104 of the SiC semiconductor layer 102.

[0928] A plurality of second protrusions 315B are formed at intervals in the first direction X and the second direction Y intersecting the first direction X. The second protrusion group 316B has a first portion 317B which is a portion where several of the plurality of second protrusions 315B overlap in the second direction Y when viewed in the second direction Y.

[0929] In addition, the second protrusion group 316B has a second portion 318B which is formed separately from the first portion 317B by several of the plurality of second protrusions 315B and overlaps in the second direction Y when viewed in the second direction Y.

[0930] A plurality of second protrusions 315B are formed continuously in the second direction Y. More specifically, the plurality of second protrusions 315B have a distribution pattern distributed at intervals in the first direction X and the second direction Y.

[0931] The plurality of second protrusions 315B maintain this distribution pattern and are formed continuously in the second direction Y. In this manner, the distribution pattern of the plurality of second protrusions 315B is formed from the periphery on one side surface 105B side to the periphery on the other side surface 105D side of the SiC semiconductor layer 102 in a plan view.

[0932] When viewed in the second direction Y, the second protrusion group 316B has a layout in which a plurality of second protrusions 315B overlap in the second direction Y. Thus, the second protrusion group 316B is formed by a collective pattern of a plurality of second protrusions 315B continuously distributed in the second direction Y into a second protrusion group region 319B extending in a band shape in the second direction Y.

[0933] In other words, the second protrusion group region 319B includes a plurality of second protrusions 315B (second protrusion group 316B) formed in a band-shaped region extending in the second direction Y on the second main surface 104 of the SiC semiconductor layer 102.

[0934] The second protrusion group 316B (second protrusion group region 319B) crosses the first protrusion group 316A (first protrusion group region 319A). Thus, a crossing region 352 where the first protrusion group 316A (first protrusion group region 319A) and the second protrusion group 316B (second protrusion group region 319B) cross each other is formed on the second main surface 104 of the SiC semiconductor layer 102.

[0935] In this manner, a plurality of first protrusion groups 316A are formed at intervals in the second direction Y on the second main surface 104 of the SiC semiconductor layer 102. That is, the distribution pattern of the plurality of first protrusions 315A is formed intermittently with respect to the second direction Y.

[0936] Further, in this method, a plurality of second protrusion groups 316B are formed at intervals in the first direction X on the second main surface 104 of the SiC semiconductor layer 102. That is, the distribution pattern of the plurality of second protrusions 315B is formed intermittently with respect to the first direction X.

[0937] Therefore, in this method, the crossing regions 352 are formed in a row-like arrangement with intervals from each other in the first direction X and the second direction Y. Further, a space 320 is defined by the first protrusion group 316A and the second protrusion group 316B. The space 320 is formed in a row-like arrangement with intervals from each other in the first direction X and the second direction Y.

[0938] In the crossing regions 352, the plurality of first protrusions 315A and the plurality of second protrusions 315B may also overlap each other. The thicknesses of the plurality of first protrusions 315A and the plurality of second protrusions 315B formed in the crossing regions 352 may also be larger than the thicknesses of the first protrusions 315A and the second protrusions 315B formed in the regions outside the crossing regions 352.

[0939] Further, the number of the plurality of first protrusions 315A and the plurality of second protrusions 315B formed in the crossing regions 352 may also be larger than the number of the first protrusions 315A and the second protrusions 315B formed in the regions outside the crossing regions 352.

[0940] The first direction X may also be set to the [11 - 20] direction, and the second direction Y may also be set to the [1 - 100] direction. That is, the first protrusion group 316A (the first protrusion group region 319A) may be formed substantially parallel or parallel to the [11 - 20] direction, and the second protrusion group 316B (the second protrusion group region 319B) may be formed substantially parallel or parallel to the [1 - 100] direction.

[0941] The first direction X may also be set to the [1 - 100] direction, and the second direction Y may also be set to the [11 - 20] direction. That is, the first protrusion group 316A (the first protrusion group region 319A) is formed substantially parallel or parallel to the [1 - 100] direction, and the second protrusion group 316B (the second protrusion group region 319B) is formed substantially parallel or parallel to the [11 - 20] direction.

[0942] The first raised portion 315A and the first raised portion group 316A correspond to the raised portion 315 and the raised portion group 316 of the 22nd embodiment. The description of the raised portion 315 and the raised portion group 316 of the 22nd embodiment is applied to the description of the first raised portion 315A and the first raised portion group 316A, and other specific descriptions for the first raised portion 315A and the first raised portion group 316A are omitted.

[0943] The second raised portion 315B and the second raised portion group 316B correspond to the raised portion 315 and the raised portion group 316 of the 22nd embodiment. The description of the raised portion 315 and the raised portion group 316 of the 22nd embodiment is applied to the other description of the second raised portion 315B and the second raised portion group 316B, and other specific descriptions for the second raised portion 315B and the second raised portion group 316B are omitted.

[0944] In this mode, the drain pad 113 covers the first raised portion group 316A and the second raised portion group 316B on the second main surface 104 of the SiC semiconductor layer 102. In this mode, the drain pad 113 covers a plurality of first raised portion groups 316A and a plurality of second raised portion groups 316B together.

[0945] The drain pad 113 is formed in a film shape imitating the outer surface of the first raised portion group 316A (the outer surface of the first raised portion 315A), the outer surface of the second raised portion group 316B (the outer surface of the second raised portion 315B), and the inner surface of the groove 321.

[0946] Thereby, although not shown, raised portions 113a are formed on the portion of the outer surface of the drain pad 113 covering the first raised portion group 316A (the first raised portion 315A) and the second raised portion group 316B (the second raised portion 315B). In addition, recessed portions 113b are formed on the portion of the outer surface of the drain pad 113 covering the groove 321.

[0947] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the first raised portion group 316A and the second raised portion group 316B.

[0948] More specifically, the drain pad 113 forms an ohmic contact with a plurality of first raised portion groups 316A and a plurality of second raised portion groups 316B. In addition, in this mode, the drain pad 113 also forms an ohmic contact with the space 320.

[0949] The portion of the drain pad 113 covering the first raised portion group 316A and the second raised portion group 316B engages with the uneven portion defined by the plurality of first raised portion groups 316A, the plurality of second raised portion groups 316B, and the plurality of grooves 321.

[0950] That is, the contact area of the drain pad 113 with respect to the second main surface 104 of the SiC semiconductor layer 102 is increased by the plurality of first raised portion groups 316A, the plurality of second raised portion groups 316B, and the plurality of grooves 321. Thereby, the adhesion force of the drain pad 113 with respect to the second main surface 104 of the SiC semiconductor layer 102 is improved.

[0951] The semiconductor device 351 having such a structure is manufactured by performing the following processes in the above-described laser annealing process ( Figure 42 step S3).

[0952] First, a plurality of first raised portion groups 316A are formed by a laser annealing treatment method in a direction substantially parallel or parallel to the orientation plane 335. Next, a plurality of second raised portion groups 316B are formed by a laser annealing treatment method in a direction intersecting (orthogonal to) the orientation plane 335.

[0953] In this process, a plurality of first raised portion groups 316A may be formed in a direction intersecting (orthogonal to) the orientation plane 335, and a plurality of second raised portion groups 316B may also be formed in a direction substantially parallel or parallel to the orientation plane 335. Then, through Figure 42 the processes of step S4 to step S9, the semiconductor device 351 is manufactured.

[0954] The first raised portion group 316A and the second raised portion group 316B may be formed in any order. Therefore, a plurality of first raised portion groups 316A may be formed after forming a plurality of second raised portion groups 316B. In addition, a plurality of first raised portion groups 316A and a plurality of second raised portion groups 316B may be alternately formed.

[0955] As described above, according to the semiconductor device 351, the same effects as those described for the semiconductor device 311 can be achieved.

[0956] Figure 45 is a cross-sectional view corresponding to Figure 39 and is a cross-sectional view showing the semiconductor device 361 according to the 24th embodiment of the present invention. Figure 46 is Figure 45 an enlarged view of the region XLVI shown. Hereinafter, the structures corresponding to the structures described for the semiconductor device 311 are denoted by the same reference numerals and the description thereof is omitted.

[0957] In the semiconductor device 361, the drain pad 113 has a three-layer structure including a Ni layer 325, an Au layer 326, and an Ag layer 327 laminated in sequence from the second main surface 104 of the SiC semiconductor layer 102. That is, the drain pad 113 is formed by omitting the formation process of the Ti layer 324 in the step S9 of Figure 42 forming.

[0958] The Ni layer 325 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ni layer 325 covers a plurality of sets of protrusions 316 together.

[0959] The Ni layer 325 forms an ohmic contact between the sets of protrusions 316 and the space 320. The Au layer 326 covers substantially the entire region or the entire region of the Ni layer 325. The Ag layer 327 covers substantially the entire region or the entire region of the Au layer 326.

[0960] As described above, according to the semiconductor device 361, the same effects as those described for the semiconductor device 311 can be achieved. In the semiconductor device 361, the drain pad 113 may also have a single-layer structure composed of the Ni layer 325.

[0961] Figure 47 is a cross-sectional view corresponding to Figure 39 and is a cross-sectional view showing the semiconductor device 371 according to the 25th embodiment of the present invention. Figure 48 is Figure 47 an enlarged view of the region XLVIII shown in the figure. Hereinafter, the structures corresponding to those described for the semiconductor device 311 will be denoted by the same reference numerals and description thereof will be omitted.

[0962] In the semiconductor device 371, the drain pad 113 includes a metal layer 341, an Au layer 326, and an Ag layer 327. In this embodiment, the metal layer 341 has a stacked structure including a carbon layer 342, a NiSi layer 343, and a Ni layer 344 laminated in sequence from the second main surface 104 side of the SiC semiconductor layer 102.

[0963] The metal layer 341 is connected to the second main surface 104 of the SiC semiconductor layer 102. The metal layer 341 covers a plurality of sets of protrusions 316 together.

[0964] The metal layer 341 forms an ohmic contact between the sets of protrusions 316 and the space 320. The Au layer 326 covers substantially the entire region or the entire region of the metal layer 341. The Ag layer 327 covers substantially the entire region or the entire region of the Au layer 326.

[0965] The semiconductor device 371 is formed by omitting the removal process of the metal layer 341 in Figure 42 (see Figure 42formed by the steps S4 to S8 shown. In the semiconductor device 371, in the above-mentioned Figure 42 in step S9, an Au layer 326 and an Ag layer 327 are formed on the metal layer 341.

[0966] As described above, according to the semiconductor device 371, the drain pad 113 includes a carbon layer 342 and a NiSi layer 343. According to the semiconductor device 371, although the connection strength of the drain pad 113 cannot be improved as in the semiconductor device 311, it can achieve an effect substantially the same as that described for the semiconductor device 311. In the semiconductor device 371, the drain pad 113 may also be composed only of the metal layer 341.

[0967] As described above, the 22nd to 25th embodiments of the present invention have been described, but the 22nd to 25th embodiments of the present invention can also be implemented in other ways.

[0968] In the above 22nd to 25th embodiments, an example in which the SiC semiconductor layer 102 has a stacked structure including a SiC semiconductor substrate 111 and a SiC epitaxial layer 112 has been described.

[0969] However, the SiC semiconductor layer 102 may also have a single-layer structure composed of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may also have a single-layer structure composed of the SiC epitaxial layer 112.

[0970] In the above 22nd to 25th embodiments, an example in which the SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b is formed by the epitaxial growth method has been described. However, the SiC epitaxial layer 112 can also be formed by the following process.

[0971] First, a SiC epitaxial layer 112 having a relatively low n-type impurity concentration is formed by the epitaxial growth method. Then, n-type impurities are introduced into the surface layer portion of the SiC epitaxial layer 112 by the ion implantation method. Thus, a SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b is formed.

[0972] In the above 22nd to 25th embodiments, an example in which the gate electrode layer 132 and the gate wiring layer 133 including p-type polysilicon doped with p-type impurities are formed has been described. However, when the increase in the gate threshold voltage Vth is not emphasized, the gate electrode layer 132 and the gate wiring layer 133 may also include n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0973] That is, the low-resistance electrode layer 134 may also include n-type polysilicon. The low-resistance electrode layer 134 may also be formed by forming a silicide of a part of the silicon on the surface layer of the gate electrode layer 132 (n-type polysilicon) using a metal material. In this case, a reduction in gate resistance can be achieved.

[0974] In the above-described 22nd to 25th embodiments, a structure in which the conductivity type of each semiconductor part is inverted may also be adopted. That is, a p-type part may be made n-type and an n-type part may be made p-type.

[0975] In the above-described 22nd to 25th embodiments, a p+-type SiC semiconductor substrate (111) may be used instead of the n+-type SiC semiconductor substrate 111. In this case, in the description of the above-described 22nd to 25th embodiments, "source" is replaced with "emitter" and "drai" is replaced with "collector".

[0976] Figure 49 FIG. is a plan view showing a semiconductor device 401 according to a 26th embodiment of the present invention. Figure 50 It represents Figure 49 A plan view of the semiconductor device 401 shown, which is a plan view with the resin layer 416 removed.

[0977] Referring to Figure 49 And Figure 50 The semiconductor device 401 includes a SiC semiconductor layer 402 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 402 may also include a 4H-SiC single crystal.

[0978] The 4H-SiC single crystal has an inclination angle of 10° or less with respect to the [11-20] direction from the

[0001] plane. The inclination angle may be 0° or more and 4° or less. The inclination angle may be greater than 0° and less than 4°. Typically, the inclination angle is set in the range of 2° or 4°, and more specifically, in the range of 2°±0.2° or 4°±0.4°.

[0979] In this embodiment, the SiC semiconductor layer 402 is formed in a rectangular parallelepiped shape. The SiC semiconductor layer 402 has a first main surface 403 on one side, a second main surface 404 on the other side, and side surfaces 405A, 405B, 405C, 405D connecting the first main surface 403 and the second main surface 404. The first main surface 403 and the second main surface 404 are formed in a quadrilateral shape (a rectangular shape in this embodiment) when viewed from the normal direction thereof (hereinafter simply referred to as "plan view").

[0980] Side surface 405A is opposed to side surface 405C. Side surface 405B is opposed to side surface 405D. Side surfaces 405A to 405D respectively extend in a planar manner along the normal direction of the first main surface 403 and the second main surface 404. The lengths of side surfaces 405A to 405D may be respectively 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0981] An active region 406 and an outer region 407 are set in the SiC semiconductor layer 402. The active region 406 is a region where a vertical MISFET is formed. The outer region 407 is a region outside the active region 406.

[0982] The active region 406 is set in the central portion of the SiC semiconductor layer 402 with a space from the side surfaces 405A to 405D of the SiC semiconductor layer 402 inward in a plan view. The active region 406 is set to have a quadrilateral shape (a rectangular shape in this embodiment) with four sides parallel to the side surfaces 405A to 405D of the SiC semiconductor layer 402 in a plan view.

[0983] The outer region 407 is set in the region between the side surfaces 405A to 405D of the SiC semiconductor layer 402 and the periphery of the active region 406. The outer region 407 is set to surround the active region 406 without break points (quadrilateral ring shape) in a plan view.

[0984] A main surface gate electrode 408 and a main surface source electrode 409 are formed on the first main surface 403 of the SiC semiconductor layer 402.

[0985] The main surface gate electrode 408 includes a gate pad 410 and gate fingers 411. In this embodiment, the gate pad 410 and the gate fingers 411 are arranged in the active region 406.

[0986] The gate pad 410 is formed along the side surface 405A of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed in the central region of the side surface 405A of the SiC semiconductor layer 402 in a plan view.

[0987] The gate pad 410 may also be formed along the corner connecting any two of the side surfaces 405A to 405D of the SiC semiconductor layer 402 in a plan view. The gate pad 410 is formed in a quadrilateral shape in a plan view.

[0988] The gate fingers 411 include outer gate fingers 411A and inner gate fingers 411B.

[0989] The outer gate finger 411A extends from the gate pad 410 and extends in a strip shape along the periphery of the active region 406. In this manner, the outer gate finger 411A is formed along three side surfaces 405A, 405B, and 405D of the SiC semiconductor layer 402 in such a way as to divide the inner region of the active region 406 from three directions.

[0990] The outer gate finger 411A has a pair of open end portions 412A and 412B. The pair of open end portions 412A and 412B of the outer gate finger 411A are formed in a region that faces the gate pad 410 with the inner region of the active region 406 therebetween. In this manner, the pair of open end portions 412A and 412B of the outer gate finger 411A are formed along the side surface 405C of the SiC semiconductor layer 402.

[0991] The inner gate finger 411B is led out from the gate pad 410 into the inner region of the active region 406. The inner gate finger 411B extends in a strip shape in the inner region of the active region 406. The inner gate finger 411B extends from the side surface 405A side toward the side surface 405C side.

[0992] In this manner, the main surface source electrode 409 includes a source pad 413, a source pull-back wiring 414, and a source connection portion 415.

[0993] The source pad 413 is formed in the active region 406 at an interval from the gate pad 410 and the gate finger 411. The source pad 413 is formed in a C shape (in Figure 49 and Figure 50 is an inverted C shape) so as to cover a region having a C shape (in Figure 49 and Figure 50 is an inverted C shape) defined by the gate pad 410 and the gate finger 411 in a plan view.

[0994] The source pull-back wiring 414 is formed in the outer region 407. The source pull-back wiring 414 extends in a strip shape along the active region 406. In this manner, the source pull-back wiring 414 is formed in a continuous (quadrilateral ring shape) that surrounds the active region 406 in a plan view. The source pull-back wiring 414 is electrically connected to the SiC semiconductor layer 402 in the outer region 407.

[0995] The source connection portion 415 connects the source pad 413 and the source pull-back wiring 414. The source connection portion 415 is provided in a region between the pair of open end portions 412A and 412B of the outer gate finger 411A. The source connection portion 415 crosses the boundary region between the active region 406 and the outer region 407 from the source pad 413 and is connected to the source pull-back wiring 414.

[0996] The MISFET formed in the active region 406 includes a parasitic bipolar transistor of npn type in its structure. If the avalanche current generated in the outer region 407 flows into the active region 406, the parasitic bipolar transistor becomes in an on state. In this case, for example, there is a possibility that the control of the MISFET becomes unstable due to latch-up.

[0997] Here, in the semiconductor device 401, an avalanche current absorption structure for absorbing the avalanche current generated in the region outside the active region 406 is formed by using the structure of the main surface source electrode 409.

[0998] More specifically, the source pull-back wiring 414 is used to absorb the avalanche current generated in the outer region 407. Thereby, the avalanche current reaches the source pad 413 via the source connection portion 415. When an external connection wire (e.g., a bonding wire) is connected to the source pad 413, the avalanche current is output through this wire.

[0999] Thereby, it is possible to suppress the case where the parasitic bipolar transistor becomes in an on state due to the unwanted current generated in the outer region 407. Thus, since latch-up can be suppressed, the stability of the control of the MISFET can be improved.

[1000] A gate voltage is applied to the gate pad 410 and the gate fingers 411. The gate voltage can be 10 V or more and 50 V or less (e.g., about 30 V). A source voltage is applied to the source pad 413. The source voltage can be a reference voltage (e.g., GND voltage).

[1001] A resin layer 416 is formed on the first main surface 403 of the SiC semiconductor layer 402 (more specifically, on the interlayer insulating layer 491 described later). In Figure 49 it, for clarity, the resin layer 416 is shown by hatching. The resin layer 416 covers the gate pad 410, the gate fingers 411, and the source pad 413.

[1002] The resin layer 416 can also contain a negative or positive photosensitive resin. In this embodiment, the resin layer 416 contains polybenzoxazole as an example of a positive photosensitive resin. The resin layer 416 can also contain polyimide as an example of a negative photosensitive resin.

[1003] A gate pad opening 417 and a source pad opening 418 are formed in the resin layer 416. The gate pad opening 417 exposes the gate pad 410. The source pad opening 418 exposes the source pad 413.

[1004] The peripheral portion 419 of the resin layer 416 is formed at a space from the side surfaces 405A to 405D of the SiC semiconductor layer 402 in the inward region. Thereby, the resin layer 416 exposes the peripheral portion of the SiC semiconductor layer 402 (more specifically, the interlayer insulating layer 491 described later).

[1005] The peripheral portion 419 of the resin layer 416 is a portion where a dicing street is formed when the semiconductor device 401 is diced from a single SiC semiconductor wafer. By exposing the peripheral portion of the SiC semiconductor layer 402 from the resin layer 416, it is not necessary to physically cut the resin layer 416.

[1006] Therefore, the semiconductor device 401 can be smoothly diced from a single SiC semiconductor wafer. The side surfaces 405A to 405D of the SiC semiconductor layer 402 may be cut surfaces (ground surfaces). The side surfaces 405A to 405D of the SiC semiconductor layer 402 may have grinding marks.

[1007] Figure 51 Is Figure 50 An enlarged view of the region LI shown, and is a view for explaining the structure of the first main surface 403 of the SiC semiconductor layer 402. Figure 52 Is along Figure 51 A cross-sectional view taken along the line LII-LII shown, and is a cross-sectional view showing a first exemplary embodiment of the gate trench 431 and a first exemplary embodiment of the source trench 441. Figure 53 Is along Figure 51 A cross-sectional view taken along the line LIII-LIII shown, and is a cross-sectional view showing a first exemplary embodiment of the gate wiring layer 436. Figure 54 Is Figure 52 An enlarged view of the region LIV shown.

[1008] Figure 55 Is along Figure 50 A cross-sectional view taken along the line LV-LV shown, and is a cross-sectional view showing a first exemplary embodiment of the active sidewall 464, a first exemplary embodiment of the outer main surface 462, a first exemplary embodiment of the sidewall 482, a first exemplary embodiment of the diode region 471, a first exemplary embodiment of the outer deep well region 472, a first exemplary embodiment of the field limiting structure 473, and a first exemplary embodiment of the anchor hole 495. Figure 56 Is Figure 55 An enlarged view of the region LVI shown, and is an enlarged view showing a first exemplary embodiment of the active sidewall 464 and a first exemplary embodiment of the outer main surface 462.

[1009] Referring to Figures 51 to 55 , in this embodiment, the SiC semiconductor layer 402 has a stacked structure including an n+-type SiC semiconductor substrate 421 and an n-type SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 is formed by the SiC semiconductor substrate 421.

[1010] The first main surface 403 of the SiC semiconductor layer 402 is formed by the SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 may also be a ground surface. The second main surface 404 of the SiC semiconductor layer 402 may also have grinding marks.

[1011] The thickness of the SiC semiconductor substrate 421 may be 1 μm or more and less than 1000 μm. The thickness of the SiC semiconductor substrate 421 may be 5 μm or more. The thickness of the SiC semiconductor substrate 421 may be 25 μm or more. The thickness of the SiC semiconductor substrate 421 may be 50 μm or more. The thickness of the SiC semiconductor substrate 421 may be 100 μm or more.

[1012] The thickness of the SiC semiconductor substrate 421 may be 700 μm or less. The thickness of the SiC semiconductor substrate 421 may be 500 μm or less. The thickness of the SiC semiconductor substrate 421 may be 400 μm or less. The thickness of the SiC semiconductor substrate 421 may be 300 μm or less.

[1013] The thickness of the SiC semiconductor substrate 421 may be 250 μm or less. The thickness of the SiC semiconductor substrate 421 may be 200 μm or less. The thickness of the SiC semiconductor substrate 421 may be 150 μm or less. The thickness of the SiC semiconductor substrate 421 may be 100 μm or less.

[1014] The thickness of the SiC semiconductor substrate 421 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 421, a reduction in the resistance value can be achieved by shortening the current path.

[1015] The thickness of the SiC epitaxial layer 422 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 422 may be 5 μm or more. The thickness of the SiC epitaxial layer 422 may be 10 μm or more.

[1016] The thickness of the SiC epitaxial layer 422 may be 50 μm or less. The thickness of the SiC epitaxial layer 422 may be 40 μm or less. The thickness of the SiC epitaxial layer 422 may be 30 μm or less.

[1017] The thickness of the SiC epitaxial layer 422 may be 20 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 10 μm or less.

[1018] The n-type impurity concentration of the SiC epitaxial layer 422 is equal to or less than the n-type impurity concentration of the SiC semiconductor substrate 421. The n-type impurity concentration of the SiC epitaxial layer 6 may also be 1.0×1015 cm －3 1.0×10 or more 18 cm －3 Less than the following value.

[1019] In this method, the SiC epitaxial layer 422 has a plurality of regions with different n-type impurity concentrations in the normal direction of the first main surface 403 of the SiC semiconductor layer 402. More specifically, the SiC epitaxial layer 422 includes a high-concentration region 422a with a relatively high n-type impurity concentration and a low-concentration region 422b with an n-type impurity concentration lower than that of the high-concentration region 422a.

[1020] The high-concentration region 422a is formed in the region on the side of the first main surface 403. The low-concentration region 422b is formed in the region on the side of the second main surface 404 of the SiC semiconductor layer 402 with respect to the high-concentration region 422a.

[1021] The n-type impurity concentration of the high-concentration region 422a can also be 1×10 16 cm －3 or more and 1×10 18 cm －3 Less than the following value. The n-type impurity concentration of the low-concentration region 422b can also be 1×10 15 cm －3 or more and 1×10 16 cm －3 Less than the following value.

[1022] The thickness of the high-concentration region 422a is less than or equal to the thickness of the low-concentration region 422b. More specifically, the thickness of the high-concentration region 422a is less than the thickness of the low-concentration region 422b. That is, the thickness of the high-concentration region 422a is less than half of the total thickness of the SiC epitaxial layer 422.

[1023] A drain pad 423 as a second main surface electrode is connected to the second main surface 404 of the SiC semiconductor layer 402. When disconnected, the maximum voltage that can be applied between the source pad 413 and the drain pad 423 can also be 1000V or more and 10000V or less.

[1024] The drain pad 423 may also include at least one of a Ti layer, a Ni layer, an Au layer, or an Ag layer. The drain pad 423 has a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in sequence starting from the second main surface 404 of the SiC semiconductor layer 402.

[1025] The SiC semiconductor substrate 421 is formed as a drain region 424 of the MISFET. The SiC epitaxial layer 422 is formed as a drift region 425 of the MISFET.

[1026] In the active region 406, a p-type body region 426 is formed in the surface layer portion of the first main surface 403 of the SiC semiconductor layer 402. The body region 426 demarcates the active region 406.

[1027] That is, in this method, the body region 426 is formed in the entire region of the region where the active region 406 is formed on the first main surface 403 of the SiC semiconductor layer 402. The p-type impurity concentration of the body region 426 may also be 1×10 17 cm －3 or more and 1×10 20 cm －3 or less.

[1028] In the active region 406, a plurality of gate trenches 431 are formed in the surface layer portion of the first main surface 403 of the SiC semiconductor layer 402. The plurality of gate trenches 431 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 431 are formed in a strip shape extending along a second direction Y intersecting the first direction X.

[1029] More specifically, the first direction X is a direction along the side surfaces 405B and 405D of the SiC semiconductor layer 402. The second direction Y is a direction orthogonal to the first direction X. The second direction Y is also a direction along the side surfaces 405A and 405C of the SiC semiconductor layer 402.

[1030] The plurality of gate trenches 431 are formed in a striped shape in a top view. In this method, each gate trench 431 extends in a strip shape from the peripheral portion on one side (side surface 405B side) to the peripheral portion on the other side (side surface 405D side) in the active region 406.

[1031] Each gate trench 431 crosses the middle portion between the peripheral portion on one side and the peripheral portion on the other side in the active region 406. One end portion of each gate trench 431 is located at the peripheral portion on one side in the active region 406. The other end portion of each gate trench 431 is located at the peripheral portion on the other side in the active region 406.

[1032] The first direction X may also be set to the [11 - 20] direction ([ - 1 - 120] direction). In this case, each gate trench 431 may also extend along the [11 - 20] direction. The first direction X may also be set to the [ - 1100] direction ([1 - 100] direction) orthogonal to the [11 - 20] direction. In this case, each gate trench 431 may also extend along the [ - 1100] direction ([1 - 100] direction).

[1033] Each gate trench 431 has a length on the order of millimeters. That is, in Figure 53In the cross-section shown, the length of the gate trench 431 is the length from the end on the side of the connecting portion of the gate trench 431 and the gate finger 411 to the end on the opposite side.

[1034] The length of each gate trench 431 may also be 0.5 mm or more. In this mode, the length of each gate trench 431 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total extension of one or more gate trenches 431 per unit area may also be 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less.

[1035] Each gate trench 431 integrally includes an active trench portion 431a and a contact trench portion 431b. The active trench portion 431a is a portion along the channel region of the MISFET in the active region 406.

[1036] The contact trench portion 431b is a portion for the purpose of contacting the gate finger 411 in the gate trench 431. The contact trench portion 431b is led out from the active trench portion 431a to the peripheral portion of the active region 406. The contact trench portion 431b is formed in the region directly below the gate finger 411. The amount of lead-out of the contact trench portion 431b is arbitrary.

[1037] Each gate trench 431 penetrates the body region 426 until the SiC epitaxial layer 422. The bottom wall of each gate trench 431 is located within the SiC epitaxial layer 422.

[1038] More specifically, the bottom wall of each gate trench 431 is located in the high-concentration region 422a of the SiC epitaxial layer 422. The bottom wall of the gate trench 431 may also be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[1039] The side wall of the gate trench 431 may also extend along the normal direction of the first main surface 403 of the SiC semiconductor layer 402. That is, the side wall of the gate trench 431 may also be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402.

[1040] In the normal direction of the first main surface 403 of the SiC semiconductor layer 402, the depth of the gate trench 431 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the gate trench 431 is preferably 0.5 μm or more and 1.0 μm or less.

[1041] The width of the gate trench 431 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). The width of the gate trench 431 in the first direction is preferably 0.1 μm or more and 0.5 μm or less.

[1042] Reference Figure 54 , the opening edge portion 432 of each gate trench 431 includes an inclined portion 433 that slopes downward from the first main surface 403 of the SiC semiconductor layer 402 toward the inner direction of the gate trench 431. The opening edge portion 432 of the gate trench 431 is a corner portion connecting the first main surface 403 of the SiC semiconductor layer 402 and the side wall of the gate trench 431.

[1043] In this manner, the inclined portion 433 is formed in a concave curved shape toward the inner side of the SiC semiconductor layer 402. The inclined portion 433 may also be formed in a convex curved shape toward the inner side of the gate trench 431.

[1044] The electric field with respect to the opening edge portion 432 of the gate trench 431 is dispersed along the inclined portion 433. Thereby, the electric field concentration with respect to the opening edge portion 432 of the gate trench 431 can be alleviated.

[1045] A gate insulating layer 434 and a gate electrode layer 435 are formed in each gate trench 431. For clarity, the gate insulating layer 434 and the gate electrode layer 435 are shown by hatching in Figure 51 .

[1046] The gate insulating layer 434 contains silicon oxide. The gate insulating layer 434 may also contain other insulating films such as silicon nitride. The gate insulating layer 434 is formed in a film shape along the inner wall surface of the gate trench 431 so as to define a...

Claims

1. A semiconductor device, It is characterized in that include: a semiconductor layer having a main surface; A gate trench formed on the main surface; A gate insulating layer formed along the inner wall of the gate trench; a gate electrode layer, which is made of polysilicon and is buried in the gate trench via the gate insulating layer; as well as The low resistance electrode layer includes a conductive material having a sheet resistance lower than that of the gate electrode layer and covers the gate electrode layer.

2. The semiconductor device according to claim 1, It is characterized in that The low-resistance electrode layer covers the gate electrode layer in the gate trench.

3. The semiconductor device according to claim 1 or 2, It is characterized in that The length of the gate trench is greater than or equal to 1 mm and less than or equal to 10 mm.

4. The semiconductor device according to any one of claims 1 to 3, It is characterized in that In a plan view, the total extension of the gate trench per unit area is 0.5 μm / μm 2 Above and 0.75μm / μm 2 the following.

5. The semiconductor device according to any one of claims 1 to 4, It is characterized in that comprising a plurality of the above-mentioned gate trenches formed at intervals in one direction, In a top view, the total extension of one or more of the above-described gate trenches per unit area is 0.5 μm / μm 2 or more and 0.75 μm / μm 2 or less.

6. The semiconductor device according to any one of claims 1 to 5, It is characterized in that In a cross-sectional view when cutting in a direction orthogonal to the direction in which the above-mentioned gate trench extends, the cross-sectional area of the above-mentioned gate electrode layer is 0.05 μm 2 or more and 0.5 μm 2 or less.

7. The semiconductor device according to any one of claims 1 to 6, It is characterized in that The thickness of the low-resistance electrode layer is less than the thickness of the gate electrode layer.

8. The semiconductor device according to any one of claims 1 to 7, It is characterized in that The thickness of the low resistance electrode layer is smaller than the thickness of the gate electrode layer.

9. The semiconductor device according to any one of claims 1 to 8, It is characterized in that A ratio of the thickness of the low-resistance electrode layer to the thickness of the gate electrode layer is greater than or equal to 0.01 and less than or equal to 1.

10. The semiconductor device according to any one of claims 1 to 9, It is characterized in that The gate electrode layer has a thickness of 0.5 μm or more and 3 μm or less.

11. The semiconductor device according to any one of claims 1 to 10, It is characterized in that The low-resistance electrode layer has a thickness of 0.01 μm or more and 3 μm or less.

12. The semiconductor device according to any one of claims 1 to 11, It is characterized in that The gate electrode layer is made of n-type polysilicon to which n-type impurities are added, or p-type polysilicon to which p-type impurities are added.

13. The semiconductor device according to any one of claims 1 to 12, It is characterized in that The gate electrode layer is made of p-type polysilicon to which p-type impurities are added.

14. The semiconductor device according to any one of claims 1 to 13, It is characterized in that The semiconductor layer includes SiC.

15. The semiconductor device according to any one of claims 1 to 14, It is characterized in that The entire low-resistance electrode layer is located below the main surface of the semiconductor layer.

16. The semiconductor device according to any one of claims 1 to 15, It is characterized in that Also includes: a main body region formed on a surface portion of the main surface; and a source region formed in a surface portion of the body region, The gate trench is formed on the main surface so as to penetrate the body region.

17. The semiconductor device according to claim 16, wherein, the low-resistance electrode layer is formed in a region closer to the main surface side of the semiconductor layer than a boundary region between the main body region and the source region.

18. A semiconductor device, wherein, it includes: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; and a set of protrusions including a plurality of protrusions formed on the second main surface at intervals from each other, having a first part in which several of the plurality of protrusions overlap each other in a first perspective view when viewed from a first direction which is one of the surface directions of the second main surface; and an electrode connected to the set of protrusions above the second main surface.

19. A semiconductor device, wherein, it includes: a semiconductor layer including a first main surface on one side and a second main surface on the other side; a gate trench formed on the first main surface; a source trench formed on the first main surface at an interval from the gate trench; a first-conductivity-type main body region formed on the side of the gate trench in the surface layer portion of the first main surface; a second-conductivity-type source region formed on the side of the gate trench in the surface layer portion of the main body region; a second-conductivity-type drift region formed in a region of the semiconductor layer on the second main surface side with respect to the main body region and along the gate trench and the source trench; a gate insulating layer covering the inner wall of the gate trench; a gate electrode disposed in the gate trench and facing the main body region, the source region, and the drift region with the gate insulating layer therebetween; and a source electrode buried in the source trench and forming a Schottky junction with the drift region.

20. A semiconductor device, wherein, it includes: a semiconductor layer having a first main surface on one side and a second main surface on the other side, and partitioning a mesa-shaped active mesa having an active main surface and active sidewalls in the first main surface; a step relaxation structure formed on the first main surface and relaxing the steps of the active mesa; and a coating layer covering the step relaxation structure and extending from above the active main surface toward a region outside the active mesa.

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