Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a plurality of gate structures located on a logic region, a plurality of resistor structures located on a resistor region and source and drain regions located in the logic region on the two sides of each gate structure are formed, the resistor structures and the gate structures extend in the first direction, and the resistor structures are arranged in an array mode in the first direction; forming buffer material layers on the surface of the substrate, the surfaces of the plurality of gate structures and the surfaces of the plurality of resistor structures; forming a stress material layer on the surface of the buffer material layer; performing rapid thermal annealing treatment on the substrate, the plurality of gate structures, the plurality of resistor structures and the stress material layer; after the rapid thermal annealing treatment, the stress material layer is removed, so that the buffer material layer is exposed; forming a planarization material layer on the surface of the exposed buffer material layer; after the planarization material layer is formed, dynamic surface annealing treatment is performed on the substrate, the plurality of gate structures and the plurality of resistor structures, so that the uniformity of resistance distribution is improved, and the resolution of the Kelvin frequency divider is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] A digital-to-analog converter (DAC) receives data represented by a digital code and generates an equivalent input output. The DAC also requires an analog reference voltage or current to operate. As a DAC structure, a Kelvin divider requires a large number of resistors and switches to achieve high resolution.

[0003] However, in the existing Kelvin divider structure, the uniformity of the resistor distribution is poor, seriously affecting the resolution of the Kelvin divider. Therefore, the existing Kelvin divider structure needs to be further improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0005] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a logic region and a resistor region; forming a plurality of gate structures on the logic region, a plurality of resistor structures on the resistor region, and source / drain regions in the logic region on both sides of each of the gate structures, the resistor structures and the gate structures both extending along a first direction, and the plurality of resistor structures being arranged in an array along the first direction; forming a buffer material layer on the surface of the substrate, on the surfaces of the plurality of gate structures, and on the surfaces of the plurality of resistor structures; forming a stress material layer on the surface of the buffer material layer; performing rapid thermal annealing on the substrate, the plurality of gate structures, the plurality of resistor structures, and the stress material layer; after the rapid thermal annealing treatment, removing the stress material layer to expose the buffer material layer; forming a planarization material layer on the exposed surface of the buffer material layer; after forming the planarization material layer, performing dynamic surface annealing on the substrate, the plurality of gate structures, and the plurality of resistor structures.

[0006] Optionally, the resistor region includes a main region and a peripheral region, and the peripheral region surrounds the main region; before forming a plurality of gate structures and a plurality of the resistor structures, it further includes: forming a first isolation structure in the peripheral region and the main region, and forming a plurality of first active regions in the main region, the plurality of first active regions are arranged in an array along the first direction, and the first isolation structure is located between adjacent first active regions; forming a first well region, a second isolation structure and a second well region in the logic region, the second isolation structure is located between the first well region and the second well region, and the first well region and the second well region have different conductivity types.

[0007] Optionally, the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, the plurality of source / drain regions include a plurality of first source / drain regions and a plurality of second source / drain regions, the first source / drain regions and the second source / drain regions have different conductivity types, the first gate structures are formed on the first well region, the second gate structures are formed on the second well region, the first source / drain regions are formed in the first well region, the second source / drain regions are formed in the second well region, the first source / drain regions and the first well region have different conductivity types, and the second source / drain regions and the second well region have different conductivity types.

[0008] Optionally, the plurality of resistor structures are formed on the surface of the first isolation structure between the first active regions adjacent in the second direction, and the second direction is perpendicular to the first direction.

[0009] Optionally, the resistor region further includes a heat dissipation region, and the heat dissipation region is located between the main region and the peripheral region; the method further includes: forming a plurality of second active regions in the heat dissipation region, the plurality of second active regions surround the plurality of first active regions and are arranged along their surrounding direction; before forming the buffer material layer, it further includes: forming at least one heat dissipation structure on the heat dissipation region, the heat dissipation structure is disposed around the plurality of resistor structures, the heat dissipation structure includes a plurality of heat dissipation layers, the plurality of heat dissipation layers are arranged along the surrounding direction of the heat dissipation structure, the heat dissipation layers are located on the surface of the first isolation structure, and each second active region is located between adjacent heat dissipation layers.

[0010] Optionally, the forming methods of the plurality of resistor structures, the plurality of gate structures and the plurality of heat dissipation layers include: forming a gate material layer on the surface of the substrate; patterning the gate material layer to form the plurality of resistor structures, a plurality of gate layers and the plurality of heat dissipation layers, and the gate structure includes the gate layer.

[0011] Optionally, the buffer material layer has a first thickness, the planarization material layer has a second thickness, and the ratio range of the second thickness to the first thickness is from 15:1 to 60:1.

[0012] Optionally, the range of the second thickness is from 3000 Å to 5000 Å.

[0013] Optionally, the buffer material layer on the surface of the resistance structure has a first protrusion height relative to the buffer material layer on the surface of the substrate, and the planarization material layer on the surface of the resistance structure has a second protrusion height relative to the planarization material layer on the surface of the substrate, and the second protrusion height is less than the first protrusion height.

[0014] Optionally, the material of the planarization material layer includes amorphous carbon.

[0015] Optionally, the substrate has opposite front and back surfaces, and a plurality of the gate structures, a plurality of the resistance structures, and the stress material layer are located on the front surface.

[0016] Optionally, the rapid thermal annealing treatment of the substrate, a plurality of the gate structures, a plurality of the resistance structures, and the stress material layer includes: heating the substrate, a plurality of the gate structures, a plurality of the resistance structures, and the stress material layer from the back surface of the substrate.

[0017] Optionally, the dynamic surface annealing treatment of the substrate, a plurality of the gate structures, and a plurality of the resistance structures includes: heating the substrate, a plurality of the gate structures, and a plurality of the resistance structures from the front surface of the substrate.

[0018] Optionally, the material of the buffer material layer includes silicon oxide; the material of the stress material layer includes silicon nitride.

[0019] Optionally, the process parameters of the rapid thermal annealing treatment include: the process temperature range is from 1010 °C to 1050 °C, and the process time range is from 1 s to 3 s.

[0020] Optionally, the process parameters of the dynamic surface annealing treatment include: the process temperature range is from 1200 °C to 1300 °C, and the process time range is from 2 min to 5 min.

[0021] Optionally, after the dynamic surface annealing treatment, it further includes: removing the planarization material layer; the process of removing the planarization material layer includes an ashing process.

[0022] Optionally, after removing the planarization material layer, it further includes: removing the buffer material layer; the process of removing the buffer material layer includes a wet etching process.

[0023] Optionally, the thickness range of the buffer material layer is from 80 Å to 200 Å; the thickness range of the stress material layer is from 200 Å to 400 Å.

[0024] Optionally, the forming process of the buffer material layer includes plasma enhanced chemical vapor deposition; the forming process of the stress material layer includes plasma enhanced chemical vapor deposition; the forming process of the planarization material layer includes chemical vapor deposition process.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the planarization material layer flattens the contact surface of the laser, which can reduce the influence of the pattern effect on the laser absorption, thereby improving the laser absorption efficiency. Moreover, in the dynamic surface annealing treatment, the laser does not need to be incident at the Brewster angle, so that the laser environment of each of the resistor structures arranged in the array is the same. Thus, while improving the performance of MOS devices (especially NMOS devices) in the logic region by using the stress memory technology, the uniformity of the resistance distribution of the resistor structures is improved as a whole, which is beneficial to improving the resolution of the Kelvin frequency divider and improving the performance of the Kelvin frequency divider.

[0027] Further, a plurality of second active regions are further formed in the heat dissipation region, and at least one heat dissipation structure is formed on the heat dissipation region. The heat dissipation structure is disposed around the outside of the plurality of resistor structures. The heat dissipation structure and the plurality of second active regions are used to make the resistor structures at the periphery in the plurality of resistor structure arrays have a similar heat dissipation environment to the resistor structures at the middle, so as to reduce the influence of heat on the resistance value of the resistor structures, improve the uniformity of the resistance distribution of the resistor structures on the resistor region, which is beneficial to improving the resolution of the Kelvin frequency divider and improving the performance of the Kelvin frequency divider. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 4 is a schematic structural diagram of each step of a method for forming a Kelvin frequency divider;

[0029] Figure 5 is a schematic flow diagram of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 6 to 17 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether they are in direct contact.

[0032] As described in the background art, the performance of the Kelvin divider formed by the existing technology needs to be further improved. A method for forming a Kelvin divider will be described and analyzed below.

[0033] Figures 1 to 4 It is a schematic structural diagram of each step of a method for forming a Kelvin divider.

[0034] Please refer to Figure 1 , provide a substrate 100, the material of the substrate 100 includes silicon, the substrate 100 includes a logic region I and a resistor region II, a first isolation structure 101 is provided in the logic region I, and a second isolation structure 102 is provided in the resistor region II; form a plurality of MOS structures on the logic region I and a plurality of resistor structures 103 arranged in an array on the resistor region II, the MOS structure includes a gate layer 104 and source / drain regions 105 in the substrate 100 on both sides of the gate layer 104, the first isolation structure 101 is located between different MOS structures, the second isolation structure 102 is located at the bottom of the resistor structure 103, and the materials of the first isolation structure 101 and the second isolation structure 102 are both silicon dioxide.

[0035] Please refer to Figure 2 , form a silicon oxide material layer 106 on the surface of the substrate 100, the surfaces of a plurality of MOS structures, and the surfaces of a plurality of the resistor structures 103; form a silicon nitride material layer 107 on the surface of the silicon oxide material layer 106; perform rapid thermal annealing (RTA) on a plurality of the MOS structures.

[0036] Please refer to Figure 3 and Figure 4 , Figure 4 is Figure 3 a top-view structural diagram of the resistor region II in Figure 3 , only the resistor structures of a partial resistor region II are shown. After removing the silicon nitride material layer 107, perform laser spike annealing (LSA) on a plurality of the MOS structures.

[0037] In the above formation method, the stress memorization technique (SMT) is adopted, the silicon nitride material layer 107 is used as a stress material, and the stress is transferred to the source / drain regions 105 and the gate layer 104 through rapid thermal annealing, and then the stress is transferred to the device channel. The stress is still memorized after removing the silicon nitride material layer 107, so that both the effective mass of the electron conductance and the scattering probability in the channel direction are reduced, thereby improving the speed of NMOS in a plurality of the MOS structures.

[0038] However, for the Kelvin divider structure, the MOS structure is integrated with several resistor structures 103 arranged in an array. The silicon oxide material layer 106 and the silicon nitride material layer 107 will also be simultaneously deposited on the surfaces of the several resistor structures 103 and will be affected during rapid thermal annealing treatment and laser spike annealing treatment. Specifically, the resistance value uniformity of the several resistor structures 103 arranged in an array is poor.

[0039] The resistance uniformity of the several resistor structures 103 arranged in an array formed in the above method will be described below in combination with a specific test result. Please refer to Figure 4 , Figure 4 FIG. shows a top view structural schematic diagram of the several resistor structures 103 arranged in an array, where a, b... m and C, D... M are used to indicate the measurement positions of the resistance values. It is found through testing that there is a certain regularity: the resistance values at the middle positions (such as a and b) are relatively low, while the resistance values at the surrounding areas (such as h, i, L, M, etc.) are relatively high, and there is asymmetry in the resistance distribution above and below the center line MM1. For example, the resistance value at c is higher than that at C, and the resistance value at j is higher than that at J, etc.

[0040] The non-uniformity of the above resistance value distribution will seriously affect the resolution of the Kelvin divider. Therefore, it is necessary to improve the performance of the existing Kelvin divider structure. Through research, it is found that first, since the thermal conductivity of silicon is about 150 W / (m*K) and the thermal conductivity of silicon dioxide is about 1.4 W / (m*K), the temperature of the resistor structures 103 at the surrounding areas is lower than that of the resistor structures 103 at the middle, resulting in relatively higher resistance values at the surrounding areas. In addition, during the laser spike annealing process, the laser scans along the X direction (as shown in Figure 4 ) and is incident at the Brewster angle θ to reduce light loss, which leads to different laser environments for the resistor structures 103 above and below the center line MM1, and further leads to the asymmetry of the above resistance distribution.

[0041] To solve the above problems, in a method for forming a semiconductor structure provided by the present invention, the planarization material layer flattens the contact surface of the laser, which can reduce the influence of the pattern effect on laser absorption, thereby improving the laser absorption efficiency. Moreover, in the dynamic surface annealing treatment, the laser does not need to be incident at a specific Brewster angle, so that the laser environments of the resistor structures arranged in an array are the same. Thus, while improving the performance of MOS devices (especially NMOS devices) in the logic region by using the stress memory technology, the uniformity of the resistance distribution of the resistor structures is improved as a whole, which is beneficial to improving the resolution of the Kelvin divider and the performance of the Kelvin divider.

[0042] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following provides a detailed description of specific embodiments of the present invention with reference to the accompanying drawings.

[0043] Figure 5 It is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 5 , the method for forming the semiconductor structure includes the following steps:

[0045] Step S201: Provide a substrate, where the substrate includes a logic region and a resistance region;

[0046] Step S202: Form a plurality of gate structures on the logic region, a plurality of resistance structures on the resistance region, and source / drain regions in the logic region on both sides of each of the gate structures. The resistance structures and the gate structures both extend along a first direction, and the plurality of resistance structures are arranged in an array along the first direction;

[0047] Step S203: Form a buffer material layer on the surface of the substrate, the surfaces of the plurality of gate structures, and the surfaces of the plurality of resistance structures;

[0048] Step S204: Form a stress material layer on the surface of the buffer material layer;

[0049] Step S205: Perform a rapid thermal annealing process on the substrate, the plurality of gate structures, the plurality of resistance structures, and the stress material layer;

[0050] Step S206: After the rapid thermal annealing process, remove the stress material layer to expose the buffer material layer;

[0051] Step S207: Form a planarization material layer on the exposed surface of the buffer material layer;

[0052] Step S208: After forming the planarization material layer, perform a dynamic surface annealing process on the substrate, the plurality of gate structures, and the plurality of resistance structures.

[0053] The following will be described in detail with reference to the accompanying drawings.

[0054] Figures 6 to 17 It is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0055] Please refer to Figure 6 and Figure 7 , Figure 6 is a top-view structural schematic diagram omitting the logic region I, Figure 7 is Figure 6Schematic cross-sectional structure diagram along the EE1 direction (only a part of the resistance region II is shown, as indicated by the blue frame), perform step S201, provide a substrate 300, and the substrate 300 includes a logic region I and a resistance region II.

[0056] In this embodiment, the material of the substrate 300 is silicon.

[0057] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0058] In this embodiment, the resistance region II includes a main region A and a peripheral region B, and the peripheral region B surrounds the main region A. Here, the main region A is used to define the position of the resistance structure, and the peripheral region B is used to define the range where no resistance structure is provided.

[0059] In this embodiment, the resistance region II further includes a heat dissipation region C, and the heat dissipation region C is located between the main region A and the peripheral region B. Here, the heat dissipation region C is used to define the position of the heat dissipation structure.

[0060] In another embodiment, the resistance region may not include the heat dissipation region.

[0061] In this embodiment, the substrate 300 has opposite front (not shown in the figure) and back (not shown in the figure) surfaces, and several gate structures, several resistance structures, and a stress material layer are formed on the front surface subsequently.

[0062] In this embodiment, before forming several gate structures and several of the resistance structures, please also refer to Figure 8 and Figure 9 , Figure 8 is a top view structure diagram omitting the logic region I, Figure 9 is Figure 8 Schematic cross-sectional structure diagram along the EE1 direction (only a part of the resistance region II is shown, as indicated by the blue frame), and a first isolation structure 301 is further formed in the peripheral region B and the main region A, and several first active regions 302 are further formed in the main region A. The several first active regions 302 are arranged in an array along the first direction X, and the first isolation structure 301 is located between adjacent first active regions 302.

[0063] In this embodiment, the first isolation structure 301 is also formed in the heat dissipation region C.

[0064] In this embodiment, a plurality of second active regions 306 are further formed in the heat dissipation region C. The plurality of second active regions 306 surround the plurality of first active regions 302 and are arranged along their surrounding direction.

[0065] In this embodiment, a first well region 303, a second isolation structure 304, and a second well region 305 are further formed in the logic region I. The second isolation structure 304 is located between the first well region 303 and the second well region 305, and the first well region 303 and the second well region 305 have different conduction types. The second isolation structure 304 is used for electrical isolation of different types of devices.

[0066] In this embodiment, the first well region 303 has a P-type conduction type and is used to form NMOS devices, and the second well region 303 has an N-type conduction type and is used to form PMOS devices.

[0067] Please refer to Figure 10 and Figure 11 , Figure 10 which is a top view structural schematic diagram of the logic region I omitted, Figure 11 is Figure 10 a cross-sectional structural schematic diagram along the EE1 direction in

[0068] (only a part of the resistor region II is shown, as indicated by the blue frame), and step S202 is performed to form a plurality of gate structures on the logic region I, a plurality of resistor structures 307 on the resistor region II, and source-drain regions in the logic region I on both sides of each gate structure. The resistor structures 307 and the gate structures both extend along the first direction X, and the plurality of resistor structures 307 are arranged in an array along the first direction X.

[0069] In this embodiment, the plurality of gate structures include a plurality of first gate structures 308 and a plurality of second gate structures 309, the plurality of source-drain regions include a plurality of first source-drain regions 310 and a plurality of second source-drain regions 311, the first source-drain regions 310 and the second source-drain regions 311 have different conduction types, the first gate structures 308 are formed on the first well region 303, the second gate structures 309 are formed on the second well region 305, the first source-drain regions 310 are formed in the first well region 303, the second source-drain regions 311 are formed in the second well region 305, the first source-drain regions 310 and the first well region 303 have different conduction types, and the second source-drain regions 311 and the second well region 305 have different conduction types.

[0070] In this embodiment, the first source-drain regions 310 have an N-type conduction type, and the second source-drain regions 311 have a P-type conduction type.

[0071] In this embodiment, a plurality of the resistor structures 307 are formed on the surface of the first isolation structure 301 between the adjacent first active regions 302 in the second direction Y, and the second direction Y is perpendicular to the first direction X.

[0072] In this embodiment, before forming the buffer material layer subsequently, at least one heat dissipation structure is further formed on the heat dissipation region C, the heat dissipation structure is disposed around the outside of a plurality of the resistor structures 307, the heat dissipation structure includes a plurality of heat dissipation layers 312, the plurality of heat dissipation layers 312 are arranged along the circumferential direction of the heat dissipation structure, the heat dissipation layer 312 is located on the surface of the first isolation structure 301, and each of the second active regions 306 is located between the adjacent heat dissipation layers 312.

[0073] Herein, the heat dissipation structure and the plurality of second active regions 306 are used to enable the resistor structures 307 at the periphery in the plurality of resistor structure arrays to have a heat dissipation environment similar to that of the resistor structures 307 in the middle, thereby reducing the influence of heat on the resistance value of the resistor structures 307, improving the uniformity of the resistance distribution of the resistor structures 307 on the resistor region, being beneficial to improving the resolution of the Kelvin frequency divider, and improving the performance of the Kelvin frequency divider.

[0074] It should be noted here that Figure 10 Two ring-shaped heat dissipation structures are shown. In other embodiments, the heat dissipation structure may be one or multiple.

[0075] It should be further noted that the plurality of second active regions 306 can be correspondingly arranged according to the sizes, positions, etc. of the heat dissipation layers 312 in the heat dissipation structure, and are not limited to Figure 10 as shown.

[0076] In this embodiment, the forming methods of the plurality of resistor structures 307, the plurality of gate structures and the plurality of heat dissipation layers 312 include: forming a gate material layer (not shown in the figure) on the surface of the substrate 300; patterning the gate material layer to form the plurality of resistor structures 307, the plurality of gate layers and the plurality of heat dissipation layers 312, and the gate structure includes the gate layer.

[0077] In this embodiment, the forming method of the plurality of resistor structures 307 further includes: implanting first doping ions into the plurality of resistor structures 307 to make the resistor structures 307 have a preset resistance value.

[0078] In this embodiment, the first doping ions are P-type conductive ions.

[0079] In another embodiment, the first doping ions may be N-type conductive ions.

[0080] In this embodiment, the material of the gate material layer includes polysilicon. That is, the materials of the resistance structure 307, the gate layer, and the heat dissipation layer 312 are all polysilicon.

[0081] In this embodiment, before forming the gate material layer, a gate oxide material layer (not shown in the figure) is further formed on the surface of the substrate 300; the gate oxide material layer is etched to form a gate oxide layer (not shown in the figure) between the gate layer and the substrate 300, and the gate structure further includes the gate oxide layer.

[0082] In this embodiment, the gate oxide layer is also formed between the resistance structure 307 and the substrate 300.

[0083] In this embodiment, after forming the gate layer, it further includes: forming a sidewall (not shown in the figure) on the sidewall of the gate layer, and the gate structure further includes the sidewall.

[0084] In this embodiment, the sidewall is also formed on the sidewall of the resistance structure 307.

[0085] In this embodiment, the method for forming the source-drain region includes: using the first gate structure 308 as a mask, injecting a second doping ion into the first well region 303 to form the first source-drain region 310. Using the second gate structure 309 as a mask, injecting a third doping ion into the second well region 305 to form the second source-drain region 311.

[0086] In this embodiment, the second doping ion is an N-type conductive ion, and the third doping ion is a P-type conductive ion.

[0087] In this embodiment, while forming the second source-drain region 311, the second doping ion is also injected into the first active region 302 and the second active region 306.

[0088] Please refer to Figure 12 , Figure 12 The view direction of Figure 11 , perform steps S203 and S204 to form a buffer material layer 313 on the surface of the substrate 300, the surfaces of several gate structures, and the surfaces of several resistance structures 307; form a stress material layer 314 on the surface of the buffer material layer 313.

[0089] The buffer material layer 313 has a first thickness.

[0090] In this embodiment, the range of the first thickness is 80 Å to 200 Å; the thickness range of the stress material layer 314 is 200 Å to 400 Å.

[0091] In this embodiment, the material of the buffer material layer 313 includes silicon oxide; the material of the stress material layer 314 includes silicon nitride.

[0092] In this embodiment, the formation process of the buffer material layer 313 includes plasma enhanced chemical vapor deposition; the formation process of the stress material layer 314 includes plasma enhanced chemical vapor deposition.

[0093] Please refer to Figure 13 , Figure 13 The view direction of Figure 12 is the same as that of

[0094] In this embodiment, the rapid thermal annealing treatment of the substrate 300, several gate structures, several resistor structures 307 and the stress material layer 314 includes: heating the substrate 300, several gate structures 307, several resistor structures 307 and the stress material layer 314 from the back surface of the substrate 300.

[0095] In this embodiment, the process parameters of the rapid thermal annealing treatment include: the process temperature range is 1010 °C to 1050 °C, and the process time range is 1 s to 3 s.

[0096] Please refer to Figure 14 , Figure 14 The view direction of Figure 13 is the same as that of

[0097] The process of removing the stress material layer 314 to expose the buffer material layer 313 includes one or both of a wet etching process and a dry etching process.

[0098] In this embodiment, the stress material layer 314 is removed by a wet etching process. Specifically, the stress material layer 314 is removed by etching with phosphoric acid.

[0099] Please refer to Figure 15 , Figure 15 The view direction of Figure 14 is the same as that of

[0100] In this embodiment, the formation process of the planarization material layer 315 includes a chemical vapor deposition process.

[0101] In this embodiment, the material of the planarization material layer 315 includes amorphous carbon.

[0102] Here, the buffer material layer 313 on the surface of the resistive structure 307 has a first protrusion height relative to the buffer material layer 313 on the surface of the substrate 300, and the planarization material layer 315 on the surface of the resistive structure 307 has a second protrusion height relative to the planarization material layer 315 on the surface of the substrate 300, and the second protrusion height is less than the first protrusion height. That is, the buffer material layer 313 makes the contact surface of the subsequent laser more planar.

[0103] In this embodiment, the buffer material layer 313 has a first thickness, and the planarization material layer 315 has a second thickness. The ratio range of the second thickness to the first thickness is from 15:1 to 60:1. The purpose of limiting the second thickness to the first thickness here is to improve the planarization of the substrate surface.

[0104] In this embodiment, the range of the second thickness is from 3000 Å to 5000 Å.

[0105] Please refer to Figure 16 , Figure 16 The view direction of Figure 15 is the same as

[0106] After forming the planarization material layer 315, perform step S208 to perform dynamic surface annealing treatment on the substrate 300, several gate structures, and several resistive structures 307.

[0107] At this point, the planarization material layer 315 makes the contact surface of the laser flat, which can reduce the influence of the pattern effect on the laser absorption, thereby improving the absorption efficiency of the laser. Moreover, in the dynamic surface annealing treatment, the laser does not need to be incident at the Brewster angle, so that the laser environment where each of the resistive structures 307 arranged in an array is located is the same. Thus, while improving the performance of MOS devices (especially NMOS devices) in the logic region by using the stress memory technology, the uniformity of the resistance distribution of the resistive structure 307 is improved as a whole, which is beneficial to improving the resolution of the Kelvin frequency divider and improving the performance of the Kelvin frequency divider.

[0108] In this embodiment, the process parameters of the dynamic surface annealing treatment include: the process temperature range is from 1200°C to 1300°C, and the process time range is from 2 minutes to 5 minutes.

[0109] In this embodiment, the dynamic surface annealing treatment of the substrate 300, several of the gate structures, and several of the resistor structures 307 includes: heating the substrate 300, several of the gate structures, and several of the resistor structures 307 from the front side of the substrate 300.

[0110] In this embodiment, after the dynamic surface annealing treatment, please also refer to Figure 17 .

[0111] Please refer to Figure 17 , Figure 17 The view direction of Figure 16 is the same as

[0112] In this embodiment, the process of removing the planarization material layer 315 includes an ashing process.

[0113] Here, it should be noted that while the planarization material layer 315 improves the absorption efficiency of the laser, since it is easily removed, the process of removing the planarization material layer 315 can reduce the adverse effects on the device performance.

[0114] In this embodiment, the process of removing the buffer material layer 313 includes a wet etching process.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a logic region and a resistance region; Forming a plurality of gate structures located on the logic region, a plurality of resistor structures located on the resistor region, and source and drain regions located in the logic region on both sides of each of the gate structures, wherein the resistor structures and the gate structures extend along a first direction, and the plurality of resistor structures are arranged in an array along the first direction; forming a buffer material layer on the surface of the substrate, the surfaces of the plurality of gate structures and the surfaces of the plurality of resistor structures; forming a stress material layer on the surface of the buffer material layer; Performing a rapid thermal annealing process on the substrate, the plurality of gate structures, the plurality of resistor structures and the stress material layer; After the rapid thermal annealing treatment, removing the stress material layer to expose the buffer material layer; forming a planarization material layer on the exposed surface of the buffer material layer; After forming the planarization material layer, a dynamic surface annealing process is performed on the substrate, the plurality of gate structures and the plurality of resistor structures.

2. The method for forming a semiconductor structure according to claim 1, wherein: The resistance region includes a main region and a peripheral region, and the peripheral region surrounds the main region; before forming a plurality of gate structures and a plurality of the resistance structures, it also includes: forming a first isolation structure in the peripheral region and the main region, and forming a plurality of first active regions in the main region, wherein the plurality of first active regions are arranged in an array along the first direction, and the first isolation structure is located between adjacent first active regions; forming a first well region, a second isolation structure, and a second well region in the logic region, wherein the second isolation structure is located between the first well region and the second well region, and the first well region and the second well region have different conductivity types.

3. The method for forming a semiconductor structure according to claim 2, wherein: The plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, the plurality of source and drain regions include a plurality of first source and drain regions and a plurality of second source and drain regions, the first source and drain regions and the second source and drain regions have different conductivity types, the first gate structure is formed on the first well region, the second gate structure is formed on the second well region, the first source and drain region is formed in the first well region, the second source and drain region is formed in the second well region, the first source and drain region and the first well region have different conductivity types, and the second source and drain region and the second well region have different conductivity types.

4. The method for forming a semiconductor structure according to claim 2, wherein: A plurality of the resistance structures are formed on the surface of the first isolation structure between adjacent first active regions in a second direction, and the second direction is perpendicular to the first direction.

5. The method for forming a semiconductor structure according to claim 2, wherein: The resistance area also includes a heat dissipation area, and the heat dissipation area is located between the main area and the peripheral area; the method also includes: forming a plurality of second active areas in the heat dissipation area, and the plurality of second active areas surround the plurality of first active areas and are arranged along their surrounding direction; before forming the buffer material layer, it also includes: forming at least one heat dissipation structure on the heat dissipation area, and the heat dissipation structure is arranged in a surrounding manner outside the plurality of resistance structures, and the heat dissipation structure includes a plurality of heat dissipation layers, and the plurality of heat dissipation layers are arranged along the surrounding direction of the heat dissipation structure, and the heat dissipation layer is located on the surface of the first isolation structure, and each of the second active areas is located between adjacent heat dissipation layers.

6. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the plurality of the resistor structures, the gate structures and the heat dissipation layers comprises: forming a gate material layer on the surface of the substrate; patterning the gate material layer to form the plurality of the resistor structures, the gate layers and the heat dissipation layers, wherein the gate structure comprises the gate layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The buffer material layer has a first thickness, the planarization material layer has a second thickness, and a ratio of the second thickness to the first thickness ranges from 15:1 to 60:

1.

8. The method for forming a semiconductor structure according to claim 7, wherein: The second thickness ranges from 3000Å ​​to 5000Å.

9. The method for forming a semiconductor structure according to claim 1, wherein: The buffer material layer on the surface of the resistor structure has a first protrusion height relative to the buffer material layer on the substrate surface, and the planarization material layer on the surface of the resistor structure has a second protrusion height relative to the planarization material layer on the substrate surface, and the second protrusion height is smaller than the first protrusion height.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the planarization material layer includes amorphous carbon.

11. The method for forming a semiconductor structure according to claim 1, wherein: The substrate has a front side and a back side opposite to each other, and a plurality of the gate structures, a plurality of the resistor structures and the stress material layer are located on the front side.

12. The method for forming a semiconductor structure according to claim 11, wherein: The rapid thermal annealing treatment of the substrate, the gate structures, the resistor structures and the stress material layer includes: heating the substrate, the gate structures, the resistor structures and the stress material layer from the back side of the substrate.

13. The method for forming a semiconductor structure according to claim 11, wherein: The performing of dynamic surface annealing treatment on the substrate, the gate structures and the resistor structures comprises: heating the substrate, the gate structures and the resistor structures from the front side of the substrate.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the buffer material layer includes silicon oxide; the material of the stress material layer includes silicon nitride.

15. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the rapid thermal annealing treatment include: a process temperature range of 1010° C. to 1050° C., and a process time range of 1 s to 3 s.

16. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the dynamic surface annealing treatment include: a process temperature range of 1200° C. to 1300° C., and a process time range of 2 min to 5 min.

17. The method for forming a semiconductor structure according to claim 1, wherein: After the dynamic surface annealing treatment, the method further includes: removing the planarization material layer; the process of removing the planarization material layer includes an ashing process.

18. The method for forming a semiconductor structure according to claim 17, wherein: After removing the planarization material layer, the method further includes: removing the buffer material layer; the process of removing the buffer material layer includes a wet etching process.

19. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the buffer material layer ranges from 80Å to 200Å; the thickness of the stress material layer ranges from 200Å to 400Å.

20. The method for forming a semiconductor structure according to claim 1, wherein: The forming process of the buffer material layer includes plasma enhanced chemical vapor deposition; the forming process of the stress material layer includes plasma enhanced chemical vapor deposition; and the forming process of the planarization material layer includes a chemical vapor deposition process.

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