Preparation method of stacked transistor, stacked transistor and semiconductor device

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: forming a fin-shaped structure on a semiconductor substrate, wherein the fin-shaped structure comprises a first fin-shaped structure and a second fin-shaped structure; sequentially forming a first source-drain structure, a first gate structure and first source-drain metal based on the first fin-shaped structure; on the basis of the second fin-shaped structure, a second source-drain structure, a second gate structure and second source-drain metal are sequentially formed; a back side through hole structure and a back side power supply rail are formed on the second gate structure and the second source drain metal to obtain a back side transistor, and the back side power supply rail is communicated with the second source drain metal and the first gate structure through the back side through hole structure; and forming a front through hole structure and a front power supply rail on the first gate structure and the first source drain metal to obtain a front transistor, and the front power supply rail is respectively communicated with the first source drain metal and the second gate structure through the front through hole structure.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and particularly to a method for manufacturing a stacked transistor, a stacked transistor, and a semiconductor device. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, the stacked transistor can further improve the transistor integration density, and has become one of the important technologies for continuing the miniaturization of integrated circuit size.

[0003] In some solutions for manufacturing a stacked transistor, the active regions of the upper and lower layers of homogeneous transistors are formed by etching, and the stacked transistor is fabricated on the front and back sides of the wafer by flipping the wafer. This can also be called the "self-aligned flip transistor" solution. However, the front and back structures of the "self-aligned flip transistor" have a mirror symmetry relationship, resulting in complex internal wiring of the transistor during the process of forming a decoupling capacitor (decap cell) based on the "self-aligned flip transistor", great manufacturing difficulty, and being not conducive to the miniaturization of integrated circuits. Summary of the Invention

[0004] This application provides a method for manufacturing a stacked transistor, a stacked transistor, and a semiconductor device, so as to realize an interleaved design using a front power rail and a back power rail, thereby enabling the interconnection lines inside the decoupling capacitor to be realized through a front via structure and a back via structure, effectively reducing the manufacturing difficulty, and not increasing the transistor cell size, which helps to further improve the integration degree of the circuit.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked transistor, including: forming a fin structure on a semiconductor substrate, where the fin structure includes a first fin structure and a second fin structure stacked along a first direction; based on the first fin structure, sequentially forming a first source-drain structure, a first gate structure, and a first source-drain metal, where the first source-drain metal covers the first source-drain structure, and the first source-drain metal is farther from the second fin structure than the first source-drain structure; based on the second fin structure, sequentially forming a second source-drain structure, a second gate structure, and a second source-drain metal, where the second source-drain structure and the first source-drain structure are stacked along the first direction, and the second gate structure and the first gate structure are stacked along the first direction; the second source-drain metal covers the second source-drain structure, and the second source-drain metal is farther from the first fin structure than the second source-drain structure; forming a back via structure and a back power rail on the second gate structure and the second source-drain metal to obtain a back transistor, where the back power rail is connected to the second source-drain metal and the first gate structure respectively through the back via structure; forming a front via structure and a front power rail on the first gate structure and the first source-drain metal to obtain a front transistor, where the front power rail is connected to the first source-drain metal and the second gate structure respectively through the front via structure; the front power rail is located on a first side of the fin structure in a second direction, and the back power rail is located on a second side of the fin structure in the second direction, the first side and the second side are opposite, and the second direction is perpendicular to the first direction.

[0006] In some possible implementation manners, based on the second fin structure, sequentially forming a second source-drain structure, a second gate structure, and a second source-drain metal includes: based on the second fin structure, sequentially forming a second source-drain structure and a second gate structure; removing a first part of the second gate structure and retaining a second part of the second gate structure to form a back trench, and depositing an insulating material in the back trench to form a back isolation structure; where the first part and the second part of the second gate structure are arranged along a second direction; forming a second source-drain metal on the second source-drain structure; forming a back via structure and a back power rail on the second gate structure and the second source-drain metal includes: forming a back dielectric layer on the back isolation structure, the second gate structure, and the second source-drain metal; etching the back dielectric layer until the second source-drain metal is exposed to form a back source-drain metal via, and etching the back dielectric layer and the back isolation structure until the first gate structure is exposed to form a back gate metal via; depositing a metal in the back source-drain metal via and the back gate metal via to respectively form a back source-drain via structure and a back gate via structure; where the back source-drain via structure and the back gate via structure are included in the back via structure; forming a back power rail on the back dielectric layer, where the back power rail is connected to the second source-drain metal through the back source-drain via structure, and the back power rail is connected to the first gate structure through the back gate via structure.

[0007] In some possible embodiments, based on the first fin structure, a first source / drain structure, a first gate structure, and a first source / drain metal are sequentially formed, including: based on the first fin structure, the first source / drain structure and the first gate structure are sequentially formed; a first portion of the first gate structure is removed, and a second portion of the first gate structure is retained to form a front trench, and an insulating material is deposited in the front trench to form a front isolation structure; wherein, the first portion of the first gate structure and the second portion of the second gate structure are arranged along a second direction; the front isolation structure is located on a first side of the fin structure, and the back isolation structure is located on a second side of the fin structure; the first source / drain metal is formed on the first source / drain structure.

[0008] In some possible embodiments, a front via structure and a front power rail are formed on the first gate structure and the first source / drain metal, including: a front dielectric layer is formed on the front isolation structure, the first gate structure, and the first source / drain metal; the front dielectric layer is etched until the first source / drain metal is exposed to form a front source / drain metal via, and the front dielectric layer and the front isolation structure are etched until the second gate structure is exposed to form a front gate metal via; a metal is deposited in the front source / drain metal via and the front gate metal via to respectively form a front source / drain via structure and a front gate via structure; wherein, the front source / drain via structure and the front gate via structure are included in the front via structure; a front power rail is formed on the front dielectric layer, wherein the front power rail is connected to the first source / drain metal through the front source / drain via structure, and the front power rail is connected to the second gate structure through the front gate via structure.

[0009] In some possible embodiments, after a back metal interconnect layer is formed on the second gate structure and the second source / drain metal, the method further includes: forming a back insulating layer on the back metal interconnect layer; bonding the back carrier wafer to the back insulating layer, and flipping the bonded back carrier wafer; before forming the front via structure and the front power rail on the first gate structure and the first source / drain metal, the method further includes: removing the back carrier wafer and the back insulating layer to expose the first gate structure and the first source / drain metal.

[0010] In some possible embodiments, the extending direction of the front power rail and the back power rail is a third direction, and the third direction is perpendicular to the first direction and the second direction; the projection of the front via structure along the first direction falls within the projection of the front power rail along the first direction; the projection of the back via structure along the first direction falls within the projection of the back power rail along the first direction.

[0011] Second aspect, an embodiment of the present application provides a stacked transistor, which includes: a front transistor, the front transistor includes: a first source / drain structure, a first gate structure, a first source / drain metal, and a front metal interconnect layer; a back transistor, the back transistor includes: a second source / drain structure, a second gate structure, a second source / drain metal, and a back metal interconnect layer; the front transistor and the back transistor are stacked along a first direction; wherein, the front metal interconnect layer includes a front power rail and a front via structure, and the front power rail is respectively connected to the first source / drain metal and the second gate structure through the front via structure; the back metal interconnect layer includes a back power rail and a back via structure, and the back power rail is respectively connected to the second source / drain metal and the first gate structure through the back via structure; the front power rail is located on a first side of the fin structure in a second direction, the back power rail is located on a second side of the fin structure in the second direction, the first side and the second side are opposite to each other, and the second direction is perpendicular to the first direction.

[0012] In some possible implementation manners, the extending directions of the front power rail and the back power rail are a third direction, and the third direction is perpendicular to the first direction and the second direction; the projection of the front via structure along the first direction falls within the projection of the front power rail along the first direction; the projection of the back via structure along the first direction falls within the projection of the back power rail along the first direction.

[0013] In some possible implementation manners, the front via structure includes: a front source / drain via structure and a front gate via structure; the front power rail is connected to the first source / drain metal through the front source / drain via structure, and the front power rail is connected to the second gate structure through the front gate via structure; the back via structure includes: a back source / drain via structure and a back gate via structure; the back power rail is connected to the second source / drain metal through the back source / drain via structure, and the back power rail is connected to the first gate structure through the back gate via structure.

[0014] Third aspect, an embodiment of the present application provides a semiconductor device, which includes: the stacked transistor as described in the above embodiment.

[0015] In the embodiments of the present application, based on a first fin structure and a second fin structure stacked along a first direction, a front transistor and a back transistor can be respectively fabricated, thereby realizing self-aligned flip stacking of transistors. During the process of forming the back-end metal interconnect layers of the front transistor and the back transistor, a front power rail is fabricated on the first side of the fin structure, and a back power rail is fabricated on the second side opposite to the first side. Thus, on one side of the stacked transistors, the front power rail is connected to the first source / drain metal and the second gate structure respectively through front vias; on the other side of the stacked transistors, the back power rail is connected to the second source / drain metal and the first gate structure respectively through back vias. It can be seen that the front power rail and the back power rail adopt an interleaved design, so that the interconnection lines inside the decoupling capacitor can be realized through the front vias and the back vias. On the one hand, there is no need to rely on complex back-end metal lines, effectively reducing the complexity of the fabrication process; on the other hand, there is no need to increase the area of the transistors, effectively improving the integration performance of the stacked transistors.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of a circuit composition of a decoupling capacitor in an embodiment of the present application;

[0019] Figure 2 In an embodiment of the present application Figure 1 A schematic diagram of a layout of the decoupling capacitor shown;

[0020] Figure 3 A schematic flow chart of an implementation process of a method for fabricating stacked transistors in an embodiment of the present application;

[0021] Figures 4 to 18 A schematic diagram of a fabrication process of stacked transistors in an embodiment of the present application.

[0022] In the above figures: 11, front transistor; 112, first source / drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source / drain metal; 116, front metal interconnect layer; 12, back transistor; 122, second source / drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source / drain metal; 126, back metal interconnect layer;

[0023] 20. Semiconductor substrate; 21. Fin structure; 211. First fin structure; 212. Second fin structure; 22. Shallow trench isolation structure; 23. First dummy gate structure; 24. Front isolation structure; 25. Front insulating layer; 26. Front carrier wafer; 27. Second dummy gate structure; 28. Back isolation structure; 29. Back dielectric layer; 30. Back source / drain via structure; 31. Back gate via structure; 32. Back power rail; 33. Back insulating layer; 34. Back carrier wafer; 35. Front dielectric layer; 36. Front source / drain via structure; 37. Front gate via structure; 38. Front power rail. Detailed implementation manners

[0024] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present application.

[0025] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By three-dimensional transistor stacking, stacked transistors can achieve the integration of two or more layers of transistors in the vertical space, which helps to further improve the transistor integration density and circuit performance, and is considered to be one of the important technologies to continue the miniaturization of integrated circuit size.

[0026] In one embodiment, there are two schemes for the manufacturing process of stacked transistors. The first is the monolithic scheme, and the second is the sequential scheme.

[0027] For the first scheme, N field effect transistors (NFET) and P field effect transistors (PFET) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, that is, NFET or PFET. Moreover, the upper and lower layer transistors must be strictly in the same planar space without alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) The process is complex and a large amount of process technology development and optimization are required; (2) The polarity of each layer of transistors is fixed, and it is necessary to rely on two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0028] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding a wafer on top of the previously fabricated lower transistor, stacking the two transistors vertically. However, during the thermal process of fabricating the upper transistor, the temperature needs to be strictly controlled to avoid affecting the lower transistor and the interconnecting lines. The advantage of this solution is that due to wafer bonding, the device structures, channel crystal orientations, and even channel materials used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0029] To solve the technical problems existing in the above two solutions, a "self-aligned flip-chip transistor" solution is proposed. This "self-aligned flip-chip transistor" solution forms the active regions of the upper and lower homologous transistors through etching and realizes the fabrication of stacked transistors on the front and back sides of the wafer by flipping the wafer, so as to overcome the disadvantages of the above two solutions.

[0030] For the complementary field-effect transistor (CFET) formed by the above "self-aligned flip-chip transistor" solution, since the power supply lines and signal lines are both arranged on the front side of the transistor, for relatively complex metal interconnections, such as when forming decoupling capacitors with a cross-coupled structure, there may be difficulties in wiring and processing. At the same time, for the industry-standard common-gate CFET, there may also be a problem of an increase in the design area of the standard cell. Therefore, there is an urgent need to provide a decoupling capacitor design solution that can overcome the above difficulties.

[0031] In some embodiments, a decoupling capacitor is a capacitor installed at the power supply terminal of a component in a circuit. This capacitor can provide a relatively stable power supply and at the same time reduce the noise coupled by the component to the power supply terminal, indirectly reducing the influence of the noise of this component on other components.

[0032] In some embodiments, the decoupling capacitor can be composed of a parallel connection of an N-type Metal-Oxide-Semiconductor (NMOS) transistor and a P-type Metal-Oxide-Semiconductor (PMOS) transistor.

[0033] Therefore, the embodiments of the present application provide a method for fabricating a stacked transistor, a stacked transistor, and a semiconductor device to achieve the use of

[0034] Figure 1 This is a schematic diagram of a circuit composition of a decoupling capacitor in the embodiments of the present application. Refer to Figure 1As shown, between the power supply rail VDD and the power supply rail VSS, two transistors with opposite polarities can be connected in parallel to form a decoupling capacitor. Among them, one of the two transistors is an NMOS transistor, and the other is a PMOS transistor. The source and drain of the NMOS transistor are short-circuited and connected to the power supply rail VSS, and the gate is connected to the power supply rail VDD. The source and drain of the PMOS transistor are short-circuited and connected to the power supply rail VDD, and the gate is connected to the power supply rail VSS.

[0035] Figure 2 For the Figure 1 schematic diagram of a layout of the decoupling capacitor shown in this embodiment of the present application, see Figure 2 as shown, Figure 2 shows an NMOS transistor and a PMOS transistor. The NMOS transistor and the PMOS transistor can be composed of structures such as a fin structure, a gate structure, source-drain metal, a single diffusion isolation structure, a metal interconnect layer, a gate metal structure, and a source-drain metal structure. Among them, the power supply rail VDD and the power supply rail VSS are included in the metal interconnect layer.

[0036] Here, according to Figure 2 the layout shown, the NMOS transistor and the PMOS transistor are stacked transistors.

[0037] In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked transistor. Figure 3 For the schematic implementation process diagram of the method for manufacturing a stacked transistor in this embodiment of the present application, see Figure 3 as shown, to prepare and form the Figures 1 to 2 structure shown, the method for manufacturing a stacked transistor may include:

[0038] Step S301: Form a fin structure on a semiconductor substrate, where the fin structure includes a first fin structure and a second fin structure stacked along a first direction;

[0039] Step S302: Based on the first fin structure, sequentially form a first source-drain structure, a first gate structure, and a first source-drain metal, where the first source-drain metal covers the first source-drain structure, and the first source-drain metal is farther from the second fin structure than the first source-drain structure;

[0040] Step S303: Based on the second fin structure, sequentially form a second source-drain structure, a second gate structure, and a second source-drain metal, where the second source-drain structure and the first source-drain structure are stacked along the first direction, and the second gate structure and the first gate structure are stacked along the first direction; the second source-drain metal covers the second source-drain structure, and the second source-drain metal is farther from the first fin structure than the second source-drain structure;

[0041] Step S304: Form a back via structure and a back power rail over the second gate structure and the second source / drain metal to obtain a back transistor, wherein the back power rail is connected to the second source / drain metal and the first gate structure respectively through the back via structure;

[0042] Step S305: Form a front via structure and a front power rail over the first gate structure and the first source / drain metal to obtain a front transistor, wherein the front power rail is connected to the first source / drain metal and the second gate structure respectively through the front via structure; the front power rail is located on a first side of the fin structure in a second direction, and the back power rail is located on a second side of the fin structure in the second direction, the first side and the second side are opposite to each other, and the second direction is perpendicular to the first direction.

[0043] It should be noted that Figure 3 the steps shown in Figure 3 are not exclusive, and other steps may also be performed before, after or between any of the steps shown;

[0044] In step S301, a fin structure is formed on the semiconductor substrate.

[0045] In some embodiments, when fabricating a stacked transistor, a semiconductor substrate may be provided first. The semiconductor substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, etc. Secondly, a plurality of fin structures standing upright on the semiconductor substrate may be formed on the semiconductor substrate.

[0046] In some embodiments, when the stacked transistor is a fin field-effect transistor, step S301 may include: forming a semiconductor epitaxial layer on the surface of the semiconductor substrate through an epitaxial growth process; etching the semiconductor epitaxial layer to a certain depth in the semiconductor epitaxial layer or to the surface of the semiconductor substrate or to a certain depth in the substrate, so as to form a plurality of fin structures.

[0047] In some embodiments, when the stacked transistor is a gate-all-around transistor, step S301 may include: performing processes such as material layer deposition and epitaxial growth over the semiconductor substrate to form a stacked structure on the semiconductor substrate. Subsequently, the stacked structure is etched using a single etching process to form a fin structure on the semiconductor substrate.

[0048] In the embodiments of the present application, since the stacked transistors include upper and lower layers of transistors (composed of a front transistor and a back transistor), and the active structures of the upper and lower layers of transistors are formed by the same etching process. That is, the first active structure of the front transistor and the second active structure of the back transistor are formed by the same etching process. Therefore, when etching the semiconductor substrate, a relatively large etching depth can be adopted. For example, the height of the fin structure obtained by etching can be greater than 100 nm. It should be noted that the height of the fin structure can be set according to actual situations, and the embodiments of the present application do not limit this.

[0049] In some embodiments, the fin structure includes a first fin structure and a second fin structure. The first fin structure and the second fin structure are stacked along a first direction (perpendicular to the direction of the semiconductor substrate), and the second fin structure is closer to the semiconductor substrate than the first fin structure. It can be understood that the first fin structure is used to form the active region of the front transistor in subsequent steps; the second fin structure is used to form the active region of the back transistor in subsequent steps.

[0050] In step S302, based on the first fin structure, a first source / drain structure, a first gate structure, and a first source / drain metal are sequentially formed.

[0051] It can be understood that based on the first fin structure, semiconductor standard preparation processes can be used to sequentially prepare and form a first source / drain structure, a first gate structure, and a first source / drain metal. Among them, the first source / drain metal covers the first source / drain structure, and the first source / drain metal is farther away from the second fin structure than the first source / drain structure.

[0052] It should be noted that the preparation processes of the first source / drain structure, the first gate structure, and the first source / drain metal can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0053] In some embodiments, step S302 may include: based on the first fin structure, sequentially forming a first source / drain structure and a first gate structure; removing a first part of the first gate structure and retaining a second part of the first gate structure to form a front trench, and depositing an insulating material in the front trench to form a front isolation structure. A first source / drain metal is formed on the first source / drain structure.

[0054] In one embodiment, the first part of the first gate structure and the second part of the second gate structure are arranged along a second direction. In one embodiment, a gate cutting process is used to remove the first part of the first gate structure and retain the second part of the first gate structure.

[0055] In one embodiment, the first part of the first gate structure is located on one side of the first fin structure in the second direction, and the second part of the first gate structure can wrap the first fin structure.

[0056] In some embodiments, the first gate structure may be composed of a first gate dielectric layer and a first gate electrode layer.

[0057] In some embodiments, the materials of the first gate dielectric layer and the first gate electrode layer can be set according to actual requirements, and the embodiments of the present application do not limit this. Exemplarily, the first gate dielectric layer may be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thicknesses of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. Exemplarily, the first gate electrode layer may be composed of multiple layers of electrode materials, and each layer of electrode materials includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In one example, the first gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0058] In some embodiments, the front isolation structure is used to electrically isolate two adjacent transistor units. Or, the front isolation structure is used to isolate the front gate via structure from the first gate structure.

[0059] In one embodiment, the insulating material for forming the front isolation structure may be silicon nitride (Si 3 N 4 ).

[0060] In some embodiments, based on the first fin structure, a first source / drain structure and a first gate structure are sequentially formed, including: depositing an insulating material on the semiconductor substrate to form a shallow trench isolation (STI) structure. On the shallow trench isolation structure, based on the first fin structure, a dummy gate structure is formed in the gate region of the stacked transistors. After the first source / drain structure is formed in the source / drain region of the stacked transistors, the dummy gate structure is removed to form the first gate structure at the position where the dummy gate structure is removed.

[0061] In one embodiment, the insulating material for forming the shallow trench isolation structure may be silicon-based oxide (SiOx, where x is the number of oxygen atoms), for example, silicon dioxide (SiO 2 ).

[0062] In some embodiments, the material for forming the dummy gate structure may be a dummy gate material such as polysilicon or amorphous silicon.

[0063] In some embodiments, after the dummy gate structure is formed, an insulating material may be deposited on the sidewalls of the dummy gate structure to form a dummy gate sidewall covering the sidewalls of the dummy gate structure.

[0064] In one embodiment, the insulating material for forming the dummy gate sidewall may be silicon dioxide.

[0065] In some embodiments, forming the first source / drain metal on the first source / drain structure includes: etching the first interlayer dielectric layer wrapping the first source / drain structure until the first source / drain structure is exposed to form a first source / drain metal groove; depositing a metal material in the first source / drain metal groove to form the first source / drain metal. Here, the length of the first source / drain metal in the second direction can be selected according to actual needs so that the first source / drain metal is located below the front source / drain metal via formed in subsequent preparation.

[0066] In some embodiments, after step S302, it may include: depositing an insulating material on the first gate structure and the first source / drain metal to form a front insulating layer; bonding the front carrier wafer to the front insulating layer and flipping the bonded front carrier wafer.

[0067] In step S303, based on the second fin structure, a second source / drain structure, a second gate structure, and a second source / drain metal are sequentially formed.

[0068] It can be understood that based on the second fin structure, a semiconductor standard fabrication process can be used to sequentially fabricate a second source / drain structure, a second gate structure, and a second source / drain metal. Among them, the second source / drain metal covers the second source / drain structure, and the second source / drain metal is farther from the first fin structure than the second source / drain structure.

[0069] Among them, the second source / drain structure and the first source / drain structure are stacked in the first direction, and the second gate structure and the first gate structure are stacked in the first direction.

[0070] In some embodiments, step S303 may include: based on the second fin structure, sequentially forming the second source / drain structure and the second gate structure; removing the first part of the second gate structure and retaining the second part of the second gate structure to form a back trench, and depositing an insulating material in the back trench to form a back isolation structure. Forming the second source / drain metal on the second source / drain structure.

[0071] In some embodiments, the second source / drain metal and the first source / drain metal are staggered in the first direction. Among them, the second source / drain metal is on the side close to the back power rail in the second direction, and the first source / drain metal is on the side close to the front power rail in the second direction.

[0072] In some embodiments, the first part of the second gate structure and the second part of the second gate structure are arranged in the second direction. In one embodiment, the first part of the second gate structure is removed by a gate resection process, and the second part of the second gate structure is retained.

[0073] In one embodiment, a first portion of the second gate structure is located on one side of the second fin structure in a second direction, and a second portion of the second gate structure may wrap the second fin structure. It should be noted that the first portion of the second gate structure may be disposed opposite to the second portion of the first gate structure, and the second portion of the second gate structure may be disposed opposite to the first portion of the first gate structure. That is to say, the front isolation structure is located on the first side of the fin structure in the second direction, and the back isolation structure is located on the second side of the fin structure in the second direction.

[0074] In some embodiments, the second gate structure may be composed of a second gate dielectric layer and a second gate electrode layer. The materials of the second gate dielectric layer and the second gate electrode layer can be set according to actual needs, and the embodiments of the present application do not limit this.

[0075] In some embodiments, the back isolation structure is used to electrically isolate two adjacent transistor units. Or, the back isolation structure is used to isolate the back gate via structure and the second gate structure.

[0076] In one embodiment, the insulating material forming the back isolation structure may be the same as the insulating material forming the front isolation structure. In one embodiment, the insulating material forming the back isolation structure may be different from the insulating material forming the front isolation structure.

[0077] In some embodiments, based on the second fin structure, a second source / drain structure and a second gate structure are sequentially formed, including: removing the semiconductor substrate to expose the shallow trench isolation structure; thinning the shallow trench isolation structure to expose the second fin structure; based on the second fin structure, forming a dummy gate structure in the gate region of the stacked transistor; after forming the second source / drain structure in the source / drain region of the stacked transistor, removing the dummy gate structure to form the second gate structure at the position where the dummy gate structure is removed.

[0078] In some embodiments, forming the second source / drain metal on the second source / drain structure includes: etching the second interlayer dielectric layer wrapping the second source / drain structure until the second source / drain structure is exposed to form a second source / drain metal groove; depositing a metal material in the second source / drain metal groove to form the second source / drain metal. Here, the length of the second source / drain metal in the second direction can be selected according to actual needs so that the second source / drain metal is located below the subsequently formed back source / drain metal via.

[0079] In step S304, a back via structure and a back power rail are formed on the second gate structure and the second source / drain metal.

[0080] It can be understood that after forming the second gate structure and the second source / drain metal, a back via structure can be formed. Subsequently, standard back-end processes in semiconductor manufacturing (such as deposition of interconnection dielectrics, formation of metal lines, formation of lead pads, etc.) can be employed on the second gate structure and the second source / drain metal to form a back metal interconnection layer. The back metal interconnection layer includes a back power rail and a first metal line (M0 metal line). The back power rail can be connected to the second source / drain metal and the first gate structure respectively through the back via structure.

[0081] In some embodiments, step S304 may include: forming a back dielectric layer on the back isolation structure, the second gate structure, and the second source / drain metal; etching the back dielectric layer until the second source / drain metal is exposed to form a back source / drain metal via, and etching the back dielectric layer and the back isolation structure until the first gate structure is exposed to form a back gate metal via; depositing metal in the back source / drain metal via and the back gate metal via to form a back source / drain via structure and a back gate via structure respectively; forming a back power rail on the back dielectric layer.

[0082] It can be understood that according to the position of the back power rail, etching the back dielectric layer (i.e., the back dielectric layer above the second source / drain metal) until the second source / drain metal is exposed can form a back source / drain metal via. According to the position of the back power rail, etching the back dielectric layer (i.e., the back dielectric layer above the back isolation structure) and the back isolation structure until the first gate structure is exposed can form a back gate metal via.

[0083] The back source / drain via structure and the back gate via structure are included in the back via structure. The back power rail is connected to the second source / drain metal through the back source / drain via structure, and the back power rail is connected to the first gate structure through the back gate via structure.

[0084] In one embodiment, the back source / drain via structure and the back gate via structure can be directly connected. In one embodiment, the back source / drain via structure and the back gate via structure can be indirectly connected through the back power rail.

[0085] In some embodiments, the back power rail can be connected to a positive power pin and has a positive power voltage. In one embodiment, the back power rail can be the power rail VDD. In some embodiments, the back power rail is the power rail VDD disposed in the back metal interconnection layer. It can be understood that the back metal interconnection layer can be a conductive layer for signal transmission and power distribution inside the stacked transistors. In one embodiment, the back metal interconnection layer further includes metal lines different from the back power rail, which can also be referred to as M0 metal lines.

[0086] In some embodiments, the material for forming the back dielectric layer may be a dielectric material, such as silicon nitride, aluminum oxide, etc.

[0087] In one embodiment, after forming the back metal interconnect layer, the second source / drain structure, the second gate structure, the second source / drain metal, the back vias structure, and the back metal interconnect layer together constitute a back transistor.

[0088] In some embodiments, after step S304, it may include: forming a back insulating layer on the back metal interconnect layer; bonding the back carrier wafer to the back insulating layer, and flipping the bonded back carrier wafer.

[0089] It can be understood that flipping the bonded back carrier wafer can make the back transistor located in the lower layer, which is convenient for continuing to fabricate the front transistor.

[0090] In one embodiment, an insulating material is deposited on the back metal interconnect layer to form a back insulating layer. In one embodiment, the insulating material for forming the back insulating layer can be set according to actual requirements, and the embodiments of the present application do not limit this.

[0091] In step S305, a front via structure and a front power rail are formed on the first gate structure and the first source / drain metal.

[0092] It can be understood that after forming the back transistor, the front transistor can be fabricated. After forming the first gate structure and the first source / drain metal, a back via structure can be formed, and then a front metal interconnect layer is formed by using standard back-end processes in semiconductor fabrication (such as inter-metal dielectric deposition, metal line formation, lead pad formation, etc.). The front metal interconnect layer includes a front power rail and a first metal line (M0 metal line). The front power rail is connected to the first source / drain metal and the second gate structure respectively through the front via structure; the front power rail is located on the first side of the fin structure, and the back power rail is located on the second side of the fin structure.

[0093] In some embodiments, step S305 may include: forming a front dielectric layer on the front isolation structure, the first gate structure, and the first source / drain metal; etching the front dielectric layer until the first source / drain metal is exposed to form a front source / drain metal via, and etching the front dielectric layer and the front isolation structure until the second gate structure is exposed to form a front gate metal via; depositing metal in the front source / drain metal via and the front gate metal via to form a front source / drain via structure and a front gate via structure respectively; forming a front power rail on the front dielectric layer.

[0094] It can be understood that, according to the position of the positive power rail, the positive dielectric layer (i.e., the positive dielectric layer located above the first source / drain metal) is etched until the first source / drain metal is exposed, and a positive source / drain metal via can be formed. According to the position of the positive power rail, the positive dielectric layer (i.e., the positive dielectric layer located above the positive isolation structure), the positive isolation structure are etched until the second gate structure is exposed, and a positive gate metal via can be formed.

[0095] Among them, the positive source / drain via structure and the positive gate via structure are included in the positive via structure. The positive power rail is connected to the first source / drain metal through the positive source / drain via structure, and the positive power rail is connected to the second gate structure through the positive gate via structure.

[0096] In one embodiment, the positive source / drain via structure and the positive gate via structure can be directly connected. In one embodiment, the positive source / drain via structure and the positive gate via structure can be indirectly connected through the positive power rail.

[0097] In some embodiments, the positive power rail can be connected to a negative power pin and has a negative power voltage. In one embodiment, the positive power rail can be the power rail VSS. In some embodiments, the back power rail is the power rail VSS disposed in the positive metal interconnect layer. It can be understood that the positive metal interconnect layer can be a conductive layer for signal transmission and power distribution inside the stacked transistors. In one embodiment, the positive metal interconnect layer further includes metal lines different from the back power rail, which can also be called M0 metal lines.

[0098] In some embodiments, the material for forming the positive dielectric layer can be a dielectric material, such as silicon nitride, aluminum oxide and other materials.

[0099] In some embodiments, before step S305, it can include: removing the positive carrier wafer and the positive insulating layer to expose the first gate structure and the first source / drain metal.

[0100] In one embodiment, after forming the positive metal interconnect layer, the first source / drain structure, the first gate structure, the first source / drain metal, the positive via structure and the positive metal interconnect layer together constitute a positive transistor.

[0101] In the embodiment of the present application, based on the first fin structure and the second fin structure stacked in the first direction, a front transistor and a back transistor can be respectively fabricated, thereby realizing self-aligned flip-chip stacking of transistors. During the process of forming the back-end metal interconnect layers of the front transistor and the back transistor, a front power rail is fabricated on the first side of the fin structure, and a back power rail is fabricated on the second side opposite to the first side. Thus, on one side of the stacked transistors, the front power rail is connected to the first source / drain metal and the second gate structure respectively through the front via structure; on the other side of the stacked transistors, the back power rail is connected to the second source / drain metal and the first gate structure respectively through the back via structure. It can be seen that the front power rail and the back power rail adopt an interleaved design, so that the interconnecting wires inside the decoupling capacitor can be realized through the front via structure and the back via structure. On the one hand, there is no need to rely on complex back-end metal wires, effectively reducing the complexity of the fabrication process; on the other hand, there is no need to increase the area of the transistors, effectively improving the integration performance of the stacked transistors.

[0102] Next, a specific example is used to introduce the fabrication method of the stacked transistors in the embodiment of the present application. Figures 4 to 18 is a schematic diagram of a fabrication process of the stacked transistors in the embodiment of the present application. For easy understanding, Figures 4 to 18 in (a) shows a cross-sectional view along Figure 2 the dashed line A-A' direction in Figures 4 to 18 in (b) shows a cross-sectional view along Figure 2 the dashed line B-B' direction in Figures 4 to 18 in (c) shows a cross-sectional view along Figure 2 the dashed line C-C' direction in. Combining Figures 1 to 18 , the fabrication method of the stacked transistors may include:

[0103] The first step, as shown in Figure 4 , the fin structure 21 is formed on the semiconductor substrate 20 (silicon wafer) by using an etching process. The fin structure 21 includes a first fin structure 211 and a second fin structure 212 stacked in the first direction, and the second fin structure 212 is close to the semiconductor substrate 20. The first direction is the stacking direction of the stacked transistors.

[0104] The second step, as shown in Figure 5As shown, an insulating material is deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 22 covering the fin structure 21, and the shallow trench isolation structure 22 is subjected to chemical-mechanical planarization (CMP) treatment to ensure that the shallow trench isolation structure 22 in any region has the same height. Subsequently, an etching process is used to etch the shallow trench isolation structure 22 until the first fin structure 211 is exposed. Here, the etched shallow trench isolation structure 22 can expose the first fin structure 211 and wrap the second fin structure 212.

[0105] In the third step, refer to Figure 6 As shown, pseudo-gate materials such as polysilicon and single-crystalline silicon are deposited in the gate region to form a first pseudo-gate structure 23. Subsequently, a pseudo-gate sidewall can be formed on the sidewalls of the first pseudo-gate structure 23. Here, the pseudo-gate sidewall formed on the sidewalls of the first pseudo-gate structure 23 can constitute the first pseudo-gate sidewall of the front transistor 11. The first pseudo-gate sidewall is used for electrically isolating the first gate structure and the active structure in the front transistor 11.

[0106] In the fourth step, refer to Figure 7 As shown, using the first pseudo-gate structure 23 as a hard mask, the first fin structure 211 in the source-drain region is etched to form a first source-drain groove, and a first source-drain structure 112 is epitaxially grown inside and outside the first source-drain groove; on the first source-drain structure 112, a dielectric material is deposited to form an initial first interlayer dielectric layer, and the initial first interlayer dielectric layer is subjected to mechanical planarization treatment to obtain a first interlayer dielectric layer 113, and the upper surface of the first interlayer dielectric layer 113 is flush with the upper surface of the first pseudo-gate structure 23.

[0107] In the fifth step, refer to Figure 8 As shown, the first pseudo-gate structure 23 is removed, and a gate dielectric material and a gate metal material are sequentially deposited at the position where the first pseudo-gate structure 23 is removed to form a first gate dielectric layer and a first gate electrode layer respectively, thereby obtaining a first gate structure 114; a first part of the first gate structure is removed, and a second part of the first gate structure is retained to form a front trench, and an insulating material is deposited in the front trench to form a front isolation structure 24.

[0108] Among them, the first part and the second part of the first gate structure are arranged along a second direction. The second direction is a direction perpendicular to the first direction.

[0109] In the sixth step, refer to Figure 9 As shown, the first interlayer dielectric layer 113 is etched until the first source-drain structure 112 is exposed to form a first source-drain metal groove, and a metal material is deposited in the first source-drain metal groove to form a first source-drain metal 115 of the front transistor 11.

[0110] Here, the length of the first source-drain metal groove in the second direction can be set according to actual requirements. In this embodiment, the first source-drain metal groove in the second direction can extend from the first source-drain structure 112 to the region where the front isolation structure 24 is located, so that the first source-drain metal 115 is in contact with the front isolation structure 24. In this way, the source-drain via structure formed subsequently can be arranged in the third direction with the gate via structure formed in the front isolation structure 24, so that the front power rail only needs to be arranged along the third direction, effectively reducing the complexity of preparing the front power rail.

[0111] The seventh step, refer to Figure 10 As shown, deposit an insulating material on the first source-drain metal 115, the first gate structure 114, and the front isolation structure 24 to form a front insulating layer 25, bond the front carrier wafer 26 to the front insulating layer 25, and flip the bonded front carrier wafer 26. Subsequently, use a chemical mechanical planarization process to remove the semiconductor substrate 20 until the shallow trench isolation structure 22 is exposed.

[0112] The eighth step, refer to Figure 11 As shown, thin the shallow trench isolation structure 22 to expose the second fin structure 212.

[0113] Here, the thinned shallow trench isolation structure 22 is located on the peripheral side of the junction of the first fin structure 211 and the second fin structure 212. The thinned shallow trench isolation structure 22 is used for electrically isolating the front transistor 11 and the back transistor 12.

[0114] The ninth step, refer to Figure 12 As shown, deposit pseudo-gate materials such as polysilicon and single-crystalline silicon in the gate region to form a second pseudo-gate structure 27. Subsequently, a pseudo-gate sidewall can be formed on the sidewall of the second pseudo-gate structure 27. Here, the pseudo-gate sidewall formed on the sidewall of the second pseudo-gate structure 27 can constitute the second pseudo-gate sidewall of the back transistor 12. The second pseudo-gate sidewall is used for electrically isolating the second gate structure 124 and the active structure in the back transistor 12.

[0115] The tenth step, refer to Figure 13 As shown, use the second pseudo-gate structure 27 as a hard mask to etch the second fin structure 212 in the source-drain region to form a second source-drain groove, and epitaxially grow a second source-drain structure 122 in the second source-drain groove; deposit a dielectric material on the second source-drain structure 122 to form an initial second interlayer dielectric layer, and perform a mechanical planarization process on the initial second interlayer dielectric layer to obtain a second interlayer dielectric layer 123, and the upper surface of the second interlayer dielectric layer 123 is flush with the upper surface of the second pseudo-gate structure 27.

[0116] The eleventh step, refer to Figure 14As shown, the second dummy gate structure 27 is removed, and a gate dielectric material and a gate metal material are sequentially deposited at the position where the second dummy gate structure 27 is removed to form a second gate dielectric layer and a second gate electrode layer respectively, thereby obtaining a second gate structure 124; a first part of the second gate structure is removed, and a second part of the second gate structure is retained to form a back trench, and an insulating material is deposited in the back trench to form a back isolation structure 28.

[0117] Among them, the first part and the second part of the second gate structure are arranged along a second direction. The front trench is located on a first side of the fin structure in the second direction, and the back trench is located on a second side of the fin structure in the second direction, and the first side and the second side are opposite to each other. It can be seen that staggered front trenches and back trenches can be formed in the stacked transistors. It can also be understood that the projection of the front trench along the first direction does not coincide with the projection of the back trench along the first direction.

[0118] The twelfth step, referring to Figure 15 As shown, the second interlayer dielectric layer 123 is etched until the second source / drain structure 122 is exposed to form a second source / drain metal groove, and a metal material is deposited in the second source / drain metal groove to form the second source / drain metal 125 of the second transistor.

[0119] Here, the length of the second source / drain metal 125 groove in the second direction can be set according to actual requirements. In this embodiment, the second source / drain metal 125 groove can extend from the second source / drain structure 122 to the area where the back isolation structure 28 is located in the second direction, so that the second source / drain metal 125 is connected to the back isolation structure 28. In this way, the source / drain via structure formed subsequently can be arranged in the third direction with the gate via structure formed in the back isolation structure 28, so that the back power rail only needs to be arranged along the third direction, effectively reducing the preparation complexity of the back power rail.

[0120] The thirteenth step, referring to Figure 16 As shown, a back dielectric layer 29 is formed on the back isolation structure 28, the second gate structure 124 and the second source / drain metal 125; the back dielectric layer 29 is etched until the second source / drain metal 125 is exposed to form a back source / drain metal via, and the back dielectric layer 29 and the back isolation structure 28 are etched until the first gate structure 114 is exposed to form a back gate metal via. Metals are deposited in the back source / drain metal via and the back gate metal via to form a back source / drain via structure 30 and a back gate via structure 31 respectively. After the back source / drain via structure 30 and the back gate via structure 31 are formed, a metal layer is prepared on the back dielectric layer 29 to form a back power rail 32.

[0121] Among them, the projection of the back via structure in the first direction falls within the projection of the back power rail in the first direction; the back via structure includes: a back source / drain via structure 30 and a back gate via structure 31; the back power rail 32 is connected to the second source / drain metal 125 through the back source / drain via structure 30, and the back power rail 32 is connected to the first gate structure 114 through the back gate via structure 31.

[0122] The fourteenth step, refer to Figure 17 As shown, after the back metal interconnect layer 126 is fabricated, an insulating material is deposited on the back metal interconnect layer 126 to form a back insulating layer 33. The back carrier wafer 34 is bonded to the back insulating layer 33, and the bonded back carrier wafer 34 is flipped. Subsequently, a chemical mechanical planarization process is used to remove the front carrier wafer 26 and the front insulating layer 25 to expose the first source / drain metal 115, the first gate structure 114, and the front isolation structure 24.

[0123] The fifteenth step, refer to Figure 18 As shown, a front dielectric layer 35 is formed on the first source / drain metal 115, the first gate structure 114, and the front isolation structure 24; the front dielectric layer 35 is etched until the first source / drain metal 115 is exposed to form a front source / drain metal via, and the front dielectric layer 35 and the front isolation structure 24 are etched until the second gate structure 124 is exposed to form a front gate metal via. Metal is deposited in the front source / drain metal via and the front gate metal via to form a front source / drain via structure 36 and a front gate via structure 37 respectively. After the front source / drain via structure 36 and the front gate via structure 37 are formed, a metal layer is fabricated on the front dielectric layer 35 to form a front power rail 38. The front power rail 38 is included in the front metal interconnect layer 116.

[0124] Among them, the projection of the front via structure in the first direction falls within the projection of the front power rail 38 in the first direction; the front via structure includes: a front source / drain via structure 36 and a front gate via structure 37; the front power rail 38 is connected to the first source / drain metal 115 through the front source / drain via structure 36, and the front power rail 38 is connected to the second gate structure 124 through the front gate via structure 37.

[0125] Thus far, a stacked transistor is fabricated.

[0126] In the embodiment of the present application, after the front source / drain metal is formed, the first wafer flip is performed. After the wafer flip, the fabrication of the back transistor is completed, and the first gate structure is directly connected to the back power rail by using the back gate via structure. After the fabrication of the back transistor is completed, the second wafer flip is performed. After the wafer flip, the fabrication of the front transistor is completed. Similarly, the second gate structure is directly connected to the front power rail by using the front gate via structure, thereby obtaining a decoupling capacitor.

[0127] In a second aspect, an embodiment of the present application provides a stacked transistor. Refer to Figure 18 As shown, a front transistor 11 and a back transistor 12; the front transistor 11 includes: a first source / drain structure 112, a first gate structure 114, a first source / drain metal 115, and a front metal interconnect layer 116; the back transistor 12 includes: a second source / drain structure 122, a second gate structure 124, a second source / drain metal 125, and a back metal interconnect layer 126; the front transistor 11 and the back transistor 12 are stacked along a first direction;

[0128] Among them, the front metal interconnect layer 116 includes a front power rail 38 and a front via structure, and the front power rail 38 is respectively connected to the first source / drain metal 115 and the second gate structure 124 through the front via structure; the back metal interconnect layer 126 includes a back power rail 32 and a back via structure, and the back power rail 32 is respectively connected to the second source / drain metal 125 and the first gate structure 114 through the back via structure; the front power rail 38 is located on a first side of the fin structure in a second direction, and the back power rail 32 is located on a second side of the fin structure in the second direction, the first side and the second side are opposite to each other, and the second direction is perpendicular to the first direction.

[0129] It can be understood that the front power rail 38 is formed on the first side of the fin structure in the stacked transistor, and the back power rail 32 is formed on the second side opposite to the first side, so that on one side of the stacked transistor, the front power rail 38 is respectively connected to the first source / drain metal 115 and the second gate structure 124 through the front via structure; on the other side of the stacked transistor, the back power rail 32 is respectively connected to the second source / drain metal 125 and the first gate structure 114 through the back via structure. It can be seen that the front power rail 38 and the back power rail 32 adopt an interleaved design, so that a decoupling capacitor can be realized through the front via structure and the back via structure. On the one hand, it is no longer necessary to rely on complex post-metal wires, effectively reducing the complexity of the manufacturing process; on the other hand, it is not necessary to increase the area of the transistor, effectively improving the integration performance of the stacked transistor.

[0130] In some embodiments, the extending directions of the front power rail 38 and the back power rail 32 are a third direction, and the third direction is perpendicular to the first direction and the second direction; the projection of the front via structure along the first direction falls within the projection of the front power rail 38 along the first direction; the projection of the back via structure along the first direction falls within the projection of the back power rail 32 along the first direction.

[0131] It can be understood that the front power rail 38 and the back power rail 32 can be arranged only in one direction, thereby reducing the complexity of preparing the power rails. Further, since the first source-drain metal 115 can extend from the first source-drain structure 112 to below the front power rail 38 in the second direction, the projection of the front via structure connecting the first source-drain metal 115 in the first direction can fall within the projection of the front power rail 38 in the first direction. This indicates that only by increasing the area of the first source-drain metal 115 can the connection between the front via structure and the front power rail 38 be achieved, without increasing the area of the front transistor 11, thus ensuring the integration performance of the stacked transistors. Similarly, the projection of the back via structure in the first direction falls within the projection of the back power rail 32 in the first direction, which can also ensure the integration performance of the stacked transistors.

[0132] In some embodiments, the front via structure includes: a front source-drain via structure 36 and a front gate via structure 37; the front power rail 38 is connected to the first source-drain metal 115 through the front source-drain via structure 36, and the front power rail 38 is connected to the second gate structure 124 through the front gate via structure 37.

[0133] In some embodiments, the back via structure includes: a back source-drain via structure 30 and a back gate via structure 31; the back power rail 32 is connected to the second source-drain metal 125 through the back source-drain via structure 30, and the back power rail 32 is connected to the first gate structure 114 through the back gate via structure 31.

[0134] In the embodiments of the present application, the front power rail 38 and the back power rail 32 adopt an interleaved design, so that the internal interconnection lines of the decoupling capacitor formed by the stacked transistors (including an NMOS and a PMOS) do not need to rely on complex post-metal lines (such as M0 metal lines), and can be achieved only by using the source-drain via structures (including the front source-drain via structure 36 and the back source-drain via structure 30) and the gate via structures (including the front gate via structure 37 and the back gate via structure 31).

[0135] Based on this, the embodiments of the present application can enable the internal interconnection lines of the decoupling capacitor not to rely on complex post-metal lines, the stacked transistors can be completed within 2 contact pitches (CPP), and no additional area needs to be wasted.

[0136] In one or more of the above embodiments of fabricating stacked transistors, the stacked transistors also have self-alignment. On the one hand, it solves the long-term problems such as complex processes and difficult alignment existing in the existing mainstream technical solutions of stacked transistors, and promotes the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through the stacked transistors. Without changing the design of the extremely miniaturized 4T track unit, the metal wiring resources are greatly released.

[0137] Finally, the solution of realizing the upper and lower transistors through flip-chip is compatible with the existing mainstream device architectures, and can realize the front-back stacking of planar transistors, FinFETs, GAA Nanosheets and even vertical transistors (VTFETs) without the need for special process development for specific device architectures. It has strong flexibility and great extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is conceptually very advanced, has important industrial value, and has strong practicality and broad development prospects.

[0138] In a third aspect, embodiments of the present application provide a semiconductor device, including: a stacked transistor as in the above embodiments. The specific limitations of the stacked transistor can be at least referred to the Figure 18 stacked transistor shown above and will not be elaborated here.

[0139] In a fourth aspect, embodiments of the present application provide an electronic device, including: a circuit board and a semiconductor device as in the above embodiments, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above stacked transistor. The specific limitations of the stacked transistor can be at least referred to the Figure 18 structure shown above and will not be elaborated here.

[0140] In the description of the present application, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine different embodiments or examples described in the present application and the features of different embodiments or examples.

[0141] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: include: Forming a fin structure on a semiconductor substrate, wherein the fin structure includes a first fin structure and a second fin structure stacked along a first direction; Based on the first fin structure, forming a first source-drain structure, a first gate structure and a first source-drain metal in sequence, wherein the first source-drain metal covers the first source-drain structure, and the first source-drain metal is farther away from the second fin structure than the first source-drain structure; Based on the second fin structure, a second source-drain structure, a second gate structure, and a second source-drain metal are sequentially formed, wherein the second source-drain structure and the first source-drain structure are stacked along the first direction, and the second gate structure and the first gate structure are stacked along the first direction; the second source-drain metal covers the second source-drain structure, and the second source-drain metal is farther away from the first fin structure than the second source-drain structure; forming a backside via structure and a backside power rail on the second gate structure and the second source-drain metal to obtain a backside transistor, wherein the backside power rail is connected to the second source-drain metal and the first gate structure respectively through the backside via structure; A front through-hole structure and a front power rail are formed on the first gate structure and the first source-drain metal to obtain a front transistor, wherein the front power rail is connected to the first source-drain metal and the second gate structure respectively through the front through-hole structure; the front power rail is located on a first side of the fin structure in a second direction, and the back power rail is located on a second side of the fin structure in the second direction, the first side is opposite to the second side, and the second direction is perpendicular to the first direction.

2. The preparation method according to claim 1, characterized in that: The forming of a second source-drain structure, a second gate structure, and a second source-drain metal in sequence based on the second fin structure includes: Based on the second fin structure, sequentially forming the second source-drain structure and the second gate structure; Removing the first portion of the second gate structure and retaining the second portion of the second gate structure to form a back trench, and depositing an insulating material in the back trench to form a back isolation structure; wherein the first portion of the second gate structure and the second portion of the second gate structure are arranged along the second direction; forming a second source-drain metal on the second source-drain structure; The forming of a backside via structure and a backside power rail on the second gate structure and the second source-drain metal comprises: forming a back dielectric layer on the back isolation structure, the second gate structure and the second source-drain metal; Etching the back dielectric layer until the second source-drain metal is exposed to form a back source-drain metal through hole, and etching the back dielectric layer and the back isolation structure until the first gate structure is exposed to form a back gate metal through hole; Depositing metal in the back source-drain metal through hole and the back gate metal through hole to form a back source-drain through hole structure and a back gate through hole structure, respectively; wherein the back source-drain through hole structure and the back gate through hole structure are included in the back through hole structure; The back power rail is formed on the back dielectric layer, wherein the back power rail is connected to the second source-drain metal through the back source-drain via structure, and the back power rail is connected to the first gate structure through the back gate via structure.

3. The preparation method according to claim 2, characterized in that: The method of sequentially forming a first source-drain structure, a first gate structure and a first source-drain metal based on the first fin structure includes: Based on the first fin structure, sequentially forming the first source-drain structure and the first gate structure; A first portion of the first gate structure is removed, and a second portion of the first gate structure is retained to form a front trench, and an insulating material is deposited in the front trench to form a front isolation structure; wherein the first portion of the first gate structure and the second portion of the second gate structure are arranged along the second direction; the front isolation structure is located on a first side of the fin structure, and the back isolation structure is located on a second side of the fin structure; The first source-drain metal is formed on the first source-drain structure.

4. The preparation method according to claim 3, characterized in that: The forming of a front through-hole structure and a front power rail on the first gate structure and the first source-drain metal comprises: forming a front dielectric layer on the front isolation structure, the first gate structure and the first source-drain metal; Etching the front dielectric layer until the first source-drain metal is exposed to form a front source-drain metal through hole, and etching the front dielectric layer and the front isolation structure until the second gate structure is exposed to form a front gate metal through hole; Depositing metal in the front source-drain metal through hole and the front gate metal through hole to form a front source-drain through hole structure and a front gate through hole structure, respectively; wherein the front source-drain through hole structure and the front gate through hole structure are included in the front through hole structure; A front power rail is formed on the front dielectric layer, wherein the front power rail is connected to the first source-drain metal through the front source-drain via structure, and the front power rail is connected to the second gate structure through the front gate via structure.

5. The preparation method according to claim 1, characterized in that: After forming a backside via structure and a backside power rail on the second gate structure and the second source-drain metal, the method further comprises: forming a back side insulating layer on the back side metal interconnection layer; Bonding the backside carrier wafer to the backside insulating layer, and flipping the bonded backside carrier wafer; Before forming a front through-hole structure and a front power rail on the first gate structure and the first source-drain metal, the method further includes: The backside carrier wafer and the backside insulating layer are removed to expose the first gate structure and the first source-drain metal.

6. The preparation method according to claim 1, characterized in that: The front power rail and the back power rail extend in a third direction, and the third direction is perpendicular to the first direction and the second direction; The projection of the front via structure along the first direction falls within the projection of the front power rail along the first direction; the projection of the back via structure along the first direction falls within the projection of the back power rail along the first direction.

7. A stacked transistor, characterized in that: include: A front transistor, the front transistor comprising: a first source-drain structure, a first gate structure, a first source-drain metal and a front metal interconnection layer; A back side transistor, the back side transistor comprising: a second source-drain structure, a second gate structure, a second source-drain metal and a back side metal interconnection layer; the front side transistor and the back side transistor are stacked and arranged along a first direction; Wherein, the front metal interconnection layer includes a front power rail and a front through-hole structure, and the front power rail is connected to the first source and drain metal and the second gate structure respectively through the front through-hole structure; the back metal interconnection layer includes a back power rail and a back through-hole structure, and the back power rail is connected to the second source and drain metal and the first gate structure respectively through the back through-hole structure; the front power rail is located on the first side of the fin structure in the second direction, and the back power rail is located on the second side of the fin structure in the second direction, the first side is opposite to the second side, and the second direction is perpendicular to the first direction.

8. The stacked transistor according to claim 7, characterized in that: The front power rail and the back power rail extend in a third direction, and the third direction is perpendicular to the first direction and the second direction; The projection of the front via structure along the first direction falls within the projection of the front power rail along the first direction; the projection of the back via structure along the first direction falls within the projection of the back power rail along the first direction.

9. The stacked transistor according to claim 8, characterized in that The front through-hole structure comprises: a front source-drain through-hole structure and a front gate through-hole structure; the front power rail is connected to the first source-drain metal through the front source-drain through-hole structure, and the front power rail is connected to the second gate structure through the front gate through-hole structure; The back side via structure comprises: a back side source-drain via structure and a back side gate via structure; the back side power rail is connected to the second source-drain metal through the back side source-drain via structure, and the back side power rail is connected to the first gate structure through the back side gate via structure.

10. A semiconductor device, characterized in that: include: A stacked transistor as claimed in any one of claims 7 to 9.

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