Semiconductor structure and preparation method thereof, and light-emitting array and preparation method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure, a preparation method of the semiconductor structure, a light-emitting array and a preparation method of the light-emitting array. The side wall of at least one side, close to a mask opening, of a mask structure comprises at least one step structure; at least part of the first conductive layer in the sub-light-emitting unit is located on one side of the mask table-board and / or at least part of the second conductive layer in the sub-light-emitting unit is located on one side of the mask table-board, so that the first conductive layer forms a first electrode table-board and / or the second conductive layer forms a second electrode table-board at the position corresponding to the mask table-board. The first electrode mesa and / or the second electrode mesa are / is naturally exposed at the position corresponding to the mask mesa. The first electrode mesa and / or the second electrode mesa can be formed without etching the epitaxial structure, so that the first electrode mesa and / or the second electrode mesa are relatively flat, ohmic contact is easy to form, the reduction of process steps of electrode formation is facilitated, and the manufacturing cost of the Micro-LED chip is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a semiconductor structure and a method for preparing the same, a light-emitting array and a method for preparing the same. Background Art

[0002] Micro-sized light-emitting diodes (Micro-LEDs) are regarded as the next-generation display devices due to their advantages such as high responsivity, high brightness, high contrast, ultra-high resolution, and low power consumption, and have been rapidly developed in recent years.

[0003] At the current stage, for different-sized Micro-LEDs, whether the main technical solutions are tiling or vertical stacking, mesa etching technology is required, that is, etching the epitaxial structure to form a mesa. As the size decreases, the sidewall damage in the mesa etching of Micro-LED pixels will cause the light-emitting efficiency of Micro-LEDs to drop sharply. This is because the sidewall defects caused by the sidewall damage provide non-radiative recombination centers and current leakage paths, thus seriously deteriorating the device performance. Moreover, it is difficult to form a reliable ohmic contact on the surface of the etched semiconductor layer. Summary of the Invention

[0004] The present invention provides a semiconductor structure and a method for preparing the same, a light-emitting array and a method for preparing the same, so as to form a mesa of the epitaxial structure without mesa etching of the epitaxial structure, reduce the sidewall damage of the epitaxial structure, and facilitate the realization of ohmic contact.

[0005] According to one aspect of the present invention, a semiconductor structure is provided, including:

[0006] A mask structure, the mask structure encloses a mask opening, and at least one sidewall of the mask structure close to the mask opening includes at least one stepped structure, the stepped structure includes a mask mesa, and the mask mesa intersects with the thickness direction of the semiconductor structure;

[0007] A light-emitting unit, including at least one sub-light-emitting unit, at least a part of the sub-light-emitting unit is located in the mask opening, the sub-light-emitting unit includes a first conductive layer, a light-emitting layer, and a second conductive layer stacked, along the thickness direction of the semiconductor structure, at least a part of the first conductive layer is located on one side of the mask mesa and / or at least a part of the second conductive layer is located on one side of the mask mesa.

[0008] According to another aspect of the present invention, a light-emitting array is provided, including:

[0009] A light-emitting unit, including at least one sub-light-emitting unit, the sub-light-emitting unit includes a first conductive layer, a light-emitting layer, and a second conductive layer stacked;

[0010] The first conductive layer includes a first electrode mesa, a first electrode is disposed on one side of the first electrode mesa, and the first electrode is electrically connected to the first conductive layer; and / or, the second conductive layer includes a second electrode mesa, a second electrode is disposed on one side of the second electrode mesa, and the second electrode is electrically connected to the second conductive layer.

[0011] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, including:

[0012] Forming a mask structure layer on one side of a substrate;

[0013] Patterning the mask structure layer to form a mask structure, the mask structure encloses a mask opening, at least one sidewall of the mask structure near the mask opening includes at least one step structure, and the step structure includes a mask mesa, and the mask mesa intersects with the thickness direction of the semiconductor structure;

[0014] Forming a light-emitting unit in the mask opening, including at least one sub-light-emitting unit, the sub-light-emitting unit is at least partially located in the mask opening, and the sub-light-emitting unit includes a first conductive layer, a light-emitting layer, and a second conductive layer stacked, along the thickness direction of the semiconductor structure, at least a part of the first conductive layer is located on one side of the mask mesa and / or at least a part of the second conductive layer is located on one side of the mask mesa.

[0015] According to another aspect of the present invention, there is provided a method for manufacturing a light-emitting array, including:

[0016] Removing the mask structure of the semiconductor structure, and the semiconductor structure is the semiconductor structure of any embodiment of the present invention;

[0017] Forming a first electrode at the first electrode mesa corresponding to the first conductive layer, and / or forming a second electrode at the second electrode mesa corresponding to the second conductive layer;

[0018] In the semiconductor structure, the first electrode mesa is located on one side of the mask mesa, and / or the second electrode mesa is located on one side of the mask mesa.

[0019] The semiconductor structure and its manufacturing method according to the embodiments of the present invention, the light-emitting array and its manufacturing method, by setting at least one side wall of the mask structure near the mask opening to include at least one stepped structure, the stepped structure includes a mask tabletop, along the thickness direction of the semiconductor structure, at least part of the first conductive layer in the sub-light-emitting unit is located on one side of the mask tabletop and / or at least part of the second conductive layer is located on one side of the mask tabletop, so that at the position corresponding to the mask tabletop, the first conductive layer forms a first electrode tabletop and / or the second conductive layer forms a second electrode tabletop, so that when forming the light-emitting array subsequently, after removing the mask structure, at the position corresponding to the mask tabletop, the first electrode tabletop and / or the second electrode tabletop are naturally exposed. When forming the light-emitting array, the mesa etching technology is not required, and the side wall damage to the epitaxial structure is reduced. Since the first electrode tabletop and / or the second electrode tabletop can be formed without etching the epitaxial structure, the first electrode tabletop and / or the second electrode tabletop are relatively flat, which is easy to form an ohmic contact, reduces the difficulty of ohmic contact, and is beneficial to reducing the process steps of electrode formation, thereby reducing the manufacturing cost of the Micro-LED chip.

[0020] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention;

[0023] Figure 2 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0024] Figure 3 is a top view of a semiconductor structure provided by an embodiment of the present invention;

[0025] Figure 4 is a schematic structural diagram of yet another semiconductor structure provided by an embodiment of the present invention;

[0026] Figure 5 is a schematic structural diagram of yet another semiconductor structure provided by an embodiment of the present invention;

[0027] Figure 6It is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0028] Figure 7 It is a schematic structural diagram of yet another semiconductor structure provided by an embodiment of the present invention;

[0029] Figure 8 It is a flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0030] Figure 9 It is a schematic structural diagram of a semiconductor structure obtained by using the method for preparing a semiconductor structure;

[0031] Figure 10 It is a schematic structural diagram of a light-emitting array provided by an embodiment of the present invention;

[0032] Figure 11 It is a flowchart of a method for preparing a light-emitting array provided by an embodiment of the present invention. Detailed implementation manners

[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0035] As described in the background technology, the main technical solutions for Micro-LEDs of different sizes at this stage, whether they are tiled or vertically stacked, require table etching technology, and it is difficult to form a reliable ohmic contact on the surface of the etched semiconductor layer. The inventors have found that the reason for the above problems is that it is extremely difficult to produce ohmic contact on the surface of p-type GaN after plasma etching. Although the contact resistivity of n-GaN will be significantly improved by making ohmic contact on the etched surface, this is due to the formation of a large number of N vacancies near the surface, but this is very unfavorable for the ohmic contact of P-type materials. N vacancies are equivalent to donors, which will compensate for part of the acceptor carrier concentration, resulting in a significant decrease in the quality of the ohmic contact on the etched surface. In addition, the unevenness of the surface after etching, the contamination of the surface etching reactants, and the generation of some defects, etc., will increase the barrier between the metal electrode and the p-GaN material, increasing the difficulty of ohmic contact.

[0036] Based on the above reasons, an embodiment of the present invention provides a semiconductor structure. Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention, Figure 2 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention, Figure 3 is a top view of a semiconductor structure provided by an embodiment of the present invention, with reference to Figures 1 - 3 The semiconductor structure includes: a mask structure 100, the mask structure 100 encloses a mask opening 101, the sidewall of the mask structure 100 near at least one side of the mask opening 101 includes at least one step structure 110, the step structure 110 includes a mask table 111, and the mask table 111 intersects with the thickness direction y of the semiconductor structure; a light-emitting unit 200, including at least one sub-light-emitting unit 210, the sub-light-emitting unit 210 is at least partially located in the mask opening 101, and the sub-light-emitting unit 210 includes a first conductive layer 211, a light-emitting layer 212, and a second conductive layer 213 that are stacked, along the thickness direction y of the semiconductor structure, at least a portion of the first conductive layer 211 is located on one side of the mask table 111 and / or at least a portion of the second conductive layer 213 is located on one side of the mask table 111. Wherein, Figure 3 The light emitting unit 200 is not shown. Figure 3 The middle dashed line indicates the location of the step structure.

[0037] Optionally, the semiconductor structure further includes a substrate 300, and the mask structure 100 is located on one side of the substrate 300. Among them, the formation process of the mask structure 100 may include: forming a mask structure 100 layer on one side of the substrate 300, patterning the mask structure 100 layer to form a mask opening 101, where the number of mask openings 101 is at least one. In some embodiments, the semiconductor structure includes a plurality of independent mask structures 100, and one mask structure 100 encloses one mask opening 101. Correspondingly, a plurality of mask structures 100 enclose a plurality of mask openings 101. In some other embodiments, the mask structure 100 is an integral structure, and the integral mask structure 100 encloses a plurality of mask openings 101. Among them, the shape of the orthographic projection of the mask opening 101 on the substrate 300 may be circular, elliptical, rectangular or other polygons. Optionally, the material of the substrate 300 may be sapphire or silicon. Exemplarily, on a cleaned sapphire or silicon substrate 300, a periodic mask structure 100 is prepared by using a photolithography process in combination with coating equipment such as magnetron sputtering PVD, electron beam evaporation EB, and plasma enhanced chemical vapor deposition (PECVD). The material of the mask structure 100 includes at least one of oxides, nitrides, and metals.

[0038] In this embodiment, the side wall of the mask structure 100 close to the mask opening 101 includes at least one step structure 110. The step structure 110 may include a mask table surface 111 and a support surface 112. The plane where the mask table surface 111 is located intersects with the thickness direction y of the semiconductor structure. In some embodiments, the mask table surface 111 is parallel to the surface of the substrate 300 close to the mask structure 100 layer, and / or the mask table surface 111 is parallel to the horizontal plane (the mask table surface 111 is perpendicular to the thickness direction y of the semiconductor structure). The support surface 112 is connected to and intersects with the mask table surface 111. In some embodiments, the support surface 112 is perpendicular to the horizontal plane, that is, the support surface 112 is parallel to the thickness direction y of the semiconductor structure.

[0039] The semiconductor structure further includes a light-emitting unit 200, which includes at least one sub-light-emitting unit 210. Refer to Figure 1 , when the light-emitting unit 200 includes one sub-light-emitting unit 210, this one sub-light-emitting unit 210 serves as the light-emitting unit 200. Refer to Figure 2, in some embodiments, the light-emitting unit 200 includes at least two sub-light-emitting units 210, and the at least two sub-light-emitting units 210 are stacked in the thickness direction y of the semiconductor structure. Optionally, the at least two sub-light-emitting units 210 have different light-emitting colors. Exemplarily, the light-emitting unit 200 includes a first sub-light-emitting unit 201, a second sub-light-emitting unit 202, and a third sub-light-emitting unit 203. Among the first sub-light-emitting unit 201, the second sub-light-emitting unit 202, and the third sub-light-emitting unit 203, one has a red light-emitting color, one has a green light-emitting color, and the other has a blue light-emitting color.

[0040] The sub-light-emitting unit 210 is at least partially located in the mask opening 101. The sub-light-emitting unit 210 includes a first conductive layer 211, a light-emitting layer 212, and a second conductive layer 213 which are stacked. Among them, the first conductive layer 211 at least includes a first semiconductor layer. In some embodiments, the first conductive layer 211 further includes an ohmic contact layer on the side of the first semiconductor layer away from the light-emitting layer. The second conductive layer 213 at least includes a second semiconductor layer. In some embodiments, the second conductive layer 213 further includes an ohmic contact layer on the side of the second semiconductor layer away from the light-emitting layer 212. Among them, the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer; or the first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer. Among them, the P-type semiconductor layer may include, for example, P-type GaN, and the N-type semiconductor layer may include, for example, N-type GaN. In other alternative embodiments of the present invention, the P-type semiconductor layer may include other P-type semiconductor materials, and the N-type semiconductor layer may include other N-type semiconductor materials. The light-emitting layer 212 may be a quantum well layer, optionally a multi-quantum well layer, such as a multi-quantum well layer of InGaN / GaN.

[0041] In this embodiment, along the thickness direction y of the semiconductor structure, at least a part of the first conductive layer 211 is located on one side of the mask table 111 of the mask structure 100 and / or at least a part of the second conductive layer 213 is located on one side of the mask table 111. Among them, at least a part of the first conductive layer 211 being located on one side of the mask table 111 of the mask structure 100 enables, when forming the light-emitting array subsequently, after removing the mask structure 100, at the position corresponding to the mask table 111, the first conductive layer 211 to form a first electrode table, such that the first electrode table of the first conductive layer 211 is naturally exposed, without the need for mesa etching of the first conductive layer 211, so that the first electrode can be directly formed at the position of the first electrode table. Thus, when forming the light-emitting array, mesa etching technology is not required, reducing the sidewall damage to the epitaxial structure. Moreover, the first electrode table of the first conductive layer 211 for forming the first electrode, since it can be formed without etching the epitaxial structure, makes the first electrode table relatively flat, facilitating the formation of ohmic contact, reducing the difficulty of ohmic contact, and being conducive to reducing the process steps for forming the first electrode, thereby reducing the manufacturing cost of the Micro-LED chip. Among them, Figure 1 and Figure 2 exemplarily shows the situation where part of the first conductive layer 211 is higher than the mask table 111 and part is lower than the mask table 111. In other alternative embodiments, the first conductive layer 211 can be entirely higher than the mask table 111.

[0042] Among them, at least a part of the second conductive layer 213 being located on one side of the mask table 111 of the mask structure 100 enables, when forming the light-emitting array subsequently, after removing the mask structure 100, at the position corresponding to the mask table 111, the second conductive layer 213 to form a second electrode table, such that the second electrode table of the second conductive layer 213 is naturally exposed, without the need for mesa etching of the second conductive layer 213, so that the second electrode can be directly formed at the position of the second electrode table. Thus, when forming the light-emitting array, mesa etching technology is not required, reducing the sidewall damage to the epitaxial structure. Moreover, the second electrode table of the second conductive layer 213 for forming the second electrode, since it can be formed without etching the epitaxial structure, makes the second electrode table relatively flat, facilitating the formation of ohmic contact, reducing the difficulty of ohmic contact, and being conducive to reducing the process steps for forming the second electrode, thereby reducing the manufacturing cost of the Micro-LED chip. Among them, Figure 1 the situation where the entire second conductive layer 213 is higher than the mask table 111, Figure 2 exemplarily shows the situation where part of the second conductive layer 213 is higher than the mask table 111 and part is lower than the mask table 111.

[0043] In the semiconductor structure according to the embodiment of the present invention, by providing that at least one sidewall of the mask structure near the mask opening includes at least one stepped structure, the stepped structure includes a mask tabletop, and along the thickness direction of the semiconductor structure, at least a part of the first conductive layer in the sub-light-emitting unit is located on one side of the mask tabletop and / or at least a part of the sub-second conductive layer is located on one side of the mask tabletop, so that at the position corresponding to the mask tabletop, the first conductive layer forms a first electrode tabletop and / or the second conductive layer forms a second electrode tabletop. When forming a light-emitting array subsequently, after removing the mask structure, at the position corresponding to the mask tabletop, the first electrode tabletop and / or the second electrode tabletop are naturally exposed. When forming the light-emitting array, the mesa etching technology is not required, and the sidewall damage to the epitaxial structure is reduced. Since the first electrode tabletop and / or the second electrode tabletop can be formed without etching the epitaxial structure, the first electrode tabletop and / or the second electrode tabletop are relatively flat, which is conducive to forming an ohmic contact, reducing the difficulty of the ohmic contact, and is beneficial to reducing the process steps for forming the electrodes, thereby reducing the manufacturing cost of the Micro-LED chip.

[0044] Continue to refer to Figure 2 , in some embodiments, the sidewall of the mask structure 100 near the mask opening 101 includes a first stepped structure 113, and the first stepped structure 113 includes a first mask tabletop 1131; the first conductive layer 211 includes a first semiconductor layer, and along the thickness direction y of the semiconductor structure, at least a part of the first semiconductor layer is located on one side of the first mask tabletop 1131. In this case, the first semiconductor layer forms a first electrode tabletop at the position corresponding to the first mask tabletop 1131. After removing the mask structure 100 subsequently, the first electrode can be directly formed on the first electrode tabletop of the first semiconductor layer, or the first electrode can be formed after forming an ohmic contact layer.

[0045] Figure 4 is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present invention, Figure 5 is a schematic structural diagram of another semiconductor structure provided by the embodiment of the present invention. Refer to Figure 4 and Figure 5, in some embodiments, the first conductive layer 211 includes a first semiconductor layer 2111 and an ohmic contact layer 2112. The ohmic contact layer 2112 is located on a side of the first semiconductor layer 2111 away from the light-emitting layer 212. Along the thickness direction y of the semiconductor structure, at least a part of the ohmic contact layer 2112 is located on one side of the first mask mesa 1131. For such a semiconductor structure, during the process of forming the light-emitting unit 200, the ohmic contact layer 2112 is formed, and at least a part of the ohmic contact layer 2112 is disposed on the first mask mesa 1131, so that a first electrode mesa can be formed at a position corresponding to the first mask mesa 1131. After the mask structure 100 is removed subsequently, the first electrode can be directly formed on the first electrode mesa. Optionally, the first semiconductor layer 2111 is a P-type semiconductor layer. By providing the ohmic contact layer 2112 on one side of the first semiconductor layer 2111, a better ohmic contact can be formed between the P-type semiconductor layer and the first electrode.

[0046] Continue to refer to Figure 4 , optionally, at the position of the second conductive layer 213, the sidewall of the mask structure 100 is a vertical sidewall, an inclined sidewall or a smooth sidewall. That is, at the position of the second conductive layer 213, the sidewall of the mask structure 100 may not be provided with the step structure 110. In this way, the mask structure 100 can include fewer step structures 110, thereby improving the formation efficiency of the mask structure 100 and enhancing the preparation efficiency of the semiconductor structure and the light-emitting array. Optionally, the second semiconductor layer included in the second conductive layer 213 is an N-type semiconductor layer. Since a relatively good ohmic contact can still be formed after the N-type semiconductor layer is etched compared with the P-type semiconductor layer, in this embodiment, by providing that at the position of the second conductive layer 213, the sidewall of the mask structure 100 is a vertical sidewall, an inclined sidewall or a smooth sidewall, it can ensure reducing the sidewall damage of the epitaxial structure and being easy to realize the ohmic contact of the first conductive layer 211, and on this basis, the preparation efficiency of the semiconductor structure and the light-emitting array is enhanced. Optionally, Figure 4 , the pitch D1 (the size of the mask opening 101 closest to the substrate 300) of the openings of the mask structure 100 is 4 μm, and the height of the mask structure 100 is 4.5 μm. The mesa surface lengths of the four step structures 110 from bottom to top are all 3 μm. The heights of the four step structures 110 from bottom to top are 1.9 μm, 1.2 μm, 0.8 μm, and 0.6 μm in sequence. The first conductive layers 211 of the three sub-light-emitting units 210 are not combined together, and independent electrodes can be realized. Optionally, Figure 4 the material of the mask structure 100 in

[0047] Continue to refer to Figure 2 and Figure 5, Optionally, the sidewall of the second conductive layer 213 adjacent to the mask opening 101 includes a second step structure 114, and the second step structure 114 includes a second mask tabletop 1141. Along the thickness direction y of the semiconductor structure, at least a part of the second conductive layer 213 is located on one side of the second mask tabletop 1141; wherein, along the horizontal direction x, the second step structure 114 and the first step structure 113 are located on the same side or different sides of the light-emitting unit 200.

[0048] In some embodiments, the second conductive layer 213 includes a second semiconductor layer, and at least a part of the second semiconductor layer is located on one side of the second mask tabletop 1141. In this case, a second electrode tabletop is formed at the position of the second semiconductor layer corresponding to the second mask tabletop 1141. After the mask structure 100 is removed subsequently, a second electrode can be directly formed on the second electrode tabletop of the second semiconductor layer, or a second electrode can be formed after forming an ohmic contact layer.

[0049] In other embodiments, the second conductive layer 213 includes a second semiconductor layer and an ohmic contact layer on the side of the second semiconductor layer away from the light-emitting layer 212, and at least a part of the ohmic contact layer is located on one side of the second mask tabletop 1141. For such a semiconductor structure, during the process of forming the light-emitting unit 200, an ohmic contact layer is formed, and at least a part of the ohmic contact layer is disposed on the second mask tabletop 1141, so that the ohmic contact layer can form a second electrode tabletop at the position corresponding to the second mask tabletop 1141. After the mask structure 100 is removed subsequently, a second electrode can be directly formed on the second electrode tabletop.

[0050] Combined with Figure 2 and Figure 5 , in some embodiments, along the horizontal direction x, the second step structure 114 and the first step structure 113 are located on different sides of the light-emitting unit 200. In this case, the first electrode and the second electrode of the light-emitting unit 200 will also be formed on both sides of the light-emitting unit 200 respectively, so that the effective light-emitting area of the light-emitting unit 200 is concentrated in the central region of the light-emitting unit 200, which is beneficial to improving the light-emitting effect.

[0051] Continuing to refer to Figure 2 and Figure 5 , along the horizontal direction x, the second step structure 114 and the first step structure 113 are located on different sides of the light-emitting unit 200, and the first step structure 113 and the second step structure 114 are asymmetric. In this way, on the one hand, the first electrode tabletop of the first conductive layer 211 at the first mask tabletop 1131 and the second electrode tabletop of the second conductive layer 213 at the second mask tabletop 1141 can be naturally exposed, which is beneficial to subsequent electrode preparation. In addition, the asymmetric setting of the first step structure 113 and the second step structure 114 is beneficial to the bending and merging of dislocations, thereby improving the crystal quality and light efficiency of the sub-light-emitting unit 210.

[0052] Continue to refer to Figure 2 and Figure 5 , optionally, the light-emitting unit 200 includes at least two sub-light-emitting units 210, and an isolation layer 400 is provided between adjacent sub-light-emitting units 210; the semiconductor structure further includes a substrate 300 on one side of the mask structure 100. In the sub-light-emitting unit 210, the positive projections of the first semiconductor layer 2111, the light-emitting layer 212, and the second conductive layer 213 on the substrate 300 overlap; the ohmic contact layer 2112 and the adjacent isolation layer 400 overlap in the positive projection on the substrate 300. In this way, a mask structure 100 with an asymmetric step structure 110 can be formed. Combining Figure 2 and Figure 5 , in some embodiments, one side edge of the positive projection of the ohmic contact layer 2112 and the adjacent isolation layer 400 on the substrate 300( Figure 2 and Figure 5 the left edge in), in the sub-light-emitting unit 210 where the ohmic contact layer 2112 is located, one side edge of the positive projections of the first semiconductor layer 2111, the light-emitting layer 212, and the second conductive layer 213 on the substrate 300( Figure 2 and Figure 5 the left edge in) overlap. One side edge of the positive projection of the ohmic contact layer 2112 and the adjacent isolation layer 400 on the substrate 300( Figure 2 and Figure 5 the right edge in), in the sub-light-emitting unit adjacent to the sub-light-emitting unit 210 where the ohmic contact layer 2112 is located, one side edge of the positive projections of the first semiconductor layer 2111, the light-emitting layer 212, and the second conductive layer 213 on the substrate 300( Figure 2 and Figure 5 the right edge in) overlap.

[0053] Wherein, the isolation layer 400 may include at least one of gallium nitride doped with carbon, Mn, and Fe. Exemplarily, the isolation layer 400 includes iron-doped gallium nitride to achieve the high-resistance characteristic of the isolation layer 400. The principle is that deep-level dopants C, Fe, and Mn are used to compensate for the shallow donors (Si impurities and O impurities) in the GaN background to increase the resistivity, so as to achieve the insulation isolation of the light-emitting unit 200 and avoid current crosstalk between units.

[0054] In some other embodiments, along the horizontal direction x, the second step structure 114 and the first step structure 113 are located on the same side of the light-emitting unit 200. In this case, the first step structure 113 and the second step structure 114 can be on the same side wall of the mask structure 100, and the formation of the step structure 110 is more simplified.

[0055] Figure 6 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention. Refer toFigure 6 , Optionally, the opposite sidewalls of the mask structure 100 adjacent to the mask opening 101 respectively include a first step structure 113 and a second step structure 114, and the first step structures 113 of the opposite sidewalls are symmetric, and the second step structures 114 of the opposite sidewalls are symmetric. In this way, the first conductive layer 211 can form a first electrode mesa at the first step structures 113 of the opposite sidewalls, and the second conductive layer 213 can form a second electrode mesa at the second step structures 114 of the opposite sidewalls, so that when forming electrodes subsequently, there are more selectable regions, facilitating the preparation of subsequent electrodes. In addition, the effective light-emitting areas of different sub-light-emitting units 210 are all concentrated in the central region, which is beneficial to improving the light-emitting effect.

[0056] As described above, the semiconductor structure includes a substrate 300, and the substrate 300 is located on one side of the mask structure 100. Optionally, from the side of the mask structure 100 close to the substrate 300 to the side far from the substrate 300, the size of the mask opening 101 gradually changes. In this way, it can ensure the formation of a mask sidewall with a step structure 110, so that the light-emitting area of the sub-light-emitting unit 210 gradually increases or decreases. The gradual change in the size of the mask opening 101 includes that the size of the mask opening 101 remains unchanged within a partial thickness range of the semiconductor structure, and within at least three thickness ranges from the side of the mask structure 100 close to the substrate 300 to the side far from the substrate 300, the sizes of the mask opening 101 are not equal and gradually increase or gradually decrease. In some embodiments, at any thickness position of the semiconductor structure, the size of the mask opening 101 can be the straight-line distance between the two farthest points on the mask opening 101 at this thickness position.

[0057] In some embodiments, the substrate 300 is located on one side of the mask structure 100, and from the side of the mask structure 100 close to the substrate 300 to the side far from the substrate 300, the size of the mask opening 101 gradually increases. This special design of the mask structure 100 will cause the lateral epitaxial growth to continuously bend the dislocations as the window becomes larger during epitaxial growth, thereby achieving bending annihilation, reducing the dislocations, and thus improving the crystal quality and light efficiency of the display unit.

[0058] , Optionally, the sub-light-emitting unit 210 includes a first sub-light-emitting unit 201, a second sub-light-emitting unit 202, and a third sub-light-emitting unit 203 stacked from the substrate 300. The first sub-light-emitting unit 201, the second sub-light-emitting unit 202, and the third sub-light-emitting unit 203 have different light-emitting colors, and the third sub-light-emitting unit 203 is a red photon light-emitting unit 210. In this way, the red photon light-emitting unit 210 can have a larger light-emitting area, which helps to improve the red light brightness and improve the final display effect of the Micro-LED.

[0059] In some embodiments, the light-emitting layer 212 includes In element, and along the thickness direction y of the semiconductor structure, the In element composition in the light-emitting layer 212 of different sub-light-emitting units 210 increases or decreases.

[0060] Optionally, from the side of the self-masking structure 100 close to the substrate 300 to the side far from the substrate 300, the In element composition in different sub-light-emitting units 210 gradually increases. In this way, during the formation of the light-emitting unit 200, the sub-light-emitting unit 210 with a smaller In element composition can be epitaxially grown first, and then the sub-light-emitting unit 210 with a larger In element composition can be epitaxially grown, which is more conducive to realizing the epitaxial growth of the sub-light-emitting unit 210. Exemplarily, the light-emitting unit 200 includes a first sub-light-emitting unit 201, a second sub-light-emitting unit 202, and a third sub-light-emitting unit 203 stacked on the substrate 300. The In element composition in the light-emitting layer 212 of the first sub-light-emitting unit 201 is less than that in the light-emitting layer 212 of the second sub-light-emitting unit 202, and the In element composition in the light-emitting layer 212 of the second sub-light-emitting unit 202 is less than that in the light-emitting layer 212 of the third sub-light-emitting unit 203.

[0061] Figure 7 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention. Refer to Figure 7 , optionally, the semiconductor structure further includes a substrate 300. The substrate 300 is located on one side of the masking structure 100, and the first conductive layer 211 of the sub-light-emitting unit 210 in the light-emitting unit 200 that is farthest from the substrate 300 covers the surface of the masking structure 100 on the side far from the substrate 300.

[0062] In this way, in different light-emitting units 200, the first conductive layers 211 of the sub-light-emitting units 210 that are farthest from the substrate 300 are connected to each other. Subsequently, a structure of a common electrode connected to the first conductive layer 211 can be formed, reducing the process steps of electrode preparation. Optionally, the material of the masking structure 100 is SiNx. Figure 7 In, the pitch D1 (the dimension of the masking opening 101 closest to the substrate 300) of the opening of the masking structure 100 is 4 μm, and the height of the masking structure 100 is 4 μm. The lengths of the tabletop surfaces of the 4 step structures 110 from bottom to top are all 3 μm. The heights of the four step structures 110 from bottom to top are 2 μm, 1.6 μm, and 1.4 μm in sequence. The first conductive layers 211 of the third light-emitting unit 200 are combined together to realize the common electrode structure of the third light-emitting unit 200.

[0063] Combined with Figures 1 - 6 , optionally, the semiconductor structure includes a plurality of masking structures 100. Each masking structure 100 encloses a masking opening 101, and the distance between adjacent masking structures 100 is greater than 0.

[0064] In some embodiments, the spacing between adjacent mask structures 100 is greater than 0, which may mean that there is a gap between adjacent mask structures 100, so that when the mask structures 100 are removed subsequently, the etchant can be accommodated in the gap, facilitating the removal of the mask structures 100, improving the removal efficiency of the mask structures 100, and further improving the preparation efficiency of the light-emitting array.

[0065] Continue to refer to Figure 1 、 Figure 2 、 Figures 4 - 7 Optionally, between the sub-light-emitting unit closest to the substrate 300 and the substrate 300, there is also a buffer layer 500, and the buffer layer 500 can be an AlN / AlGaN composite buffer layer 500 with a thickness of 10-200 nm.

[0066] Continue to refer to Figure 1 、 Figure 2 、 Figures 4 - 7 Optionally, between the first conductive layer 311 and the light-emitting layer 212, there is also an electron blocking layer 214.

[0067] The embodiments of the present invention also provide a method for preparing a semiconductor structure. Figure 8 It is a flowchart of a method for preparing a semiconductor structure provided by the embodiments of the present invention. Refer to Figure 8 The method for preparing the semiconductor structure includes:

[0068] S610. Form a mask structure layer on one side of the substrate.

[0069] Optionally, a whole-layer mask structure layer is formed on one side of the substrate.

[0070] S620. Pattern the mask structure layer to form a mask structure. The mask structure encloses a mask opening, and at least one side wall of the mask structure close to the mask opening includes at least one step structure, and the step structure includes a mask tabletop, and the mask tabletop intersects with the thickness direction of the semiconductor structure.

[0071] Optionally, the mask structure layer is patterned by a patterning process to form a mask structure with a step structure.

[0072] S630. Form a light-emitting unit in the mask opening, including at least one sub-light-emitting unit. The sub-light-emitting unit is at least partially located in the mask opening. The sub-light-emitting unit includes a first conductive layer, a light-emitting layer, and a second conductive layer stacked. Along the thickness direction of the semiconductor structure, at least a part of the first conductive layer is located on one side of the mask tabletop and / or at least a part of the second conductive layer is located on one side of the mask tabletop.

[0073] In this step, a light-emitting unit can be formed in the mask opening through an epitaxial growth process. In some embodiments, when the light-emitting unit includes at least two stacked sub-light-emitting units, each sub-light-emitting unit can be epitaxially grown in sequence. By controlling the thickness of each structural layer in the sub-light-emitting unit, at least a part of the first conductive layer is located on the mask table surface, so that the first conductive layer forms a first electrode table surface at the position of the mask table surface; and / or at least a part of the second conductive layer is located on the mask table surface, so that the second conductive layer forms a second electrode table surface at the position of the mask table surface.

[0074] In the method for preparing a semiconductor structure according to an embodiment of the present invention, by first forming a mask structure with a stepped structure on the sidewall, when growing a sub-light-emitting unit in the mask opening surrounded by the mask structure subsequently, at least a part of the first conductive layer is located on the mask table surface, so that the first conductive layer forms a first electrode table surface at the position of the mask table surface; and / or at least a part of the second conductive layer is located on the mask table surface, so that the second conductive layer forms a second electrode table surface at the position of the mask table surface. Since the first electrode table surface and / or the second electrode table surface can be formed without etching the epitaxial structure, the first electrode table surface and / or the second electrode table surface are relatively flat, which is conducive to forming an ohmic contact, reducing the difficulty of ohmic contact, and is also beneficial to reducing the process steps for forming the electrode, thereby reducing the manufacturing cost of the Micro-LED chip.

[0075] A specific example of the method for preparing a semiconductor structure is given below. The method for preparing a semiconductor structure includes the following processes. Figure 9 It is a schematic structural diagram of a semiconductor structure obtained by using the method for preparing a semiconductor structure. Refer to Figure 9 , the preparation process of the semiconductor structure includes:

[0076] 1) On the cleaned sapphire substrate 300, using photolithography and PECVD, prepare a periodic pattern of SiO 2The opening pitch D1 (the dimension closest to the substrate 300 side of the mask opening) of the mask layer and the mask structure 100 is 1 to 30 μm, and the height h1 of the mask structure 100 is 1 to 20 μm. Exemplarily, the opening pitch D1 of the mask structure 100 is 5 μm, and the height h1 of the mask structure 100 is 3.2 μm. The length a1 of the tabletop of each step structure is 2.5 μm. The upper surface (i.e., the tabletop) of the step structure 701 is 500 to 1500 nm lower than the upper surface of the step structure 702, and can be optionally 770 nm; the upper surface of the step structure 703 is 500 to 1500 nm lower than the upper surface of the step structure 704, and can be optionally 670 nm; the upper surface of the step structure 605 is 500 to 1500 nm lower than the upper surface of the step structure 706, and can be optionally 650 nm; the height of the step structure 701 is 800 to 2500 nm, and can be optionally 1000 nm; the height of the step structure 703 is 800 to 2500 nm, and can be optionally 820 nm; the height of the step structure 705 is 800 to 2500 nm, and can be optionally 800 nm; the height of the step structure 707 is 100 to 500 nm, and can be optionally 200 nm.

[0077] 2) An epitaxial growth buffer layer 500 is formed within the mask opening enclosed by the above-mentioned mask structure 100. Subsequently, the growth of the first sub-light-emitting unit 201 is carried out, including a second conductive layer 213, a light-emitting layer 212, an electron blocking layer, and a first conductive layer 211. The second conductive layer 213 may include a second semiconductor layer, which may be an N-type semiconductor layer, such as N-GaN. The light-emitting layer 212 includes quantum wells. The first conductive layer 211 includes a first semiconductor layer 2111 and an ohmic contact layer 2112. The first semiconductor layer 2111 may be a P-type conductive layer, such as P-GaN, and the ohmic contact layer 2112 may include P+GaN. The buffer layer 500 may be an AlN / AlGaN composite buffer layer 500 with a thickness of 10 - 200 nm. The thickness of the N-type semiconductor layer is 0.8 - 2 μm, and the silicon doping concentration is in the range of 4E18 - 9E19 / cm2. The quantum wells of the first sub-light-emitting unit 201 are InGaN / GaN, and the In composition is 0.08 - 0.2. The quantum well region contains 2 - 14 pairs of MQW. The thickness of the barrier GaN is 3 - 16 nm, the thickness of the well InGaN is 2 - 8 nm, and the growth temperature of InGaN is 680 - 790 °C. The electron blocking layer is a Mg-doped P-type AlGaN layer with a thickness of 20 - 100 nm and a growth temperature of 900 - 1030 °C. A Mg-doped P-GaN is grown on the electron blocking layer to form the P-type conductive layer of the first sub-light-emitting unit 201. The thickness of the P-GaN is 50 - 300 nm, and the growth temperature is 930 - 1000 °C. The Mg doping concentration is in the range of 2E18 - 1E19 / cm2. The thickness of the P+GaN is 10 - 100 nm, and the growth temperature is 900 - 1000 °C. The Mg doping concentration is in the range of 1E19 - 5E19 / cm2.

[0078] 3) A spacer layer 400 is grown above the first sub-light-emitting unit 201. The spacer layer 400 is Fe-doped GaN, with a ferrocene flow rate of 20 - 300 sccm and a thickness of 50 - 300 nm, preferably 100 nm.

[0079] 4) Subsequently, a second sub-light-emitting unit 202 is epitaxially grown above the first isolation layer 400, which includes a second conductive layer 213, a light-emitting layer 212, an electron blocking layer, and a first conductive layer 211. The second conductive layer 213 may include a second semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer, such as N-GaN. The light-emitting layer 212 includes quantum wells. The first conductive layer 211 includes a first semiconductor layer 2111 and an ohmic contact layer 2112. The first semiconductor layer 2111 may be a P-type conductive layer, such as P-GaN, and the ohmic contact layer 2112 may include P+GaN. The thickness of the N-type semiconductor layer is 100 - 800 nm, optionally 300 nm, and the silicon doping concentration is 4E18 - 9E19 / cm2. The quantum wells of the second sub-light-emitting unit 202 are InGaN / GaN, and the In composition is 0.18 - 0.3. The quantum well region contains 2 - 14 pairs of MQWs. The thickness of the barrier GaN is 3 - 16 nm, the thickness of the well InGaN is 2 - 8 nm, and the growth temperature of InGaN is 670 - 770 °C. The electron blocking layer is a Mg-doped P-type AlGaN layer with a thickness of 20 - 110 nm and a growth temperature of 900 - 1030 °C. A Mg-doped P-GaN is grown on the electron blocking layer to form the P-type conductive layer of the second sub-light-emitting unit 202. The thickness of the P-GaN is 50 - 300 nm, and the growth temperature is 930 - 1000 °C. The Mg doping concentration is 2E18 - 1E19 / cm2. The thickness of the P+GaN is 10 - 100 nm, and the growth temperature is 900 - 1000 °C. The Mg doping concentration is 1E19 - 5E19 / cm2.

[0080] 5) The isolation layer 400 is grown above the second sub-light-emitting unit 202. The isolation layer 400 is Fe-doped GaN, the ferrocene flow rate is 20 - 300 sccm, the thickness is 50 - 300 nm, and optionally 100 nm.

[0081] 6) Above the isolation layer 400, a third sub-light-emitting unit 203 is then epitaxially grown, including a second conductive layer 213, a light-emitting layer 212, an electron blocking layer, and a first conductive layer 211. The second conductive layer 213 may include a second semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer, such as N-GaN. The light-emitting layer 212 includes quantum wells. The first conductive layer 211 includes a first semiconductor layer 2111 and an ohmic contact layer 2112. The first semiconductor layer 2111 may be a P-type conductive layer, such as P-GaN, and the ohmic contact layer 2112 may include P+GaN. The thickness of the N-type semiconductor layer N-GaN is 100 - 800 nm, optionally 300 nm, and the silicon doping concentration is 4E18 - 9E19 / cm2. The quantum wells of the third sub-light-emitting unit 203 are InGaN / GaN, and the In component is 0.25 - 0.45. The quantum well region contains 2 - 8 pairs of MQWs. The thickness of the barrier GaN is 3 - 16 nm, the thickness of the well InGaN is 2 - 8 nm, and the growth temperature of InGaN is 630 - 720 °C. The electron blocking layer is a Mg-doped P-type AlGaN layer with a thickness of 20 - 110 nm and a growth temperature of 900 - 1030 °C. A Mg-doped P-GaN is grown on the electron blocking layer to become the P-type conductive layer of the third sub-light-emitting unit 203. The thickness of the P-GaN is 50 - 300 nm, and the growth temperature is 930 - 1000 °C. The Mg doping concentration is 2E18 - 1E19 / cm2. The thickness of the P+GaN is 10 - 100 nm, and the growth temperature is 900 - 1000 °C. The Mg doping concentration is 1E19 - 5E19 / cm2.

[0082] 7) The schematic diagram of the structure after epitaxial growth in the final mask pattern structure is as Figure 9 shown. At the position corresponding to the mask mesa, the first conductive layer 211 can form a corresponding first electrode mesa 11, and the second conductive layer 213 can form a corresponding second electrode mesa 12.

[0083] Figure 10 is a schematic structural diagram of a light-emitting array provided by an embodiment of the present invention. Referring to Figure 10 , the light-emitting array includes: a light-emitting unit including at least one sub-light-emitting unit 210. The sub-light-emitting unit 210 includes a first conductive layer 211, a light-emitting layer 212, and a second conductive layer 213 stacked. The first conductive layer 211 includes a first electrode mesa 11, and a first electrode 10 is provided on one side of the first electrode mesa 11. The first electrode 10 is electrically connected to the first conductive layer 211; and / or, the second conductive layer 213 includes a second electrode mesa 12, and a second electrode 20 is provided on one side of the second electrode mesa 12. The second electrode 20 is electrically connected to the second conductive layer 213.

[0084] Among them, the first electrode mesa 11 of the first conductive layer 211 is formed at the position of the first mask mesa in the first step structure of the mask structure, and the second electrode mesa 12 of the second conductive layer 213 is formed at the position of the second mask mesa in the second step structure of the mask structure.

[0085] In this embodiment, the light-emitting array can be obtained by removing the mask structure from the semiconductor structure in the above embodiments of the present invention. When the semiconductor structure includes a substrate, the substrate can also be removed. The light-emitting array can be transferred onto the driving backplane 30 to form a display panel.

[0086] In the light-emitting array of this embodiment, the first electrode mesa and the second electrode mesa naturally expose the first conductive layer and the second conductive layer. Subsequently, a first electrode can be prepared at the first electrode mesa, and a second electrode can be prepared at the second electrode mesa, without the need for mesa etching technology, reducing the sidewall damage to the epitaxial structure. Since the first electrode mesa and / or the second electrode mesa can be formed without etching the epitaxial structure, the first electrode mesa and / or the second electrode mesa are relatively flat, which is conducive to forming ohmic contacts, reducing the difficulty of ohmic contacts, and also facilitating the reduction of the process steps for electrode formation, thereby reducing the manufacturing cost of the Micro-LED chip.

[0087] The embodiment of the present invention also provides a method for manufacturing a light-emitting array. Figure 11 It is a flowchart of a method for manufacturing a light-emitting array provided by the embodiment of the present invention. Refer to Figure 11 and the method for manufacturing the light-emitting array includes:

[0088] S810. Remove the mask structure of the semiconductor structure.

[0089] The semiconductor structure is the semiconductor structure in any of the above embodiments of the present invention.

[0090] S820. Form a first electrode at the first electrode mesa corresponding to the first conductive layer, and / or form a second electrode at the second electrode mesa corresponding to the second conductive layer.

[0091] Among them, in the semiconductor structure, the first electrode mesa is located on one side of the mask mesa, and / or the second electrode mesa is located on one side of the mask mesa. Exemplarily, after removing the mask structure of the semiconductor structure, laser lift-off is performed on the substrate 300 and the light-emitting unit of the semiconductor structure. For example, for a sapphire substrate, it can be transparent sio2, Al2O3, SiNx, etc., and laser lift-off can be used to realize the transfer of the Micro-LED array. For an opaque silicon substrate, a metal Cr mask or a SiO2 mask can be used, and then wet etching can be performed using solutions such as FeCl3 and BOE to separate the Micro-LED array, the mask layer, and the substrate, so as to further realize the transfer. Subsequently, using the temporary bonding technology, the array of light-emitting units is transferred to a temporary substrate or a substrate, and then through photolithography and metal coating, metal pads are deposited on the first electrode mesa and the second electrode mesa, such as Ni / Au with a thickness of 100 / 80 nm, and annealing is completed. After achieving ohmic contact, the light-emitting array with deposited electrodes is bonded to the driving backplane using a flip-chip bonder, thereby realizing independent control of each pixel and each color for Micro-LED full-colorization.

[0092] The method for preparing the light-emitting array of this embodiment is prepared using the semiconductor structure of any embodiment of the present invention and has the beneficial effects of the semiconductor structure of any of the above embodiments of the present invention.

[0093] It should be understood that various forms of processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0094] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: A mask structure, wherein the mask structure encloses a mask opening, wherein a sidewall of at least one side of the mask structure close to the mask opening comprises at least one step structure, wherein the step structure comprises a mask mesa, and the mask mesa intersects with a thickness direction of the semiconductor structure; A light-emitting unit, comprising at least one sub-light-emitting unit, wherein the sub-light-emitting unit is at least partially located in the mask opening, and the sub-light-emitting unit comprises a first conductive layer, a light-emitting layer, and a second conductive layer which are stacked, and along the thickness direction of the semiconductor structure, at least a portion of the first conductive layer is located on one side of the mask table and / or at least a portion of the second conductive layer is located on one side of the mask table.

2. The semiconductor structure according to claim 1, characterized in that: The sidewall of the mask structure close to the mask opening includes a first step structure, and the first step structure includes a first mask table; The first conductive layer includes a first semiconductor layer, and along the thickness direction of the semiconductor structure, at least a portion of the first semiconductor layer is located on one side of the first mask mesa; or, The first conductive layer includes a first semiconductor layer and an ohmic contact layer, wherein the ohmic contact layer is located on a side of the first semiconductor layer away from the light emitting layer; along the thickness direction of the semiconductor structure, at least part of the ohmic contact layer is located on one side of the first mask table.

3. The semiconductor structure according to claim 2, characterized in that: At the position of the second conductive layer, the sidewalls of the mask structure are vertical sidewalls, inclined sidewalls or smooth sidewalls.

4. The semiconductor structure according to claim 2, characterized in that: The sidewall of the second conductive layer close to the mask opening includes a second step structure, the second step structure includes a second mask mesa, and along the thickness direction of the semiconductor structure, at least a portion of the second conductive layer is located on one side of the second mask mesa; Wherein, along the horizontal direction, the second step structure and the first step structure are located on the same side or different sides of the light emitting unit.

5. The semiconductor structure according to claim 4, characterized in that: In the horizontal direction, the second step structure and the first step structure are located on different sides of the light emitting unit, and the first step structure and the second step structure are asymmetric.

6. The semiconductor structure according to claim 4, characterized in that: The opposite side walls of the mask structure close to the mask opening respectively include the first step structure and the second step structure, and the first step structures of the opposite side walls are symmetrical, and the second step structures of the opposite side walls are symmetrical.

7. The semiconductor structure according to claim 4, characterized in that: The light-emitting unit includes at least two sub-light-emitting units, and an isolation layer is arranged between adjacent sub-light-emitting units; the semiconductor structure also includes a substrate located on one side of the mask structure, and in the sub-light-emitting units, the first semiconductor layer, the light-emitting layer and the second conductive layer have overlapping orthographic projections on the substrate; the ohmic contact layer overlaps with the orthographic projection of the adjacent isolation layer on the substrate.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: It also includes a substrate, which is located on one side of the mask structure. The size of the mask opening changes gradually from the side of the mask structure close to the substrate to the side far from the substrate.

9. The semiconductor structure according to claim 8, characterized in that: The size of the mask opening gradually increases from a side of the mask structure close to the substrate to a side far away from the substrate.

10. The semiconductor structure according to claim 9, characterized in that: The light-emitting unit includes a first sub-light-emitting unit, a second sub-light-emitting unit and a third sub-light-emitting unit stacked from the substrate, the first sub-light-emitting unit, the second sub-light-emitting unit and the third sub-light-emitting unit have different light-emitting colors, and the third sub-light-emitting unit is a red light-emitting unit.

11. The semiconductor structure according to claim 1, characterized in that: The light-emitting layer includes In elements, and along the thickness direction of the semiconductor structure, the In element composition in the light-emitting layers of different sub-light-emitting units increases or decreases.

12. The semiconductor structure according to claim 1, characterized in that It also includes a substrate, which is located on one side of the mask structure, and the first conductive layer of the sub-light-emitting unit in the light-emitting unit farthest from the substrate covers the surface of the mask structure farthest from the substrate.

13. The semiconductor structure according to claim 1, characterized in that It comprises a plurality of the mask structures, each of the mask structures encloses a mask opening, and the spacing between adjacent mask structures is greater than 0.

14. A light emitting array, characterized in that: include: A light-emitting unit, comprising at least one sub-light-emitting unit, wherein the sub-light-emitting unit comprises a first conductive layer, a light-emitting layer, and a second conductive layer which are stacked; The first conductive layer includes a first electrode mesa, a first electrode is disposed on one side of the first electrode mesa, and the first electrode is electrically connected to the first conductive layer; and / or the second conductive layer includes a second electrode mesa, a second electrode is disposed on one side of the second electrode mesa, and the second electrode is electrically connected to the second conductive layer.

15. A method for preparing a semiconductor structure, characterized in that: include: forming a mask structure layer on one side of the substrate; Patterning the mask structure layer to form a mask structure, wherein the mask structure encloses a mask opening, and a sidewall of at least one side of the mask structure close to the mask opening includes at least one step structure, wherein the step structure includes a mask table, and the mask table intersects with the thickness direction of the semiconductor structure; A light-emitting unit is formed in the mask opening, including at least one sub-light-emitting unit, wherein the sub-light-emitting unit is at least partially located in the mask opening, and the sub-light-emitting unit includes a first conductive layer, a light-emitting layer, and a second conductive layer that are stacked, and along the thickness direction of the semiconductor structure, at least a portion of the first conductive layer is located on one side of the mask table and / or at least a portion of the second conductive layer is located on one side of the mask table.

16. A method for preparing a light emitting array, characterized in that: include: Removing a mask structure of a semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 14; forming a first electrode at a first electrode mesa corresponding to the first conductive layer, and / or forming a second electrode at a second electrode mesa corresponding to the second conductive layer; In the semiconductor structure, the first electrode mesa is located on one side of the mask mesa, and / or the second electrode mesa is located on one side of the mask mesa.

Images