Gate driver circuit and converter

Abstract

A gate driver circuit for a half-bridge of a converter in which a first switching device having a first gate and a second switching device having a second gate are independently controlled in a complementary manner by a controller through a first gate driver buffer and a second gate driver buffer, respectively, the controller provides a gate pull-up pulse signal and a gate pull-down pulse signal to the first gate driver buffer and the second gate driver buffer, characterized in that the gate driver circuit comprises an overlap protection circuit comprising: on a source branch of the first gate driver buffer, a gate pull-up pulse signal and a gate pull-down pulse signal; the first gate current mirror circuit provides a first detection signal when the first gate driver buffer is turned on; the first detection circuit is used for processing the first detection signal and transmitting the first detection signal to a second protection circuit of the second gate buffer; the second protection circuit is configured to cut off the second switching device when the first detection signal appears; on a source branch of the second gate driver buffer, a second gate current mirroring circuit providing a second detection signal when the second gate driver buffer is on, and a second detection circuit for processing and transmitting the first detection signal to a first protection circuit of the first gate buffer; the first protection circuit is configured to turn off the first switching device when the second detection signal occurs.

Description

Technical Field

[0001] The present disclosure relates to a power converter including at least one switched half - bridge, and more particularly, to protecting against overlap during the switching transition period of the switches of the switched half - bridge. Background Art

[0002] In a power converter composed of at least one half - bridge, the switches are independently controlled in a complementary manner to provide transitions from conduction to blocking and from blocking to conduction. A dead - time during which both switches are off is necessary between these transitions. The main reason for the dead - time is the risk of control voltage overlap caused by various factors, including propagation delay, mismatch between turn - on and turn - off delay times, drift of the threshold voltage with temperature, and shoot - through current that can damage the device.

[0003] In existing converters, there are different methods to ensure that the control signals applied to the half - bridge do not overlap.

[0004] The first method is to use off - the - shelf dedicated half - bridge gate driver ICs with overlap protection. Generally, these devices include logic conditioning circuits that avoid overlap of the output signals that control the gates of the half - bridge power devices even if the signals from the controller overlap. The signal conditioning achieved depends on the manufacturer and is not known to the external user. For example, the gate driver IC known from the reference Si8273 from SiliconLabs Corporation presents an overlap protection circuit that detects when both input levels are high and forces one of the outputs to GND, thus avoiding any short - circuit on the power side.

[0005] The second method involves gate driver ICs without overlap protection and requires proper sequencing of the control signals fed to the gate driver to avoid any problems. Therefore, sufficient dead - time must be arranged.

[0006] As mentioned above, in a power converter, fast and precise control of the two switches of the half - bridge is mandatory. However, wide - bandgap devices such as SiC or GaN have fast switching capabilities, which lead to an increase in the switching frequency and thus an increase in the constraints on the control section.

[0007] The commonly implemented half - bridge configuration requires proper control timing to avoid cross - conduction and shoot - through current, which can result in significant additional losses or even semiconductor destruction.

[0008] However, an incorrect control signal is applied to the gate electrode, resulting in cross-conduction. There can be multiple reasons for this, such as control errors in pulling up one of the gate driver outputs at the wrong time, a faulty gate driver IC that blocks in the high state, or an incorrect control signal caused by EMI issues. Therefore, overlap detection / protection can prevent short circuits caused by controller errors or faulty gate drivers. SUMMARY OF THE INVENTION

[0009] In view of this situation, the present disclosure proposes a simple protection system that uses current-based gate current sensing technology to detect these incorrect control signals, and a circuit for avoiding short circuits in a half-bridge in these situations.

[0010] The proposed circuit is based on current mirror technology. The current mirror circuit allows the gate current of one of the switches to be sensed during its conduction period, and in the case where the other switch has conducted, the protection circuit can turn off the other switch.

[0011] Then the mirrored current is processed and transmitted through an insulating barrier to the opposite gate driver. The conditioning and / or buffering circuit allows the detection of whether a positive gate current is sensed while the second gate driver voltage is already high. Therefore, protection can be implemented using appropriate dedicated logic.

[0012] In view of the above, the present disclosure proposes a gate driver circuit for a half-bridge of a converter, wherein a controller independently controls a first switching device having a first gate and a second switching device having a second gate in a complementary manner through a first gate driver buffer and a second gate driver buffer respectively, the controller provides a gate pull-up pulse signal and a gate pull-down pulse signal to the first gate driver buffer and the second gate driver buffer, and the gate driver circuit includes an overlap protection circuit, the overlap protection circuit includes:

[0013] - A first gate current mirror circuit on the source branch of the first gate driver buffer that provides a first detection signal when the first gate driver buffer is conducting, and a first detection circuit of a second protection circuit for processing the first detection signal and transmitting it to the second gate buffer, the second protection circuit being configured to turn off the second switching device when the first detection signal appears;

[0014] - A second gate current mirror circuit on the source branch of the second gate driver buffer that provides a second detection signal when the second gate driver buffer is conducting, and a second detection circuit of a first protection circuit for processing the first detection signal and transmitting it to the first gate buffer, the first protection circuit being configured to turn off the first switching device when the second detection signal appears.

[0015] This gate driver circuit protects the overlapping protection half-bridge through a fast protection circuit.

[0016] To provide an insulation barrier between the upper and lower circuits, the first detection circuit may be connected to the first gate mirror circuit through a first insulation barrier, and the second detection circuit may be connected to the second gate mirror circuit through a second insulation barrier. In the implementation mode, this insulation barrier is a current transformer.

[0017] To improve the signal and avoid false detection, the first detection circuit and the second detection circuit may each include an adjustment circuit.

[0018] The present disclosure also relates to a gate driver circuit for a half-bridge of a converter, wherein the first detection circuit and the second detection circuit each include a trigger circuit and an error detection protection circuit, and only allow the detection of overlap errors when a detection signal is issued when the opposite pre-driver positive-driver command output is on.

[0019] In this case, the first detection circuit and the second detection circuit may each include a latch circuit to latch the detected overlap error, transmit the detected overlap error to the controller, and trigger the protection circuit.

[0020] This provides both protection of the half-bridge and information about defects at the controller level.

[0021] Each of the first protection circuit and the second protection circuit may be composed of a controllable switch that pulls down the gate electrode of the corresponding switching device. The controllable switch may be made of a diode and a MOSFET.

[0022] The controller may include a reset output for resetting the detection circuit to restart the conversion.

[0023] The reset output may be connected to the reset input of the latch circuit through an insulating device.

[0024] The gate driver buffer associated with the current mirror circuit may be driven by a pre-driver circuit that transmits a control signal from the controller to the gate driver buffer and provides electrical insulation between the controller and the gate driver buffer.

[0025] The present disclosure also relates to a half-bridge converter including the gate driver circuit as described above.

[0026] The detailed description of the exemplary embodiments of the present invention will be discussed below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Figure 1 is a schematic diagram of a conventional half-bridge in a converter. ​​

[0028] Figure 2 Figure 2 is a schematic diagram showing a block of a half - bridge command circuit including a detection / protection circuit according to the present disclosure.

[0029] Figure 3 Figure 3 are details of the upper detection / protection circuit of the present disclosure.

[0030] Figure 4 Figure 4 is a schematic diagram of a complete half - bridge command circuit including a detection / protection circuit according to the present disclosure.

[0031] Figure 5 Figure 5 shows the switching waveforms of the overlap control signal in the absence of an overlap protection circuit.

[0032] Figure 6 Figure 6 shows the switching waveforms of the overlap control signal in the presence of an overlap protection circuit. Detailed Description

[0033] Figure 1 is a schematic diagram of a half - bridge in a converter having an upper - leg switch S H and a lower - leg switch S L . The upper - leg switch includes a transistor Q1 which, in the present case, is a MOSFET represented by its body diode D1 and its parasitic output capacitor C1, while the lower - leg switch includes a transistor Q2 represented by its body diode D2 and parasitic output capacitor C2. The anti - parallel diodes D1 and D2 can be additional components.

[0034] In this figure, MOSFET devices are considered in the switching unit. The switch symbol includes the intrinsic body diode and the output capacitor COSS. The load 51 is connected between the mid - point of the switching unit and the high potential of the DC voltage source. The load current is considered positive, meaning the current flows from the positive DC bus to the mid - point of the switching unit, and the load current is considered constant during the transition time scale.

[0035] The switches S H and S L are controlled by a gate control circuit 50a for the upper - leg switch and a gate control circuit 50b for the lower - leg switch, and the capacitor 52 on the DC side filters the HF signals created by the switching sequence. The gate control circuits 50a, 50b include push - pull output transistors known in the art.

[0036] ​​​​​​​​​​Starting from these basic diagrams, the present disclosure relates to a detection / protection circuit for a half-bridge of an interleaved protection converter and to prevent short circuits due to controller errors or faulty gate drivers.

[0037] This circuit is designed to detect the overlap of gate control signals or the mis-conduction of power devices due to faulty gate drivers. Both will result in a short circuit in the power stage. Interleaved protection can be implemented in any type of voltage source converter where short circuits must be absolutely avoided.

[0038] Figure 2 A schematic diagram of the functional blocks of the circuit of the present disclosure is provided. The circuit starts with an upper current mirror circuit 32a and a lower current circuit 32b. The circuit includes an upper protection circuit 34a and a lower protection circuit 34b, pre-drivers 10a, 10b, which receive commands from a controller 60 and provide electrical insulation between such a controller and the upper driver circuit and the lower driver circuit. The circuit also includes an upper protection circuit 34a connected to a bottom detection circuit 33b, a lower protection circuit 34b connected to an upper detection circuit 33a, and electrical insulation circuits 36a, 36b that send error signals from the detection circuits to the controller through an insulation barrier (e.g., an opto-coupler or other insulation device). Since these parts of the half-bridge converter are powered by different voltage sources, electrical insulation between the controller, the upper gate buffer circuit, and the lower gate buffer circuit is required.

[0039] Electrical insulation (also known as an insulation barrier) can also be accomplished using an opto-coupler, a current transformer, or a voltage transformer.

[0040] In the drawings, it should be noted that the element driving the second switching device S L is referred to as the bottom element, also known as "Bot.", e.g., "Bot.Detection" or "Bot.Detect.", "Bot.Protection" or "Bot.Prot.", and the element driving the first switching device S H is referred to as the top element and has the prefix "Top", e.g., "Top Protection" or "Top Prot.", "Top Detection" or "Top Detect.".

[0041] The upper circuit ground is labeled GNDt, the lower circuit ground is labeled GNDb, the upper circuit VDD is labeled V DDtop and the lower circuit VDD is labeled V DDbot and the upper circuit VSS is labeled V SStop and the lower circuit VSS is labeled V SSbot .

[0042] Both the upper circuit and the lower circuit are constructed on the same design. Figure 3A more detailed diagram of the upper part of the half-bridge command circuit is provided, where the upper current mirror circuit 32a is connected to the top detection circuit 33a through a current transformer 321. This current transformer can be replaced by another type of insulation barrier, such as an optocoupler, a current transformer, or a voltage transformer.

[0043] The current mirror circuit made of transistors T5 T and T3 T and resistors RT T and R MonT is used to copy the gate current from the gate buffer to the gate driver through an insulation barrier (here provided by the current transformer 321). The detection circuit consists of multiple sub-functions, the conditioning circuit C1 that conditions the signal from the current transformer 321 B 、D1 B and R1 B and, in the case of overlap detection, the transistor Q2 B triggers the comparator 331, which receives the reference voltage "Ref Bot." that sets the system response time on its negative input. In this design, MOSFETs Q1 B and Q3 B are used to avoid false triggering of the protection. The comparator is necessary to latch the detected error, transmit the detection to the controller with the "FaultDetect.Bot" signal, and trigger the protection circuit of the bottom gate buffer, which consists of a controllable switch that pulls down the base of the gate buffer 1b shown in Figure 4 and the gate electrode of the bottom power device (here made of the diode D3 B and MOSFET Q5 B ). For example, the controllable switch function can be implemented using some other known controllable switch components (e.g., JFET, BJT, HEMT).

[0044] The bottom circuit is the same as C1 that conditions the signal from the current transformer 322 T 、D1 T and R1 T and it can also be replaced by another type of insulation barrier, such as an optocoupler or a voltage transformer. In the case of overlap detection, the transistor Q2 T triggers the comparator 332, which receives the reference voltage "Ref Top" on its negative input. MOSFETs Q1 T and Q3 T are used to avoid false triggering of the protection. The comparator is necessary to latch the detected error, transmit the detection to the controller with the "Fault Detect.Bot" signal, and trigger the protection circuit of the bottom gate buffer, which has a pull-down Figure 4The controllable switch of the base of the gate buffer 1a shown and the gate electrode of the top power device (here by diode D3 B and MOSFET Q5 T fabricated).

[0045] In summary, the gate driver circuit of the half-bridge of the converter 100 (where the controller 60 independently controls the first switching device S with the first gate and the second switching device S with the second gate in a complementary manner through the first gate driver buffer 1a and the second gate driver buffer 1b respectively), and the controller 60 provides a gate pull-up pulse signal and a gate pull-down pulse signal to the first gate driver buffer and the second gate driver buffer) includes an overlap protection circuit, which includes: H and the second switching device S with the second gate L , the controller 60 includes an overlap protection circuit, which includes:

[0046] - On the source branch of the first gate driver buffer 1a, a first gate current mirror circuit 32a that provides a first detection signal when the first gate driver buffer is conducting, and a first detection circuit 33a for processing the first detection signal and transmitting it to the second protection circuit 34b of the second gate buffer 1b. The second protection circuit 34b is configured to turn off the second switching device S L when the first detection signal appears;

[0047] - On the source branch of the second gate driver buffer 1b, a second gate current mirror circuit 32b that provides a second detection signal when the second gate driver buffer is conducting, and a second detection circuit 33b for processing the first detection signal and transmitting it to the first protection circuit 34a of the first gate buffer 1a. The first protection circuit 34a is configured to turn off the first switching device S H when the second detection signal appears.

[0048] As mentioned above, since the detection circuit connected to the gate mirror circuit uses the voltage of another gate buffer as a reference to trigger the protection of that another gate buffer, insulation is required between the detection circuit and the gate mirror circuit of the gate buffer. Therefore, the first detection circuit 33a (for example, the top detection circuit) is connected to the first gate mirror circuit 32a (for example, the top gate mirror circuit) through the first current transformer 321 that provides the first insulation barrier, and the second detection circuit 33b (for example, the bottom detection circuit) is connected to the second gate mirror circuit 32b (for example, the bottom gate mirror circuit) through the second current transformer 322 that provides the second insulation barrier.

[0049] The trigger circuits Q2 B 、Q2 T of the first detection circuit and the second detection circuit each include an error detection protection circuit Q1B , Q1 T , Q3 B , Q3 T , so that when the positive driver commands of the reverse pre-drivers 10a and 10b output "vo+" to be on, the detection of overlap errors is allowed only when a detection signal is issued.

[0050] The latch circuit with comparators 331 and 332 allows latching of the detected overlap errors, transmits the detected overlap error "Fault Detect." to the controller, and triggers the protection circuits 34a and 34b of the reverse gates by sending the error signal "Err.To Bot.Prot." or the error signal "Err.To Top Prot." respectively. The reset inputs of the comparators can be enabled by the controller with Rs1 and Rs2 outputs through the MOSFET transistors Q4 of the top detection circuit 33a and the bottom detection circuit 33b B , Q4 T to be enabled.

[0051] The influence of the overlap control signal is presented in Figure 5 and depicted below.

[0052] Refer to Figure 1 the notations in, the initial state corresponds to the freewheeling time, and the load current flows through the top switch S H . At time t0, the control signal switches from negative to positive, and the gate-source voltage V L of Q2 of the switch S GS2 starts to increase. At t1, the gate-source voltage of the conducting device S L reaches the threshold, so the drain current (the current flowing through S L ) rises to the load current value. During the Miller flat region, from t2 to t3, the drain-source voltage V DS2 of Q2 drops from VDC to 0, while the drain-source voltage V H of Q1 of the switch S DS1 rises accordingly. From t3 to t4, the gate-source voltage V GS2 of Q2 continues to rise, but the power waveform does not change. At t5, a signal is sent to the gate of the second switch Q1 due to improper operation caused by one or more of the previously listed reasons. Once the gate voltage reaches the threshold, at t6, Q1 and Q2 conduct simultaneously, resulting in a short circuit. The current flowing through the switch rises within the limit set by the total switch unit impedance. In fact, it can reach several kA, which may cause damage to the power device. After a specific amount of time, due to the self-heating of the power device, the on-resistance increases, and a slight decrease in the current can be noticed. The two devices will share the DC bus voltage across their transconductances respectively.

[0053] Then the impact of the proposed protection method is introduced, and the updated waveforms are presented in Figure 6 In the case where the gate driver includes overlap protection, from t0 to t4, the conduction operation of Q2 remains the same as before. Changes occur during the mis-conduction of Q1. In fact, at t5, an error signal is sent to the gate driver, the gate voltage starts to rise, and a positive gate current is sensed. At t6, the threshold is reached, so the current starts to rise. However, after a slight delay, the feedback of the gate current sensed on Q1 is sent to the gate driver of Q2, forcing the gate driver to turn off. Thus, the short circuit stops before a critical failure.

[0054] The above description is based on MOSFET applications such as those described in Figure 1 but can be extended to any unipolar transistor such as JFET, IGFET, HEMT or bipolar transistors BJT or IGBT, with changes in electrode names as known to those skilled in the art.

[0055] The present disclosure is not limited to the above description. In particular, the overlap protection circuit described herein can be used in converters having more than one half-bridge, with each half-bridge having such a protection circuit for its top and bottom switches.

Claims

1. A gate driver circuit for a half-bridge of a converter, wherein a controller independently controls a first switching device having a first gate and a second switching device having a second gate in a complementary manner through a first gate driver buffer and a second gate driver buffer respectively, and the controller provides a gate pull-up pulse signal and a gate pull-down pulse signal to the first gate driver buffer and the second gate driver buffer. Characterized in that, the gate driver circuit includes an overlap protection circuit, and the overlap protection circuit includes: - a first gate current mirror circuit on the source branch of the first gate driver buffer, which provides a first detection signal when the first gate driver buffer is turned on, and a first detection circuit of a second protection circuit for processing the first detection signal and transmitting the first detection signal to the second gate buffer, and the second protection circuit is configured to turn off the second switching device when the first detection signal appears; - a second gate current mirror circuit on the source branch of the second gate driver buffer, which provides a second detection signal when the second gate driver buffer is turned on, and a second detection circuit of a first protection circuit for processing the first detection signal and transmitting the first detection signal to the first gate buffer, and the first protection circuit is configured to turn off the first switching device when the second detection signal appears.

2. The gate driver circuit for a half-bridge of a converter according to claim 1, wherein, the first detection circuit is connected to the first gate mirror circuit through a first insulation barrier, and the second detection circuit is connected to the second gate mirror circuit through a second insulation barrier.

3. The gate driver circuit for a half-bridge of a converter according to claim 2, wherein, the first insulation barrier and the second insulation barrier are made of a current transformer, an optocoupler or a voltage transformer.

4. The gate driver circuit for a half-bridge of a converter according to any one of claims 1 to 3, wherein, each of the first detection circuit and the second detection circuit includes an adjustment circuit.

5. The gate driver circuit for a half-bridge of a converter according to any one of claims 1 to 4, wherein, each of the first detection circuit and the second detection circuit includes a trigger circuit and an error detection protection circuit, and when the opposite pre-driver positive driver command output is on, the overlap error is only allowed to be detected when a detection signal is issued.

6. The gate driver circuit for a half-bridge of a converter according to claim 5, wherein, each of the first detection circuit and the second detection circuit includes a latch circuit to latch the detected overlap error, transmit the detected overlap error to the controller and trigger the protection circuit.

7. The gate driver circuit for a half-bridge of a converter according to claim 6, wherein, each of the first protection circuit and the second protection circuit is composed of at least one controllable switch for pulling down the gate electrode of the corresponding switching device.

8. The gate driver circuit for a half - bridge of a converter according to claim 7, wherein, the at least one controllable switch is made of a diode and a MOSFET.

9. The gate driver circuit for a half - bridge of a converter according to any one of claims 1 to 8, wherein, the controller includes a reset output for resetting the detection circuit.

10. The gate driver circuit for a half - bridge of a converter according to claims 6 and 9, wherein, the reset output is connected to the reset input of the latch circuit through an insulating device.

11. The gate driver circuit according to any one of claims 1 to 10, wherein, the gate driver buffer associated with the current mirror circuit is driven by a pre - driver circuit that conveys a control signal from the controller to the gate driver buffer and provides electrical insulation between the controller and the gate driver buffer.

12. A converter having at least a half - bridge, the half - bridge including the gate driver circuit according to any one of claims 1 to 11.

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