Semiconductor device

Abstract

The invention provides a semiconductor device which operates appropriately. To this end, a semiconductor device is provided with: a first conductive layer (20) having a drift region; a first insulating layer (34) in contact with the first conductive layer (20); a side gate layer (30) which is formed in a long shape, has at least one end connected to a gate wiring line (106), extends along the first insulating layer (34), and applies a voltage to the first conductive layer (20) via the first insulating layer (34); and a contact layer (32) which is formed of a metal-containing material having a lower volume resistivity than that of the side gate layer (30), and which is provided so as to extend in contact with the side gate layer (30).

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] As background art in this technical field, it is described in the abstract of Patent Document 1 below that "characteristics such as turn-on loss of a semiconductor device are adjusted."

[0003] In addition, it is described in the abstract of Patent Document 2 below that "a semiconductor element with improved electrical characteristics."

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2021-122076

[0007] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2007-273907 Summary of the Invention

[0008] Problems to be Solved by the Invention

[0009] However, in the above technologies, there is an urgent desire to make the semiconductor device operate more appropriately.

[0010] The present invention is a solution proposed in view of the above circumstances, and an object thereof is to provide a semiconductor device that operates appropriately.

[0011] Means for Solving the Problems

[0012] To solve the above problems, the semiconductor device of the present invention is characterized by including: a first conductive layer having a drift region; a first insulating layer in contact with the first conductive layer; a gate wiring; a side gate layer formed in a long shape and connected to at least one end of the gate wiring, extending along the first insulating layer, and applying a voltage to the first conductive layer via the first insulating layer; and a contact layer formed of a metal-containing material having a lower volume resistivity than the side gate layer, in contact with the side gate layer and extending.

[0013] Effects of the Invention

[0014] According to the present invention, a semiconductor device that operates appropriately can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic top view of the semiconductor device of the first embodiment.

[0016] Figure 2 is a schematic enlarged top view of the main part of the semiconductor device.

[0017] Figure 3 It is a schematic cross-sectional view of the main part of a semiconductor device. Detailed implementation

[0018] [First implementation]

[0019] Figure 1 It is a schematic top view of the semiconductor device 100 of the first implementation.

[0020] The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor) and is formed in a substantially rectangular plate shape. Let the orthogonal axes in the surface direction of the semiconductor device 100 be the X-axis and the Y-axis, and let the axis in the thickness direction of the semiconductor device 100 be the Z-axis. In addition, in the following description, for convenience, the positive and negative directions of the X-axis direction are referred to as "right" and "left", the positive and negative directions of the Y-axis direction are referred to as "front" and "rear", and the positive and negative directions of the Z-axis direction are referred to as "up" and "down". These do not refer to the direction when the semiconductor device 100 is installed.

[0021] A substantially rectangular gate pad 102 is formed at the right rear corner of the semiconductor device 100. A pair of gate wirings 104 extend in the front-rear direction along the left and right sides of the semiconductor device 100. In addition, two of the five gate wirings 106 extend in the left-right direction along the front and rear sides of the semiconductor device 100, and the remaining three extend in the left-right direction at positions that divide the semiconductor device 100 into substantially four equal parts in the front-rear direction. The gate pad 102 is connected to the gate wirings 104 and 106 in a mutually conductive manner.

[0022] In addition, at the positions of the four parts surrounded by the gate pad 102 and the gate wirings 104 and 106, four substantially rectangular emitter electrodes 110 that are insulated from the gate pad 102 and the gate wirings 104 and 106 are formed. The gate pad 102, the gate wirings 104 and 106, and the emitter electrodes 110 are formed of a metal-containing material. Here, the "metal-containing material" is a material that contains metal in at least a part of the region, and the metal contained here is, for example, aluminum, aluminum-silicon alloy, etc.

[0023] Figure 2 It is a schematic enlarged top view of the main part of the semiconductor device 100. That is, Figure 2 It is Figure 1 An enlarged top view of the active region in part II of

[0024] A pair of gate wirings 106 adjacent in the front-rear direction (refer toFigure 1 ) are formed with a plurality of first conductive layers 20 at a predetermined interval in the left - right direction. The first conductive layer 20 is formed in a long - sized substantially rectangular parallelepiped shape extending in the front - rear direction, and is a semiconductor having a drift region of a first conductivity type (e.g., P - type).

[0025] In addition, on the left - right side surfaces of the first conductive layer 20, side gate layers 30 are formed such that their upper surfaces are inclined in the left - lower direction and the right - lower direction. The side gate layer 30 is, for example, polysilicon, and its volume resistivity is higher than that of a metal - containing material such as the gate wiring 106. A first insulating layer 34 is inserted between the first conductive layer 20 and the side gate layer 30. The first insulating layer 34 is formed of an insulator such as silicon dioxide.

[0026] On the upper surface of the side gate layer 30, a contact layer 32 formed in a columnar shape with a substantially trapezoidal cross - section is formed in the front - rear direction (refer to Figure 3 ). The front and rear ends of the contact layer 32 are joined to a pair of gate wirings 106. In addition, on the upper surface of the first conductive layer 20, a substantially rectangular parallelepiped - shaped contact layer 22 is formed in the front - rear direction. In addition, the front and rear ends of the contact layer 22 are separated from the gate wiring 106 by a predetermined distance.

[0027] In addition, at a substantially middle position between a pair of adjacent first conductive layers 20 in the left - right direction, a polysilicon layer 40 formed in a substantially rectangular parallelepiped shape is formed. The front and rear ends of the polysilicon layer 40 are separated from the gate wiring 106 by a predetermined distance. In addition, on the upper surface of the polysilicon layer 40, a substantially rectangular parallelepiped - shaped contact layer 42 is formed in the front - rear direction. These contact layers 22, 32, and 42 are formed of a metal - containing material.

[0028] Figure 3 is a schematic cross - sectional view of the main part of the semiconductor device 100. That is, Figure 3 is Figure 2 a cross - sectional view taken along line III - III in Figure 3 . In addition, in

[0029] As Figure 3 shown, the above - mentioned first conductive layer 20, side gate layer 30, and polysilicon layer 40 are formed on the upper surface of the second conductive layer 50. In addition, the above - mentioned first insulating layer 34 is inserted between the side gate layer 30 and the first conductive layer 20, and between the side gate layer 30 and the second conductive layer 50.

[0030] The second conductive layer 50 is a semiconductor having a drift region of a second conductivity type (e.g., N-type). The first conductive layer 20, the side gate layer 30, the polysilicon layer 40, and the contact layers 22, 32, 42 formed on their upper surfaces are embedded in the second insulating layer 60. The second insulating layer 60 is a layer formed of an insulator such as silicon dioxide, for example. As described above, the contact layer 32 is formed such that its cross-section is substantially trapezoidal. In particular, the lower surface of the contact layer 32 is inclined so as to face downward as it is farther away from the first conductive layer 20.

[0031] The upper surfaces of the contact layers 22, 32, 42 are exposed on the upper surface of the second insulating layer 60. Further, on the upper surface of the second insulating layer 60, a third insulating layer 62 of the same insulator is formed so as to cover the upper surface of the contact layer 32. And, the emitter electrode 110 is formed so as to cover the upper surfaces of the second insulating layer 60, the third insulating layer 62, and the contact layers 22, 42. Thereby, the contact layers 22, 42 are joined to the emitter electrode 110 and conduct with the emitter electrode 110.

[0032] The above-described contact layers 22, 32, 42 may be formed after the second insulating layer 60 is formed. That is, the semiconductor device 100 at the stage of forming the second insulating layer 60 is etched, and contact holes are formed in the portions where the contact layers 22, 32, 42 should be formed. At this time, these contact holes are formed so as to reach a predetermined depth from the upper surfaces of the first conductive layer 20, the side gate layer 30, and the polysilicon layer 40.

[0033] Then, the contact layers 22, 32, 42 can be formed by embedding the above-described metal-containing material in each contact hole. That is, the contact layers 22, 32, 42 are formed of a metal-containing material (e.g., the above-described aluminum, aluminum-aluminum alloy, etc.) having a volume resistivity lower than that of the side gate layer 30, and are in contact with and extend along the side gate layer 30. In other words, groove-shaped recesses (not labeled) are formed in the front-rear direction on the upper surfaces of the first conductive layer 20, the side gate layer 30, and the polysilicon layer 40, and the contact layers 22, 32, 42 are embedded in these recesses.

[0034] [Comparative Example]

[0035] Next, in order to clarify the effects of the first embodiment, a comparative example will be described.

[0036] Regarding the structure of the comparative example, although the illustration is omitted, in the comparative example, except that the contact layer 32 is not provided in the side gate layer 30, it is the same as the structure of the above-described first embodiment (refer to Figures 1 to 3 ).

[0037] The gate voltage applied to the gate pad 102 is also applied to the side gate layer 30 via the gate wirings 104 and 106. However, the volume resistivity of the material of the side gate layer 30 is higher than that of the metal-containing material, and the side gate layer 30 is formed in a long size in the front-rear direction. Therefore, the influence of the parasitic capacitance possessed by the side gate layer 30 and the like becomes large.

[0038] That is, in the side gate layer 30, the farther the position is from the gate wiring 106, the higher the resistance value observed from the gate wiring 106. Thus, according to the structure of the comparative example, problems such as a longer delay time in the propagation of the gate voltage and a longer delay time in the switching operation of the semiconductor device 100 occur.

[0039] [Effects of the Embodiment]

[0040] As described above, according to the above-described embodiment, the semiconductor device 100 includes: a side gate layer 30 that is connected to at least one end of the gate wiring 106, extends along the first insulating layer 34, and applies a voltage to the first conductive layer 20 via the first insulating layer 34; and a contact layer 32 that is formed of a metal-containing material having a lower volume resistivity than the side gate layer 30, is in contact with the side gate layer 30, and extends.

[0041] Thereby, the semiconductor device 100 can operate properly. That is, the resistance values of the respective parts from the gate wiring 106 to the contact layer 32 can be reduced via the contact layer 32. Therefore, the delay time in the switching operation of the semiconductor device 100 can be shortened.

[0042] In addition, a recess is formed in the side gate layer 30 along the extending direction thereof, and the contact layer 32 is more preferably embedded in the recess. Thereby, the contact area between the side gate layer 30 and the contact layer 32 can be enlarged, and the resistance values of the respective parts from the gate wiring 106 to the side gate layer 30 can be further reduced.

[0043] In addition, the gate wiring 106 is more preferably formed in at least a pair parallel to a predetermined direction (X-axis direction), and both ends of the contact layer 32 are respectively joined to the pair of gate wirings 106. Thereby, a voltage can be applied to both ends of the contact layer 32 from the pair of gate wirings 106. Therefore, the resistance values of the respective parts from the gate wiring 106 to the side gate layer 30 can be further reduced.

[0044] In addition, it is further preferable that the first conductive layer 20 is formed on the surface of the second conductive layer 50. The first conductive layer 20 has a drift region of a first conductivity type, and the second conductive layer 50 has a drift region of a second conductivity type. The first insulating layer 34 is formed over both the first conductive layer 20 and the second conductive layer 50, and the side gate layer 30 applies a voltage to both the first conductive layer 20 and the second conductive layer 50 via the first insulating layer 34. Thus, a voltage can be applied to both the first conductive layer 20 and the second conductive layer 50 from the gate wiring 106 via the contact layer 32.

[0045] [Modified Example]

[0046] The present invention is not limited to the above-described embodiments, and various modifications can be made. The above-described embodiments are illustrated for the purpose of easily understanding the present invention and are not limited to having all the structures described. In addition, other structures can be added to the structures of the above-described embodiments, or a part of the structures can be replaced with other structures. In addition, the control lines and information lines shown in the drawings are for illustrative purposes and are not limited to all the control lines and information lines required for production. In fact, it can be considered that almost all the structures are interconnected. Modifications to the above-described embodiments can be as follows.

[0047] (1) In the above-described embodiment, as the semiconductor device 100, an example in which an IGBT is applied is described. However, the present invention is not limited to an IGBT, and for example, it can also be other semiconductor devices such as a FET (Field-Effect Transistor) to which the side gate layer 30 can be applied.

[0048] (2) In the above-described embodiment, an example in which "P-type" is applied as the first conductivity type and "N-type" is applied as the second conductivity type is described, but conversely, "N-type" can be applied as the first conductivity type and "P-type" can be applied as the second conductivity type.

[0049] (3) In the above-described embodiment, the front and rear ends of the contact layer 32 are respectively joined to a pair of gate wirings 106. However, only one of the front and rear ends of the contact layer 32 can be joined to one of the gate wirings 106.

[0050] Description of Reference Numerals

[0051] 20 - First conductive layer, 30 - Side gate layer, 32 - Contact layer, 34 - First insulating layer, 50 - Second conductive layer, 100 - Semiconductor device, 106 - Gate wiring.

Claims

1. A semiconductor device, characterized in that, it comprises: a first conductive layer having a drift region; a first insulating layer in contact with the first conductive layer; gate wiring; a side gate layer formed in a long size, at least one end of which is connected to the gate wiring, extending along the first insulating layer, and applying a voltage to the first conductive layer via the first insulating layer; and a contact layer formed of a metal-containing material having a volume resistivity lower than that of the side gate layer, in contact with and extending along the side gate layer.

2. The semiconductor device according to claim 1, characterized in that, a recess is formed in the side gate layer along the extending direction thereof, and the contact layer is embedded in the recess.

3. The semiconductor device according to claim 2, characterized in that, at least a pair of the gate wirings are formed in parallel along a predetermined direction, and both ends of the contact layer are respectively joined to a pair of the gate wirings.

4. The semiconductor device according to claim 3, characterized in that, the first conductive layer is formed on the surface of a second conductive layer, the first conductive layer has a drift region of a first conductivity type, the second conductive layer has a drift region of a second conductivity type, the first insulating layer is formed over both the first conductive layer and the second conductive layer, and the side gate layer applies a voltage to both the first conductive layer and the second conductive layer via the first insulating layer.

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