Semiconductor packaging structure

Abstract

In some aspects, a package structure includes a substrate and a semiconductor device stacked over the substrate. The semiconductor devices are stacked in a first direction, and at least one of the semiconductor devices includes one or more pads on a side surface of the at least one of the semiconductor devices.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. Background Art

[0002] Semiconductor packaging refers to the process of encapsulating and protecting semiconductor dies or chips after they are fabricated on a semiconductor wafer. This packaging provides a means of connecting the die or chip to the device (such as a computer, smartphone, or countless other electronic accessories) that it will power. The choice of packaging technology is based on several factors, including the intended application, power consumption, heat generation, and desired footprint. As technology continues to advance, there is a need for smaller, more efficient, and more functional packaging solutions. Summary of the Invention

[0003] In one aspect, a package structure includes a substrate and semiconductor devices stacked on the substrate. The semiconductor devices are stacked along a first direction. At least one of the semiconductor devices includes one or more pads located on a side surface of at least one of the semiconductor devices.

[0004] Certain embodiments may include one or more of the following features.

[0005] In some embodiments, the semiconductor devices are aligned along one side of the semiconductor devices.

[0006] In some embodiments, at least one of the semiconductor devices includes a side surface parallel to the first direction, and one or more pads of at least one of the semiconductor devices are disposed on the side surface.

[0007] In some embodiments, at least one of the semiconductor devices includes a side surface having an acute angle with the first direction, and one or more pads of at least one of the semiconductor devices are disposed on the side surface.

[0008] In some embodiments, at least one of the semiconductor devices includes a side surface having an acute angle with the first direction, and one or more pads of at least one of the semiconductor devices are disposed in a recessed structure at the side surface.

[0009] In some embodiments, the substrate includes one or more pads, and the package structure further includes bonding wires coupling the pads of the semiconductor devices to the pads of the substrate. In such embodiments, the package structure further includes one or more contact structures on the substrate, wherein the one or more contact structures are coupled to adjacent semiconductor dies.

[0010] In some embodiments, the encapsulation structure further includes a coupling structure parallel to the first direction, and the coupling structure is configured to couple the semiconductor device and the substrate. In such an embodiment, the coupling structure includes a contact structure that couples a pad of the semiconductor device and a pad of the substrate.

[0011] In some embodiments, at least one of the semiconductor devices includes one or more sealing structures. In such an embodiment, at least one of the semiconductor devices further includes one or more wires that pass through the one or more sealing structures and are isolated from the one or more sealing structures. The one or more wires are coupled to one or more pads of at least one of the semiconductor devices.

[0012] In another aspect, the coupling structure includes a first contact structure on a first side surface of the coupling structure and a second contact structure on a second side surface of the coupling structure, where the second side surface is perpendicular to the first side surface.

[0013] Certain embodiments may include one or more of the following features.

[0014] In some embodiments, the first contact structure is coupled to the semiconductor device, and the second contact structure is coupled to the substrate.

[0015] In some embodiments, the coupling structure includes a circuit layer that couples the first contact structure and the second contact structure.

[0016] In another aspect, a method for manufacturing an encapsulation structure includes: forming a coupling structure on a substrate, where the coupling structure is perpendicular to and coupled to the substrate, the coupling structure includes a first contact structure on a first side surface of the coupling structure and a second contact structure on a second side surface of the coupling structure, and the second side surface is perpendicular to the first side surface; stacking a semiconductor device on top of the substrate; and bonding the coupling structure to the semiconductor device.

[0017] Certain embodiments may include one or more of the following features.

[0018] In some embodiments, the method further includes forming one or more pads on a side surface of at least one of the semiconductor devices.

[0019] In some embodiments, forming one or more pads on a side surface of at least one semiconductor device in a semiconductor device includes: forming a semiconductor layer, where the semiconductor layer includes one or more sealing structures; forming one or more wires and one or more pads in the semiconductor layer, where the one or more wires are routed through the one or more sealing structures and isolated from the one or more sealing structures, and the one or more wires are coupled to the one or more pads; and removing a portion of the semiconductor layer to expose the one or more pads.

[0020] In some embodiments, forming one or more pads on a side surface of at least one semiconductor device in a semiconductor device includes: forming one or more wires at a surface of a first semiconductor layer, where the one or more wires are routed through one or more sealing structures in the first semiconductor layer and isolated from the one or more sealing structures; forming a second semiconductor layer over the surface of the first semiconductor layer to form a stacked layer; forming one or more pads in the stacked layer, where the one or more wires are coupled to the one or more pads; and removing a portion of the stacked layer to expose the one or more pads.

[0021] In some embodiments, a substrate includes one or more pads. Forming a coupling structure on the substrate includes bonding one or more second contact structures in the second contact structure of the coupling structure to the one or more pads of the substrate. Bonding the coupling structure to a semiconductor device includes bonding one or more first contact structures in the first contact structure of the coupling structure to one or more pads of at least one semiconductor device in the semiconductor device.

[0022] Details of one or more embodiments of the subject matter of the present disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of an example package structure according to some embodiments of the present disclosure is shown.

[0024] Figure 2 A schematic diagram of an example semiconductor die according to some embodiments of the present disclosure is shown.

[0025] Figure 3 A schematic diagram of an example package structure according to some embodiments of the present disclosure is shown.

[0026] Figure 4 A schematic diagram of an example package structure according to some embodiments of the present disclosure is shown.

[0027] Figure 5 A schematic diagram of an example semiconductor die according to some embodiments of the present disclosure is shown.

[0028] Figure 6 A schematic diagram of an example semiconductor die in accordance with some embodiments of the present disclosure is shown.

[0029] Figure 7 An example process for fabricating a semiconductor die in accordance with some embodiments of the present disclosure is shown.

[0030] Figure 8 Another example process for fabricating a semiconductor die in accordance with some embodiments of the present disclosure is shown.

[0031] Figure 9 An example process for fabricating a packaging structure in accordance with some embodiments of the present disclosure is shown.

[0032] Figure 10 Another example process for fabricating a packaging structure in accordance with some embodiments of the present disclosure is shown.

[0033] Figure 11 A schematic diagram of an example coupling structure in accordance with some embodiments of the present disclosure is shown.

[0034] Figure 12 A flowchart of an example process for fabricating a packaging structure in accordance with some embodiments of the present disclosure is shown.

[0035] Like reference numerals and names in the various figures represent like elements. DETAILED DESCRIPTION

[0036] Encapsulating semiconductor chips or dies is a critical step in the semiconductor manufacturing process. The primary purpose of encapsulation is to protect the delicate semiconductor chips or dies and provide a means for connecting them to external devices or systems. In some cases, semiconductor chips or dies are stacked to achieve improved performance, reduced power consumption, and potentially reduced cost. Example methods of stacking semiconductor chips or dies can include wire bonding, through-silicon vias (TSVs), flip-chip stacking, package-on-package (PoP), stacked wafer stacking, etc. The choice of stacking method can depend on various factors, including the intended application, cost, thermal conditions, and performance requirements.

[0037] Figure 1FIG. 0 shows a schematic diagram of an exemplary package structure 100 in accordance with some embodiments of the present disclosure. As shown, the package structure 100 includes a plurality of semiconductor devices 102 stacked on a substrate 104. Note that, for illustrative purposes only, the package structure 100 is shown as including four semiconductor devices 102. In some examples, the package structure 100 may have any suitable number of semiconductor devices 102, such as 5, 10, or 100, based on factors including technological constraints, thermal conditions, signal integrity and interference, physical size and application, cost and yield, reliability issues, etc.

[0038] In some embodiments, the semiconductor device 102 includes a semiconductor die. In some embodiments, the semiconductor device 102 includes a semiconductor chip.

[0039] In some examples, the semiconductor device 102 may include a semiconductor material, such as silicon, germanium (Ge), gallium arsenide (GaAs), silicon germanium (SiGe), gallium nitride (GaN), or silicon carbide (SiC).

[0040] In some embodiments, the size and shape of the semiconductor device 102 vary based on its function, the complexity of the integrated circuit, and the manufacturing technology used. In some examples, the width of the semiconductor device 102 may be several centimeters. In some examples, the semiconductor device 102 may be several millimeters from one side to the other. In some examples, the semiconductor device 102 may be rectangular or square in shape. In some examples, the semiconductor device 102 may have an irregular shape to fit a particular package or device. In some examples, the semiconductor device 102 may have rounded corners.

[0041] In some embodiments, the semiconductor device 102 includes an integrated circuit. In some examples, the integrated circuit of the semiconductor device 102 may include one or more of the following: digital circuits, analog circuits, mixed-signal circuits, power management circuits, application-specific circuits, communication interfaces, microcontrollers, microprocessors, or input / output (I / O) modules, etc. In some examples, the semiconductor device 102 may include a non-volatile storage device (e.g., NAND memory) or a volatile storage device (e.g., dynamic random access memory (DRAM)).

[0042] In some embodiments, the semiconductor device 102 includes one or more pads 106. In the example shown, each semiconductor device 102 includes two pads 106. Note that, for illustrative purposes only, each semiconductor device 102 is shown as including two pads 106. In some examples, the semiconductor device 102 may include any suitable number of pads 106, such as 1, 3, or 5.

[0043] In some embodiments, the pad 106 is configured to provide electrical connections between semiconductor devices 102. In some embodiments, the pad 106 is configured to provide electrical connections from the semiconductor device 102 to other components of the package structure 100 or to external devices or systems. In some embodiments, the pad 106 includes a conductive layer to facilitate soldering and improve connection reliability. In some examples, the pad 106 may include a metal layer, such as a copper layer. In some examples, the pad 106 may include a metal layer coated with a thin solder layer such as gold to prevent oxidation and improve solderability.

[0044] In some embodiments, the size and shape of the pad 106 vary based on its intended application, design rules, and manufacturing process. In some examples, the pad 106 may be square or rectangular in shape. In some examples, the pad 106 may have a special or customized shape to accommodate thermal or electrical requirements. In some examples, the size and shape of the pad 106 may be configured to match the solder balls or bumps bonded to the pad 106.

[0045] In some embodiments, the substrate 104 is configured to provide mechanical support and electrical functionality for device structures (e.g., semiconductor devices 102) built thereon. In some examples, the substrate 104 may act as an intermediary to provide electrical interconnection between the semiconductor device 102 and the external environment (e.g., a circuit board). In some examples, the substrate 104 may include multiple layers of conductive traces to convey signals to and from the semiconductor device 102 to facilitate connection to the outside world through pins, solder balls, or pads. In some examples, the substrate 104 may include a ceramic or organic material, such as FR-4 (glass-reinforced epoxy laminate), and the choice of material for the substrate 104 may depend on various factors, including thermal performance, electrical performance, and cost considerations.

[0046] In the example shown, the substrate 104 includes two pads 110. In some embodiments, the pads 110 are similar to the pads 106. Therefore, some descriptions of the pads 110 are omitted here for the sake of brevity.

[0047] In some embodiments, the semiconductor device 102 and the substrate 104 are interconnected using wire bonding (e.g., ball bonding or wedge bonding). In an example ball bonding process, a solder ball may first be created at the end of a wire by melting the end of the wire using an electric flame, and then the solder ball is pressed onto a bonding pad on the semiconductor die to form a bond. In an example wedge bonding process, a wedge tool may be used to directly bond the wire to the bonding pad.

[0048] In the example shown, a semiconductor device and a substrate 104 are interconnected using ball bonding. In the example shown, bonding wires 112 are coupled to pads 106 and 110 using contact structures 108 and 111 (e.g., solder balls or bumps). As shown, contact structure 108 is coupled to pad 106, and contact structure 111 is coupled to pad 110.

[0049] In some embodiments, bonding wires 112 serve as a connection mechanism between semiconductor device 102 and substrate 104. In some examples, bonding wires 112 can establish the necessary electrical connections between semiconductor device 102 and substrate 104. Bonding wires 112 can provide a power connection and enable signal transmission between semiconductor device 102 and substrate 104, such as data, clock, and control signals.

[0050] In some examples, bonding wires 112 can include a conductive material, such as gold, aluminum, copper, or silver. In some examples, contact structure 108 can be a solder ball or bump. In some examples, contact structure 108 or 111 can include a solder material, such as a lead-tin (Pb-Sn) alloy or a tin-silver-copper (Sn-Ag-Cu). In some examples, contact structure 108 or 111 can include a eutectic or near-eutectic composition to ensure a distinct melting point and improved performance.

[0051] Package structure 100 also includes contact structure 116 to bond substrate 104 to an adjacent semiconductor device 102. In the example shown, contact structure 116 is used to couple an adjacent semiconductor device 102 to substrate 104 using flip-chip bonding. In some embodiments, contact structure 116 is similar to contact structures 108 and 111. Thus, some descriptions of contact structure 116 are omitted here for brevity.

[0052] Package structure 100 also includes contact structure 118 attached to the bottom side of substrate 104. In some embodiments, contact structure 118 is configured to enable connection from package structure 100 to an external component or system (e.g., a printed circuit board (PCB)). In some embodiments, contact structure 118 is similar to contact structures 108 and 111. Thus, some descriptions of contact structure 118 are omitted here for brevity.

[0053] In some embodiments, semiconductor devices 102 are aligned along one side of semiconductor device 102. In the example shown, semiconductor devices 102 are aligned along the side of semiconductor device 102 on which pads 106 are located, and the side on which pads 106 are located has a surface parallel to the stacking direction (e.g., the z-axis). In some embodiments, the side of semiconductor device 102 on which pads 106 are located can have various configurations, which will be referred to below with reference to Figures 2-6The configuration will be discussed in more detail. By aligning semiconductor devices on one side and bonding the semiconductor devices on the aligned side, the stacking area of the semiconductor devices can be reduced, thereby increasing the stacking density and improving performance.

[0054] Figure 2 A schematic diagram of an exemplary semiconductor device 200 in accordance with some embodiments of the present disclosure is shown. In some embodiments, the semiconductor device 200 is an example of one or more of the semiconductor devices 102 in Figure 1 In some embodiments, the semiconductor device 200 is similar to the semiconductor device 102. Therefore, for the sake of brevity, some descriptions of the semiconductor device 200 are omitted herein.

[0055] As shown, the semiconductor device 200 includes sealing structures 202a and 202b. Note that for illustrative purposes only, the semiconductor device 200 is shown as including two sealing structures. In some examples, the semiconductor device 200 may have any suitable number of sealing structures, such as 1, 3, or 4.

[0056] In some embodiments, the sealing structures 202a and 202b are configured to provide a boundary between the active devices of the semiconductor device 200 and the edge of the device 200, acting as a moisture barrier, an electrical shield, and a stress relief structure. In some examples, the sealing structures 202a and 22b may be configured to protect sensitive internal components (e.g., circuits) from potential contaminants or particles during die manufacturing, and act as a barrier against impurities that may be inadvertently introduced during the wafer dicing process. In some examples, the sealing structures 202a and 202b may be configured to provide a stable mechanical structure that can absorb some stress and strain during packaging, thereby reducing the chance of internal cracking or damage of the device 200. In some examples, the sealing structures 202a and 202b may be configured to provide electrical isolation, thereby ensuring that potential crosstalk or interference between the internal and external components of the device 200 is minimized. In some examples, the sealing structures 202a and 202b may be configured to help control or prevent the propagation of unintended leakage current around the perimeter of the device 200. In some examples, the sealing structures 202a and 202b may be configured to be used as a well-defined area for testing purposes.

[0057] In some embodiments, the sealing structures 202a and 202b include one or more of the following materials: polysilicon, silicon nitride (Si 3 N 4 )), silicon oxynitride (SiON), silicon dioxide (SiO 2) metals, low-k dielectrics, etc. In some examples, the composition and layering of the materials in the sealing structures 202a and 202b can depend on the specific die manufacturing technology, application requirements, and potential challenges (such as moisture, contaminants, or electrical interference) that the device 200 may encounter in its intended environment.

[0058] In some embodiments, the sealing structures 202a and 202b extend vertically into the semiconductor device 200, for example, along the z-axis. In some examples, the vertical depth of the sealing structures 202a and 202b can range from a few micrometers to dozens of micrometers, depending on the technology node (e.g., 5nm, 10nm, or 28nm), the intended application of the die, and the specific requirements of the die design.

[0059] The semiconductor device 200 also includes wires 204a and 204b. In some embodiments, the wires 204a and 204b are configured such that they are routed through the sealing structures 202a and 202b, but they are isolated from the sealing structures 202a and 202b. In the illustrated example, the wires 204a and 204b are configured to have a zigzag route through the sealing structures 202a and 202b. In some examples, the wires 204a and 204b can have any suitable route configuration through the sealing structures 202a and 202b. In some examples, the wires 204a and 204b can include a conductive material, such as gold, aluminum, copper, or silver, depending on the application and the desired properties.

[0060] In the illustrated example, one end of each of the wires 204a and 204b is coupled to pads 206a and 206b, respectively. As shown, the pads 206a and 206b are located on the side surface 201 of the semiconductor device 200 that is parallel to the z-axis. In some embodiments, the pads 206a and 206b are similar to the pads 106. Therefore, for the sake of brevity, some descriptions of the pads 206a and 206b are omitted here. In the illustrated example, the pads 206a and 206b have a rectangular structure. In some examples, the pads 206a and 206b can have any suitable type of structure, such as square, oval, trapezoidal, or rhomboidal.

[0061] In the illustrated example, the other end of each of the wires 204a and 204b is coupled to contact structures 208a and 208b. In some embodiments, the contact structures 208a and 208b are configured to provide connections to the internal components or circuits (not shown) of the semiconductor device 200. In some examples, the contact structures 208a and 208b can include a conductive material, such as aluminum, copper, or tungsten.

[0062] Figure 3FIG. 0 shows a schematic diagram of an exemplary package structure 300 in accordance with some embodiments of the present disclosure. As shown, the package structure 300 includes a plurality of semiconductor devices 302 stacked on a substrate 304. In some embodiments, some elements of the package structure 300 are similar or analogous to some elements of the package 100. For example, the semiconductor devices 302 are analogous to the semiconductor devices 102, and the substrate 304 is analogous to the substrate 104. Thus, for the sake of brevity, some descriptions of these similar or analogous elements are omitted herein.

[0063] In the illustrated example, the package structure 300 includes a coupling structure 315. In some embodiments, the coupling structure 315 is configured to horizontally interconnect the semiconductor devices 302 and the substrate 304, thereby allowing for a high-density, high-performance multi-die configuration. In some embodiments, the coupling structure 315 serves as an intermediate layer providing electrical wiring between the semiconductor devices 302 and the substrate 304, thereby allowing for more complex and denser connections between the semiconductor devices 302 and the substrate 304. In some examples, the coupling structure 315 is an interposer.

[0064] In the illustrated example, the coupling structure 315 includes a contact structure 308 coupled to the pads 306 of the semiconductor devices 302. In some embodiments, the coupling structure 315 further includes an internal circuit layer 312 configured to interconnect the contact structures 308. In the illustrated example, the internal circuit layer 312 includes wires interconnecting the contact structures 308. In some examples, the wires may include one or more conductive materials such as gold, aluminum, copper, or silver.

[0065] In some examples, the coupling structure 315 may include a material such as single-crystalline silicon, silicon-on-insulator (SOI), or compound semiconductor. In some examples, the contact structure 308 may include a solder material such as a lead-tin (Pb-Sn) alloy or a tin-silver-copper (Sn-Ag-Cu) alloy. In some examples, the contact structure 308 may include a eutectic or near-eutectic composition to ensure a distinct melting point and improved performance. In an exemplary process of bonding the coupling structure 315 to the semiconductor devices 302 and the substrate 304, the contact structure 308 may be melted and bonded to the corresponding pads 306.

[0066] In some embodiments, the contact structures 316 and 318 are similar to the contact structures 116 and 118. Thus, for the sake of brevity, some descriptions of the contact structures 316 and 318 are omitted herein.

[0067] Note that in Figure 3In the example shown, the semiconductor device 302 is aligned on the side surface where the pad 306 is located. The coupling structure 315 is parallel to the stacking direction (e.g., the z-direction) and is used to interconnect the pads 306, thus bonding the semiconductor devices 302. By aligning the semiconductor devices 302 on one side and using the coupling structure 315 to bond the semiconductor devices 302 on the aligned side, the stacking area of the semiconductor devices 302 can be reduced, thereby increasing the stacking density and improving the performance.

[0068] Figure 4 FIG. 4 shows a schematic diagram of an example package structure 400 according to some embodiments of the present disclosure. In some embodiments, some elements of the package structure 400 are similar or analogous to some elements of the package 100. For example, the semiconductor device 402 is similar to the semiconductor device 102, and the substrate 404 is similar to the substrate 104. Therefore, for the sake of brevity, some descriptions of these similar or analogous elements are omitted here.

[0069] In some embodiments, the semiconductor devices 402 are aligned along one side of the semiconductor device 402. In the example shown, the semiconductor devices 402 are aligned along the side where the pads 406 of the semiconductor device 402 are located. Each semiconductor device 402 includes an inclined side surface on the aligned side, and the inclined side surface has an acute angle θ with respect to the stacking direction (e.g., the z-axis), for example, 0 < θ < 90°. The pads 406 are located on the inclined side surface. In some examples, the inclined side surfaces of the semiconductor devices 402 may have varying acute angles.

[0070] By aligning the semiconductor devices 402 on one side and bonding them on the aligned side, the stacking area of the semiconductor devices 402 can be reduced, thereby increasing the stacking density and improving the performance.

[0071] Figure 5 FIG. 5 shows a schematic diagram of an example semiconductor device 500 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 500 is Figure 4 an example of one or more of the semiconductor devices 402 in Figure 5 In some embodiments, Figure 2 some elements of

[0072] In some embodiments, the sealing structures 502a and 502b are configured to provide a boundary between the active devices of the semiconductor device 500 and the edge of the device 500, serving as a moisture barrier, an electrical shield, and a stress relief structure.

[0073] In some embodiments, the wires 504a and 504b are configured such that they are routed through the sealing structures 502a and 502b, but they are isolated from the sealing structures 502a and 502b. In the example shown, the wires 504a and 504b are configured to have a zigzag route through the sealing structures 502a and 502b. In some examples, the wires 504a and 504b may have any suitable route configuration through the sealing structures 502a and 502b.

[0074] In the example shown, one end of each of the wires 504a and 504b is coupled to the pads 506a and 506b, respectively. The other ends of the wires 504a and 504b are coupled to the contact structures 508a and 508b. As shown, the pads 506a and 506b are located on the inclined side surface 501 of the semiconductor device 500, and the inclined side surface 501 has an acute angle with respect to the z-axis.

[0075] Figure 6 A schematic diagram showing an example semiconductor device 600 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 600 is Figure 4 an example of one or more of the semiconductor devices 402 in Figure 6 Some of the elements in Figure 2 are similar or analogous to some of the elements in

[0076] In some embodiments, the sealing structures 602a and 602b are configured to provide a boundary between the active devices of the semiconductor device 600 and the edge of the device 600, serving as a moisture barrier, an electrical shield, and a stress relief structure.

[0077] In some embodiments, wires 604a and 604b are configured such that they are routed through the sealing structures 602a and 602b, but they are isolated from the sealing structures 602a and 602b. In the illustrated example, wires 604a and 604b are configured to have a Z-shaped route through the sealing structures 602a and 602b. In some examples, wires 604a and 604b may have any suitable route configuration through the sealing structures 602a and 602b.

[0078] In the illustrated example, one end of each of wires 604a and 604b is coupled to pads 606a and 606b, respectively. The other ends of wires 604a and 604b are coupled to contact structures 608a and 608b. As shown, semiconductor device 600 includes an inclined side surface 610, and recessed structures 603a and 603b are located at the inclined side surface 601. Pads 606a and 606b are disposed in recessed structures 603a and 603b, respectively. In the illustrated example, pads 606a and 606b have a polyhedral structure having two triangular side surfaces. In some examples, pads 606a and 606b may have any suitable size and shape to fit the recessed structures 603a and 603b.

[0079] Figure 7 An example process for manufacturing a semiconductor device in accordance with some embodiments of the present disclosure is shown. In some examples, the processes described herein may be used to manufacture any suitable semiconductor device, such as semiconductor devices 102, 200, 302, 402, 500, or 600. As shown, the example process begins with providing a semiconductor layer 700. In some examples, one or more processes such as wafer preparation, oxidation, lithography, etching, doping, chemical vapor deposition (CVD), metallization, planarization, layering, dicing, packaging, etc. may be used to manufacture the semiconductor layer 700.

[0080] In some embodiments, semiconductor layer 700 includes functional circuits. In some examples, semiconductor layer 700 may be manufactured by depositing multiple layers of various materials and etching them into a semiconductor wafer in a complex pattern defined by a chip design. After the wafer manufacturing process is completed, the wafer including the individual circuits is diced and cut into individual pieces, each of which is a die. Each die includes a fully functional electronic circuit, which may be a microprocessor, a memory, a sensor, or any other suitable type of integrated circuit. In some embodiments, each die is encapsulated in a protective package to provide physical support, protection from environmental factors, and connection to external devices or systems (e.g., via pins or solder balls).

[0081] In the example shown, the semiconductor layer 700 includes sealing structures 704a and 704b. In some embodiments, the sealing structures 704a and 704b are fabricated by masking a surface (e.g., surface 702 of the semiconductor layer 700) and etching unprotected regions on the masked surface. For example, to define the shape and location of the sealing structures 704a and 704b, a layer of photoresist material is deposited on the surface 702 of the semiconductor layer 700. The semiconductor layer 700 is then exposed to ultraviolet (UV) light through a mask that blocks light in the shape of a desired pattern (including the sealing structures 704a and 704b). The exposed regions can undergo a chemical change that allows them to be etched away, leaving the desired pattern. In some examples, wet or dry etching techniques can be used to etch away the unprotected regions (those not covered by the photoresist material) to further define the sealing structures 704a and 704b.

[0082] In some embodiments, some space is left at the surface 702 to allow wires (e.g., wires 708a and 708b) to be routed through the sealing structures 704a and 704b. In some embodiments, an example process for fabricating the wires 708a and 708b includes dielectric deposition, trench patterning, etching, barrier layer deposition, metal deposition, chemical mechanical planarization (CMP), etc. For example, a dielectric layer can be deposited on the surface 702 of the semiconductor layer 700. The dielectric layer can electrically isolate the wires from other components and from each other. The dielectric layer can include silicon dioxide (SiO 2 ) or a low-k dielectric, which reduces capacitive crosstalk between adjacent metal lines. A pattern of trenches (which will accommodate the horizontal wires) defined on the dielectric layer can then be formed using photolithography. In some examples, a layer of photoresist material can be applied on the dielectric layer, exposed through a mask with a desired pattern, and developed to leave a patterned protective layer. Plasma (dry) etching can be used to etch away the unprotected regions of the dielectric, creating the trenches. In some examples, a thin barrier layer is deposited before depositing the metal for the wires. This can prevent the metal from diffusing into the dielectric. The barrier layer can include materials such as titanium, titanium nitride, tantalum, or tantalum nitride. The wires 708a and 708b can be formed by depositing a metal material (e.g., copper) into the trenches using an electroplating process. After the metal deposition, CMP can be used to polish away the excess metal and dielectric, leaving only a flat surface with metal in the trenches.

[0083] In some embodiments, the wires 708a and 708b and the pads 706a and 706b are fabricated simultaneously or within the same time period and using a similar manufacturing process. Thus, for the sake of brevity, the manufacturing process for the pads 706a and 706b is omitted here.

[0084] After forming conductive lines 708a and 708b and pads 706a and 706b, a portion of the semiconductor layer 700 is removed to expose pads 706a and 706b.

[0085] Figure 8 Another example process for fabricating a semiconductor device in accordance with some embodiments of the present disclosure is shown. In some examples, the processes described herein can be used to fabricate any suitable semiconductor device, such as semiconductor devices 102, 200, 302, 402, 500, or 600. The example process can begin with forming conductive lines 808a and 808b on a surface 802 of a first semiconductor layer 800. In the example shown, conductive lines 808a and 808b are configured to route through encapsulation structures 804a and 804b, but are isolated from encapsulation structures 804a and 804b.

[0086] In some embodiments, example processes for fabricating conductive lines 808a and 808b include dielectric deposition, trench patterning, etching, barrier layer deposition, metal deposition, chemical mechanical planarization (CMP), etc. For example, a dielectric layer can be deposited on the surface 802 of the first semiconductor layer 800. The dielectric layer can electrically isolate the conductive lines from other components and from each other. The dielectric layer can include silicon dioxide (SiO 2 ) or a low-k dielectric, which reduces capacitive crosstalk between adjacent metal lines. Then, lithography can be used to form a pattern of trenches (which will accommodate the conductive lines) defined on the dielectric layer. In some examples, a layer of photoresist material can be applied on the dielectric layer, exposed through a mask having a desired pattern, and developed to leave a patterned protective layer. Plasma (dry) etching can be used to etch away the unprotected regions of the dielectric, thereby creating trenches. In some examples, a thin barrier layer is deposited before depositing the metal for the conductive lines. This can prevent metal diffusion into the dielectric. The barrier layer can include materials such as titanium, titanium nitride, tantalum, or tantalum nitride. Conductive lines 808a and 808b can be formed by depositing a metal material (e.g., copper) into the trenches using an electroplating process. After metal deposition, CMP can be used to polish away excess metal and dielectric, leaving only a flat surface with metal in the trenches.

[0087] After forming conductive lines 808a and 808b on the surface 802, a second semiconductor layer 809 is deposited on the surface 802 of the first semiconductor layer 800 to form a stacked semiconductor layer 810. In some embodiments, the second semiconductor layer 809 and the first semiconductor layer 800 comprise the same material.

[0088] Then, pads 812a and 812b are formed in the stacked semiconductor layer 810. In some embodiments, pads 812a and 812b can be formed by using a similar process to that for forming pads 706a and 706b. Thus, for the sake of brevity, the manufacturing process of pads 812a and 812b is omitted herein. In some embodiments, for example Figure 8 In the example shown, after depositing the second semiconductor layer 809 on the first semiconductor layer 800, wires 808a and 808b are hidden (“invisible”) in the stacked layer 810. As shown, one end of each of wires 808a and 808b is coupled to contact structures 806a and 806b respectively. The other ends of wires 808a and 808b are coupled to pads 812a and 812b respectively.

[0089] In some embodiments, pads 812a and 812b are formed near the edge of the stacked layer 810. Then, a portion of the stacked layer 810 near the edge is removed to expose pads 812a and 812b.

[0090] Figure 9 An example process for manufacturing a packaged structure according to some embodiments of the present disclosure is shown. In some examples, the processes described herein can be used to manufacture any suitable packaged structure, such as packaged structure 100 or 400.

[0091] The process can begin with providing a substrate 902 that includes pads 904. Then, semiconductor devices 906 are stacked on top of the substrate 902. Each semiconductor device 906 includes two pads 908. The first semiconductor device 906 (or the bottom semiconductor device 906 adjacent to the substrate 902) can be attached to the substrate 902 using a die attach material, which can be an adhesive, an epoxy, or solder. Then, the second semiconductor device 906 can be aligned and attached to the first semiconductor device 906. This process can be repeated until all semiconductor devices 906 are attached. Then, pads 904 on one semiconductor device 906 can be bonded to pads 904 on an adjacent semiconductor device 906 using wires 912 (e.g., copper wires or gold wires).

[0092] In some examples, for example Figure 9 In the example shown, a ball bonding process can be used to bond pads 904 using leads 912. In an example ball bonding process, a solder ball can be generated at the end of wire 912 (e.g., by melting the end of wire 912 using an electro - flame), and then the solder ball is pressed onto pad 904 to form a bond.

[0093] In some examples, a wedge bonding process can be used to bond pads 904 using leads 912. In an example wedge bonding process, wire 912 is directly coupled to pad 904 using a wedge tool.

[0094] In some embodiments, the process of bonding the pad 904 of the substrate 902 to the pad 908 of an adjacent semiconductor device 906 is similar to the process of bonding the pads 904 of two adjacent semiconductor devices 906. Therefore, for the sake of brevity, the process of bonding the pad 904 to the pad 908 is omitted here.

[0095] Figure 10 Another example process of manufacturing a packaged structure according to some embodiments of the present disclosure is shown. In some examples, the processes described herein can be used to manufacture any suitable packaged structure, such as the packaged structure 300.

[0096] The process can begin by bonding the coupling structure 1004 to the substrate 1002. In the example shown, the coupling structure 1004 includes a contact structure 1006. In some examples, the contact structure 1006 can be a solder ball or a solder bump. In some embodiments, one or more contact structures 1006 of the coupling structure 1004 are coupled to one or more pads (not shown) of the substrate 1002. In the example shown, the contact structures 1006 are arranged in two columns. In some examples, the contact structures 1006 can be arranged in any suitable number of columns or any suitable arrangement. In some embodiments, the coupling structure 1004 includes an internal circuit layer. In the example shown, the internal circuit layer includes wires 1008 that interconnect the contact structures 1006, such as gold wires or copper wires.

[0097] After bonding the coupling structure 1004 to the substrate 1002, the semiconductor devices 1010 are stacked on top of the substrate 1002. In Figure 10 this, each semiconductor device 1010 includes two pads 1012. In some examples, each semiconductor device 1010 can have any suitable number of pads 1012.

[0098] The first semiconductor device 1010 (or the bottom semiconductor device 1010 adjacent to the substrate 1002) is attached to the substrate 1002 using a die attach material, which can be an adhesive, an epoxy resin, or solder. Then, the second semiconductor device 1010 can be aligned and attached to the first semiconductor device 1010. This process can be repeated until all the semiconductor devices 1010 are attached.

[0099] The coupling structure 1004 can be used to bond the pads 1012 of one semiconductor device 1010 to the pads 1012 of an adjacent semiconductor device 1010. In the example shown, the contact structure 1006 of the coupling structure 1004 is aligned with and contacts the corresponding pads 1012 of the semiconductor device 1010. In some examples, when the contact structure 1006 is a solder ball or a solder bump, the solder ball or solder bump can be melted to bond to the corresponding pad 1012.

[0100] Figure 11 A schematic diagram of an example coupling structure 1100 in accordance with some embodiments of the present disclosure is shown. In some embodiments, the coupling structure 1100 is an example of one or more of the coupling structures 315 and 1004. In some examples, the coupling structure 1100 can include materials such as single-crystalline silicon, silicon-on-insulator (SOI), or compound semiconductors.

[0101] In the example shown, the coupling structure 1100 includes a contact structure 1102. In some examples, the contact structure 1102 can be a solder ball or a solder bump. In some examples, the contact structure 1102 can include a solder material, such as a lead-tin (Pb-Sn) alloy or a tin-silver-copper (Sn-Ag-Cu) alloy. In some examples, the contact structure 1102 can include eutectic or near-eutectic components to ensure a distinct melting point and improved performance.

[0102] The coupling structure 1100 further includes an internal circuit layer 1104. In some examples, the internal circuit layer 1104 can include wires that interconnect the contact structures 1102, and the wires can include one or more conductive materials such as gold, aluminum, copper, or silver.

[0103] In the example shown, the coupling structure 1100 includes a surface 1106 and a surface 1108. One or more contact structures 1102 are disposed on the surface 1106, and one or more contact structures 1102 are disposed on the surface 1108. In some examples, the surface 1106 and the surface 1108 are perpendicular to each other. In some examples, one or more contact structures 1102 on the surface 1106 can be bonded to the pads of one or more semiconductor devices (e.g., semiconductor devices 102, 200, 302, 1010). One or more contact structures 1102 on the surface 1108 can be bonded to the pads of a substrate (e.g., substrate 104, 304, 1002).

[0104] Figure 12 A flowchart of an example process 1200 for manufacturing a packaged structure in accordance with some embodiments of the present disclosure is shown. In some implementations, based on the combination Figures 1-11The described techniques are used to implement some or all of the operations in process 1200. The operations shown in process 1200 may not be exhaustive, and other operations may be performed before, after, or between any of the shown operations. Additionally, some operations may be performed simultaneously or in a different order than Figure 12 shown.

[0105] Process 1200 begins with forming a coupling structure (1202) over a substrate. In some embodiments, the coupling structure (e.g., coupling structure 1004) is perpendicular to the substrate (e.g., substrate 1002).

[0106] In some embodiments, the coupling structure includes a first contact structure (e.g., contact structure 1102) on a first side surface (e.g., surface 1106) of the coupling structure and a second contact structure on a second side surface (e.g., surface 1108) of the coupling structure. In some examples, the first side surface of the coupling structure is perpendicular to the second side surface of the coupling structure. In some examples, the second side surface of the coupling structure may be parallel to the substrate, and one or more contact structures on the second side surface may be bonded to one or more pads of the substrate.

[0107] A semiconductor device stack is formed over the substrate (1204). In some embodiments, one or more pads (e.g., pad 1012) are formed on side surfaces of one or more of the semiconductor devices (e.g., device 1010).

[0108] In some examples, forming one or more pads on side surfaces of one or more semiconductor devices includes forming a semiconductor layer (e.g., semiconductor layer 700), forming one or more wires (e.g., wires 708a and 708b) and one or more pads (e.g., pads 706a and 706b) on the semiconductor layer, and removing a portion of the semiconductor layer to expose the one or more pads. In some examples, the wires and pads may be fabricated simultaneously or within the same time period.

[0109] In some examples, forming one or more pads on side surfaces of one or more semiconductor devices includes forming one or more wires (e.g., wires 808a and 808b) at a surface of a first semiconductor structure (e.g., semiconductor layer 800). The one or more wires may be routed through one or more encapsulation structures (e.g., encapsulation structures 804a and 804b) of the first semiconductor layer, but the wires are isolated from the encapsulation structures. A second semiconductor layer (e.g., semiconductor layer 809) may be deposited on the surface of the first semiconductor layer to form a stacked layer (e.g., semiconductor layer 810). In some examples, the first semiconductor layer and the second semiconductor layer may include the same semiconductor material. Then, a portion of the stacked layer may be removed to expose the one or more pads.

[0110] Process 1200 also includes bonding a coupling structure to a semiconductor device (1206). In some embodiments, bonding the coupling structure to the semiconductor device includes bonding one or more of the first contact structures of the coupling structure to one or more pads of the semiconductor device.

[0111] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those of ordinary skill in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those of ordinary skill in the relevant art that the present disclosure can also be used in a variety of other applications.

[0112] References in this disclosure to "one embodiment", "an embodiment", "example embodiment", "some embodiments", etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but other embodiments may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, implementation of such feature, structure, or characteristic in connection with other embodiments is within the knowledge of those of ordinary skill in the relevant art, whether or not explicitly described.

[0113] Generally, the meaning of terms can be understood, at least in part, from their usage in context. For example, as used herein, the term "one or more" depends, at least in part, on context and can be used to describe any feature, structure, or characteristic in a singular sense or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a", "an", or "the" can also be understood to convey a singular usage or a plural usage, at least in part, depending on context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors and can allow for the existence of other factors that may not be explicitly described, which also depends, at least in part, on context.

[0114] It should be readily understood that the meanings of "on", "above", and "over" in this disclosure should be construed in the broadest possible manner such that "on" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above something" or "over something", but can also include the meaning of "above something" or "over something" with no intermediate features or layers therebetween (i.e., directly on something).

[0115] In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to another (or some) element or feature. In addition to the orientation shown in the drawings, the spatial relative terms are intended to also cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted accordingly.

[0116] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0117] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. In addition, the layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein interconnect lines and / or vertical interconnect vias (through-holes) contacts are formed) and one or more dielectric layers.

[0118] As used herein, the term "about" means a given value that may vary based on the particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may mean a given value that varies within that value.

[0119] It should be noted that although process steps, method steps, algorithms, etc. may be described in sequence above, such processes, methods, and algorithms can generally be configured to work in an alternating order, unless there is a specific contrary indication.

[0120] Although many details may be described herein, these details should not be construed as limiting the scope of the claimed invention or what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Moreover, although features may have been described above as acting in certain combinations and even initially claimed as such, in some cases one or more features from a claimed combination may be deleted from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination. Similarly, although operations are shown in the drawings in a particular order, this should not be understood as requiring that the operations be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed, to achieve a desired result.

[0121] Only a few examples and embodiments are disclosed. Variations, modifications, and enhancements may be made to the described examples and embodiments as well as other embodiments based on the disclosed content.

Claims

1. An encapsulation structure includes a substrate and semiconductor devices stacked on the substrate, wherein, the semiconductor devices are stacked in a first direction, and at least one of the semiconductor devices includes one or more pads located on a side surface of the at least one semiconductor device among the semiconductor devices.

2. The encapsulation structure according to claim 1, wherein, the semiconductor devices are aligned along one side of the semiconductor devices.

3. The encapsulation structure according to any one of claims 1-2, wherein, at least one of the semiconductor devices includes a side surface parallel to the first direction, and one or more pads of the at least one semiconductor device among the semiconductor devices are disposed on the side surface.

4. The encapsulation structure according to any one of claims 1-3, wherein, at least one of the semiconductor devices includes a side surface having an acute angle with the first direction, and one or more pads of the at least one semiconductor device among the semiconductor devices are disposed on the side surface.

5. The encapsulation structure according to any one of claims 1-4, wherein, at least one of the semiconductor devices includes a side surface having an acute angle with the first direction, and one or more pads of the at least one semiconductor device among the semiconductor devices are disposed in a recessed structure at the side surface.

6. The encapsulation structure according to any one of claims 1-5, wherein, the substrate includes one or more pads, and the encapsulation structure further includes bonding wires coupling the pads of the semiconductor devices to the pads of the substrate.

7. The encapsulation structure according to any one of claims 1-6, wherein, the encapsulation structure further includes one or more contact structures on the substrate, wherein the one or more contact structures are coupled to adjacent semiconductor devices.

8. The encapsulation structure according to any one of claims 1-7, wherein, the encapsulation structure further includes a coupling structure parallel to the first direction, and the coupling structure is configured to couple the semiconductor devices and the substrate.

9. The encapsulation structure according to claim 8, wherein, the coupling structure includes a contact structure coupled to the pads of the semiconductor devices and the pads of the substrate.

10. The encapsulation structure according to any one of claims 1-9, wherein, at least one of the semiconductor devices includes one or more sealing structures.

11. The encapsulation structure according to claim 10, wherein, the at least one semiconductor device among the semiconductor devices further includes one or more wires passing through the one or more sealing structures and isolated from the one or more sealing structures.

12. The encapsulation structure according to claim 11, wherein, the one or more wires are coupled to one or more pads of the at least one semiconductor device among the semiconductor devices.

13. A coupling structure, comprising: a first contact structure on a first side surface of the coupling structure; and A second contact structure on a second side surface of the coupling structure, wherein the second side surface is perpendicular to the first side surface.

14. The coupling structure according to claim 13, wherein, the first contact structure is coupled to a semiconductor device, and the second contact structure is coupled to a substrate.

15. The coupling structure according to any one of claims 13-14, wherein, the coupling structure includes a circuit layer coupled to the first contact structure and the second contact structure.

16. A method for manufacturing a packaging structure, the method comprises: forming a coupling structure on a substrate, wherein the coupling structure is perpendicular to and coupled to the substrate, the coupling structure includes a first contact structure on a first side surface of the coupling structure and a second contact structure on a second side surface of the coupling structure, and the second side surface is perpendicular to the first side surface; stacking a semiconductor device on top of the substrate; and bonding the coupling structure to the semiconductor device.

17. The method according to claim 16, further comprises: forming one or more pads on a side surface of at least one of the semiconductor devices.

18. The method according to claim 17, wherein, forming the one or more pads on the side surface of the at least one of the semiconductor devices comprises: forming a semiconductor layer, wherein the semiconductor layer includes one or more sealing structures; forming one or more wires and one or more pads in the semiconductor layer, wherein the one or more wires are routed through the one or more sealing structures and isolated from the one or more sealing structures, and the one or more wires are coupled to the one or more pads; and removing a portion of the semiconductor layer to expose the one or more pads.

19. The method according to claim 17, wherein, forming the one or more pads on the side surface of the at least one of the semiconductor devices comprises: forming one or more wires at a surface of a first semiconductor layer, wherein the one or more wires are routed through one or more sealing structures in the first semiconductor layer and isolated from the one or more sealing structures; forming a second semiconductor layer on the surface of the first semiconductor layer to form a stacked layer; forming the one or more pads in the stacked layer, wherein the one or more wires are coupled to the one or more pads; and removing a portion of the stacked layer to expose the one or more pads.

20. The method according to any one of claims 17-19, wherein: the substrate includes one or more pads; forming the coupling structure on the substrate includes bonding one or more of the second contact structures of the coupling structure to the one or more pads of the substrate; and Bonding the coupling structure to the semiconductor device includes bonding one or more of the first contact structures in the coupling structure to one or more pads of the at least one semiconductor device in the semiconductor device.

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