Mask splicing for extreme ultraviolet lithography

Abstract

The invention relates to mask stitching for extreme ultraviolet lithography. A first position within a mask pattern of a semiconductor circuit layout is determined based on a feature of the mask pattern within a threshold distance of a boundary in the mask pattern. The mask pattern is based on a first mask exposure and a second mask exposure that intersect at the boundary. The first position defines a position where a first auxiliary feature is to be placed that reduces a sensitivity of the feature of the mask pattern to lithographic process variations. A second position of the mask pattern is also determined. The second position defines a position where a second auxiliary feature is to be placed that reduces stray light at the boundary during the first mask exposure and the second mask exposure. The mask pattern is then modified to place the first auxiliary feature in the first position and the second auxiliary feature in the second position.

Description

Technical Field

[0001] The present disclosure relates generally to the fabrication of semiconductor devices, and more particularly, to methods for stitching masks to minimize irregularities in boundary areas between masks. Background Art

[0002] Extreme ultraviolet (EUV) lithography is an optical lithography technique used to fabricate semiconductor devices based on semiconductor circuit layouts. EUV lithography uses EUV wavelengths (e.g., close to 13.5 nanometers (nm)) and laser pulses to create a desired pattern by exposing a substrate covered by photoresist using a reflective photomask.

[0003] High numerical aperture (high NA) EUV lithography is a specific type of EUV lithography in which the numerical aperture of the EUV system (which may be 0.33 for some EUV systems) is increased to 0.55. The higher numerical aperture allows for the projection of smaller spot sizes and smaller pitches (e.g., up to sixty percent smaller than can be achieved using a system with an aperture of 0.33), making high NA EUV lithography ideal for lower process technology nodes (e.g., the 2nm node and below). Summary of the invention

[0004] A non-transitory computer-readable medium includes stored instructions that, when executed by a processor, cause the processor to determine a first position within a mask pattern of a semiconductor circuit layout based on features within a threshold distance of a boundary in the mask pattern. The mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary. The first position is where a first assist feature will be placed, the first assist feature reducing the sensitivity of the feature of the mask pattern to lithography process variations. A second position of the mask pattern is also determined. The second position is where a second assist feature will be placed, the second assist feature reducing stray light at the boundary during the first mask exposure and the second mask exposure. The mask pattern is then modified to place the first assist feature in the first position and the second assist feature in the second position.

[0005] A method includes determining a location of a mask pattern of a semiconductor circuit layout where an assist feature is to be placed based on a feature of the mask pattern within a threshold distance of a boundary in the mask pattern. The mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary. The assist feature reduces the sensitivity of the feature of the mask pattern to lithography process variations. The mask pattern is then modified to place the assist feature in the location.

[0006] A system includes: a memory storing instructions; and a processor coupled to the memory and executing the instructions, the instructions, when executed, causing the processor to reposition a feature within a threshold distance of a boundary in a mask pattern of a semiconductor circuit layout. The mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary. The feature defines the location of an electrical interconnect or transistor. The instructions, when executed, further cause the processor to determine a location of the mask pattern where an assist feature is to be placed. The assist feature reduces stray light at the boundary during the first mask exposure and the second mask exposure. The instructions, when executed, further cause the processor to modify the mask pattern to place the assist feature in the location. The instructions, when executed, further cause the processor to perform mechanical reinforcement on the assist feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood based on the detailed description given below and the accompanying drawings of the embodiments of the present disclosure. The drawings are used to provide knowledge and understanding of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0008] Figure 1 illustrates an exemplary method for performing mask stitching for use in extreme ultraviolet lithography according to examples of the present disclosure;

[0009] Figure 2 illustrates an example of a feature of a mask pattern that has been partially repositioned due to the feature crossing a boundary between a first portion of the substrate to be exposed during a first mask exposure and a second portion of the substrate to be exposed during a second mask exposure;

[0010] Figure 3 illustrates some exemplary assist features that may be added to a mask pattern that requires multiple mask exposures to print on a substrate;

[0011] Figure 4 The diagram may be deployed to form a bond Figure 2 Described and Figure 3 Several examples of mechanically enhanced patterns of second assist features illustrated in ;

[0012] Figure 5 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure; and

[0013] Figure 6 A diagram depicting an exemplary computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure relate to mask stitching for extreme ultraviolet lithography. As discussed above, high NA EUV lithography is a specific type of EUV lithography in which the numerical aperture of the EUV system (which may be 0.33 for some EUV systems) is increased to 0.55. The higher numerical aperture allows for the projection of smaller spot sizes and smaller pitches (e.g., up to sixty percent smaller than can be achieved using a system with an aperture of 0.33), making high NA EUV lithography ideal for lower process technology nodes (e.g., the 2nm node and below).

[0015] A high NA EUV scanner can image the pattern on the photomask onto the substrate with a 4X reduction in one orientation and an 8X reduction in the other orientation. This asymmetric reduction forces such high NA EUV scanners to have a maximum exposure field size of 26 mm×16.5 mm. This is half the exposure field size of a non-high NA lithography scanner, which has a maximum exposure field size of 26 mm×33 mm. This also means that in order to pattern the layers of a semiconductor chip design larger than 26 mm×16.5 mm using high NA EUV lithography, the patterning process will need to be performed in two separate mask exposures, which are then stitched or joined together. Therefore, the boundary area where the two exposure fields that are stitched together meet (which may extend across the entire semiconductor chip) may be exposed twice during the lithography process. This double exposure can lead to process variations and defects in the boundary area, especially when the boundary area contains relatively small or dense features.

[0016] Examples of the present disclosure minimize process variations and defects in a substrate where two or more mask exposures are required to transfer a complete mask pattern to the substrate during a lithography process. In some examples, process variations and defects are minimized by placing auxiliary features in a mask pattern that has already been defined. The auxiliary features may include several features that, when exposed on the substrate, will reduce the sensitivity of features of the mask pattern patterned on the substrate in the boundary region to process variations and will reduce stray light. In other examples, the original features of the mask pattern may be repositioned and / or resized in the boundary region to minimize undesired patterning issues in the pattern, and the original features may define areas where interconnects or transistors are to be made on the substrate. Therefore, in short, examples of the present disclosure provide various modifications to mask patterns that need to be printed in multiple mask exposures, wherein the modifications allow mask pattern features to be better printed on the substrate.

[0017] Technical advantages of the present disclosure include the ability to perform high precision lithography processes (e.g., high NA EUV lithography processes) that require multiple mask exposures to pattern a single substrate without sacrificing accuracy in boundary regions where the multiple mask exposures meet or overlap. Thus, the advantages of high NA EUV can be realized by fewer process variations and defects caused by multiple mask exposures. Other technical advantages of the present disclosure improve the functionality of a computer system for designing mask patterns for semiconductor circuit layouts by improving the accuracy with which a processor of the computing system places features of the mask pattern for lower process technology nodes.

[0018] Figure 1 An exemplary method 100 for performing mask stitching for use in extreme ultraviolet lithography according to an example of the present disclosure is illustrated. In one example, all or some steps of method 100 may be performed by components of an EUV system (e.g., a high NA EUV system). In other examples, all or some steps of method 100 may be performed by a computer system (e.g., a Figure 6 For example, the steps of method 100 are described below as being performed by a processing system, which may be part of an EUV system, part of a computer system, or part of another device.

[0019] At 102, a processing system acquires a mask pattern for a semiconductor circuit layout, wherein the mask pattern is based on a first mask exposure and a second mask exposure that meet at a boundary of the mask pattern. For example, where a high NA EUV lithography process is used to perform lithography of a layer of a semiconductor circuit, at least two mask exposures (i.e., at least a first mask exposure and a second mask exposure) may be required to pattern the entire substrate (e.g., silicon wafer) surface on which the mask pattern is to be printed. For example, if the entire exposed substrate surface is approximately 26 mm×33 mm, then at least two mask exposures will need to be performed, each mask exposure exposing an area of ​​approximately 26 mm×16.5 mm of the substrate (this is because high NA EUV cannot pattern an area larger than 26 mm×16.5 mm in a single mask exposure). As discussed above, this may result in some portions of the substrate surface being exposed more than once.

[0020] At 104, the processing system repositions a first feature of the mask pattern that is within a threshold distance of a boundary (where the boundary is between a first portion of the substrate to be exposed during a first mask exposure and a second portion of the substrate to be exposed during a second mask exposure). In one example, the feature of the mask pattern may correspond to a portion of a substrate surface to be etched or removed during photolithography of a layer. For example, the portion of the substrate surface may be etched or removed to form a space for fabricating an interconnect or transistor on the layer.

[0021] In one example, the boundary includes a region of the substrate where the result of the first mask exposure and the result of the second mask exposure are stitched together (i.e., aligned to form a single continuous pattern on the substrate). In another example, the boundary can extend beyond the region where the result of the first mask exposure and the result of the second mask exposure are stitched together (e.g., to either side of a line where the result of the first mask exposure and the result of the second mask exposure meet). In one example, during acquisition of the mask pattern at 102, the location of the boundary can be explicitly acquired.

[0022] In one example, a threshold distance from the boundary is defined prior to execution of method 100. The value of the threshold distance may be configured by a user, such as a designer of the semiconductor circuit or an operator of a lithography system used to perform lithography of the layer. For example, a wider or narrower distance between the boundary of the mask pattern and the feature may be tolerated depending on the type or use case of the semiconductor circuit or the capabilities of the lithography system used to perform lithography of the layer.

[0023] In some cases, the actual distance from the first feature to the border may be zero. For example, the first feature may reside partially in the first portion of the substrate and partially in the second portion of the substrate. In other words, the first feature may intersect or cross the border. In one example, any feature that crosses the border will be at least partially repositioned. Repositioning may involve not only moving a portion of the first feature, but also resizing and / or changing the shape of a portion of the first feature to improve printability in the border region.

[0024] Figure 2 An example of a feature 200 of a mask pattern that has been partially repositioned due to the feature 200 crossing a boundary between a first portion of the substrate to be exposed during a first mask exposure and a second portion of the substrate to be exposed during a second mask exposure is illustrated. In one example, a stitching zone 204 is defined between the first mask exposure (e.g., Figure 2 The portion of the splicing zone 204 that resides above the splicing zone 204) and the second mask exposure (eg, Figure 22. The buffer zone 206 may be defined around an area where the stitching zone 204 and the portion of the substrate that resides below the stitching zone 204 meet. The stitching zone 204 may represent a portion of the substrate that will be exposed twice during photolithography (e.g., once during a first mask exposure and once during a second mask exposure). Additionally, a buffer zone 206 may be defined above and below the stitching zone 204. The buffer zone 206 represents an area of ​​the substrate that is unlikely to be exposed more than once during photolithography; however, the buffer zone 206 may help define an area in which feature continuity may be maintained, as described in further detail below.

[0025] like Figure 2 , feature 200 (which in this example represents a substrate region where a plurality of interconnects are to be formed) traverses stitching zone 204. Thus, portions of feature 200 that reside within stitching zone 204 may be exposed during both the first mask exposure and the second mask exposure. However, feature 200 may be at least partially repositioned (as shown by modified feature 202) in order to accommodate potential patterning issues in feature 200 due to double exposure. More specifically, portions 208, 210, and 212 of feature 200 that reside within stitching zone 204 may be repositioned to be further spaced apart, as shown by modified feature 202. The wider widths of portions 208, 210, and 212 reflect the fact that these portions 208, 210, and 212 are exposed twice during both the first mask exposure and the second mask exposure. Thus, spacing portions 208, 210, and 212 further apart allows these wider widths to be accommodated. The amount by which the widths of the portions 208, 210, and 212 are widened and the degree of spacing therebetween may depend, at least in part, on the density of other features that are part of the mask pattern. Portions 214, 216, 218, 220, 222, and 224 of the feature 200 that do not reside within the stitching zone 204 may be retained as originally defined. Auxiliary portions 226, 228, 230, and 232 may be added to the modified feature 202 in the buffer zone 206 to join the repositioned portions 208, 210, and 212 to the portions 214, 216, 218, 220, 222, and 224 that were not repositioned.

[0026] By further spacing the repositioned portions 208, 210, and 212 of feature 200 apart in modified feature 202, the risk of repositioned portions 208, 210, and 212 bleeding into each other when patterning defects occur due to double exposure can be minimized. This helps ensure robust electrical performance of interconnects that will ultimately be fabricated in the space defined by modified feature 202. In one example, the placement and routing rules can limit the number of adjacent parallel lines that can be repositioned in the illustrated manner. In another example, the placement and routing rules can also limit the number of adjacent parallel lines in the splicing zone 204 that are oriented opposite to the parallel lines (e.g., perpendicular to the splicing zone 204). Figure 2 Definition of via and routing metal of feature 200) illustrated in FIG.

[0027] In one example, if there are no features in the mask pattern that are close enough to the boundary (eg, within a threshold distance from the boundary) to risk being exposed more than once, 104 may be skipped. In this case, method 100 may proceed directly from 102 to 106.

[0028] Return to reference Figure 1 At 106, the processing system determines a first location of the mask pattern where a first assist feature is to be placed, wherein the first assist feature reduces sensitivity of features of the mask pattern to lithography process variations (e.g., process variations of the first mask exposure and the second mask exposure). In one example, the first assist feature is a feature that is not part of the mask pattern acquired at 102 and will not be resolved or printed on the substrate during lithography. The first assist feature is designed to provide a good process window for lithography of the substrate by reducing sensitivity of features of the mask pattern to lithography process variations.

[0029] In one example, the first location is a location near a feature of the mask pattern (e.g., within a threshold length of the feature). In one example, the first location can be identified using a lithography simulation of the mask pattern that predicts the effects of lithography process variations on the features of the mask pattern.

[0030] Figure 3 The diagram illustrates some exemplary assist features that can be added to a mask pattern that requires multiple mask exposures to print on a substrate. More specifically, Figure 3 A stitching line 300 is shown where a first mask exposure region of a mask pattern (e.g., represented by the region above stitching line 300) meets a second mask exposure region of the mask pattern (e.g., represented by the region below stitching line 300). As illustrated, one or both of the first mask exposure region and the second mask exposure region may include features 302 to be patterned on the substrate, such as interconnects or transistors. Figure 3 In the example illustrated in , the illustrated feature 302 does not cross the stitching line 300 ; however, the feature 302 may be positioned close enough to the stitching line 300 that portions of the feature 302 are exposed more than once during photolithography.

[0031] In order to reduce the sensitivity of the feature 302 to the lithography process variations caused by single exposure or multiple exposures, a first auxiliary feature can be added to the mask pattern. In one example, the first auxiliary feature includes one or more rectangular areas 304 added to the mask pattern near the stitching line 300. These rectangular areas 304 can be oriented in a direction parallel to the stitching line 300. In one example, the first position of at least one of the rectangular areas is adjacent to one of the features 302 but spaced apart therefrom. That is, there may be no other features (e.g., original or added auxiliary features) between the rectangular area 304 and at least one feature 302. Although Figure 3 The exemplary first assist feature illustrated in is rectangular in shape, but it will be appreciated that assist features such as the first assist feature may have any shape, including square and curvilinear shapes.

[0032] Return to reference Figure 1 At 108, the processing system determines a second location of the mask pattern where a second assist feature is to be placed, wherein the second assist feature reduces stray light at the boundary during lithography (e.g., during the first mask exposure and the second mask exposure). In one example, the second assist feature is a feature that is not part of the mask pattern acquired at 102 and will not be resolved or printed on the substrate during lithography. The second assist feature is designed to reduce stray light that occurs due to at least two mask exposures at the boundary.

[0033] In one example, the second assist feature is placed in a location adjacent to the first location, wherein the first location is positioned between the second location and a feature of the mask pattern. In one example, the second location can be identified using a flare simulation or a mask pattern density calculation (e.g., locally or remotely). The flare simulation can jointly optimize the placement of the second assist feature and the placement of the black border edge of the mask pattern (wherein the black border edge can be full angle or curved to reduce stress on the mask).

[0034] Reference again Figure 3 , the second auxiliary feature may include a diffraction grating pattern 306. Figure 3, the diffraction grating pattern 306 can be oriented in a direction substantially parallel to the stitching line 300. However, the diffraction grating pattern 306 can be positioned so that the diffraction grating pattern 306 is separated from the feature 302 (and from the stitching line 300) by the rectangular area 304 of the first assist feature. In another example, the diffraction grating pattern 306 can be oriented in a direction perpendicular to the 8X reduction direction in the EUV scanner.

[0035] It should be noted that although Figure 3 The second assist features are illustrated as diffraction gratings comprising multiple stripes, but the second assist features may have full angles or curved shapes to reduce flare or maintain a more constant flare across the wafer. Electromagnetic field effect sensing (M3D) mask simulation tools may be used to calculate the effects of different shapes and / or positions of the second assist features on flare.

[0036] The second assist features may be sized, shaped, and positioned in a manner that ensures reliable printing of the second assist features and reduction of stray light without negatively impacting sensitivity of the mask pattern features to lithographic process variations.

[0037] At 110, the processing system modifies the mask pattern to place a second assist feature in a second location.

[0038] At 112 , the processing system modifies the mask pattern to place the first assist feature in the first location (eg, after the second assist feature has been placed at 110 ).

[0039] In one example, placing a first assist feature after placing a second assist feature can allow the first assist feature to blend into the second assist feature. For example, placing the second assist feature can utilize the spacing of the first assist feature but further reduce the spacing away from the first assist feature. In other words, if the second assist feature includes Figure 3 , then the portion of the diffraction grating located closer to the first assist feature may share the same spacing with the first assist feature, and the spacing may gradually decrease for the portion of the diffraction grating located further away from the first assist feature. This mixture of the first assist feature and the second assist feature may reduce the negative diffraction effects in the region where the first assist feature transitions into the second assist feature.

[0040] In one example, the first assist feature may be placed in the first position from within a first software control script. The second assist feature may be placed in the second position from within the same first software control script or from within a second control script. However, placing both the first assist feature and the second assist feature from within the same software control script allows the first assist feature and the second assist feature to potentially be placed simultaneously. Thus, in some examples, 112 may be performed before 110, or 110 and 112 may be performed in parallel.

[0041] At 114, the processing system performs mechanical strengthening on the second assist feature. Due to its small size, the second assist feature may be mechanically fragile, especially if Figure 3 , where the segments of the diffraction grating pattern 306 are elongated. Mechanical stress effects in the substrate may cause patterning failure (e.g., collapse or peeling) of the second assist feature. In some examples, the second assist feature may be mechanically reinforced or altered to improve stability.

[0042] Figure 4 The diagram may be deployed to form a bond Figure 2 Described and Figure 3 Several examples of mechanically enhanced patterns 400, 402, 404, and 406 of second assist features are illustrated in FIG. Figure 4 , each mechanically reinforced pattern 400, 402, 404, and 406 may include at least a first plurality of parallel strips 408 oriented parallel to each other. The first plurality of parallel strips 408 may be further oriented parallel to a boundary or stitching line of the mask pattern. The first plurality of parallel strips 408 may be reinforced in any one or more of a number of ways.

[0043] For example, the mechanically reinforced pattern 400 illustrates an example in which each of the first plurality of parallel strips 408 is broken down into a plurality of shorter strips that are co-linearly spaced along the length of each strip. In other words, each of the first plurality of parallel strips 408 may include a plurality of gaps 410 along its length (for ease of illustration, the gaps are not shown in FIG. 4 ). Figure 4 A single gap 410 is marked in FIG.

[0044] In the mechanically reinforced pattern 400, the gaps 410 are positioned in the same position along each of the first plurality of parallel strips 408. That is, each gap 410 is linearly aligned with gaps 410 in all other strips in the first plurality of parallel strips 408. Alternatively, the plurality of gaps 410 may be positioned in a staggered manner, as shown in the exemplary mechanically reinforced pattern 404. In the example of the mechanically reinforced pattern 404, each gap 410 may be linearly aligned with a gap in another strip of the first plurality of parallel strips 408; the gaps 410 in the remaining strips of the first plurality of parallel strips 408 may be aligned in different manners.

[0045] By printing each of the first plurality of parallel strips 408 as a row of shorter strips, the effects of mechanical stress on the second assist features (which have been shown to affect longer, thinner, straight features more than shorter features or features containing turns or jogs) may be reduced.

[0046] The mechanically reinforced pattern 402 illustrates an example in which the second plurality of parallel strips are positioned in a substantially perpendicular orientation relative to the first plurality of parallel strips 408 (for ease of illustration, the second plurality of parallel strips 408 are positioned in a substantially perpendicular orientation). Figure 4 408). In this case, the bars 412 in the second plurality of parallel bars are spaced apart from each other along the length of the first plurality of parallel bars 408. In addition, each bar 412 in the second plurality of parallel bars can intersect each bar in the first plurality of parallel bars 408. The bars 412 in the second plurality of parallel bars act as mechanical stabilizers for the first plurality of parallel bars 408.

[0047] In another example, the bars 412 in the second plurality of parallel bars can be shortened so that each bar 412 in the second plurality of parallel bars intersects exactly one bar in the first plurality of parallel bars 408, rather than intersecting every bar in the first plurality of parallel bars 408. Using shorter bars 412 will allow the spacing between bars 412 in the second plurality of parallel bars to be staggered.

[0048] Mechanically enhanced pattern 406 illustrates an example where the plurality of parallel bars 414 are not in the form of straight lines (as in mechanically enhanced patterns 400, 402, and 404), but rather in a partially angled or curved form. This partially angled or curved shape exhibits improved mechanical stability relative to a diffraction grating pattern where the bars are all in the form of straight lines. Furthermore, the partially angled or curved shape is also superior in reducing stray light relative to a diffraction grating pattern where the shorter bars are all positioned in a parallel and uniform orientation.

[0049] In other examples, the mechanically enhanced pattern of the diffraction grating may simply include patterning the diffraction grating with fewer bars (e.g., fewer than four bars in the first plurality of parallel bars 408), but making each of the bars wider. Furthermore, the mechanically enhanced pattern may employ bar segments with bends or angles rather than straight bars or bar segments.

[0050] After 114, additional processing may be performed on the mask pattern according to optical proximity correction (OPC) and / or inverse photolithography (ILT) techniques to optimize the repositioned and assist features of the mask pattern. In one example, OPC and / or ILT may include modifying at least one of the following: the shape, size, or position of the assist features placed at 110 or 112. This additional processing may be performed in an iterative manner until a goal or result (e.g., a desired shape, size, or position of the assist features) is achieved.

[0051] Figure 5The diagram illustrates a set of exemplary processes 500 used during the design, verification and fabrication of a manufactured article (e.g., an integrated circuit) to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term 'EDA' denotes the term 'electronic design automation'. These processes begin with the formation of a product concept 510 using information provided by a designer, which is transformed to form a manufactured article using a set of EDA processes 512. When the design is finally completed, the design is taped out 534, at which time the artwork (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to produce a mask set, which is then used to fabricate the integrated circuit. After tape-out, semiconductor die are fabricated 536 and packaging and assembly processes 538 are performed to produce a finished integrated circuit 540.

[0052] The specification for a circuit or electronic structure can range from low-level transistor material layout to a high-level description language. The high-level representation can be used to design circuits and systems using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level ('RTL') description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation as a more detailed description adds more useful details to the design description, for example, more details for the modules that contain the description. The lower level of representation as a more detailed description can be computer-generated, derived from a design library, or formed by another design automation process. An example of a specification language for specifying a more detailed description of a lower-level representation language is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each representation level is enabled for use by the corresponding system of that layer (e.g., a formal verification system). The design process can use Figure 5 The process is described as being enabled by an EDA product (or EDA system).

[0053] During system design 514, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or code line), and reduced cost. The design can be partitioned into different types of modules or components at this stage.

[0054] During logic design and functional verification 516, modules or components in a circuit are specified in one or more description languages ​​and the functional accuracy of the specifications is checked. For example, the components of the circuit can be checked to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal checkers. In some embodiments, special component systems called 'emulators' or 'prototyping systems' are used to accelerate functional verification.

[0055] During synthesis and test design 518, the HDL code is transformed into a netlist. In some embodiments, the netlist may be a graph structure where the edges of the graph structure represent components of the circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical manufacturing objects that can be used by EDA products to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0056] During netlist verification 520, the netlist may be checked for compliance of timing constraints and correspondence of the HDL code.During design planning 522, the overall floor plan of the integrated circuit may be constructed and analyzed for timing and top-level routing.

[0057] During layout or physical implementation 524, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components through multiple conductors) occur, and selection of cells from a library may be performed to enable specific logic functions. As used herein, the term 'cell' may specify a group of transistors, other components, and interconnects that provide a Boolean logic function (e.g., "and", "or", "not", "exclusive or") or a storage function (e.g., a flip-flop or latch). As used herein, a circuit 'block' may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components and are enabled both as physical structures and in simulation. Parameters (e.g., size) are specified for selected cells (based on 'standard cells') and may be accessed in a database for use by an EDA product.

[0058] During analysis and extraction 526, circuit functionality is verified at the layout level, which permits improvements to the layout design. During physical verification 528, the layout design is checked to ensure that manufacturing constraints (e.g., DRC constraints, electrical constraints, lithography constraints) are correct and that the circuit system functionality matches the HDL design specifications. During resolution enhancement 530, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0059] During tape-out, data is formed for use in producing lithographic masks (after applying lithographic enhancements where appropriate).During mask data preparation 532, the 'tape-out' data is used to produce lithographic masks, which are used to produce finished integrated circuits.

[0060] Computer systems (e.g. Figure 6 The storage subsystem of the computer system 600) may be used to store programs and data structures used by some or all of the EDA products described herein and products for development of cells of the library and for physical and logical design using the library.

[0061] Figure 6 An exemplary machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0062] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0063] The exemplary computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM)), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 618, which communicate with each other via a bus 630.

[0064] Processing device 602 represents one or more processors (e.g., microprocessors, central processing units, etc.). More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices (e.g., application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc.). Processing device 602 may be configured to execute instructions 626 for performing the operations and steps described herein.

[0065] The computer system 600 may further include a network interface device 608 to communicate via a network 620. The computer system 600 may also include a video display unit 610 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse), a graphics processing unit 622, a signal generating device 616 (e.g., a speaker), a video processing unit 628, and an audio processing unit 632.

[0066] The data storage device 618 may include a machine-readable storage medium 624 (also referred to as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside completely or at least partially within the main memory 604 and / or the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media.

[0067] In some embodiments, the instructions 626 include instructions to implement functionality corresponding to the present disclosure. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated cache memory and server) storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine and processing device 602 to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0068] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to those skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0069] It should be remembered, however, that all of these terms and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated as apparent from the present disclosure, it should be understood that throughout this description, specific terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0070] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may include a computer that is selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as but not limited to any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0071] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0072] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0073] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the figures and similar elements are marked with similar numbers. Therefore, the present disclosure and the drawings should be considered in an illustrative sense rather than a restrictive sense.

Claims

1. A non-transitory computer-readable medium comprising stored instructions which, when executed by a processor, cause the processor to: determining a first location within a mask pattern of a semiconductor circuit layout at which a first assist feature is to be placed based on a feature of the mask pattern within a threshold distance of a boundary in the mask pattern, wherein the mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary, and wherein the first auxiliary feature reduces the sensitivity of the feature of the mask pattern to variations in the lithography process; determining a second position of the mask pattern where a second assist feature is to be placed, wherein the second assist feature reduces stray light at the boundary during the first mask exposure and the second mask exposure; modifying the mask pattern to place the second assist feature in the second location; and After modifying the mask pattern to place the second assist feature, modifying the mask pattern to place the first assist feature in the first location. 2 . The non-transitory computer readable medium of claim 1 , wherein both the first assist features and the second assist features comprise features that are not resolved during the first mask exposure and the second mask exposure. 3 . The non-transitory computer readable medium of claim 1 , wherein the features of the mask pattern define locations of interconnects or transistors. 4 . The non-transitory computer-readable medium of claim 3 , wherein the first assist feature comprises a region oriented in a direction substantially parallel to the boundary. 5 . The non-transitory computer readable medium of claim 1 , wherein the second position is located such that the first assist feature is located between the boundary and the second assist feature.

6. The non-transitory computer readable medium of claim 5, wherein the second assist features comprise a diffraction grating pattern oriented in a direction substantially parallel to the boundary. The non-transitory computer readable medium of claim 6 , wherein the processor performs mechanical strengthening on the second assist feature.

8. The non-transitory computer readable medium of claim 7, wherein the diffraction grating pattern comprises a first plurality of substantially parallel strips.

9. The non-transitory computer-readable medium of claim 8, wherein each of the plurality of substantially parallel strips comprises a plurality of shorter strips oriented in a co-linear manner, and wherein the mechanical strengthening performed by the processor comprises defining a gap between each pair of the plurality of shorter strips.

10. The non-transitory computer readable medium of claim 8, wherein the mechanical strengthening performed by the processor comprises positioning a second plurality of substantially parallel strips in a perpendicular orientation relative to the first plurality of substantially parallel strips.

11. The non-transitory computer readable medium of claim 10, wherein each of the second plurality of substantially parallel strips intersects one or more of the first plurality of substantially parallel strips.

12. The non-transitory computer-readable medium of claim 1, wherein the stored instructions further cause the processor to: The features of the mask pattern that are within the threshold distance of the boundary are repositioned.

13. The non-transitory computer-readable medium of claim 12, wherein repositioning the feature comprises modifying at least one of: a position, a size, or a shape of a portion of the feature.

14. The non-transitory computer-readable medium of claim 13, wherein the feature comprises a plurality of lines defining locations where a plurality of electrical interconnects are to be made, and the repositioning comprises adjusting spacing between portions of the plurality of lines that cross zones defined within the threshold distance on either side of the boundary.

15. The non-transitory computer readable medium of claim 1, wherein the processor executes a single control script to control placement of the first assist feature and the second assist feature.

16. The non-transitory computer readable medium of claim 1, wherein the mask pattern is modified to place the first assist feature in the first location after the mask pattern has been modified to place the second assist feature.

17. A method comprising: determining locations within a mask pattern of a semiconductor circuit layout where assist features are to be placed based on features of the mask pattern within a threshold distance of a boundary in the mask pattern, wherein the mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary, and wherein the assist features reduce sensitivity of the features of the mask pattern to lithography process variations; and The mask pattern is modified to place the assist features in the locations.

18. The method according to claim 17, further comprising: Prior to said determining said locations, said features of said mask pattern are repositioned, wherein said features define locations of electrical interconnects or transistors.

19. A system comprising: a memory storing instructions; as well as a processor coupled to the memory and executing the instructions, which when executed cause the processor to: repositioning features within a threshold distance of a boundary in a mask pattern of a semiconductor circuit layout, wherein the mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary, and wherein the features define the location of electrical interconnects or transistors; determining locations of the mask pattern where assist features are to be placed, wherein the assist features reduce stray light at the boundaries during the first mask exposure and the second mask exposure; modifying the mask pattern to place the assist features in the locations; and Mechanical reinforcement is performed on the assist feature.

20. The system of claim 19, wherein the feature intersects the boundary, and repositioning the feature comprises modifying at least one of: a position, a size, or a shape of a portion of the feature.

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