A bandgap reference circuit

Abstract

The application relates to a band gap reference circuit, which comprises a bias circuit, a linear voltage stabilizing circuit, a state detection circuit and a reference voltage generating circuit. The bias circuit generates a bias current according to an input power supply. The state detection circuit detects the starting state of the reference voltage generating circuit and generates a corresponding first detection signal or a second detection signal. When the reference voltage generating circuit is not started, the linear voltage stabilizing circuit generates a first power supply voltage, which is used to supply power to the reference voltage generating circuit. After the reference voltage generating circuit is started, the linear voltage stabilizing circuit stops generating the first power supply voltage and generates a second power supply voltage, which is used to supply power to the reference voltage generating circuit, so that the reference voltage generating circuit continuously generates a reference voltage. The band gap reference circuit uses the linear voltage stabilizing circuit to supply power to the reference voltage generating circuit, so that the reference voltage has smaller fluctuation, stronger anti-interference capability and higher stability.

Description

Technical Field

[0001] This application relates to the field of reference voltage, and in particular to a bandgap reference circuit. Background Technology

[0002] A bandgap reference circuit is a high-precision DC voltage reference source circuit widely used in integrated circuits to provide a reference voltage to other circuits or chips. However, bandgap reference circuits have weak anti-interference capabilities, and the reference voltage is easily affected by fluctuations in the input power supply, resulting in instability. Summary of the Invention

[0003] The embodiments of this application aim to provide a bandgap reference circuit that can improve the anti-interference capability of the bandgap reference circuit and improve the stability of the reference voltage.

[0004] To address the aforementioned technical problems, this application provides the following technical solutions:

[0005] This application provides a bandgap reference circuit, which includes a bias circuit, a linear voltage regulator circuit, a state detection circuit, and a reference voltage generation circuit.

[0006] The bias circuit is configured to generate a bias current based on the input power supply;

[0007] The state detection circuit is electrically connected to the linear voltage regulator circuit. The state detection circuit is configured to detect the start-up state of the reference voltage generation circuit, and generate a first detection signal when the reference voltage generation circuit is not started, and generate a second detection signal after the reference voltage generation circuit is started.

[0008] The linear voltage regulator circuit is electrically connected to the state detection circuit and the reference voltage generation circuit, respectively. The linear voltage regulator circuit is configured to generate a first supply voltage in response to the input of the bias current and the first detection signal.

[0009] The reference voltage generation circuit is configured to generate a reference voltage in response to the input of the first supply voltage, so that the linear regulator circuit stops generating the first supply voltage and generates a second supply voltage in response to the input of the bias current, the second detection signal and the reference voltage, thereby causing the reference voltage generation circuit to continuously generate the reference voltage in response to the input of the second supply voltage.

[0010] In some embodiments, the linear voltage regulator circuit includes a first voltage regulator unit and a second voltage regulator unit;

[0011] The first voltage regulator unit is electrically connected to the state detection circuit, and the power supply terminals of the first voltage regulator unit, the second voltage regulator unit, and the reference voltage generation circuit are all connected to the first node. The first voltage regulator unit is configured to generate the first supply voltage at the first node in response to the input of the bias current and the first detection signal, and is configured to stop generating the first supply voltage in response to the input of the bias current and the second detection signal.

[0012] The second voltage regulator unit is also electrically connected to the output of the reference voltage generation circuit. The second voltage regulator unit is configured to generate the second supply voltage at the first node in response to the input of the reference voltage and the bias current.

[0013] In some embodiments, the first voltage regulating unit includes a first voltage generating unit, a first voltage following unit, and a first switching unit;

[0014] The first voltage generation unit is electrically connected to the input terminal of the first voltage follower unit, and the first voltage generation unit is configured to generate a first voltage in response to the input of the bias current;

[0015] The output terminal of the first voltage follower unit is electrically connected to the first terminal of the first switching unit, and the first voltage follower unit is configured to generate the first supply voltage based on the first voltage;

[0016] The second terminal of the first switching unit is electrically connected to the first node, and the control terminal of the first switching unit is electrically connected to the state detection circuit. The first switching unit is configured to respond to the input of the first detection signal by connecting the output terminal of the first voltage follower unit to the first node to output the first supply voltage at the first node. The first switching unit is also configured to respond to the input of the second detection signal by disconnecting the output terminal of the first voltage follower unit from the first node.

[0017] In some embodiments, the first voltage generation unit includes a first MOSFET and a second MOSFET, the first voltage follower unit includes a third MOSFET, and the first switching unit includes a fourth MOSFET.

[0018] The drain, gate, and gate of the first MOSFET are all used to connect to the bias current. The source of the first MOSFET is connected to the drain and gate of the second MOSFET, respectively. The source of the second MOSFET is grounded. The drain of the third MOSFET is used to connect to the input power supply. The source of the third MOSFET is connected to the source of the fourth MOSFET. The drain of the fourth MOSFET is connected to the first node. The gate of the fourth MOSFET is electrically connected to the state detection circuit.

[0019] In some embodiments, the second voltage regulating unit includes a second voltage generating unit and a second voltage following unit;

[0020] The second voltage generation unit is electrically connected to the output terminal of the reference voltage generation circuit and the input terminal of the second voltage follower unit, respectively. The second voltage generation unit is configured to generate a second voltage in response to the input of the bias current and the reference voltage.

[0021] The output of the second voltage follower unit is electrically connected to the first node, and the second voltage follower unit is configured to generate the second supply voltage based on the second voltage.

[0022] In some embodiments, the second voltage follower unit includes a fifth MOSFET, and the second voltage generation unit includes a sixth MOSFET;

[0023] The source of the fifth MOS transistor is electrically connected to the first node, the drain of the fifth MOS transistor is used to connect to the input power supply, the gate of the fifth MOS transistor and the source of the sixth MOS transistor are both used to connect to the bias current, the gate of the sixth MOS transistor is electrically connected to the output terminal of the reference voltage generation circuit, and the drain of the sixth MOS transistor is grounded.

[0024] In some embodiments, the bandgap reference circuit further includes a first startup circuit, which is electrically connected to the output terminal of the reference voltage generation circuit and the state detection circuit, respectively.

[0025] The first startup circuit is configured to generate a startup current to start the reference voltage generation circuit in response to the input of the bias current, and is also configured to stop generating the startup current in response to the input of the reference voltage.

[0026] In some embodiments, the state detection circuit includes a first mirror unit, a second mirror unit, and a first inverter;

[0027] The first mirror unit, the second mirror unit, and the input terminal of the first inverter are all connected to the third node, and the output terminal of the first inverter is electrically connected to the linear voltage regulator circuit.

[0028] The first mirror unit is configured to mirror the startup current to raise the voltage of the third node, thereby causing the first inverter to output the first detection signal;

[0029] The second mirror unit is configured to mirror the bias current to pull the voltage of the third node low, thereby causing the first inverter to output the second detection signal.

[0030] In some embodiments, the first mirror unit includes a seventh MOSFET and an eighth MOSFET, and the second mirror unit includes a first transistor;

[0031] The drain of the seventh MOS transistor is connected to the gate of the seventh MOS transistor, the gate of the eighth MOS transistor, and the first startup circuit. The sources of the seventh MOS transistor and the eighth MOS transistor are both used to connect to the input power supply. The drain of the eighth MOS transistor, the collector of the first transistor, and the input terminal of the first inverter are all connected to the third node. The base of the first transistor is electrically connected to the first startup circuit, and the emitter of the first transistor is grounded.

[0032] In some embodiments, the first startup circuit includes a ninth MOSFET, a tenth MOSFET, and a second transistor;

[0033] The drain, gate, and gate of the ninth MOS transistor are all connected to the fourth node and are used to receive the bias current. The source of the ninth MOS transistor is connected to the collector, base, and second mirror unit of the second transistor, respectively. The emitter of the second transistor is grounded. The drain of the tenth MOS transistor is connected to the first mirror unit. The emitter of the tenth MOS transistor is connected to the output terminal of the reference voltage generation circuit.

[0034] In some embodiments, the bandgap reference circuit further includes a second startup circuit;

[0035] The second startup circuit is electrically connected to the enable terminals of the bias circuit and the reference voltage generation circuit, respectively. The second startup circuit is configured to send a startup signal to the bias circuit to start the bias circuit in response to the input of the input power supply, and is also configured to stop sending the startup signal in response to the input of the bias current, and generate an enable signal to drive the reference voltage generation circuit to work.

[0036] In some embodiments, the second startup circuit includes an energy storage unit, a third mirror unit, a second switching unit, and a second inverter;

[0037] The energy storage unit, the third mirror unit, the control terminal of the second switching unit, and the input terminal of the second inverter are all connected to the fifth node. The first terminal of the second switching unit is connected to the control terminal of the bias circuit, and the second terminal of the second switching unit is grounded.

[0038] The energy storage unit is configured to store energy in the input power supply to raise the voltage of the fifth node, thereby enabling the second switching unit to connect the control terminal of the bias circuit to ground, so as to send the start signal to the control terminal of the bias circuit.

[0039] The third mirroring unit is configured to mirror the bias current to pull the voltage of the fifth node low, thereby causing the second switching unit to disconnect the electrical connection between the control terminal of the bias circuit and ground, stop sending the start signal, and cause the second inverter to output the enable signal.

[0040] In some embodiments, the energy storage unit includes an energy storage capacitor, the third mirror unit includes an eleventh MOSFET, and the second switching unit includes a twelfth MOSFET;

[0041] One end of the energy storage capacitor is used to connect to the input power supply, and the other end of the energy storage capacitor is connected to the fifth node together with the drain of the eleventh MOS transistor and the gate of the twelfth MOS transistor. The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are grounded together. The gate of the eleventh MOS transistor is connected to the bias circuit, and the drain of the twelfth MOS transistor is connected to the control terminal of the bias circuit.

[0042] In some embodiments, the reference voltage generation circuit includes a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and an operational amplifier;

[0043] The base of the third transistor is connected to the base of the fourth transistor and the output terminal of the operational amplifier. The collectors of the third and fourth transistors are used to connect to the first or second supply voltage. The emitter of the third transistor is connected to one end of the third resistor and the non-inverting input terminal of the operational amplifier. The emitter of the fourth transistor is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the second resistor and the inverting input terminal of the operational amplifier. The other ends of the third and second resistors are connected to one end of the fourth resistor, which is grounded.

[0044] In various embodiments of this application, the bandgap reference circuit includes a bias circuit, a linear regulator circuit, a state detection circuit, and a reference voltage generation circuit. The bias circuit generates a bias current based on the input power supply. The state detection circuit detects the startup state of the reference voltage generation circuit and generates a corresponding first detection signal or a second detection signal. When the reference voltage generation circuit is not started, the linear regulator circuit responds to the input of the bias current and the first detection signal to generate a first supply voltage, which powers the reference voltage generation circuit. After the reference voltage generation circuit starts, it generates a reference voltage in response to the input of the first supply voltage. The reference voltage is fed back to the linear regulator circuit, causing the linear regulator circuit to stop generating the first supply voltage and generate a second supply voltage in response to the input of the bias current, the second detection signal, and the reference voltage. The second supply voltage powers the reference voltage generation circuit, allowing the reference voltage generation circuit to continuously generate the reference voltage in response to the input of the second supply voltage. Therefore, the bandgap reference circuit uses a linear voltage regulator circuit to power the reference voltage generation circuit. The stable reference voltage makes the second supply voltage generated by the linear voltage regulator circuit more stable, which in turn makes the reference voltage generated by the reference voltage generation circuit more stable until the entire circuit reaches a steady state. Since the supply voltage of the reference voltage generation circuit is stable, the fluctuation of the reference voltage it generates is small, the anti-interference ability is stronger, and the stability is higher. Attached Figure Description

[0045] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0046] Figure 1 This is a schematic diagram of the structure of one of the bandgap reference circuits provided in the embodiments of this application;

[0047] Figure 2 This is a schematic diagram of the structure of one of the bandgap reference circuits provided in the embodiments of this application;

[0048] Figure 3 This is a schematic diagram of the structure of one of the bandgap reference circuits provided in the embodiments of this application;

[0049] Figure 4 This is a schematic diagram of the structure of one of the linear voltage regulator circuits provided in the embodiments of this application;

[0050] Figure 5 This is a schematic diagram of the structure of one of the first voltage regulator units and the second voltage regulator unit provided in the embodiments of this application;

[0051] Figure 6 This is a schematic diagram of the structure of one of the state detection circuits provided in the embodiments of this application;

[0052] Figure 7 This is a schematic diagram of the structure of one of the second start-up circuits provided in the embodiments of this application;

[0053] Figure 8 This is a schematic diagram of the circuit structure of one of the second startup circuits and bias circuits provided in the embodiments of this application;

[0054] Figure 9 This is a schematic diagram of the circuit structure of one of the first start-up circuits and state detection circuits provided in the embodiments of this application;

[0055] Figure 10 This is a schematic diagram of the circuit structure of one of the linear voltage regulator circuits provided in the embodiments of this application;

[0056] Figure 11 This is a schematic diagram of the circuit structure of one of the reference voltage generation circuits provided in the embodiments of this application;

[0057] Figure 12 This is a schematic diagram of a DC simulation curve of a reference voltage temperature drift provided in one of the embodiments of this application;

[0058] Figure 13 This is a schematic diagram of an AC simulation curve of a reference voltage rejection ratio provided in one of the embodiments of this application. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0060] Please see Figure 1 , Figure 1 This is a schematic diagram of a bandgap reference circuit provided in an embodiment of this application, as shown below. Figure 1As shown, the bandgap reference circuit 100 includes a bias circuit 10, a linear regulator circuit 20, a state detection circuit 30, and a reference voltage generation circuit 40. The bias circuit 10 is electrically connected to both the linear regulator circuit 20 and the reference voltage generation circuit 40. The linear regulator circuit 20 is also electrically connected to the power supply terminal (VCC) of the reference voltage generation circuit 40. The output terminal of the reference voltage generation circuit 40 is electrically connected to both the linear regulator circuit 20 and the state detection circuit 30, and the state detection circuit 30 is also electrically connected to the linear regulator circuit 20.

[0061] The bias circuit 10 generates a bias current based on the input power supply VIN, and provides bias current to the linear regulator circuit 20 and the reference voltage generation circuit 40 respectively. The bias current provides appropriate bias to the linear regulator circuit 20 and the reference voltage generation circuit 40 to maintain their normal operating state.

[0062] When the reference voltage generation circuit 40 is not started, it needs to be pulled out of zero by other circuits. After starting, it begins to continuously generate the reference voltage. Therefore, a state detection circuit 30 is used to detect the start-up state of the reference voltage generation circuit 40, generate a corresponding detection signal, and send the corresponding detection signal to the linear regulator circuit 20 so that the linear regulator circuit 20 can provide different supply voltages to the reference voltage generation circuit 40. When the reference voltage generation circuit 40 is not started, the state detection circuit 30 generates a first detection signal, and after the reference voltage generation circuit 40 is started, it generates a second detection signal.

[0063] When the reference voltage generation circuit 40 is not started, the state detection circuit 30 generates a first detection signal. The linear voltage regulator circuit 20 responds to the bias current and the first detection input to generate a first supply voltage and supplies the first supply voltage to the reference voltage generation circuit 40, so that after the reference voltage generation circuit 40 is started, it responds to the first supply voltage and the bias current input to generate a reference voltage VBG.

[0064] The first supply voltage is generated based on the input power supply VIN. If the input power supply VIN fluctuates, it will cause the first supply voltage to fluctuate. Therefore, the first supply voltage is easily disturbed and fluctuates greatly, which in turn causes the reference voltage VBG generated by the reference voltage generation circuit 40 to fluctuate and become unstable.

[0065] When the linear regulator circuit 20 receives the reference voltage VBG and the second detection signal, it indicates that the reference voltage generation circuit 40 has been started. In response to the input of the bias current, the second detection signal and the reference voltage VBG, the linear regulator circuit 20 stops generating the first supply voltage and generates the second supply voltage. Then, the reference voltage generation circuit 40 responds to the input of the second supply voltage and continues to generate the reference voltage VBG.

[0066] The linear regulator circuit 20 generates a second supply voltage based on the reference voltage VBG, making the second supply voltage no longer affected by the fluctuation of the input power supply VIN, and thus more stable. The more stable second supply voltage continues to supply power to the reference voltage generation circuit 40, which in turn generates a more stable reference voltage VBG. The more stable reference voltage VBG further drives the second supply voltage generated by the linear regulator circuit 20 to become more stable, and then the reference voltage VBG generated by the reference voltage generation circuit 40 becomes more stable, until the loop reaches a steady state.

[0067] Therefore, since the linear voltage regulator circuit 20 provides a more stable power supply voltage to the reference voltage generation circuit 40, the reference voltage VBG generated by the reference voltage generation circuit 40 is also more stable and is not affected by the fluctuation of the input power supply VIN, thereby improving the anti-interference capability of the bandgap reference circuit 100.

[0068] Meanwhile, in related technologies, in order to improve the anti-interference capability of the bandgap reference circuit 100, the loop bandwidth of the bandgap reference circuit 100 is generally increased. However, high bandwidth means high current, which means high power consumption. In the embodiments of this application, the magnitude of the bias current affects the power consumption of the linear voltage regulator circuit 20, and the bias current is generally small, only a few milliamps or even a few nanoamps, which makes the power consumption of the linear voltage regulator circuit 20 also small.

[0069] Therefore, in this embodiment, a linear voltage regulator circuit 20 is used to provide a more stable power supply voltage to the reference voltage generation circuit 40, so that the reference voltage generation circuit 40 generates a more stable reference voltage VBG, thereby improving the anti-interference capability of the bandgap reference circuit 100. At the same time, the power consumption of the linear voltage regulator circuit 20 is also smaller, thus enabling the bandgap reference circuit 100 to have high anti-interference capability while also having low power consumption.

[0070] In summary, this bandgap reference circuit uses a linear voltage regulator circuit to power the reference voltage generation circuit. The stable reference voltage makes the second supply voltage generated by the linear voltage regulator circuit more stable, which in turn makes the reference voltage generated by the reference voltage generation circuit more stable until the entire circuit reaches a steady state. Since the supply voltage of the reference voltage generation circuit is stable, the fluctuation of the reference voltage it generates is small, the anti-interference ability is stronger, and the stability is higher.

[0071] Please see Figure 2 , Figure 2 This is a schematic diagram of a bandgap reference circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, the bandgap reference circuit 100 also includes a first startup circuit 50, which is electrically connected to the output terminal of the reference voltage generation circuit 40 and the state detection circuit 30.

[0072] When power is first applied, the reference voltage generation circuit 40 may be in a stable state with zero current, also known as the zero state. It is in an unstarted state and cannot generate a stable reference voltage VBG. To break the stable state with zero current, or to pull the reference voltage generation circuit 40 out of the zero state, this embodiment employs a first startup circuit 50 to inject an initial current into the reference voltage generation circuit 40 at the moment of power-on, causing the reference voltage generation circuit 40 to start and enter normal operating mode.

[0073] Specifically, at the moment of power-on, the bias circuit 10 provides a bias current to the first startup circuit 50, so that the first startup circuit 50 generates a startup current based on the bias current. This startup current is injected into the reference voltage generation circuit 40 to start the reference voltage generation circuit 40 and begin normal operation.

[0074] After the reference voltage generation circuit 40 is started, a reference voltage VBG is generated. The reference voltage VBG acts on the first start-up circuit 50, causing the first start-up circuit 50 to stop generating the start-up current, thus avoiding interference with the normal operation of the reference generation circuit and ensuring that the output of the reference voltage generation circuit 40 is not affected by the first start-up circuit 50.

[0075] In this embodiment, the first startup circuit 50 provides a stable and reliable startup condition for the reference voltage generation circuit 40, ensuring that the reference voltage generation circuit 40 can smoothly enter the normal working state under any circumstances as long as the input power supply VIN is powered on, thereby ensuring the stability and reliability of the entire system. At the same time, after the first startup circuit 50 completes the startup task, it stops generating startup current to ensure that the reference voltage generation circuit 40 can work normally and avoid interference from the first startup circuit 50.

[0076] Please see Figure 3 , Figure 3 This is a schematic diagram of a bandgap reference circuit provided in an embodiment of this application, as shown below. Figure 3 As shown, the bandgap reference circuit 100 also includes a second startup circuit 60, which is electrically connected to the enable terminals of the bias circuit 10 and the reference voltage generation circuit 40, respectively.

[0077] The second startup circuit 60 is used to start the bias circuit 10, enabling it to generate a bias current and thus ensuring the normal operation of other circuits. Specifically, the second startup circuit 60 is electrically connected to the input power supply VIN. When the power supply is powered on, the second startup circuit 60 sends a startup signal to the bias circuit 10 based on the input power supply VIN to start the bias circuit 10, thereby enabling the bias circuit 10 to generate a bias current normally. After the bias current is generated, the second startup circuit 60 stops sending the startup signal to avoid affecting the normal operation of the bias circuit 10 and to ensure the normal output of the bias current. At the same time, after the bias current is generated, the second startup circuit 60 also generates an enable signal based on the bias current to act on the enable terminal of the reference voltage generation circuit 40, thereby driving the reference voltage generation circuit 40 to work.

[0078] Therefore, in this embodiment of the application, when powered on, the second startup circuit 60 is used to start the bias circuit 10 so that it can generate bias current normally. At the same time, after the bias circuit 10 is started, the startup signal is stopped to prevent it from affecting the normal operation of the bias circuit 10. This also allows the reference voltage generation circuit 40 to obtain the enable signal after the bias current is generated and enter the working state, thereby reducing power consumption.

[0079] Please see Figure 4 , Figure 4 This is a schematic diagram of a linear voltage regulator circuit provided in an embodiment of this application, as shown below. Figure 4 As shown, the linear voltage regulator circuit 20 includes a first voltage regulator unit 21 and a second voltage regulator unit 22. The first voltage regulator unit 21 is electrically connected to the state detection circuit 30, and the first voltage regulator unit 21, the second voltage regulator unit 22, and the power supply terminal VCC terminal of the reference voltage generation circuit 40 are all connected to the first node A. The second voltage regulator unit 22 is also electrically connected to the output terminal of the reference voltage generation circuit 40.

[0080] The bias circuit 10 continuously provides bias current to the first voltage regulator unit 21 and the second voltage regulator unit 22 respectively, so that the first voltage regulator unit 21 and the second voltage regulator unit 22 can work normally.

[0081] When the reference voltage generation circuit 40 is not started, the state detection circuit 30 generates a first detection signal, and the first voltage regulation unit 21 responds to the input of the first detection signal and generates a first supply voltage at the first node A.

[0082] After the reference voltage generation circuit 40 is started, the first supply voltage supplies power to the reference voltage generation circuit 40, enabling it to operate normally and generate a reference voltage VBG. This reference voltage VBG then acts on the second voltage regulator unit 22, causing the second voltage regulator unit 22 to generate a second supply voltage at the first node A in response to the input of the reference voltage VBG. Simultaneously, after the reference voltage generation circuit 40 is started, the state detection circuit 30 generates a second detection signal. The first voltage regulator unit 21 responds to the input of the second detection signal and stops generating the first supply voltage at the first node A.

[0083] The second supply voltage is generated based on the reference voltage VBG. It is not affected by fluctuations in the input power supply VIN and is more stable. This causes the reference voltage generation circuit 40 to generate a more stable reference voltage VBG. The more stable reference voltage VBG drives the second stabilizing unit to generate a more stable second supply voltage. This cycle continues until the loop reaches a steady state.

[0084] After the reference voltage generation circuit 40 is started, the second voltage regulator unit 22 continuously provides a more stable second power supply voltage to the reference voltage generation circuit 40, making the reference voltage VBG generated by the reference voltage generation circuit 40 more stable, thereby making the entire circuit more resistant to interference.

[0085] Meanwhile, the first voltage regulator unit 21 and the second voltage regulator unit 22 only require a suitable bias current to operate normally. The bias current is relatively small, which makes the power consumption of the first voltage regulator unit 21 and the second voltage regulator unit 22 low, and thus the power consumption of the entire circuit is also low. Therefore, the bandgap reference circuit 100 achieves high anti-interference while also having low power consumption.

[0086] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a first voltage regulator unit and a second voltage regulator unit provided in an embodiment of this application, as shown below. Figure 5 As shown, the first voltage regulator unit 21 includes a first voltage generation unit 211, a first voltage follower unit 212, and a first switching unit 213. The first voltage generation unit 211 is electrically connected to the input terminal of the first voltage follower unit 212. The output terminal of the first voltage follower unit 212 is electrically connected to the first terminal of the first switching unit 213. The second terminal of the first switching unit 213 is electrically connected to the first node A. The control terminal of the first switching unit 213 is electrically connected to the state detection circuit 30. The power supply terminal VCC of the first voltage follower unit 212 is electrically connected to the input power supply VIN.

[0087] The first voltage generation unit 211 generates a first voltage based on the bias current, which enables the first voltage follower unit 212 to generate a first supply voltage based on the first voltage. When the reference voltage generation circuit 40 is not activated, the state detection circuit 30 generates a first detection signal to control the first switching circuit to be in the on state, thereby connecting the output terminal of the first voltage follower unit 212 with the first node A, so as to output the first supply voltage at the first node A.

[0088] After the reference voltage generation circuit 40 is started, the state detection circuit 30 generates a second detection signal, controls the first switch circuit to be in the off state, thereby disconnecting the electrical connection between the output terminal of the first voltage follower unit 212 and the first node A, and stopping the output of the first supply voltage at the first node A.

[0089] In this embodiment, a first voltage generation unit 211 generates a first voltage, which can generate a suitable first voltage according to the power supply requirements of the reference voltage generation circuit 40. However, since the load current of the first voltage generation unit 211 is a bias current, which is generally a small current, it cannot effectively carry a load. In order to improve the load-carrying capacity, this application provides a first voltage follower unit 212, which can both follow the first voltage and generate a larger load current based on the input power supply VIN, thus driving the load.

[0090] This application embodiment also employs a first switching circuit to control the output of the first power supply voltage, so that after the reference voltage generation circuit 40 starts generating the reference voltage VBG, the output of the first power supply voltage is stopped in time to prevent the first power supply voltage from affecting the second power supply voltage, so that the reference voltage generation circuit 40 is completely powered by the more stable second power supply voltage, thereby improving the anti-interference capability.

[0091] Please continue reading. Figure 5 The second voltage regulator unit 22 includes a second voltage generation unit 221 and a second voltage follower unit 222. The second voltage generation unit 221 is electrically connected to the output terminal of the reference voltage generation circuit 40 and the input terminal of the second voltage follower unit 222, respectively. The output terminal of the second voltage follower unit 222 is electrically connected to the first node A. The power supply terminal VCC of the second voltage follower unit 222 is electrically connected to the input power supply VIN.

[0092] The bias circuit 10 also provides bias current to the second voltage generation unit 221 so that it can work normally. At the same time, after the reference voltage generation circuit 40 is started, it generates a reference voltage VBG. Then, the second voltage generation unit 221 responds to the input of the reference voltage VBG and generates a second voltage, so that the second voltage follower unit 222 generates a second supply voltage at the first node A based on the second voltage, so as to provide a second supply voltage to the reference voltage generation circuit 40.

[0093] In this embodiment, the reference voltage VBG controls the second voltage generation unit 221 to generate the second voltage, thereby controlling the generation of the second supply voltage, so that the second voltage generation unit 221, the second voltage follower unit 222 and the reference voltage generation circuit 40 form a loop. When the loop reaches a steady state, both the second supply voltage and the reference voltage VBG reach a stable voltage, which has strong anti-interference ability.

[0094] Meanwhile, since the load current of the second voltage generation unit 221 is a bias current, which is generally a small current, it cannot effectively carry a load. In order to improve the load-carrying capacity, this application provides a second voltage follower unit 222, which can both follow the second voltage and generate a larger load current based on the input power supply VIN, thus driving the load.

[0095] Please see Figure 6 , Figure 6 This is a schematic diagram of a state detection circuit provided in an embodiment of this application. In this embodiment, the bandgap reference circuit 100 includes a first startup circuit 50, a bias circuit 10, a linear voltage regulator circuit 20, a state detection circuit 30, and a reference voltage generation circuit 40. The state detection circuit 30 includes a first mirror unit 31, a second mirror unit 32, and a first inverter 33. The input terminals of the first mirror unit 31, the second mirror unit 32, and the first inverter 33 are all connected to the third node C. The output terminal of the first inverter 33 is electrically connected to the linear voltage regulator circuit 20.

[0096] When the first startup circuit 50 generates a startup current to start the reference voltage generation circuit 40, the first mirror unit 31 mirrors the startup current and raises the voltage of the third node C based on the startup current, so that the third node C is in a high-level state, thereby causing the first inverter 33 to output a first detection signal, which is a low-level signal.

[0097] After the reference voltage generation circuit 40 is started, the starting current stops being generated. Then, the second mirror unit 32 mirrors the bias current and pulls down the voltage of the third node C based on the mirrored bias current, so that the third node C is in a low-level state. This causes the first inverter 33 to output the second detection signal, which is a high-level signal.

[0098] To ensure that the reference voltage generation circuit 40 can start, the starting current is large, which ensures that the first mirror unit 31 can raise the voltage at the third node C. After the reference voltage generation circuit 40 starts, since the bias current is less than the starting current, the second mirror unit 32 can pull down the voltage at the third node C. This allows the first inverter 33 to output different detection signals when the reference voltage generation circuit 40 is in different states, thereby controlling the linear regulator circuit 20 to provide different power supply voltages to the reference voltage generation circuit 40.

[0099] Please see Figure 7 , Figure 7 This is a schematic diagram of a second startup circuit provided in an embodiment of this application, as shown below. Figure 7 As shown, the second startup circuit 60 includes an energy storage unit 61, a third mirror unit 62, a second switching unit 63, and a second inverter 64. The control terminals of the energy storage unit 61, the third mirror unit 62, and the second switching unit 63, as well as the input terminal of the second inverter 64, are all connected to the fifth node E. The first terminal of the second switching unit 63 is connected to the control terminal of the bias circuit 10, and the second terminal of the second switching unit 63 is grounded to AGND.

[0100] The energy storage unit 61 stores energy in the input power supply VIN to raise the voltage of the fifth node E, so that the voltage of the fifth node E is in a high-level state, which in turn puts the second switching unit 63 into a conducting state, connecting the electrical connection between the control terminal of the bias circuit 10 and ground AGND. The control terminal of the bias circuit 10 receives a start signal, which is a low-level signal, thereby starting the bias circuit 10 and generating a bias current.

[0101] After the bias circuit 10 is started, the third mirror unit 62 mirrors the bias current. Based on the mirrored bias current, the voltage of the fifth node E point is pulled down, so that the voltage of the fifth node E point is in a low level state. This causes the second switch unit 63 to be in the off state, disconnecting the electrical connection between the bias circuit 10 and ground AGND, and stopping the sending of the start signal to the control terminal of the bias circuit 10.

[0102] The second inverter 64 generates an enable signal based on the voltage at the fifth node E after it is pulled low. When the voltage at the fifth node E is in a low-level state, the second inverter 64 outputs a high-level enable signal, thereby driving the reference voltage generation circuit 40 to work normally.

[0103] In this embodiment, the energy storage unit 61 stores energy in the input power supply VIN, so that the voltage at the fifth node E is at a high level before the bias circuit 10 is started, thereby starting the bias circuit 10. During the start-up process, no current is required, resulting in lower power consumption of the second start-up circuit 60, and further reducing the overall power consumption of the bandgap reference circuit 100.

[0104] Please see Figure 8 , Figure 8 This is a schematic diagram of the circuit structure of a second startup circuit and a bias circuit provided in an embodiment of this application, as shown below. Figure 8 As shown, the energy storage unit 61 includes an energy storage capacitor CB2, the third mirror unit 62 includes an eleventh MOSFET M11, and the second switching unit 63 includes a twelfth MOSFET M12. One end of the energy storage capacitor CB2 is connected to the input power supply VIN, and the other end of the energy storage capacitor CB2 is connected to the drain of the eleventh MOSFET M11 and the gate of the twelfth MOSFET M12 at the fifth node E. The source of the eleventh MOSFET M11 and the source of the twelfth MOSFET M12 are grounded to AGND. The gate of the eleventh MOSFET M11 is connected to the bias circuit 10, and the drain of the second MOSFET is connected to the control terminal of the bias circuit 10.

[0105] The bias circuit 10 includes a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, and a bias resistor RB1. The source of the thirteenth MOSFET M13 and the source of the fourteenth MOSFET M14 are connected to the input power supply VIN. The gate and drain of the thirteenth MOSFET M13 and the gate of the fourteenth MOSFET M14 are connected to the fifth node E. The drain of the thirteenth MOSFET M13 is also connected to the drain of the fifteenth MOSFET M15. The gate of the fifteenth MOSFET M15 is connected to the gate and drain of the sixteenth MOSFET M16, the drain of the fourteenth MOSFET M14, and the gate of the eleventh MOSFET M11. The source of the fifteenth MOSFET M15 is connected to one end of the bias resistor RB1, and the other end of the bias resistor RB1 is grounded to AGND. The source of the sixteenth MOSFET M16 is grounded to AGND.

[0106] When powered on, the energy storage capacitor CB2 stores energy in the input power supply VIN. Since the voltage on the energy storage capacitor CB2 cannot change abruptly, the voltage VS at the fifth node E is approximately equal to the voltage VIN of the input power supply VIN. The potential at the fifth node E is high, the twelfth MOSFET M12 is turned on, and the electrical connection between the gate of the thirteenth MOSFET M13, the gate of the fourteenth MOSFET M14 and ground AGND is established. That is, a low-level start signal is sent to the gate of the thirteenth MOSFET M13 and the gate of the fourteenth MOSFET M14, causing the gate potential of the thirteenth MOSFET M13 and the fourteenth MOSFET M14 to become low. The thirteenth MOSFET M13 and the fourteenth MOSFET M14 are turned on, and the entire bias circuit 10 is started, generating a bias current based on the input power supply VIN.

[0107] After the bias current is generated, the eleventh MOSFET M11 mirrors the current of the sixteenth MOSFET M16, thereby pulling down the potential of point E at the fifth node. The twelfth MOSFET M12 is turned off, disconnecting the electrical connection between the gate of the thirteenth MOSFET M13, the gate of the fourteenth MOSFET M14, and ground AGND, that is, stopping the sending of start signals to the gate of the thirteenth MOSFET M13 and the gate of the fourteenth MOSFET M14.

[0108] The input terminal of the second inverter INV2 is connected to the fifth node E. When the potential of the fifth node E is pulled low, the second inverter INV2 outputs a high-level enable signal. This enable signal acts on the enable terminal of the reference voltage generation circuit 40 to drive the reference voltage generation circuit 40 to work.

[0109] Before the bias circuit 10 is started, the potential at point E of the fifth node is high, causing the twelfth MOSFET M12 to conduct, thereby starting the bias circuit 10 to generate a bias current. This embodiment achieves zero-current startup of the bias circuit 10, resulting in no current consumption in the second startup circuit 60. Furthermore, the bias current can be set as needed. In this embodiment, by selecting the models of the thirteenth MOSFET M13 to the sixteenth MOSFET M16, and the resistance value of the bias resistor RB1, a bias current of 5nA is generated, resulting in a total current consumption of only 10nA for the entire bias circuit 10, which is relatively low.

[0110] Please see Figure 9 , Figure 9 This is a schematic diagram of the circuit structure of a first startup circuit and a state detection circuit provided in an embodiment of this application, as shown below. Figure 9As shown, the first mirror unit 31 includes a seventh MOSFET M7 and an eighth MOSFET M8, and the second mirror unit 32 includes a first transistor Q1. The drain of the seventh MOSFET M7 is connected to the gate of the seventh MOSFET M7, the gate of the eighth MOSFET M8, and the first startup circuit 50, respectively. The sources of the seventh MOSFET M7 and the eighth MOSFET M8 are both used to connect to the input power supply VIN. The drain of the eighth MOSFET M8, the collector of the first transistor Q1, and the input terminal of the first inverter INV1 are all connected to the third node C. The base of the first transistor Q1 is electrically connected to the first startup circuit 50, and the emitter of the first transistor Q1 is grounded to AGND.

[0111] The first startup circuit 50 includes a ninth MOSFET M9, a tenth MOSFET M10, and a second transistor Q2. The drain and gate of the ninth MOSFET M9 and the gate of the tenth MOSFET M10 are connected to the fourth node D and are used to connect the bias current. The source of the ninth MOSFET M9 is connected to the collector and base of the second transistor Q2 and the second mirror unit 32, respectively. Specifically, the source of the ninth MOSFET M9 is connected to the collector, base, and base of the second transistor Q2 and the first transistor Q1, respectively. The emitter of the second transistor Q2 is grounded to AGND. The drain of the tenth MOSFET M10 is connected to the first mirror unit 31. Specifically, the drain of the tenth MOSFET M10 is connected to the drain of the seventh MOSFET M7. The emitter of the tenth MOSFET M10 is connected to the output terminal of the reference voltage generation circuit 40.

[0112] The bias current of the first startup circuit 50 is current I7, which is generated by the bias circuit 10. Current I7 is applied to the ninth MOSFET M9 and the second transistor Q2 connected in diode configuration, generating a startup voltage VSY at point D of the fourth node. The aspect ratio of the tenth MOSFET M10 is much larger than that of the ninth MOSFET M9. When the reference voltage generation circuit 40 is not started, the reference voltage VBG is zero. Since the source voltage of the tenth MOSFET M10 is zero and its gate voltage is the startup voltage VSY, the tenth MOSFET M10 sinks current to its source, causing the source voltage of the tenth MOSFET M10 to rise. This raises the reference voltage VBG output by the reference voltage generation circuit 40, thereby pulling the reference voltage generation circuit 40 out of zero and starting the reference voltage generation circuit 40.

[0113] The tenth MOSFET M10 is turned off because its gate-source voltage becomes low. For example, if the current I7 is 5nA, the startup voltage VSY is about 1.4V, which can raise the source voltage of the tenth MOSFET M10 to 1V. Then the gate-source voltage VGS of the tenth MOSFET M10 is only 0.4V, so the tenth MOSFET M10 is turned off.

[0114] The state detection circuit 30 detects the startup state of the reference voltage generation circuit 40. Specifically, during the startup process of the reference voltage generation circuit 40 when current I7 is injected, due to the high startup voltage VSY, a large current flows through the tenth MOSFET M10, which in turn causes a large current to flow through the seventh MOSFET M7. The eighth MOSFET M8 mirrors the current of the seventh MOSFET M7, and a large current flows through the eighth MOSFET M8, which raises the voltage at the third node C, causing the first inverter INV1 to output the first detection signal. The first detection signal is a low-level signal, i.e., the signal VBG_OK is a low-level signal.

[0115] After the reference voltage generation circuit 40 is started, the tenth MOSFET M10 is turned off, and the current of the eighth MOSFET M8 is zero. The current of the first transistor Q1 is mirrored by the current of the second transistor Q2. The current of the second transistor Q2 is I7, which is small. Therefore, the voltage generated on the first transistor Q1 is small, which pulls down the voltage at the third node C, so that the first inverter INV1 outputs the second detection signal. The second detection signal is a high-level signal, that is, the signal VBG_OK is a high-level signal.

[0116] In some embodiments, the state detection circuit 30 further includes a capacitor CS1, which is connected in parallel between the input power supply VIN and the input terminal of the first inverter INV1. When the reference voltage generation circuit 40 is not started, the capacitor CS1 stores energy in the input power supply VIN, raising the voltage at the third node C, thereby ensuring that the first inverter INV1 outputs a low-level first detection signal. After the reference voltage generation circuit 40 is started, the first transistor Q1 pulls down the voltage at the third node C, thereby causing the first inverter INV1 to output a high-level second detection signal.

[0117] In this embodiment, capacitor CS1 is used to ensure that the first inverter INV1 generates a low-level first detection signal when the reference voltage generation circuit 40 is not started, providing a redundancy measure and thereby improving the reliability of the circuit operation.

[0118] If the current I7 is 5nA, then the power consumption of the first startup circuit 50 is only 5nA, which is low.

[0119] Please see Figure 10 , Figure 10 This is a schematic diagram of the circuit structure of a linear voltage regulator circuit provided in an embodiment of this application, as shown below. Figure 10As shown, the first voltage generation unit 211 includes a first MOSFET M1 and a second MOSFET M2, the first voltage follower unit 212 includes a third MOSFET M3, and the first switching unit 213 includes a fourth MOSFET M4. The drain and gate of the first MOSFET M1 and the gate of the third MOSFET M3 are all used to connect to the bias current. The source of the first MOSFET M1 is connected to the drain and gate of the second MOSFET M2, respectively. The source of the second MOSFET M2 is grounded to AGND. The drain of the third MOSFET M3 is used to connect to the input power supply VIN. The source of the third MOSFET M3 is connected to the source of the fourth MOSFET M4. The drain of the fourth MOSFET M4 is connected to the power supply terminal VCC of the reference voltage generation circuit 40 at the first node A. The gate of the fourth MOSFET M4 is electrically connected to the state detection circuit 30.

[0120] The second voltage follower unit 222 includes a fifth MOSFET M5, and the second voltage generation unit 221 includes a sixth MOSFET M6. The source of the fifth MOSFET M5 is electrically connected to the first node A, the drain of the fifth MOSFET M5 is used to connect to the input power supply VIN, the gate of the fifth MOSFET M5 and the source of the sixth MOSFET M6 are both used to connect to the bias current, the gate of the sixth MOSFET M6 is electrically connected to the output terminal of the reference voltage generation circuit 40, and the drain of the sixth MOSFET M6 is grounded to AGND.

[0121] The bias current of the first voltage regulator unit 21 is current I1, and the bias current of the second voltage regulator unit 22 is current I2. Both current I1 and current I2 are generated by the bias circuit 10.

[0122] Current I1 flows through the first MOSFET M1 and the second MOSFET M2. The first MOSFET M1 and the second MOSFET M2 are connected in a diode configuration. Therefore, the gate voltage of the first MOSFET M1, i.e. the first voltage VX, is VGS1 + VGS2. The third MOSFET M3 generates the first supply voltage VCC1 based on the first voltage. At this time, the reference voltage generation circuit 40 is not activated. The gate of the fourth MOSFET M4 is a low-level first detection signal. Therefore, the fourth MOSFET M4 is turned on, and the voltage at the first node A is set to the first supply voltage VCC1 through the fourth MOSFET M4.

[0123] The first supply voltage VCC1 is generated based on the input power supply VIN. It is easily affected by process, voltage, and temperature, resulting in large fluctuations, significant deviations, and poor stability. Therefore, using the first supply voltage VCC1 to provide the power supply voltage for the reference voltage generation circuit 40 will also make the reference voltage VBG unstable. In order to obtain a more stable reference voltage VBG, the second voltage regulator unit 22 generates a second supply voltage to power the reference voltage generation circuit 40.

[0124] The first supply voltage VCC1 serves as the supply voltage for the reference voltage generation circuit 40. After the reference voltage generation circuit 40 is started, it generates a reference voltage VBG. When the gate of the fourth MOSFET M4 receives a high-level second detection signal, the fourth MOSFET M4 turns off, stopping the output of the first supply voltage VCC1. Simultaneously, the reference voltage VBG acts on the gate of the sixth MOSFET M6, resulting in the second voltage VY = VBG + VGS. M6 Then, after passing through the fifth MOSFET M5, a second supply voltage is generated at point A of the first node:

[0125] VCC2=VY--VGS M5 =VBG+VGS M6 -VGS M5 (1)

[0126] Where VCC2 is the second supply voltage, VBG is the reference voltage VBG, and VGS is the reference voltage. M6 VGS is the gate-source voltage of the sixth MOSFET M6. M5 This is the gate-source voltage of the fifth MOSFET M5.

[0127] Therefore, the second supply voltage VCC2 is not affected by the input power supply VIN, but is only related to the reference voltage VBG. If the reference voltage VBG is more stable, it will drive the second supply voltage VCC2 to be more stable as well. The second supply voltage VCC2 supplies power to the reference voltage generation circuit 40, which in turn drives the reference voltage generation circuit 40 to generate a more stable reference voltage VBG. The loop repeats in this way until a steady state is reached.

[0128] In this embodiment, when the reference voltage generation circuit 40 is not started, a first supply voltage is provided to it so that the reference voltage generation circuit 40 generates a reference voltage VBG. After the reference voltage generation circuit 40 is started, a more stable second supply voltage is generated based on the reference voltage VBG. The more stable second supply voltage is then supplied to the reference voltage generation circuit 40, so that the reference voltage generation circuit 40 generates a more stable reference voltage VBG. The more stable the supply voltage of the reference voltage generation circuit 40, the less affected it is by power fluctuations, and the stronger its anti-interference ability.

[0129] Furthermore, since both currents I1 and I2 are bias currents and are relatively small, the current consumption of both the first voltage regulator unit 21 and the second voltage regulator unit 22 is relatively small.

[0130] The values ​​of the first supply voltage VCC1 and the second supply voltage VCC2 can be set as needed. For example, if the current I1 is 5nA and the current I2 is 5nA, then the first voltage VX is approximately 1.8V, which is easily affected by interference, and the first supply voltage is approximately 1.4V, with significant fluctuations. After the reference voltage generation circuit 40 is started, if the reference voltage VBG is 1.2V, then the second voltage VY is a more accurate 1.8V, and the second supply voltage is approximately 1.4V, with smaller fluctuations. The entire linear regulator circuit 20 consumes only 10nA of current.

[0131] Please see Figure 11 , Figure 11 This is a schematic diagram of the circuit structure of a reference voltage generation circuit provided in an embodiment of this application, as shown below. Figure 11 As shown, the reference voltage generation circuit 40 includes a third transistor Q3, a fourth transistor Q4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and an operational amplifier U1.

[0132] The base of the third transistor Q3 is connected to the base of the fourth transistor Q4 and the output of the operational amplifier U1. The collectors of the third transistor Q3 and the fourth transistor Q4 are connected to the power supply terminal VCC of the reference voltage generation circuit. The emitter of the third transistor Q3 is connected to one end of the third resistor R3 and the non-inverting input of the operational amplifier U1. The emitter of the fourth transistor Q4 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to one end of the second resistor R2 and the inverting input of the operational amplifier U1. The other ends of the third resistor R3 and the other ends of the second resistor R2 are connected to one end of the fourth resistor R4. The fourth resistor R4 is grounded to AGND.

[0133] If the voltage VP at the non-inverting input terminal of operational amplifier U1 is equal to the voltage VN at its inverting input terminal, then the current IR1 flowing through the first resistor R1 can be calculated using the following formula:

[0134] (2)

[0135] Where IR1 is the current in the first resistor R1, This is the base-emitter voltage difference of the third transistor Q3. This is the base-emitter voltage difference of the fourth transistor Q4.

[0136] The current flowing through the first resistor R1, the second resistor R2, and the third resistor R3 is equal, all being IR1. Therefore, the current flowing through the fourth resistor R4 is 2*IR1. Thus, the reference voltage VBG is:

[0137] (3)

[0138] Where VBG is the reference voltage VBG, r4 is the resistance value of the fourth resistor R4, and r3 is the resistance value of the third resistor R3. This is the base-emitter voltage difference of the third transistor Q3.

[0139] By designing the resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3, different reference voltages VBG can be obtained. If the resistance value of the first resistor R1 is 2.7MΩ, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3 (18MΩ), the resistance value of the fourth resistor R4 is 10MΩ, and the bias current is 5nA, then the reference voltage VBG can be obtained as 1.204V through formulas (2) and (3).

[0140] In this embodiment, the third transistor Q3 and the fourth transistor Q4 are NPN transistors, and they are directly connected to the first or second power supply voltage, i.e., directly connected to the power supply VCC terminal, away from ground AGND. This effectively isolates the interference of chip substrate noise and provides good immunity to ground AGND interference. Furthermore, since the collectors of the third transistor Q3 and the fourth transistor Q4 are directly connected to the power supply VCC terminal, at high temperatures, the nA-level leakage current from the collector to the substrate will not cause a large shift in the reference voltage VBG, thus improving the temperature drift characteristics of the bandgap reference. This embodiment uses a linear voltage regulator circuit 20 to provide a clean VCC power supply to the reference voltage generation circuit 40, greatly reducing the impact of noise from the input power supply VINVIN on the reference voltage VBG.

[0141] If the bias circuit 10 provides a bias current of 5nA to the operational amplifier U1, then the operational amplifier U1 has a current consumption of only 35nA, and the current flowing through the first resistor R1, IR1, is only 20nA, so the current consumption is also relatively small.

[0142] Please see Figure 12 , Figure 12 This is a schematic diagram of a DC simulation curve of a reference voltage temperature drift provided in an embodiment of this application, as shown below. Figure 12 As shown, the horizontal axis represents temperature, and the vertical axis represents the reference voltage. The simulation is based on a bias current of 5nA. Curve L1 in the figure is the DC simulation curve of the reference voltage temperature drift. The coordinates of point F are (-24.8C, 1.20477V), and the coordinates of point G are (127.2C, 1.204003V). The difference dx between the horizontal coordinates of point G and point F is approximately 152.0C, and the difference dy between the vertical coordinates is approximately 766.685796uV. Therefore, dy / dx is 5.0439855uV / C. That is, within the temperature range of [-25C, 125C], the maximum change of the reference voltage is approximately 0.76mV, and the temperature drift is approximately 4.22ppm, which is relatively small.

[0143] Please see Figure 13 , Figure 13 This is a schematic diagram of a reference voltage rejection ratio AC simulation curve provided in an embodiment of this application, as shown below. Figure 13 As shown, the horizontal axis represents the frequency of the input power supply in Hz, and the vertical axis represents the power supply rejection ratio (PSRR) in dB. Curve L2 in the figure is the AC simulation curve of the reference voltage rejection ratio. The coordinates of point M1 are (6.91831kHz, -42.6049dB), and the coordinates of point M2 are (1.02678kHz, -69.971dB). A power supply rejection effect of more than 42.6dB can be achieved across the entire frequency range, and the DC power supply rejection ratio is greater than 80dB. The reference voltage generation circuit has a strong ability to suppress changes in the input power supply voltage, and the output voltage is relatively stable, which enhances the anti-interference capability of the reference voltage generation circuit.

[0144] In summary, this bandgap reference circuit uses a linear voltage regulator circuit to power the reference voltage generation circuit. The stable reference voltage makes the second supply voltage generated by the linear voltage regulator circuit more stable, which in turn makes the reference voltage generated by the reference voltage generation circuit more stable until the entire circuit reaches a steady state. Since the supply voltage of the reference voltage generation circuit is stable, the fluctuation of the reference voltage it generates is small, the anti-interference ability is stronger, and the stability is higher.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A bandgap reference circuit, characterized in that, The bandgap reference circuit includes a bias circuit, a linear voltage regulator circuit, a state detection circuit, and a reference voltage generation circuit. The bias circuit is configured to generate a bias current based on the input power supply; The state detection circuit is electrically connected to the linear voltage regulator circuit. The state detection circuit is configured to detect the start-up state of the reference voltage generation circuit, and generate a first detection signal when the reference voltage generation circuit is not started, and generate a second detection signal after the reference voltage generation circuit is started. The linear voltage regulator circuit is electrically connected to the state detection circuit and the reference voltage generation circuit, respectively. The linear voltage regulator circuit is configured to generate a first supply voltage in response to the input of the bias current and the first detection signal. The reference voltage generation circuit is configured to generate a reference voltage in response to the input of the first supply voltage, so that the linear regulator circuit stops generating the first supply voltage and generates a second supply voltage in response to the input of the bias current, the second detection signal and the reference voltage, thereby causing the reference voltage generation circuit to continuously generate the reference voltage in response to the input of the second supply voltage. The bandgap reference circuit further includes a first startup circuit, which is electrically connected to the output terminal of the reference voltage generation circuit and the state detection circuit, respectively. The first startup circuit is configured to generate a startup current to start the reference voltage generation circuit in response to the input of the bias current, and is also configured to stop generating the startup current in response to the input of the reference voltage.

2. The bandgap reference circuit according to claim 1, characterized in that, The linear voltage regulator circuit includes a first voltage regulator unit and a second voltage regulator unit; The first voltage regulator unit is electrically connected to the state detection circuit, and the power supply terminals of the first voltage regulator unit, the second voltage regulator unit, and the reference voltage generation circuit are all connected to the first node. The first voltage regulator unit is configured to generate the first supply voltage at the first node in response to the input of the bias current and the first detection signal, and is configured to stop generating the first supply voltage in response to the input of the bias current and the second detection signal. The second voltage regulator unit is also electrically connected to the output of the reference voltage generation circuit. The second voltage regulator unit is configured to generate the second supply voltage at the first node in response to the input of the reference voltage and the bias current.

3. The bandgap reference circuit according to claim 2, characterized in that, The first voltage regulator unit includes a first voltage generation unit, a first voltage follower unit, and a first switching unit; The first voltage generation unit is electrically connected to the input terminal of the first voltage follower unit, and the first voltage generation unit is configured to generate a first voltage in response to the input of the bias current; The output terminal of the first voltage follower unit is electrically connected to the first terminal of the first switching unit, and the first voltage follower unit is configured to generate the first supply voltage based on the first voltage; The second terminal of the first switching unit is electrically connected to the first node, and the control terminal of the first switching unit is electrically connected to the state detection circuit. The first switching unit is configured to respond to the input of the first detection signal by connecting the output terminal of the first voltage follower unit to the first node to output the first supply voltage at the first node. The first switching unit is also configured to respond to the input of the second detection signal by disconnecting the output terminal of the first voltage follower unit from the first node.

4. The bandgap reference circuit according to claim 3, characterized in that, The first voltage generation unit includes a first MOSFET and a second MOSFET, the first voltage follower unit includes a third MOSFET, and the first switching unit includes a fourth MOSFET; The drain, gate, and gate of the first MOSFET are all used to connect to the bias current. The source of the first MOSFET is connected to the drain and gate of the second MOSFET, respectively. The source of the second MOSFET is grounded. The drain of the third MOSFET is used to connect to the input power supply. The source of the third MOSFET is connected to the source of the fourth MOSFET. The drain of the fourth MOSFET is connected to the first node. The gate of the fourth MOSFET is electrically connected to the state detection circuit.

5. The bandgap reference circuit according to claim 3, characterized in that, The second voltage regulator unit includes a second voltage generation unit and a second voltage follower unit; The second voltage generation unit is electrically connected to the output terminal of the reference voltage generation circuit and the input terminal of the second voltage follower unit, respectively. The second voltage generation unit is configured to generate a second voltage in response to the input of the bias current and the reference voltage. The output of the second voltage follower unit is electrically connected to the first node, and the second voltage follower unit is configured to generate the second supply voltage based on the second voltage.

6. The bandgap reference circuit according to claim 5, characterized in that, The second voltage follower unit includes a fifth MOSFET, and the second voltage generation unit includes a sixth MOSFET; The source of the fifth MOS transistor is electrically connected to the first node, the drain of the fifth MOS transistor is used to connect to the input power supply, the gate of the fifth MOS transistor and the source of the sixth MOS transistor are both used to connect to the bias current, the gate of the sixth MOS transistor is electrically connected to the output terminal of the reference voltage generation circuit, and the drain of the sixth MOS transistor is grounded.

7. The bandgap reference circuit according to claim 1, characterized in that, The state detection circuit includes a first mirror unit, a second mirror unit, and a first inverter; The first mirror unit, the second mirror unit, and the input terminal of the first inverter are all connected to the third node, and the output terminal of the first inverter is electrically connected to the linear voltage regulator circuit. The first mirror unit is configured to mirror the startup current to raise the voltage of the third node, thereby causing the first inverter to output the first detection signal; The second mirror unit is configured to mirror the bias current to pull the voltage of the third node low, thereby causing the first inverter to output the second detection signal.

8. The bandgap reference circuit according to claim 7, characterized in that, The first mirror unit includes a seventh MOSFET and an eighth MOSFET, and the second mirror unit includes a first transistor; The drain of the seventh MOS transistor is connected to the gate of the seventh MOS transistor, the gate of the eighth MOS transistor, and the first startup circuit. The sources of the seventh MOS transistor and the eighth MOS transistor are both used to connect to the input power supply. The drain of the eighth MOS transistor, the collector of the first transistor, and the input terminal of the first inverter are all connected to the third node. The base of the first transistor is electrically connected to the first startup circuit, and the emitter of the first transistor is grounded.

9. The bandgap reference circuit according to claim 7, characterized in that, The first startup circuit includes a ninth MOSFET, a tenth MOSFET, and a second transistor; The drain, gate, and gate of the ninth MOS transistor are all connected to the fourth node and are used to receive the bias current. The source of the ninth MOS transistor is connected to the collector, base, and second mirror unit of the second transistor, respectively. The emitter of the second transistor is grounded. The drain of the tenth MOS transistor is connected to the first mirror unit. The emitter of the tenth MOS transistor is connected to the output terminal of the reference voltage generation circuit.

10. The bandgap reference circuit according to claim 1, characterized in that, The bandgap reference circuit also includes a second startup circuit; The second startup circuit is electrically connected to the enable terminals of the bias circuit and the reference voltage generation circuit, respectively. The second startup circuit is configured to send a startup signal to the bias circuit to start the bias circuit in response to the input of the input power supply, and is also configured to stop sending the startup signal in response to the input of the bias current, and generate an enable signal to drive the reference voltage generation circuit to work.

11. The bandgap reference circuit according to claim 10, characterized in that, The second startup circuit includes an energy storage unit, a third mirror unit, a second switching unit, and a second inverter; The energy storage unit, the third mirror unit, the control terminal of the second switching unit, and the input terminal of the second inverter are all connected to the fifth node. The first terminal of the second switching unit is connected to the control terminal of the bias circuit, and the second terminal of the second switching unit is grounded. The energy storage unit is configured to store energy in the input power supply to raise the voltage of the fifth node, thereby enabling the second switching unit to connect the control terminal of the bias circuit to ground, so as to send the start signal to the control terminal of the bias circuit. The third mirroring unit is configured to mirror the bias current to pull the voltage of the fifth node low, thereby causing the second switching unit to disconnect the electrical connection between the control terminal of the bias circuit and ground, stop sending the start signal, and cause the second inverter to output the enable signal.

12. The bandgap reference circuit according to claim 11, characterized in that, The energy storage unit includes an energy storage capacitor, the third mirror unit includes an eleventh MOSFET, and the second switching unit includes a twelfth MOSFET. One end of the energy storage capacitor is used to connect to the input power supply, and the other end of the energy storage capacitor is connected to the fifth node together with the drain of the eleventh MOS transistor and the gate of the twelfth MOS transistor. The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are grounded together. The gate of the eleventh MOS transistor is connected to the bias circuit, and the drain of the twelfth MOS transistor is connected to the control terminal of the bias circuit.

13. The bandgap reference circuit according to any one of claims 1-12, characterized in that, The reference voltage generation circuit includes a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and an operational amplifier; The base of the third transistor is connected to the base of the fourth transistor and the output terminal of the operational amplifier. The collectors of the third and fourth transistors are used to connect to the first or second supply voltage. The emitter of the third transistor is connected to one end of the third resistor and the non-inverting input terminal of the operational amplifier. The emitter of the fourth transistor is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the second resistor and the inverting input terminal of the operational amplifier. The other ends of the third and second resistors are connected to one end of the fourth resistor, which is grounded.

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