Flash memory controller and flash memory controller control method

Abstract

The present invention provides a flash memory controller and a control method for the flash memory controller. After the flash memory controller completes power-on reset, a host-side controller sends register configuration information and instructions to the flash memory controller and writes the instructions into an instruction cache. The instructions are read from the instruction cache and decoded according to the instruction format to obtain an opcode, an instruction weight, and a command index corresponding to the instruction. A weighted arbiter arbitrates and outputs an instruction index from instruction queues in each state according to the weight, and stores the instruction index in a command index buffer within the flash memory controller. The instruction index is read from the command index buffer and, based on the command index in the instruction corresponding to the instruction index, the command word is read. The present invention, through a customized instruction format, can implement weighted scheduling of different operations of the flash memory controller. The response order of each instruction of the arbitrator can be dynamically adjusted by changing the weight value in the instruction code, thereby achieving rapid response and dynamic scheduling of high-priority instructions.

Description

Technical Field

[0001] The present invention relates to the field of flash memory controllers, and more particularly, to a flash memory controller and a control method thereof. Background Art

[0002] Flash memory-based solid-state memory has the advantages of large capacity, low power consumption, strong vibration resistance, and fast read and write speeds, and has been widely used in various storage systems or application processing systems.

[0003] The organizational structure of flash memory chips is hierarchical, including flash memory particles (Package), chips (Chip), wafers (Die), groups (Plane), blocks (Block) and pages (Page) from top to bottom. The concurrency level and read and write latency of different levels vary. The read and write performance depends on the flash memory controller architecture and the scheduling strategy adopted.

[0004] A flash memory controller typically includes control registers, data read and write buffers, and a logic control module. The host-side controller completes operation issuance by issuing instructions or command word indexes to the flash memory controller. However, the delay and priority of flash memory particles in executing different operations vary. Conventional flash memory controllers cannot specify the response order of each instruction, making it difficult to achieve rapid response and dynamic scheduling of high-priority instructions. Existing flash memory-based storage systems use a multi-channel design. As the number of channels increases, the task scheduling overhead of the main controller increases, the transmission efficiency of a single channel decreases, and the delay increases, resulting in a decrease in service quality. Different models of flash memory particles have different time overheads when executing different operations. The software running in the host-side controller has difficulty implementing more complex wear-leveling scheduling algorithms and multi-channel concurrency control. The flash memory controller needs to provide the time overhead and operating status of the flash memory particles when executing different operations. During actual operation, the host-side controller will continuously migrate and aggregate valid data and initiate erase commands to release idle blocks in the flash memory particles to cope with the host's continuous write requests. Since flash erase and write commands are high-latency requests, much higher than read commands, once an erase operation is initiated at a certain moment, the corresponding Die cannot respond to low-latency read commands until the erase or write operation is completed, resulting in a large request delay for the host. Summary of the Invention

[0005] The present invention aims to solve the technical problems existing in the prior art and provides a flash memory controller and a control method for the flash memory controller, which can overcome the problem that it is difficult to dynamically adjust the response sequence of different operations in the flash memory controller when scheduling the flash memory controller through software.

[0006] According to a first aspect of the present invention, there is provided a flash memory controller comprising an instruction cache, a register, an instruction fetch and decode module, a weighted arbiter, a command request and transmit module, and a scheduler module;

[0007] After the flash memory controller completes power-on reset, the host-side controller sends register configuration information and instructions to the flash memory controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash memory controller;

[0008] The instruction fetch and decoding module of the flash memory controller reads an instruction from the instruction cache, and decodes an opcode, an instruction weight, and a command index corresponding to the instruction from the instruction according to the instruction format;

[0009] The weighted arbiter in the flash memory controller arbitrates and outputs instruction indexes from the instruction queues in each state according to the weights, and stores the instruction indexes in a command index buffer inside the flash memory controller;

[0010] The command request and transmission module reads the instruction index from the command index buffer, and completes reading of the command word according to the command index in the instruction corresponding to the instruction index;

[0011] The scheduler module in the flash memory controller completes the control of the write operation state machine, the read operation state machine and the erase operation state machine, thereby realizing the scheduling control of the flash memory particles.

[0012] According to a second aspect of the present invention, a control method for a flash memory controller is provided. The flash memory controller includes an instruction cache, a register, an instruction fetch and decoding module, a weighted arbiter, a command request and transmission module, and a scheduler module. The control method includes:

[0013] After the flash memory controller completes power-on reset, the host-side controller sends register configuration information and instructions to the flash memory controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash memory controller;

[0014] Reading instructions from the instruction cache through the instruction fetch and decoding module, and decoding the operation code, instruction weight and command index corresponding to the instruction from the instruction according to the instruction format;

[0015] Outputting an instruction index from the instruction queues in each state by arbitration according to the instruction weights through the weighted arbitrator, and storing the instruction index in a command index buffer inside the flash memory controller;

[0016] Reading the instruction index from the command index buffer through the command request and transmission module, and completing the reading of the command word according to the command index in the instruction corresponding to the instruction index;

[0017] The scheduler module is used to control the write operation state machine, the read operation state machine and the erase operation state machine, thereby realizing the scheduling control of the flash memory particles.

[0018] The present invention provides a flash memory controller and a control method for a flash memory controller. After the flash memory controller completes a power-on reset, a host-side controller sends register configuration information and instructions to the flash memory controller and writes the instructions into an instruction cache. The instructions are read from the instruction cache and decoded according to the instruction format to obtain an opcode, instruction weight, and a command index corresponding to the instruction. A weighted arbiter arbitrates and outputs an instruction index from instruction queues in each state according to the weight, and stores the instruction index in a command index buffer within the flash memory controller. The instruction index is read from the command index buffer and, based on the command index in the instruction corresponding to the instruction index, the command word is read. The present invention, through a customized instruction format, can implement weighted scheduling of different operations of the flash memory controller. The response order of each instruction of the arbitrator can be dynamically adjusted by changing the weight value in the instruction code, thereby achieving rapid response and dynamic scheduling of high-priority instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the instruction format of the flash memory controller of the present invention;

[0020] Figure 2 A schematic structural diagram of a flash memory controller provided by the present invention;

[0021] Figure 3 Schematic diagram of the structure of the weighted arbitrator;

[0022] Figure 4 This is the workflow diagram of the weighted arbitrator;

[0023] Figure 5 It is a state transition diagram of the command request and the read DMA request state machine of the transmitter module;

[0024] Figure 6 This is the workflow diagram of the scheduler module;

[0025] Figure 7 This is a state transition diagram of the write operation state machine;

[0026] Figure 8 It is a state transition diagram of the erase operation state machine;

[0027] Figure 9 A state transition diagram of the recovery operation state machine;

[0028] Figure 10 This is a flow chart of a control method for a flash memory controller provided by the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0030] Based on the defects of the prior art, the present invention proposes a flash memory controller designed for a custom instruction format of the flash memory controller. According to the weight information in the instruction, the scheduler and weighted arbiter can dynamically adjust the transmission and response order of different operations in the flash memory controller, thereby achieving a rapid response to high-priority instructions. Implementing the priority scheduling of different operations in a single channel through hardware can effectively reduce the software's overhead when performing task scheduling, and reduce the response time of task suspension and resumption operations in a single channel, improve the transmission efficiency of a single channel, and reduce latency. The flash memory controller has a built-in performance monitoring module and status register, which can count and record the time overhead and operating status of flash memory particles when performing different operations, helping the software to implement more complex wear-leveling scheduling and multi-channel concurrency control; the scheduler provides erase suspension, write suspension and suspension recovery support. By setting the task stack, task recovery logic and data cache, the software can achieve rapid recovery after erase suspension and write suspension operations without resending commands and data.

[0031] Before introducing the flash memory controller provided by the present invention, the instruction format customized by the present invention is described. Figure 1 This is an instruction format for a flash memory controller proposed in the present invention. Instructions can be divided into two categories: 16-bit standard instructions and 32-bit extended instructions. The upper 16 bits of standard and extended instructions have the same format. The highest bit of the opcode is a flag indicating whether the instruction is an extended instruction. When the highest bit is 1, it indicates that the current instruction is an extended instruction; when the highest bit is 0, it indicates that the current instruction is a standard instruction.

[0032] Depending on the opcode, standard instructions for flash memory controllers can be further subdivided into read, erase, write, erase suspend, write suspend, write suspend resume, erase suspend resume, and channel status read. Extended instructions for flash memory controllers can be further subdivided into copy, copy program, and copy erase. The "channel" in the instruction specifies the channel number for the current operation and can be used for multi-channel expansion of the flash memory controller. The "weight" in the instruction specifies the scheduling priority of the operation corresponding to the current instruction, with level 0 being the highest priority, level 1 being just lower than level 0, level 2 being just higher than level 3, and level 3 being the lowest priority. The "command index" in the instruction specifies the offset of the starting address of the command word in the DDR corresponding to the current instruction relative to the base address of the command buffer of this channel.

[0033] The flash memory controller architecture proposed by the present invention is as follows Figure 2 As shown in the figure, the flash memory controller consists of an instruction cache, registers, an instruction fetch and decode module, a scheduler module, a status write-back module, a command request and transmit module, a read / write DMA module, a read / write data channel, a data stream multiplexer, and a flash memory interface module. Figure 2 The host-side controller can use a processor core based on the RISC-V architecture or the ARM architecture, and perform read and write data transmission, instruction distribution, and register configuration on the flash memory controller through the AXI bus. The page mapping area of ​​DDR stores the page mapping table used for flash memory page mapping management, the data area stores data read from the flash memory particles or data to be written to the flash memory particles, the control firmware area stores the wear leveling control algorithm used to improve the service life of the flash memory particles, the storage protocol stack stores the storage protocol used for the host-side controller to interact with the host CPU file system, and the command buffer stores the command words to be transmitted to the flash memory controller. The flash memory interface module is used to transmit the microcode issued by the erase operation state machine, read operation state machine, write operation state machine, and erase / write suspend recovery operation state machine in the scheduler to the flash memory particles, and complete the data transmission between the data stream multiplexer and the flash memory particles.

[0034] Figure 2 The working principle of the flash memory controller is as follows: after the flash memory controller completes power-on reset, the host side controller sends the configuration information of the control register, the initialization information of the status register, and the configuration information of the parameter register to the flash memory controller through the AXI-Lite interface with a 64-bit data width. The host side controller sends instructions to the flash memory controller through the AXI-Lite interface with a 64-bit data width and writes them into the instruction cache in the flash memory controller. The instruction fetch and decoding module of the flash memory controller reads the instructions from the instruction cache and reads them according to the instruction cache. Figure 1The instruction format shown decodes the opcode, instruction weight and command index corresponding to the instruction. The weighted arbiter in the flash memory controller arbitrates and outputs the instruction index number from the instruction queue of each state according to the instruction weight, and the instruction index number is stored in the command index buffer inside the flash memory controller. The command request and transmission module completes the reading of the command word according to the command word index, and completes the control of the write operation state machine, read operation state machine and erase operation state machine through the scheduler module, thereby realizing the scheduling control of the flash memory particles. Among them, the write cache of the write channel includes write cache 0 and write cache 1. The write cache has two states, dirty and clean, which are used to identify whether the data in write cache 0 or write cache 1 has been overwritten by other write operations since the last write operation. The write operation state machine and the write suspend recovery operation state machine are responsible for generating the selection end signal of the write cache data selector.

[0035] The following is a detailed description of each hardware module in the flash memory controller.

[0036] A. Instruction cache and registers:

[0037] The instruction cache of the flash memory controller proposed in the present invention is implemented based on a synchronous first-in, first-out (FIFO) queue. The data bit width of the instruction cache is 64 bits, the queue depth is 16, and the memory is implemented using a dual-port RAM with independent write and read ports. It can accommodate 64 standard instructions or 32 extended instructions at the same time.

[0038] The registers of the flash memory controller proposed in the present invention include a control register, a status register and a parameter register. The bit width of all registers is 64 bits, which is consistent with the bus data bit width.

[0039] The control register stores the configuration information of the flash memory controller, which is used to specify whether to enable the ECC check function and whether to enable the hardware scrambling and descrambling function.

[0040] The status register stores instruction status information for the flash memory controller and includes three 64-bit registers. The first register uses a 64-bit one-hot encoding, corresponding to the 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready state of the current instruction. The second register of the status register uses a 64-bit one-hot encoding, corresponding to the 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready type of the instruction. The third register of the status register uses a 64-bit one-hot encoding, corresponding to the number of clock cycles consumed by the last command executed by the flash memory controller, and is used to evaluate the time overhead of the last operation. The instruction status of the flash memory controller of the present invention includes three states: ready state (the same bit field of the first and second registers is both 1), not ready state (the first register is 0 and the second register is 0), suspended state (the first register is 1 and the second register is 0), and abnormal state (the first register is 0 and the second register is 1). When a given operation is completed, the state machine in the scheduler will initiate an instruction ready state write back operation and update the status register; when a given operation (erase or program operation) is suspended, the state machine in the scheduler will initiate an instruction suspended state write back operation and update the status register; when a given operation fails to recover or the operation times out, the state machine in the scheduler will initiate an instruction abnormal state write back operation and update the status register; when a given operation is successfully transmitted from the flash memory command request and transmission module, the corresponding operation state machine in the scheduler will reset the instruction state to non-ready state during the initialization operation of the state machine.

[0041] The parameter register is used to specify the read and write timing parameters of the flash memory particles, which are used to specify the number of clock cycles occupied by the address part of the erase operation command sent by the flash memory controller to the flash memory particles, the number of clock cycles occupied by the address part of the read and write operation commands sent by the flash memory controller to the flash memory particles, the number of clock cycles between the end address of the write operation and the first byte of the write data, and the input delay of the DQ and DQS signals of the flash memory interface module.

[0042] B. Instruction decoding and weighted arbiter:

[0043] The instruction fetch and decoding module of the flash memory controller proposed in the present invention has an instruction fetch width of 64 bits (8 bytes), corresponding to 4 standard instructions or 2 extended instructions. Figure 1 The flash controller instruction format shown in the figure, the decoding circuit extracts the opcode and weight in the instruction and writes the extracted instruction index into the Figure 3 The instruction queue in the weighted arbiter consists of a level 0 queue, a level 1 queue, and a level 2 queue, all of which are implemented through synchronous FIFO circuits. Among them, the level 0 queue has the highest priority, the level 1 queue has the second highest priority, and the level 2 queue has the lowest priority.

[0044] like Figure 3 As shown, the weighted arbiter of the flash memory controller proposed in the present invention is composed of a fixed priority arbiter and a round-robin priority arbiter. The request source of the weighted arbiter comes from three instruction queues with different weights inside the arbiter, and an arbitration request is initiated to the arbiter only when the instruction queue is not an empty queue. If the instruction queue with a weight of 0 is empty, the instruction queue with a weight of 1 or a weight of 2 will be reallocated according to the result of the previous arbitration and applied to the next arbitration. The response signal generated by the arbitrator will serve as the selection end signal of the secondary data selection path, and select one from the three command word index queues to be written into the command index buffer queue. The advantage of this method is that for operations such as erase suspend, write suspend and suspend resume, the host-side controller can dynamically adjust the response order of each instruction of the arbitrator by changing the weight value in the instruction code, thereby achieving rapid response and dynamic scheduling of high-priority instructions.

[0045] The working process of the weighted arbiter for flash memory controller proposed by the present invention is as follows: Figure 4 As shown, it mainly includes the following steps:

[0046] Step S101: According to the instruction weight decoded by the instruction decoding circuit, the instruction index is written into the instruction queue of the corresponding weight; if the decoded weight is 0, the instruction index is written into the level 0 queue; if the decoded weight is 1, the instruction index is written into the level 1 queue; if the decoded weight is 2, the instruction index is written into the level 2 queue.

[0047] Step S102: Determine the status of the Level 0, Level 1, and Level 2 instruction queues, and use the status signals of the instruction queues with different weights as source requests to the arbitrator. Whether each instruction queue in the arbitrator is empty reflects whether the instruction of the current priority has been issued. If a high-priority instruction has been issued, the Level 0 instruction queue should be non-empty, so the non-empty signal of the instruction queue can be used as the source request to the arbitrator.

[0048] Step S103: If the level 0 instruction queue is in a non-empty state, the non-empty signal of the level 0 instruction queue is used as the source request of the arbitrator to initiate an arbitration request to the fixed priority arbitrator, and at the same time, the instruction index in the level 0 instruction queue is selected and read, and the instruction index is written into the command index buffer.

[0049] Step S104: If the level 0 instruction queue is in an empty state and the level 1 instruction queue and the level 2 instruction queue are in a non-empty state, the non-empty signals of the level 1 instruction queue and the level 2 instruction queue are used as the source end request of the arbitrator to initiate an arbitration request to the round-robin priority arbitrator; according to the response result of the round-robin priority arbitrator, the command word index to be written into the command index buffer is selected from the output data of the level 1 queue and the level 2 queue.

[0050] C. Command request and transmission module:

[0051] The command request and transmission module of the flash memory controller proposed in the present invention uses the instruction index read from the command index buffer as the command word offset address CMDW_OFFSET_ADDR of the DMA controller, and reads the command word base address CMDW_BASE_ADDR of the DMA controller from the control register within the flash memory controller. The command word base address and the command word offset address are concatenated to generate a 32-bit command word read address CMDW_RD_ADDR. The three parts of CMDW_RD_ADDR are concatenated, i.e., CMDW_RD_ADDR = {CMDW_BASE_ADDR[31:10], CMDW_OFFSET_ADDR, 4'b0000}. CMDW_BASE_ADDR[31:12] are the upper 22 bits of the command word base address configured in the control register, CMDW_OFFSET_ADDR is the 6-bit command word index, and 4'b0000 is four zero bits to achieve 16-byte command word alignment.

[0052] After obtaining the command word read address CMDW_RD_ADDR, the command request and transmission module will initiate a read command word arbitration request to the read-write DMA controller inside the flash memory controller. Since the data reading process of the command word read and write operations both need to occupy the read channel of the read-write DMA, the read command word request from the command request and transmission module and the read data request initiated by the write operation state machine need to be further arbitrated. The read-write DMA module of the flash memory controller architecture proposed in the present invention takes the instruction weight into consideration when arbitrating the read command word request and the read data request. The read-write arbitrator on the read-write DMA side will give priority to requesting the command word corresponding to the instruction with a priority level of 0. The command word read request corresponding to the instruction with a priority level of 1 or 2 and the data request to read the DDR initiated by the write operation state machine will be arbitrated through the polling state machine.

[0053] The command request and transmission module includes a command word cache with a depth of 4 and a data bit width of 128 bits, which is used to cache the command words obtained by the read and write DMA from the DDR, and a command word index cache with a depth of 4 and a data bit width of 8 bits, which is used to cache the command word index of the initiated DMA read request. The command word cache and command word index cache in the command request and transmission module are implemented using a synchronous FIFO circuit.

[0054] The command request and the read DMA request state machine of the transmitter module are as follows: Figure 5As shown, in the state machine, cmdw_req is the read DMA request signal, indicating that the command index buffer queue is not empty. rdma_cmd_ack is the read DMA arbitration response signal, and rdma_req_ack is the read DMA request response signal. The corresponding state transition process is as follows: After initialization, the state is in the IDLE state, indicating that the current command request and transmitter module have not received any command word requests. When the command index buffer queue is not empty, the read DMA request signal cmdw_req is 1, and the state machine state transitions from the IDLE state to the ARB state, indicating that the current command request and transmitter module have received a command word request and begin initiating a read DMA request to the read-write arbitrator. When the read-write arbitrator responds to the command request and the read command word request initiated by the transmitter module, the read DMA arbitration response signal rdma_cmd_ack is 1, and the state machine transitions from the ARB state to the REQ state, preparing to receive the command word transmitted by the DMA controller to the flash memory controller. The flash memory controller proposed in this invention uses an 8-byte command word and a 128-bit AXI4 bus data width. Therefore, the AXI4 transfer length for command requests and the transmitter module's read DMA request is set to 1. When the read channel of the read / write DMA receives a command from the DDR, the read DMA request response signal, rdma_req_ack, is 1, and the state machine transitions from the REQ state to the IDLE state.

[0055] The command request and transmission module uses the method of sequentially transmitting command words. When the command word index cache in the command request and transmission module is not an empty queue, the queue non-empty signal will serve as the command activation signal cmd_active for the erase operation state machine, read operation state machine, write operation state machine and erase / write suspend operation state machine in the scheduler.

[0056] D. Scheduler module:

[0057] The scheduler module of the flash memory controller proposed in the present invention includes not only an erase operation state machine, a read operation state machine, a write operation state machine, and an erase / write suspend operation state machine for completing basic flash memory read, write, and erase operations, but also a task stack for recording the current suspended task information, task recovery logic, and a performance monitoring module.

[0058] The scheduler module workflow of the flash memory controller proposed by the present invention is as follows: Figure 6 As shown:

[0059] Step S201: When the command request and transmission module initiates an operation request for an erase operation, a read operation, or a write operation, the erase operation state machine, the read operation state machine, or the write operation state machine exits the idle state and completes the corresponding operation according to the state machine workflow below;

[0060] Step S202: When an erase suspend or write suspend operation occurs during a write operation or an erase operation, the scheduler module writes the value of the write data counter, the command word index corresponding to the current operation, and the command word into the task stack;

[0061] Step S203: When a state transition occurs in the state machine of any operation, the scheduler module synchronizes the state of the current operation to the bit field of the status register corresponding to the command word index in the flash memory controller;

[0062] Step S204: When the state machine of any operation returns to the idle state, the scheduler module synchronizes the current operation time overhead counted by the performance monitoring module to the status register in the flash memory controller.

[0063] Specifically, the scheduler module for the flash memory controller proposed in the present invention supports both write operation suspension and erase operation suspension. Figure 7 As shown in the figure, cmd_active of the write operation state machine is a command activation signal, indicating that the queue of the command request and command word index cache of the transmitter module is not empty. Use_cmd0, use_cmd1, use_cmd2, use_cmd3, and use_cmd4 of the write operation state machine are ONFI standard commands at different stages of the write operation, respectively. The phy_ack signal of the write operation state machine is a reply signal indicating that the flash memory interface module has completed a single command or a single data transmission to the flash memory chip. The phy_ack_final signal of the write operation state machine is a reply signal indicating that the flash memory interface module has completed the transmission of the write operation address to the flash memory chip. The cnt_done signal of the write operation state machine is a flag signal indicating that the count value of the write operation data has reached the write data amount. The do_suspend signal of the write operation state machine indicates that a write operation suspend command has been received. The done_suspend signal of the write operation state machine is a suspend response signal received by the flash memory interface module from the flash memory chip, indicating that the suspension processing of the current write operation has been completed.

[0064] like Figure 7As shown in FIG, the state transition and working process of the write operation state machine are as follows: after initialization, the state is in the IDLE state, indicating that there is no write operation request at present; when the command index buffer queue is not an empty queue and the command word corresponds to a write operation, cmd_active is 1, and according to the difference of use_cmd0, use_cmd1, and use_cmd2, the state of the state machine is transferred from the IDLE state to one of the states of CMD0, CMD1, or CMD2, indicating that there is a write operation request at present and the write operation command word has been stored in the command word cache by the DMA controller, and the parsing of the command word has been completed; after the ONFI standard command in the command word is transmitted to the flash memory particle through the flash memory interface module, the write operation state machine waits for the phy_ack signal from the flash memory interface module. When phy_ When ack is 1, the write state machine transfers from the CMD2 state to the ADDR state, and transmits the write operation address in the command word to the flash memory particle through the flash memory interface module; when phy_ack_final is 1, it indicates that the flash memory interface module has transmitted the address to the flash memory particle through the ONFI interface, and the write state machine transfers from the ADDR state to the WAIT state. The data path control signal of the data stream multiplexer will be turned on, and the write data corresponding to the write operation will be transferred to the write cache by DMA according to the dirty state of the write cache; if both write caches are dirty, any write cache will be marked as clean; if only one write cache is dirty, the write cache in the clean state will be used; if both write caches are clean, the data will be written to any write cache;

[0065] When no write operation pending request is initiated and the write data is completely written from the write cache to the flash memory particles via the flash memory interface module, the write data counting signal cnt_done inside the write operation is 1, and the state machine transfers from the WAIT state to the DIN state; depending on the difference between use_cmd3 and use_cmd4, the write operation state machine transfers from the DIN state to the CMD3 or CMD4 state, and sends the corresponding command word to the flash memory particles through the flash memory interface module; when phy_ack is 1, the write state machine transfers from the CMD3 or CMD4 state to the WAIT_ACK state; when phy_ack is 1, the write state machine transfers from the WAIT_ACK state to the IDLE state, suspends the counting of the performance monitoring module, synchronizes the time overhead to the status register in the flash memory controller, and synchronizes the ready state of the write operation to the status register in the flash memory controller;

[0066] When a write operation suspend request occurs and the write data is not completely written from the write cache to the flash memory particle via the flash memory interface module, the counter value, command word index and command word of the write data counter inside the write operation will be written to the task stack in the scheduler, the data path control signal of the data stream multiplexer will be turned off, the current write cache will be marked as dirty, and the command word and address information corresponding to the write operation suspension will be sent to the flash memory interface module, and the state machine will transfer from the WAIT state to the SUSPEND state; when the do_suspend signal is 1, the state machine will transfer from the SUSPEND state to the IDLE state, and the suspension state of the write operation will be synchronized to the status register in the flash memory controller.

[0067] The erase operation state machine is as follows Figure 8 As shown in the figure, the cmd_active signal of the state machine is a queue non-empty signal of the command request and command word index cache of the transmission module. The use_cmd0, use_cmd1, use_cmd2, and use_cmd3 of the state machine are ONFI standard commands at different stages of the erase operation respectively. The phy_ack signal of the state machine is a reply signal for the flash memory interface module to complete a single command or a single data transmission to the flash memory particle. The phy_ack_final signal of the state machine is a reply signal for the flash memory interface module to complete the transmission of the erase operation address to the flash memory particle. The do_suspend signal of the state machine indicates that the erase operation suspend command has been received. The done_suspend signal of the state machine is a suspend response signal received by the flash memory interface module from the flash memory particle, indicating that the suspension processing of the current erase operation has been completed.

[0068] like Figure 8As shown in the figure, the state transition and working process of the erase operation state machine are as follows: after initialization, the state is in the IDLE state, indicating that there is no erase operation request at present; when the command index buffer queue is not an empty queue and the command word corresponds to the erase operation, cmd_active is 1, and according to the difference of use_cmd0, use_cmd1, and use_cmd2, the state of the state machine is transferred from the IDLE state to one of the states of CMD0, CMD1, or CMD2, indicating that there is an erase operation request at present and the erase operation command word has been stored in the command word cache by the DMA controller, and the parsing of the command word has been completed; after the ONFI standard command in the command word is transmitted to the flash memory particle through the flash memory interface module, the erase operation state machine waits for the phy_ack signal from the flash memory interface module. When phy_ack is 1, the erase state machine is transferred from the CMD2 state to the ADDR state, and the erase operation address in the command word is transmitted to the flash memory particle through the flash memory interface module; when phy_ack_final is 1, it indicates that the flash memory interface module has transmitted the address through ONFI The interface transmits the data to the flash memory particles, and the erase state machine transfers from the ADDR state to the CMD3 state, and sends the corresponding command word to the flash memory particles through the flash memory interface module; when phy_ack is 1, the erase state machine transfers from the CMD3 state to the WAIT_ACK state and starts waiting for the completion of the erase operation; when no erase operation suspend request is initiated and phy_ack is 1, it indicates that the erase operation is completed normally, and the erase state machine transfers from the WAIT_ACK state to the IDLE state, suspends the counting of the performance monitoring module, synchronizes the time overhead to the status register in the flash memory controller, and synchronizes the ready state of the erase operation to the status register in the flash memory controller; when an erase operation suspend request occurs and phy_ack is 0, the command word and address information corresponding to the erase operation suspend are sent to the flash memory interface module, and the state machine transfers from the WAIT state to the SUSPEND state; when the do_suspend signal is 1, the state machine transfers from the SUSPEND state to the IDLE state, and synchronizes the suspend state of the erase operation to the status register in the flash memory controller.

[0069] The state machine for erase suspend and write suspend resume operations is as follows: Figure 9As shown, the cmd_active signal of the recovery state machine is a queue non-empty signal of the command word index cache, the is_erase and is_prg of the state machine respectively indicate that the current operation is erase recovery or write recovery; the prg_idle and ers_idle signals of the state machine indicate whether the write state machine or the erase state machine is in the idle state; the is_dirty signal of the state machine indicates whether the dirty flag set when the write cache used in the last write operation is suspended is cleared; the rdma_req_ack signal of the state machine indicates whether the data of the last write operation has been received from the DMA; the cnt_ge signal of the state machine indicates whether the data position read by the current read data DMA is greater than the data position when the last write operation was interrupted.

[0070] like Figure 9 As shown in the figure, the state transition and working process of the recovery operation state machine are as follows: after initialization, the state is in the IDLE state, indicating that there is no recovery operation request at present; when the command index buffer queue is not an empty queue and the command word corresponds to the recovery operation, cmd_active is 1, and the state machine state is transferred from the IDLE state to one of the ESR or PRG states depending on whether the instruction is erase suspend recovery or write suspend recovery; the ERS state indicates that the current operation is an erase suspend recovery operation, and the command word of the last erase operation will be found from the task stack in the scheduler according to the command word index. When ers_idle is 1, the state machine will transfer from the ESR state to the SR state. When the command word index is not found from the task stack, the state machine will transfer from the ESR state to the SR state. In the SR state, the erase state machine activation operation will be initiated according to the found command word. When is_idle is 0, the state machine will transfer from the SR state to the IDLE state, and synchronize the non-ready state of the erase operation to the status register in the flash memory controller.

[0071] The PRG state indicates that the current operation is a write suspend recovery operation. The command word of the last write operation will be found from the task stack in the scheduler according to the command word index. When prg_idle is 1, the state machine will transfer from the PRG state to the MEM state. When the command word index of the last write operation is not found from the task stack, the state machine will transfer from the PRG state to the IDLE state.

[0072] In the MEM state, the write cache used in the last write operation will be checked according to the command word found. When is_dirty is 1, it means that the data in the write cache used in the last write operation has not been overwritten, and the state machine will transfer from the MEM state to the REQ state; when prg_idle is 1, the state machine will transfer from the REQ state to the SR state, and initiate the write state machine activation operation according to the command word found, and reset the write data counter to the pause position of the last write operation read from the task stack; when is_idle is 0, the state machine will transfer from the SR state to the IDLE state, and synchronize the non-ready status of the write operation to the status register in the flash memory controller.

[0073] When is_dirty is 0, it means that the data in the write cache used by the last write operation has been overwritten, and the state machine will transfer from the MEM state to the ARB state and re-initiate the read request for the write operation data; when rdma_req_ack is 1 and the read write operation data position is greater than the data position when the last write operation was interrupted, the state machine will transfer from the ARB state to the REQ state; when prg_idle is 1, the state machine will transfer from the REQ state to the SR state, and initiate the write state machine activation operation according to the command word found, and reset the write data counter to the pause position of the last write operation read from the task stack; and synchronize the non-ready state of the write operation to the status register in the flash memory controller; when is_idle is 0, the state machine will transfer from the SR state to the IDLE state, and synchronize the non-ready state of the write operation to the status register in the flash memory controller.

[0074] See also Figure 10 , provides a control method for a flash memory controller of the present invention, the control method comprising:

[0075] After the flash memory controller completes power-on reset, the host-side controller sends register configuration information and instructions to the flash memory controller through the AXI-Lite interface, and writes the instructions into the instruction cache in the flash memory controller;

[0076] Reading instructions from the instruction cache through the instruction fetch and decoding module, and decoding the operation code, instruction weight and command index corresponding to the instruction from the instruction according to the instruction format;

[0077] Outputting an instruction index from the instruction queues in each state by arbitration according to the instruction weights through the weighted arbitrator, and storing the instruction index in a command index buffer inside the flash memory controller;

[0078] Reading the instruction index from the command index buffer through the command request and transmission module, and completing the reading of the command word according to the command index in the instruction corresponding to the instruction index;

[0079] The scheduler module is used to control the write operation state machine, the read operation state machine and the erase operation state machine, thereby realizing the scheduling control of the flash memory particles.

[0080] It is understandable that the technical features of the control method of the flash memory controller provided by the present invention can refer to the relevant technical features of the flash memory controller provided by the aforementioned embodiment. Therefore, the technical features of the control method of the flash memory controller will not be repeated.

[0081] The present invention provides a flash memory controller and a flash memory controller control method, which have the following beneficial effects:

[0082] (1) Automatically implement weighted scheduling of different operations of the flash memory controller in an instruction format for the flash memory controller. By changing the weight value in the instruction code, the response order of each instruction of the arbitrator can be dynamically adjusted to achieve fast response and dynamic scheduling of high-priority instructions.

[0083] (2) The flash memory controller architecture uses the AXI bus to interact with the host-side controller for data and instructions, and has strong compatibility. The host-side controller can be implemented using the ARM architecture or the RISC-V architecture.

[0084] (3) The flash memory controller architecture can dynamically adjust the read and write timing parameters of the flash memory particles by configuring parameter registers, which facilitates prototype verification on the FPGA platform and adapts to different board-level layout schemes.

[0085] (4) The flash memory controller has a built-in performance monitoring module and status register. The host-side controller can read the status register inside the flash memory controller through the AXI bus, and then obtain the time overhead of the flash memory controller when performing different operations, providing status information for the software to implement more complex wear leveling scheduling algorithms and multi-channel concurrent control.

[0086] (5) The flash memory controller architecture implements the priority scheduling of different operations within a single channel through hardware, which can effectively reduce the task scheduling overhead of the host-side controller and shorten the response time of task suspension and task resumption within a single channel.

[0087] (6) The flash memory controller architecture facilitates multi-channel expansion. The command word base address and read / write data base address of a single channel can be flexibly configured according to the software's storage space division method. The number of channels supported by the system can be changed by increasing or decreasing the number of flash memory controllers, depending on the control capabilities of the host-side controller and the capacity and speed requirements of the storage system.

[0088] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0089] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0091] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0093] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0094] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A flash memory controller, characterized in that: The flash memory controller includes an instruction cache, a register, an instruction fetch and decode module, a weighted arbiter, a command request and transmit module, and a scheduler module; After the flash memory controller completes power-on reset, the host-side controller sends register configuration information and multiple instructions to the flash memory controller through the AXI-Lite interface, and writes the multiple instructions into the instruction cache in the flash memory controller, each of which includes an opcode, a weight, and a command index; The instruction fetching and decoding module of the flash memory controller reads a plurality of instructions from the instruction cache, and decodes an opcode, a weight, and a command index corresponding to each instruction according to an instruction format; According to the weight of each instruction, the instruction index of each instruction is stored in an instruction queue of the corresponding priority, and the status signals of the instruction queues of different priorities are input into the weighted arbiter of the flash memory controller. The weighted arbiter arbitrates the instruction index of the instruction currently to be executed from the instruction queues of different priorities and stores the instruction index in a command index buffer within the flash memory controller; The command request and transmission module reads the instruction index from the command index buffer, and completes reading of the command word according to the command index in the instruction corresponding to the instruction index; The scheduler module in the flash memory controller completes the control of the write operation state machine, the read operation state machine and the erase operation state machine, thereby realizing the scheduling control of the flash memory particles.

2. The flash memory controller according to claim 1, wherein: The instructions for the flash memory controller are divided into 16-bit standard instructions and 32-bit extended instructions, and the format of the upper 16 bits of the standard instructions and the extended instructions are the same; the upper 16 bits of the standard instructions and the extended instructions include an operation code, a channel, a weight, and a command index; Among them, the highest bit of the opcode is a flag bit indicating whether the instruction is an extended instruction. When the highest bit is 1, it means that the current instruction is an extended instruction; when the highest bit is 0, it means that the current instruction is a standard instruction; The "channel" in the instruction specifies the channel number for the operation corresponding to the current instruction, which is used for multi-channel expansion of the flash memory controller; the "weight" in the instruction specifies the scheduling priority of the operation corresponding to the current instruction, with level 0 being the highest priority and level 3 being the lowest priority; the "command index" in the instruction specifies the offset of the starting address of the command word in the DDR corresponding to the current instruction relative to the base address of the command buffer of this channel.

3. The flash memory controller according to claim 1, wherein: The registers in the flash memory controller include a control register, a status register, and a parameter register. The bit width of all registers is 64 bits, which is consistent with the bus data bit width; The control register stores configuration information of the flash memory controller, which is used to specify whether to enable the ECC check function and whether to enable the hardware scrambling and descrambling function; The status register stores instruction status information of the flash memory controller, and the status register includes three 64-bit registers; wherein the first register adopts 64-bit one-hot encoding, corresponding to the 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready state of the current instruction; the second register adopts 64-bit one-hot encoding, corresponding to the 64 standard instructions of a single channel of the flash memory controller, and is used to specify the ready type of the current instruction; the third register adopts 64-bit one-hot encoding, corresponding to the number of clock cycles consumed by the last command executed by the flash memory controller, and is used to evaluate the time overhead of the last operation; the instruction status information of the flash memory controller is indicated according to the first register and the second register, and the instruction status information includes ready state, non-ready state, suspended state and abnormal state; The parameter register is used to specify the read and write timing parameters of the flash memory particles, and is used to specify the number of clock cycles occupied by the address part of the erase operation command sent by the flash memory controller to the flash memory particles, the number of clock cycles occupied by the address part of the read and write operation commands sent by the flash memory controller to the flash memory particles, the number of clock cycles between the end address of the write operation command sent by the flash memory controller to the flash memory particles and the first byte of the write data command sent by the flash memory controller to the flash memory particles, and the input delay of the DQ and DQS signals of the flash memory interface module.

4. The flash memory controller according to claim 1, wherein: The instruction fetch and decoding module of the flash memory controller reads an instruction from the instruction cache, and decodes an opcode, an instruction weight, and a command index corresponding to the instruction from the instruction according to the instruction format, including: The instruction fetch and decoding module reads instructions from the instruction cache, extracts opcodes and weights from the instructions according to the instruction format, and writes the instruction index into the instruction queue in the weighted arbiter based on the weights. The instruction queue in the weighted arbiter includes a level 0 queue, a level 1 queue, and a level 2 queue, wherein the level 0 queue has the highest priority, the level 1 queue has the second lowest priority, and the level 2 queue has the lowest priority.

5. The flash memory controller according to claim 4, wherein: The weighted arbiter includes a fixed priority arbiter and a round-robin priority arbiter, and stores the instruction index of each instruction into the instruction queue of the corresponding priority according to the weight of each instruction, including: According to the weight decoded by the instruction fetch and decoding module, the instruction index is written into the instruction queue of the weighted arbiter corresponding to the weight, wherein if the weight obtained by decoding is 0, the instruction index is written into the level 0 queue; if the weight obtained by decoding is 1, the instruction index is written into the level 1 queue; if the weight obtained by decoding is 2, the instruction index is written into the level 2 queue; Inputting status signals of instruction queues of different priorities into the weighted arbiter of the flash memory controller, the weighted arbiter arbitrating instruction indexes of instructions currently to be executed from the instruction queues of different priorities, and storing the instruction indexes in a command index buffer within the flash memory controller, includes: Determine the status of the level 0 instruction queue, the level 1 instruction queue, and the level 2 instruction queue, and use the status signals of the instruction queues with different weights as the source end request of the weighted arbiter. Whether each instruction queue in the weighted arbiter is empty reflects whether the instruction of the current priority is issued. If the instruction of the high priority is issued, the level 0 instruction queue is in a non-empty state. If the level 0 instruction queue is in a non-empty state, the non-empty signal of the level 0 instruction queue is used as a source request of the weighted arbitrator to initiate an arbitration request to the fixed priority arbitrator, and at the same time, select and read the instruction index in the level 0 instruction queue, and write the instruction index into the command index buffer; If the level 0 instruction queue is in an empty state and the level 1 instruction queue and the level 2 instruction queue are in a non-empty state, the non-empty signals of the level 1 instruction queue and the level 2 instruction queue are used as the source request of the weighted arbitrator to initiate an arbitration request to the round-robin priority arbitrator; according to the response result of the round-robin priority arbitrator, the instruction index to be written into the command index buffer is selected from the output data of the level 1 instruction queue and the level 2 instruction queue.

6. The flash memory controller according to claim 1, wherein: The command request and transmission module reads the instruction index from the command index buffer, and completes reading of the command word according to the command index in the instruction corresponding to the instruction index, including: After obtaining the command word read address, the command request and transmission module initiates a read command word request to the read and write DMA controller inside the flash memory controller; The read / write arbiter on the read / write DMA side arbitrates the command request and the read command word request initiated by the transmitter module and the read data request for reading the DDR initiated by the write operation state machine in the scheduler module. The read / write arbiter prioritizes command words corresponding to instructions with a priority of level 0 based on the instruction weight, and arbitrates command word read requests corresponding to instructions with a priority of level 1 or level 2 and data requests for reading the DDR initiated by the write operation state machine through the polling state machine. The command word read from the DDR is cached in the command word cache, and the command word index corresponding to the read command word request initiated to the read / write DMA controller is cached in the command word index cache, wherein the command request and transmission module includes a command word cache and a command word index cache.

7. The flash memory controller according to claim 6, wherein: The obtaining of the command word read address comprises: The command request and transmission module uses the instruction index read from the command index buffer as the command word offset address CMDW_OFFSET_ADDR of the DMA controller, and reads the command word base address CMDW_BASE_ADDR of the DMA controller in the control register inside the flash memory controller; The command word base address and the command word offset address are concatenated to generate a 32-bit command word read address CMDW_RD_ADDR. CMDW_RD_ADDR consists of three parts, namely, CMDW_RD_ADDR = {CMDW_BASE_ADDR[31:10], CMDW_OFFSET_ADDR, 4'b0000}, where CMDW_BASE_ADDR [31:10] is the high 22 bits of the command word base address configured in the control register, CMDW_OFFSET_ADDR is a 6-bit command word index, and 4'b0000 is 4 zero bits for achieving 16-Bytes command word alignment.

8. The flash memory controller according to claim 6, wherein: The scheduler module includes an erase operation state machine, a read operation state machine, a write operation state machine, an erase / write suspend operation state machine, a task stack for recording currently suspended task information, a task recovery logic, and a performance monitoring module; When the command request and transmission module initiates an operation request for an erase operation, a read operation, or a write operation, the erase operation state machine, the read operation state machine, or the write operation state machine exits an idle state; When an erase suspend or write suspend operation occurs during a write operation or an erase operation, the scheduler module writes the value of the write data counter, the command word index and the command word corresponding to the current operation into the task stack; When a state transition occurs in the state machine of any operation, the scheduler module synchronizes the state of the current operation to the bit field of the status register corresponding to the command word index in the flash memory controller; When the state machine of any operation returns to the idle state, the scheduler module synchronizes the current operation time overhead counted by the performance monitoring module to the status register in the flash memory controller.

9. The flash memory controller according to claim 8, wherein: When a write operation is performed, the corresponding write data is stored in the write cache through the write channel. The write cache includes write cache 0 and write cache 1. Write cache 0 and write cache 1 have two states: dirty and clean, which are used to identify whether the data in write cache 0 or write cache 1 has been overwritten by other write operations since the last write operation; Among them, when writing the write data corresponding to the write operation into the write cache, if the write cache 0 and the write cache 1 are both in the dirty state, any one of the write caches 0 and the write cache 1 is marked as the clean state; if only one of the write caches 0 and the write cache 1 is in the dirty state, the write data is written to the write cache in the clean state; if both the write cache 0 and the write cache 1 are in the clean state, the write data is written to any one of the write caches 0 and the write cache 1.

10. A method for controlling a flash memory controller, characterized in that: The flash memory controller includes an instruction cache, a register, an instruction fetch and decoding module, a weighted arbiter, a command request and transmission module, and a scheduler module. The control method includes: After the flash memory controller completes power-on reset, the host-side controller sends register configuration information and multiple instructions to the flash memory controller through the AXI-Lite interface, and writes the multiple instructions into the instruction cache in the flash memory controller, each of which includes an opcode, a weight, and a command index; Reading instructions from the instruction cache through the instruction fetch and decoding module, and decoding the operation code, instruction weight and command index corresponding to the instruction from the instruction according to the instruction format; According to the weight of each instruction, the instruction index of each instruction is stored in the instruction queue of the corresponding priority; The weighted arbiter arbitrates the instruction index of the instruction currently to be executed from the instruction queues of different priorities according to the status signals of the instruction queues of different priorities, and stores the instruction index in a command index buffer inside the flash memory controller; Reading the instruction index from the command index buffer through the command request and transmission module, and completing the reading of the command word according to the command index in the instruction corresponding to the instruction index; The scheduler module is used to control the write operation state machine, the read operation state machine and the erase operation state machine, thereby realizing the scheduling control of the flash memory particles.

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