A modular HIL cabinet design method and system based on axiomatic design

Abstract

The present disclosure provides a modular HIL cabinet design method and system based on axiomatic design, which relates to the field of HIL cabinet design, including: obtaining the functional domain of the HIL cabinet to be designed; using a decoupling architecture based on axiomatic design theory to divide the functional domain of the cabinet into independent functions and perform parameter design to form a modular HIL cabinet initial design scheme; based on the HIL cabinet initial design scheme, defining a dynamic hardware resource allocation mechanism, and based on a topology optimization algorithm, performing path planning for the cabling within the cabinet to obtain a final HIL cabinet design scheme. The present invention realizes independent maintenance and upgrade of each functional module, reducing maintenance costs; through an expandable rack structure, it can flexibly adapt to different testing requirements; optimizes cable connection and electromagnetic interference design, improves cabinet space utilization, reduces system complexity, and improves system reliability.

Description

Technical Field

[0001] The present disclosure relates to the field of HIL cabinet design, and in particular to a modular HIL cabinet design method and system based on axiomatic design. Background Art

[0002] In traditional testing technologies, system verification is highly dependent on physical prototypes or real physical environments (such as complete vehicles and aircraft). Testing must be completed by repeatedly building experimental benches and adjusting operating parameters. This results in long testing cycles, low efficiency, high costs, and difficulty in covering extreme scenarios (such as high temperature, high pressure, and fault injection).

[0003] Hardware-in-the-loop (HIL) testing technology overcomes the limitations of physical testing by constructing a semi-physical simulation closed-loop system and replacing some physical entities with real-time simulation models. It significantly improves test safety, repeatability, and scenario coverage, and is widely used in automotive electronics, aerospace, and other fields. Its core advantage lies in the closed-loop verification of complex dynamic behaviors through the interaction between high-precision models and real hardware (such as controllers and sensors), making it a key supporting technology for the development of modern complex systems.

[0004] However, the cabinet architecture design of existing HIL test systems has significant flaws, which restricts the further release of their technological potential:

[0005] First, the problem of functional coupling is prominent: hardware modules (such as IO boards, signal conditioning units), power systems, heat dissipation devices, etc. are highly integrated in closed cabinets, which makes maintenance difficult when a single module fails, and hardware upgrades require overall replacement, which increases costs sharply.

[0006] Secondly, insufficient scalability: When the number of channels is limited, traditional HIL cabinets need to be shut down to replace software and hardware when facing different test scenarios, resulting in insufficient scalability of the cabinet when facing various testing requirements.

[0007] In addition, the cable distribution is unreasonable: complex cable connections (signal cables, high-voltage cables, and low-voltage cables) are cross-arranged in a limited space, the wiring is chaotic, the space utilization rate is low, and it is also easy to cause electromagnetic interference and uneven heat dissipation problems.

[0008] Therefore, existing traditional HIL cabinets have problems such as high functional coupling, poor scalability and unreasonable cable distribution. Summary of the Invention

[0009] To address the above-mentioned issues, the present disclosure proposes a modular HIL cabinet design method and system based on axiomatic design, which enables independent maintenance and upgrade of each functional module, reducing maintenance costs; through an expandable rack structure, it can flexibly adapt to different testing requirements; optimizes cable connection and electromagnetic interference design, improves cabinet space utilization, reduces system complexity, and improves system reliability.

[0010] According to some embodiments, the present disclosure adopts the following technical solutions:

[0011] A modular HIL cabinet design method based on axiomatic design includes:

[0012] Obtain the functional domain of the HIL cabinet to be designed;

[0013] Adopting a decoupling architecture based on axiomatic design theory, the functional domain of the cabinet is divided into independent functions and parameter design is performed to form a modular HIL cabinet initial design scheme;

[0014] Based on the initial HIL cabinet design, a dynamic hardware resource allocation mechanism is defined to allocate hardware resources for real-time computing functions. Based on the topology optimization algorithm, the cabling path within the cabinet is planned to obtain the final HIL cabinet design.

[0015] According to some embodiments, the present disclosure adopts the following technical solutions:

[0016] A modular HIL cabinet design system based on axiomatic design, including:

[0017] The function acquisition module is configured to: acquire the function domain of the HIL cabinet to be designed;

[0018] The initial design module is configured to: adopt a decoupling architecture based on axiomatic design theory to divide the functional domain of the cabinet into independent functions and perform parameter design, thus forming a modular HIL cabinet initial design scheme;

[0019] The final design module is configured to define a dynamic hardware resource allocation mechanism based on the initial HIL cabinet design to allocate hardware resources for real-time computing functions, and to plan the routing of cables within the cabinet based on a topology optimization algorithm to obtain the final HIL cabinet design.

[0020] According to some embodiments, the present disclosure adopts the following technical solutions:

[0021] A computer program product includes a computer program. When the computer program is executed by a processor, the computer program implements the axiomatic design-based modular HIL cabinet design method.

[0022] According to some embodiments, the present disclosure adopts the following technical solutions:

[0023] A non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by a processor, the axiomatic design-based modular HIL cabinet design method is implemented.

[0024] According to some embodiments, the present disclosure adopts the following technical solutions:

[0025] An electronic device includes: a processor, a memory, and a computer program; wherein the processor is connected to the memory, and the computer program is stored in the memory. When the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to implement a modular HIL cabinet design method based on axiomatic design.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] Decoupled design: Each functional module can be independently maintained / upgraded. Actual testing has shown that maintenance costs are reduced by over 20% compared to traditional HIL cabinets. During maintenance, there's no need to shut down the entire cabinet for debugging, as is required with traditional cabinets. Only the layer where the faulty module is located needs maintenance, reducing downtime and maintenance workload.

[0028] Fast Deployment: Module replacement time is reduced from hours to minutes. For example, when replacing a compute unit, magnetic rails and standard slots allow technicians to complete replacement and commissioning within 5 minutes, significantly improving testing efficiency.

[0029] High Compatibility: Supports cross-industry testing needs (e.g., automotive ECUs to avionics). By utilizing standardized interface boards and a layered, decoupled design, the cabinet system can easily adapt to the testing requirements of different industries, eliminating the need to design separate test equipment for each industry and reducing testing costs.

[0030] Design matrix verification: Analyze the relationship between the functional requirements FRs of each layer and the design parameters DPs through the design matrix to ensure that the matrix is a diagonal or triangular matrix, thus guaranteeing the rationality and stability of the system design from a theoretical perspective.

[0031] Applying the information axiom: Selecting standardized components (such as universal interface boards and modular power supplies) instead of customized designs reduces system complexity. According to the information axiom, the amount of information I = -log2(P) is minimized. Using standardized components reduces design uncertainty and improves system reliability and maintainability. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which constitute a part of the present disclosure, are used to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation to the present disclosure.

[0033] Figure 1 This is a flow chart of the method of Example 1.

[0034] Figure 2 This is a tree diagram of the functional structure mapping relationship of the modular HIL cabinet in Example 1.

[0035] Figure 3 This is a flowchart of modular HIL cabinet design in Example 1.

[0036] Figure 4 This is a diagram of the modular hardware resource allocation mechanism of Example 1.

[0037] Figure 5 Schematic diagram of the corner angle of Example 1. DETAILED DESCRIPTION

[0038] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0039] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs.

[0040] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "comprising" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0041] Example 1

[0042] In one embodiment of the present disclosure, a modular HIL cabinet design method based on axiomatic design is provided, comprising:

[0043] Step S1: Obtain the functional domain of the HIL cabinet to be designed;

[0044] Step S2: Using a decoupling architecture based on axiomatic design theory, the functional domain of the cabinet is divided into independent functions and parameter design is performed to form an initial design scheme for a modular HIL cabinet;

[0045] Step S3: Based on the initial design of the HIL cabinet, a dynamic hardware resource allocation mechanism is defined to allocate hardware resources for real-time computing functions. Based on the topology optimization algorithm, the cabling path in the cabinet is planned to obtain the final HIL cabinet design.

[0046] As an embodiment, the present disclosure discloses a modular HIL cabinet design method based on axiomatic design, which enables independent maintenance and upgrades of each functional module, reducing maintenance costs. The scalable rack structure allows for flexible adaptation to different testing requirements. The design optimizes cable connections and electromagnetic interference, improves cabinet space utilization, reduces system complexity, and enhances system reliability. The specific implementation process is as follows:

[0047] (1) In response to the functional coupling problem raised in the background technology, this embodiment proposes a four-layer decoupling architecture based on axiomatic design theory, which eliminates functional coupling through independent functional mapping and orthogonal design of the high-performance computing function layer, the multi-interface expansion function layer, the stable power management function layer, and the dynamic heat flow self-balancing function layer.

[0048] Based on the independence axiom and information axiom of axiomatic design, the HIL cabinet requirements are decomposed into independent functional layers, and decoupled design is achieved through standardized interfaces and layered architecture. The cabinet is divided into a high-performance computing functional layer, a multi-interface expansion functional layer, a stable power management functional layer, and a dynamic heat flow self-balancing functional layer. Corresponding to the functional domains FRs, physical modules are designed for each of the four independent functional layers. The physical modules are then divided into sub-functional modules and the corresponding sub-physical modules are designed, ultimately obtaining the independent design parameters DPs for each layer.

[0049] Among them, the high-performance computing function layer adopts pluggable computing units (FPGA modules) to support hot plugging and dynamic expansion; FPGA is responsible for real-time processing of high-frequency signals, and multi-core processors run complex dynamic models (such as vehicle dynamics and aircraft engine simulation), forming a collaborative architecture of "hardware acceleration + general computing"; in this way, when computing power needs to be increased, new computing units can be directly inserted without large-scale transformation of the entire system; when a computing unit fails, it can also be easily replaced without affecting the normal operation of other layers.

[0050] The multi-interface extended function layer is equipped with standardized interface boards (such as CAN, LIN, and Ethernet) and communicates with the computing layer through the backplane bus. The standardized interface boards can support multiple signal types to meet the interface requirements in different test scenarios. The backplane bus design ensures fast and stable data transmission between the computing layer and the interface layer.

[0051] The stable power management layer uses independent power modules to power each layer, supporting redundancy and load balancing. Redundancy ensures that if one power module fails, other power modules can continue to power the system, improving system stability. Load balancing ensures that the load is distributed appropriately across the power modules, extending their service life.

[0052] The dynamic heat flow self-balancing functional layer achieves localized precise heat dissipation through distributed temperature sensors and micro piezoelectric fan arrays, replacing the traditional fully redundant fan design.

[0053] Figure 2 This is a tree diagram of the mapping relationship between the functional structure of the modular HIL cabinet. "Real-time simulation and verification of the overall function FR" and "systematic integration of design parameters DP" are the overall layer, and the relationship with the FR and DP below is a hierarchical decomposition. The overall layer FR defines the system goal, and DP provides the top-level solution; decompose downward layer by layer to ensure that each level of FR-DP meets the independence axiom; select the optimal DP combination through the information axiom, so the figure shows the mapping relationship between independent functional layers, physical modules, sub-functional modules and sub-physical modules, based on Figure 2 The mapping relationship shown, the entire decomposition process is:

[0054] The mapping between independent functional layers and physical modules is taken as the first-level decomposition, and the design equation matrix obtained in the first-level decomposition is:

[0055]

[0056] Among them, FR1 is the high-performance computing function layer, FR2 is the multi-interface expansion function layer, FR3 is the stable power management function layer, FR4 is the dynamic heat flow self-balancing function layer, DP1 is the computing unit, DP2 is the interface unit, DP3 is the power module, and DP4 is the heat dissipation duct.

[0057] In linear design, when the design matrix is a triangular matrix, it is a quasi-coupled design. The independence can be guaranteed by changing the order of the design parameters to meet the axiomatic design criteria. Therefore, the above matrix is transformed into a triangular matrix through transformation.

[0058]

[0059] During the transformation process, the order of design parameters DP3 and DP4 was adjusted to make the design process reasonable and in line with the axiomatic design principle.

[0060] Similarly, the mapping between the sub-functional modules and the sub-physical modules is used as the second-level decomposition. The design equation matrix obtained by the second-level decomposition includes:

[0061]

[0062] Among them, FR11 is the real-time computing function, FR12 is the coordinated computing function, DP11 is FPGA, and DP12 is a multi-core processor.

[0063]

[0064] Among them, FR21 is the communication function, FR22 is the IO function, DP21 is the CAN interface, and DP22 is the TIF interface.

[0065]

[0066] Among them, FR31 is a strong power supply function, FR32 is a weak power supply function, DP31 is a PDU, and DP32 is a programmable power supply.

[0067] FR41=DP41

[0068] Among them, FR41 has strong wind cooling function, and DP41 is a cooling fan.

[0069] The design matrices of the above two-level decompositions are all diagonal matrices or triangular matrices. The design process is reasonable and conforms to the axiomatic design principle.

[0070] Combining the results of the design matrix in the above analysis process, we can get a design process that conforms to the axiomatic design concept. The design order in the first-level decomposition is DP1, DP2, DP4, DP3. The second-level decomposition process is the same, and we get the following: Figure 3 The overall design process is shown in FIG. 4 , and the HIL cabinet is designed according to the design process derived above.

[0071] (2) In response to the insufficient scalability problem raised in the background technology, this embodiment uses a software-defined modular hardware resource allocation mechanism to dynamically adapt to the requirements of different test scenarios and allocate resources to the FPGA of the real-time computing function in the high-performance computing function layer FR1, such as Figure 4 As shown in FIG, the modular hardware resource allocation mechanism is divided into four areas, namely, signal selection area, signal protocol area, virtual interface area, and real interface area.

[0072] The signal selection area stores unique codes for different signal protocols (such as 0x01 for PWM and 0x02 for SENT). Each code is mapped one-to-one to a specific module in the signal protocol area. Processing operations include code generation and code switching. Code generation generates the code corresponding to the signal protocol based on test requirements, while code switching generates real-time switching instructions for the signal protocol by modifying the currently active code.

[0073] The signal protocol area is a signal protocol implementation unit encapsulated as an independent module (such as the PWM generator module and the SENT encoder module). It contains protocol parsing logic and signal generation algorithms, and establishes a one-to-one correspondence between the encoded signal and the protocol module (such as 0x01 → PWM module, 0x02 → SENT module). Processing operations include module switching and signal generation. Module selection is to receive the encoded signal in the signal selection area through the software programming interface to trigger the activation of the corresponding protocol module. Signal generation is to activate the module to generate a signal data stream in a specific format based on the input parameters.

[0074] The virtual interface area stores the interface types required by each signal protocol; processing operations include interface configuration and signal routing. Interface configuration is to complete the configuration of the interface type at the software layer based on the output requirements of the signal protocol. Signal routing is to route the signal data stream generated by the protocol module to the corresponding virtual interface.

[0075] The real interface area stores the type (AI / AO / DI / DO, etc.), quantity, and electrical characteristics of the actual physical interface. Processing operations include interface matching and signal output. Interface matching is the physical mapping of the virtual interface to the real interface through hardware, and signal output is the conversion of the digital / analog signal of the virtual interface into a real physical signal. The number and type of actual physical interfaces stored in the real interface area are the maximum number and type required by all (n) communication protocols in the virtual interface area, expressed as follows:

[0076]

[0077] Where N is the number of interfaces of a certain type in the real interface area, The number of channels for each of the n communication protocols of the same type of interface in the virtual interface area.

[0078] The modular hardware resource allocation mechanism achieves channel reuse through the above four areas, reducing channel resource waste. When facing the requirements of different test scenarios, there is no need to shut down the HIL equipment to replace the hardware and software. While using a small amount of resources, it increases the scalability of the HIL cabinet when facing different test requirements.

[0079] (3) In response to the problem of unreasonable cable distribution mentioned in the background technology, this embodiment proposes to use a topology optimization algorithm to perform three-dimensional space planning of cables in the cabinet, so as to make the wiring reasonable, greatly improve space utilization, and avoid cross interference.

[0080] Cabinets primarily include high-voltage cables and low-voltage cables in the stable power management layer (FR3), and signal cables in the multi-interface expansion layer (FR2). Signal cables are further divided into high-speed and low-speed signal cables based on transmission rate. Therefore, cable type classification constraints are as follows:

[0081] (1) The distance between the high-voltage cable and the other two types of cables (low-voltage cables and signal cables) should be greater than or equal to 50 mm to avoid electromagnetic interference caused by the high-voltage cable. If this cannot be met, install a metal shielding sleeve.

[0082] (2) High-speed signal lines are routed separately to avoid sharing slots with power lines. 45° arc transitions are used at turns to reduce reflected noise.

[0083] An improved A* algorithm is used to plan cable paths. The improvement converts engineering constraints (stress cost, electromagnetic interference cost, and space occupancy cost) into computable quantitative indicators, introduces them into the evaluation function, dynamically adjusts priorities through weight coefficients (β, γ, δ), and balances the current cost g(n) and the target heuristic h(n) through the evaluation function. This allows for efficient finding of the optimal path in complex grid spaces. The improved evaluation function is:

[0084]

[0085] Where n is the path node currently being evaluated, that is, its current state or position; g*(n) is the actual cost; S(n) is the stress cost, calculated based on the spacing between fixed points and the bending radius. For example, if the fixed points are too sparse, the tension increases; E(n) is the electromagnetic interference cost, calculated based on the spacing between cable types and shielding measures. For example, the penalty value is increased when strong / weak current crosses; V(n) is the space occupancy cost, which is calculated by counting the number of three-dimensional grids occupied by the path and the distance to obstacles. The closer the path is to the wiring trough, the lower the cost; β, γ, and δ are weight coefficients, adjusted according to the cabinet type.

[0086] Based on the above evaluation function, the specific cable routing path optimization process is as follows:

[0087] Step 1: Initialization and data modeling

[0088] Input data, including the cabinet 3D model, including equipment, wiring trough, obstacle coordinates; cable parameter table, including type, diameter, flexibility coefficient , shielding level ; Constraint parameters: minimum distance D between strong and weak current EMC =50mm, maximum distance between fixed points L MAX =300mm, the weights of each target are, such as β=0.3,γ=0.4,δ=0.3.

[0089] Based on the above data, spatial discretization is performed to divide the cabinet into three-dimensional grids (granularity k = 10 mm). Each grid is marked with the following attributes: whether it is an obstacle, whether it belongs to a wiring trough, and whether it is a dedicated layer for high-voltage / low-voltage / signal.

[0090] Step 2: Set the initial node and Open / Closed table

[0091] Starting point: the coordinates of the source device terminal blocks (e.g., the high-voltage starting point (100, 50, 20));

[0092] End point: The coordinates of the target device terminal block (e.g., signal end point (800,700,800)).

[0093] Open table: Priority queue (by Arrange in ascending order), initially add the starting point node;

[0094] Closed table: records visited nodes to avoid repeated searches.

[0095] Step 3: Node expansion and adjacent node generation

[0096] Perform 8-directional expansion (3D space), where each node expands in 6 orthogonal directions (±1,0,0), (0,±1,0), (0,0,±1), and the diagonal direction to generate adjacent nodes.

[0097] During the expansion process, pay attention to the following two points:

[0098] Obstacle avoidance: If the adjacent grid is occupied by equipment or pillars, skip the node;

[0099] Minimum bending radius: Calculate the turning angle. If the bending radius is less than the cable's allowable value (such as high-voltage cables), =6D), marked as an invalid node.

[0100] Step 4: Multi-objective cost calculation

[0101] ① Considering the shortened path of the bend trough, calculate the actual cost g*(n), the formula is:

[0102] g*(n)=length of the line segment −Δg(θ)

[0103] Where Δg(θ) is the shortened path of the bend trough, which is calculated based on the corner angle, as follows: Figure 5 As shown, if the corner is 90°, then Δg(θ)=(2-π / 2)(R+r), where R represents the bending radius of the bending trough, which is used to describe the arc bending size of the cable bundle at the corner, and r represents the equivalent radius of the cable bundle.

[0104] ② Based on the three-dimensional Euclidean distance, define the target heuristic function h(n), the formula is:

[0105]

[0106] Among them, (x n ,y n ,z n ) represents the three-dimensional coordinates of the current node, (x end ,yend ,z end ) represents the three-dimensional coordinates of the target node.

[0107] Guide the search towards the target point and reduce blind exploration.

[0108] ③ The cost of the bending duct s(n) is as follows:

[0109]

[0110] Where, l is the length of the bending trough, is the unit cost coefficient, is the material cost, is the process cost, The weight cost is: for example, when the corner is 90°, the length of the bending trough l is π / 2(R+r), multiplied by the unit cost coefficient.

[0111] ④ Stress cost S(n), the formula is:

[0112] S(n)=S 间距 (n)+S 弯曲 (n)

[0113] Among them, S 间距 (n) is the fixed point spacing penalty, S 弯曲 (n) is the bending stress penalty.

[0114] If the distance L between the current node and the previous fixed point is greater than the maximum distance L between the fixed points MAX , then the fixed point spacing penalty is:

[0115] S 间距 (n)=k f ×(L−L max )

[0116] Among them, k f k is the cable flexibility coefficient. The better the flexibility, the higher the k f The larger the value, the higher the penalty; this is to prevent flexible cables (such as soft wires) from being overstretched due to large spacing between fixing points, and to ensure the mechanical stability of the cable.

[0117] If the actual bending radius R b <The minimum bending radius R allowed for the cable min , then the bending stress penalty is:

[0118]

[0119] This formula normalizes the penalty value to 0-100 points, R b The closer to R minThe lower limit, the higher the penalty, is intended to ensure that the cable bending radius is within a safe range and prevent cable damage due to excessive bending.

[0120] ⑤Electromagnetic interference cost E(n), the formula is:

[0121] E(n)=E 间距 (n)+E 平行 (n)

[0122] Among them, E 间距 (n) is the type spacing penalty, E 平行 (n) Penalty for parallel laying.

[0123] If the distance between the power node and the signal node d < the safety distance threshold D EMC , then the type spacing penalty is:

[0124]

[0125] Among them, S L Represents the signal shielding level. The formula indicates that the smaller the spacing d, the greater the interference risk and the higher the penalty value. L Used to adjust the penalty intensity according to the shielding condition of the signal line. For example, when the strong power and the unshielded signal line are close to each other, E(n) will be affected by S L The larger the value, the higher the penalty value, which prompts the algorithm to plan a path away from strong electricity.

[0126] The penalty for parallel routing is:

[0127]

[0128] If the length L is parallel to the high-voltage line p >100mm, add 1 for every 10mm

[0129] As the parallel length increases, the risk of electromagnetic interference increases, thereby increasing the penalty value so that the algorithm can try to avoid long-distance parallel laying of signals and high-voltage lines.

[0130] ⑥ Space occupation cost V(n), the formula is:

[0131] V(n)=V 栅格 (n)+V 障碍 (n)

[0132]

[0133] Among them, V 栅格 (n) is the grid occupancy rate, V 障碍 (n) is the obstacle proximity.

[0134] The space occupancy is measured by calculating the number of three-dimensional grid cells occupied by the path and normalizing it to the range of 0-1 to obtain the grid occupancy rate, which is expressed as:

[0135]

[0136] It means the ratio of the number of grids actually occupied to the number of grids available for occupation in the wiring trough. The lower this ratio is, the more reasonable the path occupies the space and the lower the cost.

[0137] The calculation method for obstacle proximity is: if the node is less than 5mm from a metal obstacle (such as a heat dissipation hole), a fixed penalty of 0.5 is added (to prevent cable wear). Otherwise, no penalty is added. The formula is:

[0138]

[0139] The main consideration is the impact of the distance between the cable and metal obstacles (such as heat dissipation holes) on the space occupancy cost. If the node is less than 5 mm from the metal obstacle, a fixed penalty value of 0.5 is added. This is to prevent the cable from getting too close to the metal obstacle and prevent possible wear. For example, when the distance between a node on a certain cable path and the metal obstacle is less than 5 mm, an additional penalty value of 0.5 is added regardless of V(n) calculated by the grid occupancy rate, making the space occupancy cost of the path higher, thereby guiding the algorithm to plan a path that keeps the cable away from metal obstacles as much as possible.

[0140] Step 5: Valuation function integration and node sorting

[0141] The total cost is calculated through the evaluation function, which is expressed as follows:

[0142]

[0143] Based on the total cost, update the priority queue:

[0144] Open table always select Minimize node expansion to ensure multi-objective balance (e.g., prioritize reducing E(n) in high EMC scenarios).

[0145] Step 6: Closed-loop verification and path correction

[0146] At the turning points and straight segments of the path, every L=200×k f mm Insert fixed point, such as hard line k f =1, spacing 200mm; soft wire k f =0.5, spacing 100mm. If the insertion point causes space conflict, go back to the previous node and search again.

[0147] If the strong electric layer path passes through the signal layer area, the E(n) penalty value is forcibly increased, triggering local replanning.

[0148] Step 7: Path Generation and Physical Verification

[0149] Trace back to the parent node from the Closed table, extract the coordinates of the inflection point and fixed point, and generate the centerline path.

[0150] Perform finite element simulation verification on the centerline path, input cable material parameters (such as Young's modulus and shielding layer conductivity), simulate stress distribution and electromagnetic radiation under different working conditions, and if the threshold is exceeded, adjust the weight coefficient (such as increasing β) and recalculate.

[0151] By using a topology optimization algorithm to perform three-dimensional spatial planning of cables within the cabinet, stress is reduced by 15%, electromagnetic interference amplitude is lowered by 10%, and space occupancy is reduced by 25% compared to manual wiring.

[0152] This embodiment successfully solves the problems of functional coupling, poor scalability, and unreasonable cable distribution in traditional HIL cabinet design, realizes independent maintenance and upgrade of each functional module, and reduces maintenance costs. Through the expandable rack structure, it can flexibly adapt to different testing requirements. It optimizes cable connection and electromagnetic interference design, improves cabinet space utilization, reduces system complexity, and improves system reliability.

[0153] Example 2

[0154] In one embodiment of the present disclosure, a modular HIL cabinet design system based on axiomatic design is provided, comprising:

[0155] The function acquisition module is configured to: acquire the function domain of the HIL cabinet to be designed;

[0156] The initial design module is configured to: adopt a decoupling architecture based on axiomatic design theory to divide the functional domain of the cabinet into independent functions and perform parameter design, thus forming a modular HIL cabinet initial design scheme;

[0157] The final design module is configured to define a dynamic hardware resource allocation mechanism based on the initial HIL cabinet design to allocate hardware resources for real-time computing functions, and to plan the routing of cables within the cabinet based on a topology optimization algorithm to obtain the final HIL cabinet design.

[0158] Example 3

[0159] In one embodiment of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the axiomatic design-based modular HIL cabinet design method is implemented.

[0160] Example 4

[0161] In one embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by a processor, the axiomatic design-based modular HIL cabinet design method is implemented.

[0162] Example 5

[0163] In one embodiment of the present disclosure, an electronic device is provided, comprising: a processor, a memory, and a computer program; wherein the processor is connected to the memory, and the computer program is stored in the memory. When the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device executes the axiomatic design-based modular HIL cabinet design method.

[0164] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0166] Although the above describes the specific implementation methods of the present disclosure in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present disclosure. Those skilled in the art should understand that on the basis of the technical solution of the present disclosure, various modifications or variations that can be made by those skilled in the art without creative work are still within the scope of protection of the present disclosure.

Claims

1. A modular HIL cabinet design method based on axiomatic design, characterized in that: include: Obtain the functional domain of the HIL cabinet to be designed; Adopting a decoupling architecture based on axiomatic design theory, the functional domain of the cabinet is divided into independent functions and parameter design is performed to form a modular HIL cabinet initial design scheme; Based on the initial HIL cabinet design, a dynamic hardware resource allocation mechanism is defined to allocate hardware resources for real-time computing functions. A topology optimization algorithm is used to plan the cabling paths within the cabinet to obtain the final HIL cabinet design. The path planning for the cabling of cables in the cabinet is performed by using the A* algorithm, which introduces stress cost, electromagnetic interference cost, and space occupancy cost into the evaluation function, and uses the evaluation function to find the optimal cabling path in the grid space of the cabinet; The formula of the valuation function is specifically: Among them, g*(n) is the actual cost, calculated based on the wiring length; S(n) is the stress cost, calculated based on the fixed point spacing and bending radius; E(n) is the electromagnetic interference cost, calculated based on the cable type spacing and shielding measures; V(n) is the space occupation cost, calculated based on the number of three-dimensional grids occupied by the statistical path and the distance to obstacles; β, γ, and δ are weight coefficients; represents the heuristic function, which is calculated based on the three-dimensional coordinates of the current node and the target node; Represents the cost of the bend duct, which is calculated based on the bend duct length and the unit cost coefficient, where the bend duct length is related to the corner angle.

2. The modular HIL cabinet design method based on axiomatic design according to claim 1, characterized in that: The decoupling architecture based on axiomatic design theory divides the functional domain of the HIL cabinet into independent functions based on the independence axiom and information axiom of axiomatic design, and realizes decoupling design through a layered architecture. The division into independent functions is to divide the cabinet into four functional layers: high-performance computing functional layer, multi-interface expansion functional layer, stable power management functional layer, and dynamic heat flow self-balancing functional layer, and each layer has independent design parameters.

3. The modular HIL cabinet design method based on axiomatic design according to claim 2, characterized in that: The layered architecture is to design physical modules for each of the four functional layers, divide the physical modules into sub-functional modules, and design corresponding sub-physical modules.

4. The modular HIL cabinet design method based on axiomatic design according to claim 1, characterized in that: The hardware resource allocation mechanism allocates hardware resources for real-time computing functions using the signal selection area, signal protocol area, virtual interface area, and real interface area. Specifically, Signal selection area: select the signal protocol according to the current test requirements and encode it and send it to the signal protocol area; The signal protocol area matches the received signal protocol with specific protocol content and generates a signal based on the matched protocol content; The virtual interface area configures the corresponding interface according to the selected signal protocol and the generated signal; The real interface area sends the generated signal to the real physical hardware corresponding to the interface.

5. A modular HIL cabinet design system based on axiomatic design, characterized by: include: The function acquisition module is configured to: acquire the function domain of the HIL cabinet to be designed; The initial design module is configured to: adopt a decoupling architecture based on axiomatic design theory to divide the functional domain of the cabinet into independent functions and perform parameter design, thus forming a modular HIL cabinet initial design scheme; The final design module is configured to: define a dynamic hardware resource allocation mechanism based on the initial HIL cabinet design to allocate hardware resources for real-time computing functions, and plan the cabling paths within the cabinet based on a topology optimization algorithm to obtain the final HIL cabinet design; The path planning for the cabling of cables in the cabinet is performed by using the A* algorithm, which introduces stress cost, electromagnetic interference cost, and space occupancy cost into the evaluation function, and uses the evaluation function to find the optimal cabling path in the grid space of the cabinet; The formula of the valuation function is specifically: Among them, g*(n) is the actual cost, calculated based on the wiring length; S(n) is the stress cost, calculated based on the fixed point spacing and bending radius; E(n) is the electromagnetic interference cost, calculated based on the cable type spacing and shielding measures; V(n) is the space occupation cost, calculated based on the number of three-dimensional grids occupied by the statistical path and the distance to obstacles; β, γ, and δ are weight coefficients; represents the heuristic function, which is calculated based on the three-dimensional coordinates of the current node and the target node; Represents the cost of the bend duct, which is calculated based on the bend duct length and the unit cost coefficient, where the bend duct length is related to the corner angle.

6. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method for designing a modular HIL cabinet based on axiomatic design according to any one of claims 1 to 4 is implemented.

7. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by the processor, the modular HIL cabinet design method based on axiomatic design as described in any one of claims 1 to 4 is implemented.

8. An electronic device, characterized in that: include: A processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to implement a modular HIL cabinet design method based on axiomatic design as described in any one of claims 1 to 4.

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