Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof. The method comprises: providing a substrate, the substrate comprising a plurality of active regions extending along a first direction; forming a plurality of patterned mask layers extending along a second direction on the substrate; etching the active regions using the patterned mask layers to form a plurality of active pillars arranged in an array along the first direction and the second direction; forming a gate dielectric layer on sidewalls of the active pillars; filling a conductive material between adjacent active pillars and covering surfaces of the gate dielectric layer to form a conductive material layer; forming a sidewall mask layer on sidewalls of the patterned mask layers; wherein the patterned mask layers and the sidewall mask layer jointly define positions of word line structures; the first direction and the second direction are both parallel to the substrate and the first direction and the second direction intersect.

Description

TECHNICAL FIELD

[0001] The embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Generally, dynamic random access memory (DRAM) utilizes a capacitor to realize data storage. The DRAM can have a structure of 1 transistor 1 capacity (1T1C), a first source-drain electrode of the transistor and the capacitor are connected, a second source-drain electrode of the transistor and a bit line are connected, and a gate electrode of the transistor and a word line are connected.

[0003] However, with the development of the semiconductor field towards higher integration density and higher electrical performance, the development of the DRAM also faces challenges brought by the manufacturing process. SUMMARY

[0004] Therefore, the embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.

[0005] To achieve the above object, the technical scheme of the present disclosure is implemented as follows:

[0006] In a first aspect, the embodiments of the present disclosure provide a manufacturing method of a semiconductor device, and the method comprises:

[0007] providing a substrate, wherein the substrate is provided with a plurality of active regions extending along a first direction;

[0008] forming a plurality of patterned mask layers extending along a second direction on the substrate;

[0009] etching the active regions by using the patterned mask layers to form a plurality of active pillars arranged in an array along the first direction and the second direction;

[0010] forming a gate dielectric layer on a sidewall of the active pillar;

[0011] filling a conductive material between adjacent active pillars and covering a surface of the gate dielectric layer to form a conductive material layer;

[0012] forming a sidewall mask layer on a sidewall of the patterned mask layer; wherein the patterned mask layer and the sidewall mask layer jointly define a position of a word line structure; the first direction and the second direction are both parallel to the substrate, and the first direction and the second direction intersect.

[0013] In some embodiments, after the sidewall mask layer is formed on the sidewall of the patterned mask layer, the method further comprises:

[0014] etching the conductive material layer by using the patterned mask layer and the sidewall mask layer to form the word line structures extending along the second direction and arranged in intervals along the first direction; wherein the word line structures cover the active pillars arranged along the second direction.

[0015] In some embodiments, the providing a substrate having a plurality of active regions extending along a first direction comprises:

[0016] providing a substrate;

[0017] etching the substrate to form a plurality of first isolation grooves extending along the first direction; the first isolation grooves divide the substrate into a plurality of active regions;

[0018] filling an isolation material in the first isolation grooves to form an isolation layer between adjacent active regions.

[0019] In some embodiments, the forming a plurality of patterned mask layers extending along a second direction on the substrate comprises:

[0020] forming an initial mask layer covering the active regions and the isolation layer;

[0021] forming a patterned photoresist layer on the initial mask layer;

[0022] etching the initial mask layer by using the patterned photoresist layer to form a plurality of the patterned mask layers extending along the second direction.

[0023] In some embodiments, the etching the active regions by using the patterned mask layer to form a plurality of active pillars arranged in an array along the first direction and the second direction comprises:

[0024] etching the active regions and the isolation layer by using the patterned mask layer to form a plurality of second isolation grooves extending along the second direction; the first isolation grooves and the second isolation grooves collectively divide the substrate into a plurality of active pillars.

[0025] In some embodiments, before the forming a gate dielectric layer on sidewalls of the active pillars, the method further comprises:

[0026] removing part of the isolation layer between adjacent active pillars through the second isolation grooves to form third isolation grooves in the first isolation grooves and expose sidewalls of the active pillars.

[0027] In some embodiments, the filling a conductive material between adjacent active pillars and covering surfaces of the gate dielectric layer to form a conductive material layer comprises:

[0028] filling conductive material in the second isolation groove and the third isolation groove and covering the surface of the gate dielectric layer to form an initial conductive material layer; the initial conductive material layer also covers the surface of the patterned mask layer;

[0029] removing the initial conductive material layer covering the top surface and the sidewall of the patterned mask layer to form the conductive material layer.

[0030] In some embodiments, each of the active pillars has a first connection end, a second connection end, and a channel region between the first connection end and the second connection end along a direction perpendicular to the substrate;

[0031] After the conductive material layer is etched using the patterned mask layer and the sidewall mask layer to form the word line structures extending along the second direction and spaced apart along the first direction, the method further comprises:

[0032] filling insulating material between adjacent word line structures to form a word line isolation layer;

[0033] etching the patterned mask layer to expose the second connection end.

[0034] In some embodiments, after the second connection end is exposed, the method further comprises:

[0035] forming a plurality of bit line structures extending along the first direction, the bit line structures being connected to the second connection ends arranged along the first direction;

[0036] performing a thinning process on the substrate to expose the first connection ends of the active pillars;

[0037] forming a plurality of storage node structures connected to the first connection ends.

[0038] In some embodiments, after the second connection end is exposed, the method further comprises:

[0039] forming a plurality of storage node structures connected to the second connection ends;

[0040] performing a thinning process on the substrate to expose the first connection ends of the active pillars;

[0041] forming a plurality of bit line structures extending along the first direction, the bit line structures being connected to the first connection ends arranged along the first direction.

[0042] In some embodiments, before forming a plurality of patterned mask layers extending along a second direction on the substrate, the method further comprises:

[0043] forming a plurality of bit line structures extending along the first direction in the substrate, the bit line structures and the portions of the active regions near the substrate being connected;

[0044] After the second connection end is exposed, the method further includes:

[0045] forming a plurality of storage node structures, the storage node structures being connected to the second connection end.

[0046] In a second aspect, the embodiments of the present disclosure provide a semiconductor device manufactured by the method for manufacturing a semiconductor device.

[0047] In some embodiments, the semiconductor device includes a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), a phase change random access memory (PCRAM), and a dynamic random access memory (DRAM).

[0048] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. In the embodiments of the present disclosure, an active region is etched by using a patterned mask layer to form a plurality of active pillars arranged in an array, and the patterned mask layer is reserved; a gate dielectric layer covering the sidewalls of the active pillars is formed; a conductive material is filled between adjacent active pillars and covers the surface of the gate dielectric layer to form a conductive material layer; a sidewall mask layer is formed on the sidewalls of the patterned mask layer; the position of a word line structure is defined by the patterned mask layer reserved by the foregoing process steps and the sidewall mask layer, so that the use of the mask layer can be reduced to reduce the process cost; and self-alignment during the formation of the word line structure can also be achieved to reduce the process difficulty. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 A top view of a semiconductor device provided for some examples;

[0050] Figures 2A-2E A cross-sectional view of a semiconductor device provided for some examples;

[0051] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided for the embodiments of the present disclosure;

[0052] Figures 4A-4J A cross-sectional view of a semiconductor device in a manufacturing process provided for the embodiments of the present disclosure. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0054] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail to avoid obscuring the present disclosure. In the interest of clarity, not all features of the actual implementation are described in detail (exemplary implementations are shown in detail, however, where possible, configuration and other well-known features are not described in detail), the actual implementation can also contain other features.

[0055] In the drawings, the size of layers, regions, elements and / or relative sizes of the same can be exaggerated for clarity. The same drawing reference numbers will be used throughout the several figures to refer to same or like elements.

[0056] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to" or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are simply used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Conversely, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0057] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0059] For a thorough understanding of the present disclosure, reference should be made to the following detailed description together with the accompanying drawings, in which:

[0060] Before introducing the embodiments of the present disclosure, three directions for describing semiconductor devices can be defined, which can include an X direction, a Y direction, and a Z direction. The X direction and the Y direction are both parallel to a substrate, and the X direction and the Y direction intersect. The Z direction is perpendicular to the substrate. In the embodiments of the present disclosure, memory cells can be arranged in an array along the X direction and the Y direction. In the embodiments of the present disclosure, the memory cells can be arranged in an array along the X direction and the Y direction. The X direction can also be referred to as a row direction, and the Y direction can also be referred to as a column direction.

[0061] It should be noted that a first direction, a second direction, and a third direction can be defined. In the embodiments of the present disclosure, the first direction is defined as the Y direction, the second direction is defined as the X direction, and the third direction is defined as the Z direction.

[0062] Reference Figure 1 , Figure 1 A top view structural schematic diagram of a semiconductor device is provided for some examples. As shown in FIG. 1, a semiconductor device 100 can include a substrate 110, a plurality of memory cells 120, a plurality of word lines 130, a plurality of bit lines 140, and a plurality of source lines 150.Figure 1 As shown, the semiconductor device 100 includes a device region 104 (e.g., Figure 1 (As shown in the dashed box) and a peripheral region 106, which may surround the device region 104; wherein, a memory cell array is provided in the device region 104, the memory cell array including multiple memory cells arranged in an array along the X and Y directions; peripheral circuitry is provided in the peripheral region 106, which can be used to control the memory cell array. Multiple active pillars 108 are arranged in an array along the X and Y directions in the device region 104, each active pillar 108 including a first connection terminal and a second connection terminal arranged opposite each other along the Z direction, and a channel region located between the first connection terminal and the second connection terminal. The drain of a transistor may be, for example, the first connection terminal of the active pillar, the source of a transistor may be, for example, the second connection terminal of the active pillar, and the gate of a transistor may surround the channel region of the active pillar. The first connection terminal of active pillars located in the same column (i.e., arranged along the Y direction) can be connected to the same bit line (BL), and the gate outside the channel region of active pillars located in the same row (i.e., arranged along the X direction) can be connected to the same word line (WL).

[0063] refer to Figures 2A-2E , Figures 2A-2E The diagram shows a cross-sectional view of a semiconductor device for some examples. Figures 2A-2E Indicate the edge Figure 1 Schematic diagram of cross-sectional structure in the aa and bb directions.

[0064] Figure 1 and Figures 2A-2E The diagram illustrates a vertical channel transistor (VGT) with a gate-all-around (GAA) structure.

[0065] like Figure 2A As shown, the etched substrate 102 forms a plurality of active pillars 108 arranged in an array; a gate dielectric layer 110 is formed covering the sidewalls of the active pillars 108; and conductive material is filled between adjacent active pillars 108 to form an initial conductive material layer 112.

[0066] like Figure 2B As shown, the active post 108 includes a first connection end 130 and a second connection end 132 disposed opposite to each other along the Z direction, and a channel region 134 located between the first connection end 130 and the second connection end 132; a portion of the initial conductive material layer 112 is etched to form a conductive material layer 114 exposing the second connection end 132; a sacrificial material is filled between adjacent active posts 108 to form a sacrificial layer 116 covering the second connection end 132; and a mask layer 118 is formed on the sacrificial layer 116.

[0067] As shown in Figure 2C , the mask layer 118 is patterned to form a patterned mask layer; the patterned mask layer is used to etch the sacrificial layer 116 to form a sacrificial cell 120 on the active pillar 108; wherein the conductive material layer 114, the second connection end 132 of the active pillar 108 and the sacrificial cell 120 are in contact after the etching is completed.

[0068] As shown in Figure 2D , a sidewall structure 122 covering the sidewall of the sacrificial cell 120 is formed.

[0069] As shown in Figure 2E , the conductive material layer 114 is etched using the sacrificial cell 120 and the sidewall structure 122 as a mask to form a word line slot 124 that divides the conductive material layer 114 between adjacent active pillars 108 in half, and the remaining conductive material layer 114 forms a gate conductive layer 126 covering the active pillars 108 in the same row; wherein the gate dielectric layer 110 and the gate conductive layer 126 together form a word line structure 128.

[0070] Figure 1 And Figures 2A-2E , the semiconductor device manufacturing process is schematically shown. The filling of the conductive material between adjacent active pillars and the formation of the word line structure need to be manufactured separately, that is, different photomask layers (Photomask) and hard mask layers (Hard Mask, HM) are required for etching to form isolation slots between different rows of active pillars and etching to form gate conductive layers, which will not be conducive to reducing process costs.

[0071] Therefore, the present disclosure provides a semiconductor device and a manufacturing method thereof.

[0072] Referring to Figure 3 , Figure 3 , a flowchart of the manufacturing method of the semiconductor device provided by the present disclosure is shown. As shown in Figure 3 , the present disclosure provides a manufacturing method of a semiconductor device, which comprises:

[0073] Step S301: providing a substrate, the substrate being provided with a plurality of active regions extending along a first direction;

[0074] Step S302: forming a plurality of patterned mask layers extending along a second direction on the substrate;

[0075] Step S303: etching the active regions using the patterned mask layers to form a plurality of active pillars arranged in an array along the first direction and the second direction;

[0076] Step S304: forming a gate dielectric layer on the sidewall of the active pillar;

[0077] Step S305: filling a conductive material between adjacent active pillars and covering the surface of the gate dielectric layer to form a conductive material layer.

[0078] Step S306: forming a sidewall mask layer on the sidewall of the patterned mask layer; wherein the patterned mask layer and the sidewall mask layer jointly define the position of the word line structure; the first direction and the second direction are both parallel to the substrate and the first direction and the second direction intersect.

[0079] In the embodiments of the present disclosure, the active region is etched by using the patterned mask layer to form a plurality of active pillars arranged in an array, and the patterned mask layer is reserved; a gate dielectric layer covering the sidewall of the active pillar is formed; a conductive material is filled between adjacent active pillars and covers the surface of the gate dielectric layer to form a conductive material layer; a sidewall mask layer is formed on the sidewall of the patterned mask layer; the position of the word line structure is jointly defined by the patterned mask layer and the sidewall mask layer reserved by the foregoing process steps, so that the use of the mask layer can be reduced to reduce the process cost; and self-alignment during the formation of the word line structure can also be achieved to reduce the process difficulty.

[0080] Reference Figures 4A-4J , Figures 4A-4J The cross-sectional structure schematic diagram of the semiconductor device provided by the embodiments of the present disclosure in the manufacturing process is shown in the following figure. Figure 3 and Figures 4A-4J The manufacturing process of the semiconductor device will be described in detail.

[0081] In the embodiments of the present disclosure, in step S301, a substrate 402 is provided, and the substrate 402 is provided with a plurality of active regions 406 extending along a first direction (i.e. Y direction).

[0082] As shown in Figure 4A , in some embodiments, step S301 includes: providing a substrate 402; etching the substrate 402 along the Z direction to form a plurality of first isolation grooves 404 extending along the Y direction; the first isolation grooves 404 divide the substrate 402 into a plurality of active regions 406 extending along the Y direction; and filling an isolation material in the first isolation grooves 404 to form an isolation layer 408 between two adjacent active regions 406.

[0083] Here, the substrate 402 can be a semiconductor substrate; specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, an arsenic gallium (GaAs) substrate, an indium phosphorous (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and can also include other semiconductor-containing substrates such as a silicon on insulator (SOI) substrate, a germanium on insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon germanium substrate, etc.

[0084] Exemplarily, a mask layer can be formed on the substrate, and the substrate can be etched along the Z direction by using the mask layer to form a plurality of active regions extending along the Y direction and a first isolation groove located between two adjacent active regions. The etching process does not penetrate the substrate, and the etching depth along the Z direction is less than the height of the substrate along the Z direction.

[0085] Here, the process of forming the first isolation groove 404 can include, but is not limited to, dry etching (Dry Etch), wet etching (Wet Etch), or a combination thereof.

[0086] Exemplarily, the isolation material is filled in the first isolation groove to form an isolation material layer filling the first isolation groove and covering the active region; and the isolation material layer is subjected to a planarization process to form an isolation layer filling the first isolation groove and exposing the active region. The planarization process can include, but is not limited to, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP).

[0087] Here, the process of forming the isolation layer 408 can include, but is not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), spin-on dielectric (Spin-On Dielectric, SOD), or any combination thereof.

[0088] Here, the material of the isolation layer 408 can include a low dielectric constant material. For example, silicon oxide is grown by CVD using tetraethyl orthosilicate (Tetraethyl Orthosilicate, TEOS). For another example, silicon oxide is formed after spin coating and solidification.

[0089] In the embodiment of the present disclosure, in step S302, a plurality of patterned mask layers 414 extending along a second direction (i.e., the X direction) are formed on the substrate 402.

[0090] As shown in Figure 4B S302, an initial mask layer 410 covering the active region 406 and the isolation layer 408 is formed. The initial mask layer 410 can be used as a hard mask layer.

[0091] Here, the process of forming the initial mask layer 410 can include but is not limited to CVD, PVD, ALD or any combination thereof.

[0092] Here, the material of the initial mask layer 410 can include but is not limited to silicon nitride.

[0093] As shown in Figure 4C A photoresist (PR) layer is formed on the initial mask layer 410; and the photoresist layer is patterned to form a patterned photoresist layer 412 on the initial mask layer 410.

[0094] Here, according to the chemical reaction mechanism and the developing principle, the photoresist can be divided into positive resist and negative resist. For the positive resist, the positive resist itself is insoluble and becomes more easily soluble after being exposed, so it is more easily removed in the developing step. For the negative resist, the negative resist forms insoluble substances after being exposed, so it is not removed in the developing step. The pattern produced by the positive resist is the same as the pattern of the hard mask layer, and the pattern produced by the negative resist is the inverse of the pattern of the hard mask layer. Figure 4C The patterned photoresist layer 412 is illustrated by taking the positive resist as an example, which does not constitute a limitation to the protection scope of the present disclosure, and the present disclosure does not have special limitations on the type of photoresist.

[0095] As shown in Figure 4D The initial mask layer 410 is etched using the patterned photoresist layer 412 to form a plurality of patterned mask layers 414 extending along the X direction.

[0096] In the embodiment of the present disclosure, in step S303, the active region 406 is etched using the patterned mask layer 414 to form a plurality of active pillars 418 arranged in an array along a first direction (i.e., the Y direction) and a second direction (i.e., the X direction).

[0097] As shown in Figure 4D In some embodiments, step S303 includes etching the active region 406 and the isolation layer 408 along the Z direction using the patterned mask layer 414 to form a plurality of second isolation grooves 416 extending along the X direction; and the first isolation grooves 404 and the second isolation grooves 416 together divide the substrate 402 into a plurality of active pillars 418 (as shown in Figure 4DThe etching process does not penetrate the substrate, and the etching depth along the Z direction is less than the height of the substrate along the Z direction. After the active pillar 418 is formed, the patterned mask layer 414 used to form the second isolation groove 416 is retained.

[0098] Here, the process of forming the second isolation groove 416 can include, but is not limited to, dry etching, wet etching, or a combination thereof.

[0099] Here, the orthogonal projection of the active pillar 418 on the XY plane can be a quadrilateral, and the active pillar includes four side walls, two of which are oppositely arranged along the X direction, and the other two are oppositely arranged along the Y direction. Of course, the orthogonal projection of the active pillar 418 on the XY plane can also be circular or elliptical, etc. The present disclosure does not have special limitations on the shape of the orthogonal projection of the active pillar on the XY plane.

[0100] In some embodiments, the depth of the first isolation groove 404 along the Z direction is greater than the depth of the second isolation groove 416 along the Z direction. In other words, the size of the two side walls of the active pillar 418 along the X direction in the Z direction is greater than the size of the two side walls of the active pillar 418 along the Y direction in the Z direction.

[0101] Here, each active pillar 418 has a first connection end 420, a second connection end 422, and a channel region 424 between the first connection end 420 and the second connection end 422 along the Z direction. The second connection end 422 is in contact with the patterned mask layer 414.

[0102] In some embodiments, when the first connection end is the source of the transistor, the second connection end is the drain of the transistor. In other embodiments, when the first connection end is the drain of the transistor, the second connection end is the source of the transistor.

[0103] In some embodiments, the substrate can be doped before being etched to form the active pillar. In this way, the active pillar formed by etching has a doped region, which can form the first connection end, the second connection end, and the channel region. In other embodiments, the substrate can be etched to form the active pillar before being doped. In this way, the active pillar formed by etching can also have a doped region after being doped, which can form the first connection end, the second connection end, and the channel region. The present disclosure does not have special limitations on the order of doping the active pillar to form the first connection end, the second connection end, and the channel region.

[0104] As shown in FIG. 4B, the substrate 402 is etched to form the active pillar 418. The etching process does not penetrate the substrate, and the etching depth along the Z direction is less than the height of the substrate along the Z direction. After the active pillar 418 is formed, the patterned mask layer 414 used to form the second isolation groove 416 is retained. Figure 4EAs shown, in some embodiments, prior to step S304, the method further includes: removing a portion of the isolation layer 408 between adjacent active pillars 418 through the second isolation groove 416 to form a third isolation groove 426 in the first isolation groove 404 and expose the sidewalls of the active pillars 418. The depth of the third isolation groove 426 along the Z direction is less than the depth of the first isolation groove 404 along the Z direction.

[0105] Here, removing a portion of the isolation layer 408 between adjacent active pillars 418 refers to removing a portion of the isolation layer 408 between adjacent active pillars 418 along the X direction to expose the two opposing sidewalls of the active pillars 418 along the X direction. As previously described, etching forms a second isolation trench 416 to expose the two opposing sidewalls of the active pillars 418 along the Y direction, and etching forms a third isolation trench 426 to expose the two opposing sidewalls of the active pillars 418 along the X direction.

[0106] Here, the etching process for forming the third isolation trench 426 may include, but is not limited to, wet etching, vapor etching, dry etching, or any combination thereof.

[0107] In this embodiment of the present disclosure, in step S304, a gate dielectric layer 428 is formed on the sidewall of the active pillar 418.

[0108] like Figure 4F As shown, a gate dielectric layer 428 is formed covering the sidewalls of each active pillar 418.

[0109] Here, the process for forming the gate dielectric layer 428 may include, but is not limited to, in-situ steam generation (ISSG), rapid thermal oxidation (RTO), ALD, or any combination thereof.

[0110] In some embodiments, the material of the gate dielectric layer 428 may include silicon oxide or other suitable dielectric materials.

[0111] In this embodiment of the present disclosure, in step S305, conductive material is filled between adjacent active pillars 418 and covers the surface of the gate dielectric layer 428 to form a conductive material layer 432.

[0112] like Figure 4GAs shown, in some embodiments, step S305 comprises: filling the second isolation trench 416 and the third isolation trench 426 with a conductive material and covering the surface of the gate dielectric layer 428 to form an initial conductive material layer 430; the initial conductive material layer 430 also covers the surface of the patterned mask layer 414. In some embodiments, the initial conductive material layer 430 not only covers the surface of the gate dielectric layer 428, but also fills the gap between the adjacent active pillars 418. In some embodiments, the initial conductive material layer 430 covers the top surface and sidewall of the patterned mask layer 414 and the exposed bottom surface.

[0113] Here, the process of forming the initial conductive material layer 430 can include, but is not limited to, CVD, PVD, ALD or any combination thereof.

[0114] Here, the material of the initial conductive material layer 430 can include, but is not limited to, titanium nitride, tungsten, tungsten, molybdenum and polysilicon, etc.

[0115] As shown, in some embodiments, step S305 further comprises: removing the initial conductive material layer 430 covering the top surface and sidewall of the patterned mask layer 414 to form a conductive material layer 432. Figure 4H

[0116] Here, the process of removing part of the initial conductive material layer 430 can include, but is not limited to, wet etching, dry etching or a combination thereof.

[0117] In step S306, a sidewall mask layer 436 is formed on the sidewall of the patterned mask layer 414 in the embodiments of the present disclosure; wherein the patterned mask layer 414 and the sidewall mask layer 436 jointly define the position of the word line structure 438; the first direction (i.e. Y direction) and the second direction (i.e. X direction) are both parallel to the substrate 402 and the first direction and the second direction intersect.

[0118] As shown, an initial mask material layer 434 is formed covering the top surface and sidewall of the patterned mask layer 414. Figure 4I

[0119] Here, the process of forming the initial mask material layer 434 can include, but is not limited to, CVD, PVD, ALD or any combination thereof.

[0120] Here, the material of the initial mask material layer 434 can include, but is not limited to, silicon nitride, silicon oxynitride or amorphous carbon.

[0121] As shown, in some embodiments, step S307 comprises: removing the initial mask material layer 434 covering the top surface and sidewall of the patterned mask layer 414 to form a mask layer 440. Figure 4J ​​As shown, the initial mask material layer 434 covering the top surface of the patterned mask layer 414 is removed, and the initial mask material layer 434 covering the sidewall of the patterned mask layer 414 is retained, and the remaining initial mask material layer 434 forms a sidewall mask layer 436. As mentioned above, after the second isolation groove 416 is formed by etching using the patterned mask layer 414, the patterned mask layer 414 and the sidewall mask layer 436 are used together to define the position of the word line structure 438, so as to realize the reuse of the patterned mask layer 414, and reduce the process cost.

[0122] As Figure 4J As shown, in some embodiments, after step S306, the method further includes: etching the conductive material layer 432 using the patterned mask layer 414 and the sidewall mask layer 436, cutting off the conductive material layer 432 between the active pillars 418 adjacent along the Y direction, to form the word line isolation groove extending along the X direction, and form the word line structure 438 extending along the second direction (i.e., the X direction) and spaced along the first direction (i.e., the Y direction); wherein each word line structure 438 covers a plurality of active pillars 418 corresponding to the same row (extending along the X direction). By using the patterned mask layer 414 and the sidewall mask layer 436 as a mask to etch the conductive material layer 432, self-alignment during the process of forming the discrete word line structure 438 can be achieved, so as to reduce the process difficulty.

[0123] In some embodiments, after the conductive material layer is etched using the patterned mask layer and the sidewall mask layer to form the word line structure extending along the X direction and spaced along the Y direction, the method further includes: filling the insulating material between the adjacent word line structures to form a word line isolation layer; and etching the patterned mask layer to expose the second connection end.

[0124] Here, the insulating material is filled in the word line isolation groove to form the word line isolation layer extending along the X direction.

[0125] Here, the process of forming the word line isolation layer can include but is not limited to CVD, PVD, ALD or any combination thereof.

[0126] Here, the material of the word line isolation layer can include but is not limited to silicon oxide and silicon nitride.

[0127] In some embodiments, the whole patterned mask layer and / or the sidewall mask layer are removed by etching to expose the top surface of the word line structure and the second connection end, and then the insulating material is filled in the word line trench, which also covers the exposed top surface of the word line structure and the second connection end. The second connection end is exposed by other etching process later. In other embodiments, the insulating material is filled in the word line trench first, and then part of the patterned mask layer is removed by etching to expose only the second connection end. The exposure of the second connection end can effectively protect the second connection end before the structure electrically connected to the second connection end is manufactured. In some embodiments, after the patterned mask layer is etched to expose the second connection end, the method further comprises: forming a plurality of bit line structures extending along the Y direction, the bit line structure being connected to the second connection end arranged along the Y direction; thinning the substrate to expose the first connection end of the active pillar; and forming a plurality of storage node structures connected to the first connection end.

[0128] Here, the second connection end of the active pillar is exposed, and a plurality of bit line structures extending along the Y direction can be formed on the front surface of the substrate, each bit line structure being connected to a plurality of second connection ends corresponding to the same column (i.e., extending along the Y direction). After the back surface of the substrate is thinned to expose the first connection end of the active pillar, a storage node structure can be formed on the back surface of the substrate, the storage node structure being connected to the first connection end.

[0129] In some embodiments, the storage node structure can be a storage capacitor, and the semiconductor device can be a DRAM. The storage capacitor includes a first electrode plate, a second electrode plate, and a dielectric layer between the first electrode plate and the second electrode plate. The dielectric layer can be a high dielectric constant material. In other embodiments, the storage node structure can be a transistor, and the semiconductor device can be a capacitorless DRAM, such as a 1T0C or 2T0C DRAM as a storage unit.

[0130] In some embodiments, the storage node structure can be a ferroelectric capacitor, a ferroelectric transistor, or a ferroelectric tunnel junction, and the semiconductor device can be a ferroelectric random access memory (FRAM). The ferroelectric capacitor includes a first electrode plate, a second electrode plate, and a ferroelectric crystal thin film between the first electrode plate and the second electrode plate. The ferroelectric transistor includes a field effect transistor with a gate dielectric layer of ferroelectric crystal material. The ferroelectric tunnel junction includes two electrodes and a potential barrier layer of ferroelectric crystal material between the electrodes.

[0131] In some embodiments, after the patterned mask layer is etched to expose the second connection end, the method further comprises: forming a plurality of storage node structures, the storage node structures being connected to the second connection end; and thinning the substrate to expose the first connection end of the active pillar; and forming a plurality of bit line structures extending along the Y direction, the bit line structures being connected to the first connection ends arranged along the Y direction.

[0132] Here, after the second connection end of the active pillar is exposed, the storage node structure can be formed on the front surface of the substrate, the storage node structure being connected to the second connection end; the substrate is thinned to expose the first connection end of the active pillar; and a plurality of bit line structures extending along the Y direction can also be formed on the back surface of the substrate, each bit line structure being connected to a plurality of first connection ends in the same column (i.e., extending along the Y direction).

[0133] In some embodiments, before step S302, the method further comprises: forming a plurality of bit line structures extending along the Y direction in the substrate, the bit line structures being connected to the part of the active region close to the substrate; and after the patterned mask layer is etched to expose the second connection end, the method further comprises: forming a plurality of storage node structures, the storage node structures being connected to the second connection end.

[0134] Here, after the active region and the first isolation groove are also formed, a plurality of bit line structures extending along the Y direction can also be formed in the substrate, each bit line structure being connected to the part of the active region close to the substrate, i.e., a buried bit line structure is formed; after the active pillar and the second isolation groove are formed, the part of the active pillar in contact with the bit line structure is the first connection end; and a storage node structure can also be formed on the front surface of the substrate, the storage node structure being connected to the second connection end.

[0135] The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to the technical solutions described above.

[0136] Here, the gate conductive layer covering the active pillar is formed by etching the conductive material layer through the patterned mask layer and the sidewall mask layer; and the gate dielectric layer covering the sidewall of the active pillar and the gate conductive layer covering the active pillars in the same row (i.e., extending along the X direction) together form a word line structure. The orthogonal projection of the gate conductive layer on the XY plane is within the orthogonal projection of the patterned mask layer and the sidewall mask layer on the XY plane.

[0137] In some embodiments, the conductive material is filled between the active pillars in the same row, and the gate conductive layer connects the two active pillars adjacent along the X direction at different height positions in the Z direction. That is, in the orthogonal projection of the two active pillars adjacent along the X direction on the XY plane at different height positions in the Z direction, the conductive material is filled between the two active pillars adjacent along the X direction.

[0138] In some embodiments, the semiconductor device includes DRAM, FeRAM, MRAM, and PCRAM. The type of semiconductor device is not particularly limited in the present disclosure.

[0139] In some embodiments, the semiconductor device includes DRAM, FeRAM, MRAM, and PCRAM. The type of semiconductor device is not particularly limited in the present disclosure.

[0140] Here, the storage unit of the MRAM includes a transistor and a magnetic tunnel junction (MTJ); wherein the source of the transistor is connected with the source line, the gate of the transistor is connected with the word line, and the drain of the transistor is connected with the bit line through the magnetic tunnel junction. Specifically, the magnetic tunnel junction includes a fixed layer, a tunneling oxide, and a free layer in sequence; wherein the drain of the transistor is connected with the fixed layer, and the free layer is connected with the bit line. The direction of the magnetic moment of the free layer and the fixed layer is used to store information, and the resistance is low when the state is parallel; and the resistance is high when the state is not parallel. That is, the first connection end (or the second connection end) of the active pillar is connected with the source line, and the second connection end (or the first connection end) of the active pillar is connected with the bit line through the magnetic tunnel junction.

[0141] Here, the storage unit of the PCRAM generally includes 1 transistor and 1 resistance (1T1R), and the difference in electrical conductivity between the crystalline state and the amorphous state of the phase change material is used to store data. Specifically, the source of the transistor is connected with the source line, the gate of the transistor is connected with the word line, and the drain of the transistor is connected with the bit line through the phase change storage unit. Specifically, the phase change storage unit may, for example, include a heater (i.e., a lower electrode), a phase change layer, and titanium nitride (i.e., an upper electrode), and the heater heats the phase change layer to realize the conversion between the crystalline state and the amorphous state. That is, the first connection end (or the second connection end) of the active pillar is connected with the source line, and the second connection end (or the first connection end) of the active pillar is connected with the bit line through the phase change storage unit.

[0142] The present disclosure provides a semiconductor device and a manufacturing method thereof. In the present disclosure, a patterned mask layer is used to etch active regions to form a plurality of active pillars arranged in an array, and the patterned mask layer is reserved; a gate dielectric layer is formed to cover the sidewalls of the active pillars; a conductive material is filled between adjacent active pillars and covers the surface of the gate dielectric layer to form a conductive material layer; a sidewall mask layer is formed on the sidewalls of the patterned mask layer; the position of the word line structure is defined by the patterned mask layer and the sidewall mask layer reserved by the foregoing process steps, so that the use of the mask layer can be reduced to reduce the process cost; and self-alignment during the formation of the word line structure can also be achieved to reduce the process difficulty.

[0143] It should be understood that every feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, these particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the processes described above does not mean the execution order, and the execution order of the processes should be determined according to the function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence of the embodiments of the present disclosure described above is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0144] The above description is only the preferred embodiments of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made according to the disclosure content of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: providing a substrate; etching the substrate to form a plurality of first isolation grooves extending along a first direction; the first isolation grooves divide the substrate into a plurality of active regions extending along the first direction; filling isolation material in the first isolation grooves to form isolation layers between adjacent active regions; forming a plurality of patterned mask layers extending along a second direction on the substrate; etching the active regions using the patterned mask layers to form a plurality of active pillars arranged in an array along the first direction and the second direction, comprising: etching the active regions and the isolation layers using the patterned mask layers to form a plurality of second isolation grooves extending along the second direction; the first isolation grooves and the second isolation grooves collectively divide the substrate into a plurality of active pillars; removing part of the isolation layers between adjacent active pillars through the second isolation grooves to form third isolation grooves in the first isolation grooves and expose sidewalls of the active pillars; forming a gate dielectric layer on the sidewalls of the active pillars; filling a conductive material between adjacent active pillars and covering the surface of the gate dielectric layer to form a conductive material layer; forming a sidewall mask layer on the sidewalls of the patterned mask layers; wherein the patterned mask layers and the sidewall mask layer collectively define the position of the word line structure; the first direction and the second direction are both parallel to the substrate and the first direction and the second direction intersect.

2. The method of manufacturing a semiconductor device according to claim 1, wherein After forming the sidewall mask layer on the sidewalls of the patterned mask layers, the method further comprises: etching the conductive material layer using the patterned mask layers and the sidewall mask layer to form the word line structure extending along the second direction and spaced apart along the first direction; wherein the word line structure covers a plurality of active pillars arranged along the second direction.

3. The method of manufacturing a semiconductor device according to claim 1, wherein The forming a plurality of patterned mask layers extending along a second direction on the substrate comprises: forming an initial mask layer covering the active regions and the isolation layers; forming a patterned photoresist layer on the initial mask layer; etching the initial mask layer using the patterned photoresist layer to form a plurality of the patterned mask layers extending along the second direction.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein The filling a conductive material between adjacent active pillars and covering the surface of the gate dielectric layer to form a conductive material layer comprises: filling a conductive material in the second isolation grooves and the third isolation grooves and covering the surface of the gate dielectric layer to form an initial conductive material layer; the initial conductive material layer also covers the surface of the patterned mask layer; removing the initial conductive material layer covering the top surface and sidewalls of the patterned mask layer to form the conductive material layer.

5. The method of manufacturing a semiconductor device according to claim 2, wherein Each of the active pillars has a first connection end, a second connection end, and a channel region between the first connection end and the second connection end along a direction perpendicular to the substrate; After etching the conductive material layer using the patterned mask layers and the sidewall mask layer to form the word line structure extending along the second direction and spaced apart along the first direction, the method further comprises: filling insulating material between adjacent word line structures to form word line isolation layers; etching the patterned mask layer to expose the second connection end.

6. The method of manufacturing a semiconductor device according to claim 5, wherein After exposing the second connection end, the method further comprises: forming a plurality of bit line structures extending along the first direction, the bit line structures being connected with the second connection ends arranged along the first direction; performing thinning treatment on the substrate to expose the first connection ends of the active pillars; forming a plurality of storage node structures, the storage node structures being connected with the first connection ends.

7. The method of manufacturing a semiconductor device according to claim 5, wherein After exposing the second connection end, the method further comprises: forming a plurality of storage node structures, the storage node structures being connected with the second connection ends; performing thinning treatment on the substrate to expose the first connection ends of the active pillars; forming a plurality of bit line structures extending along the first direction, the bit line structures being connected with the first connection ends arranged along the first direction.

8. The method of manufacturing a semiconductor device according to claim 5, wherein Before forming a plurality of patterned mask layers extending along a second direction on the substrate, the method further comprises: forming a plurality of bit line structures extending along the first direction in the substrate, the bit line structures being connected with the portions of the active regions close to the substrate; After exposing the second connection end, the method further comprises: forming a plurality of storage node structures, the storage node structures being connected with the second connection ends.

9. A semiconductor device, characterized by comprising: The semiconductor device is manufactured by the manufacturing method of the semiconductor device according to any one of claims 1 to 8.

10. The semiconductor device of claim 9, wherein, The semiconductor device includes a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), a phase change random access memory (PCRAM), or a dynamic random access memory (DRAM). The semiconductor device includes a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), a phase change random access memory (PCRAM), or a dynamic random access memory (DRAM).

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