Structure and method of forming structure

Abstract

The disclosure relates to a method of forming a structure, a method of reducing a pitch of features on a semiconductor substrate, a method of patterning a target layer, a method of depositing a material in a gap, and a semiconductor processing assembly. The method includes providing a patterned substrate including a gap in a reaction chamber, where the gap has sidewalls, and the sidewalls are covered with a spacer material. The method further includes depositing a first metal in the gap by a vapor deposition method to at least partially fill the gap.

Description

Technical Field

[0001] The present disclosure generally relates to methods and components for processing semiconductor substrates. More specifically, the present disclosure relates to methods and components for forming structures such as metal lines. The method may include selectively etching a specific material on a semiconductor substrate. Background Art

[0002] Patterning a semiconductor substrate to form structures and semiconductor devices thereon is a multi-step process in which the properties of various materials must be considered - each material is selected to perform a function during processing or in the final device. Any simplification, improved compatibility, or uniformity during processing can have a significant impact on the feasibility of the desired pattern or device structure. In addition, the reduction in the size of semiconductor devices requires the adoption of new patterning processes to enable the reduction of the critical dimensions of adjacent structures. Therefore, new materials and their combinations have been constantly sought.

[0003] Any discussion set forth in this section, including discussions of problems and solutions, has been included in the present disclosure solely to provide background for the present disclosure. Such discussion should not be construed as an admission that any information was known at the time of the invention or constitutes prior art. Summary of the Invention

[0004] This summary of the invention may introduce some concepts in a simplified form that will be further described in detail below. This summary of the invention is not necessarily intended to identify the key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Various embodiments of the present disclosure relate to methods of forming structures, methods of reducing the pitch of features in a semiconductor substrate, methods of patterning a target layer, and methods of depositing a material in a gap. Embodiments of the present disclosure also relate to methods of manufacturing semiconductor devices and semiconductor processing components.

[0005] Various embodiments of the present disclosure relate to methods of forming structures. The method of forming a structure includes providing a patterned substrate including a gap in a reaction chamber, wherein the gap has sidewalls, and the sidewalls are covered with a spacer material. The method further includes depositing a first metal in the gap by a chemical vapor deposition method to at least partially fill the gap.

[0006] In some embodiments, the gap is formed between two primary mandrels. In some embodiments, the deposited first metal and the primary mandrels define a pattern.

[0007] In some embodiments, the gap includes a bottom, and the bottom includes a material different from the sidewalls. In some embodiments, the bottom is formed by a storage layer. In some embodiments, the bottom includes silicon.

[0008] In some embodiments, the spacer material includes silicon.

[0009] In some embodiments, the chemical vapor deposition method is a cyclic chemical vapor deposition method.

[0010] In some embodiments, the sidewalls include a second metal. In some embodiments, the first metal and the second metal are the same. In some embodiments, the first metal is deposited at least partially as elemental metal. In some embodiments, the primary mandrel is substantially formed of the second metal.

[0011] In some embodiments, the gap has a width of from about 5 nm to about 60 nm. In some embodiments, the gap has a depth of from about 5 nm to about 50 nm.

[0012] In some embodiments, the thickness of the spacer material is substantially equal to the width of the gap to be filled with the first metal. In some embodiments, after depositing the first metal in the gap, the spacer material is removed.

[0013] In some embodiments, the deposited first metal and the primary mandrel form a mask for etching the underlying material.

[0014] In one aspect, a method of reducing the pitch of features in a semiconductor substrate is disclosed. The method of reducing the pitch of features in a semiconductor substrate includes providing a patterned substrate including gaps in a reaction chamber, wherein the gaps have sidewalls and the sidewalls are covered with spacer material. The method further includes depositing a first metal in the gaps by a chemical vapor deposition method to at least partially fill the gaps.

[0015] In another aspect, a method of patterning a target layer is disclosed. The method of patterning a target layer includes providing a patterned substrate including gaps in a reaction chamber, wherein the gaps have sidewalls and the sidewalls are covered with spacer material. The method further includes depositing a first metal in the gaps by a chemical vapor deposition method to at least partially fill the gaps.

[0016] In yet another aspect, a method of depositing a material in a gap is disclosed. The method of depositing a material in a gap includes providing a patterned substrate including gaps in a reaction chamber, wherein the gaps have sidewalls and the sidewalls are covered with spacer material. The method further includes depositing a first metal in the gaps by a chemical vapor deposition method to at least partially fill the gaps.

[0017] The methods according to the present disclosure can be used to fabricate semiconductor devices. Accordingly, a method of fabricating a semiconductor device is disclosed.

[0018] In another aspect, a semiconductor processing assembly is disclosed. The semiconductor processing assembly includes a reaction chamber and a controller and is configured and arranged to perform the methods disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the disclosure and constitute a part of this specification, illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure.

[0020] In the drawings:

[0021] Figure 1 is a block diagram of an exemplary embodiment of a method according to the disclosure.

[0022] Figure 2 a) to h) in are schematic diagrams of exemplary embodiments of a method according to the disclosure.

[0023] Figure 3 is a schematic diagram of an embodiment of a semiconductor processing component according to the disclosure.

[0024] It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations for describing embodiments of the disclosure. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to assist in improving understanding of the illustrated embodiments of the disclosure. Detailed Description

[0025] The following description of exemplary embodiments of methods, structures, and semiconductor processing components provided is merely exemplary and for illustrative purposes only. The following description is not intended to limit the scope of the disclosure or the claims. Additionally, the recitation of multiple embodiments with the indicated features is not intended to exclude other embodiments having additional features or other embodiments combining different combinations of the recited features. For example, various embodiments are set forth as exemplary embodiments and may be recited in the dependent claims. Unless otherwise stated, the exemplary embodiments or their components may be combined or may be applied separately from one another.

[0026] The headings (if any) provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed subject matter.

[0027] In one aspect, a method of forming a structure is disclosed. The method includes providing a patterned substrate including gaps in a reaction chamber, where the gaps have sidewalls and the sidewalls are covered with spacer material. The method further includes depositing a first metal in the gaps by a chemical vapor deposition method to at least partially fill the gaps.

[0028] The deposition method according to the present invention includes providing a substrate in a reaction chamber. The substrate can be any one or more underlying materials that can be used to form or on which structures, devices, circuits, or layers can be formed. The substrate can include a bulk material, such as silicon (e.g., single-crystalline silicon), other Group IV materials, such as germanium, or other semiconductor materials, such as Group II-VI or Group III-V semiconductor materials, and can include one or more layers covering or underlying the bulk material. Additionally, the substrate can include various features, such as depressions, protrusions, etc., formed in or on at least a portion of the layers of the substrate. For example, the substrate can include a bulk semiconductor material and a layer of insulating or dielectric material covering at least a portion of the bulk semiconductor material. The substrate can include nitrides, such as TiN, oxides, insulating materials, dielectric materials, conductive materials, metals, such as tungsten, ruthenium, molybdenum, cobalt, aluminum, or copper, or metallic materials, crystalline materials, epitaxial materials, heteroepitaxial materials, and / or single-crystalline materials. In some embodiments of the present disclosure, the substrate includes silicon. As described above, in addition to silicon, the substrate can include other materials. The other materials can form layers. Specifically, the substrate can include a partially fabricated semiconductor device.

[0029] In some embodiments, the substrate can be pretreated or cleaned before or at the start of the deposition method according to the present disclosure. In some embodiments, the substrate can be subjected to a plasma cleaning process before or at the start of the deposition method. In some embodiments, the plasma cleaning process can not include ion bombardment, or can include a relatively small amount of ion bombardment. For example, in some embodiments, the surface of the substrate can be exposed to plasma, radicals, excited species, and / or atomic species before or at the start of a selective deposition method. In some embodiments, the surface of the substrate can be exposed to a hydrogen plasma, radicals, or atomic species before or at the start of the deposition method. In some embodiments, the pretreatment or cleaning process can be performed in the same reaction chamber as the selective deposition method. However, in some embodiments, the pretreatment or cleaning process can be performed in a separate reaction chamber.

[0030] A substrate according to the present disclosure is a patterned substrate. A patterned substrate according to the present disclosure refers to a substrate that includes a pattern thereon or therein. For the purposes of the present disclosure, a pattern includes a gap. The gaps in the present disclosure are in or on the substrate. A gap should be understood as describing a change in the substrate surface topology that results in some regions of the substrate surface being lower than other regions. Thus, a gap includes a topological structure where a portion of the substrate surface is lower than most of the substrate surface. These include trenches, vias, grooves, valleys, cracks, etc. In addition, the regions between protruding features where most of the substrate surface protrudes upward also form gaps. Thus, the space between adjacent fins or pillars is considered a gap. A gap can include a top and a bottom. The upper part of the gap is the region at the gap opening, and the bottom of the gap is the portion of the gap away from the gap opening. The region outside the gap is called the top surface of the gap, such as the highest horizontal part of a fin or pillar, or the substrate region between holes or vias. The sidewall is the surface connecting the top and bottom of the gap.

[0031] A method of forming a structure according to the present disclosure includes providing a patterned substrate in a reaction chamber. In other words, the substrate is in a space where deposition conditions can be controlled. The reaction chamber can be a single-wafer reactor. Alternatively, the reaction chamber can be a batch reactor. The reaction chamber can form part of a gas-phase processing assembly for manufacturing semiconductor devices. The gas-phase processing assembly can include one or more multi-station processing chambers. The reaction chamber can be part of a cluster tool in which different processes are performed to form an integrated circuit. The various stages of the method can be carried out in a single reaction chamber, or they can be carried out in multiple reaction chambers, such as the reaction chambers of a cluster tool, or the deposition stations of a multi-station processing chamber.

[0032] In some embodiments, the reaction chamber can be a flow-type reactor, such as a cross-flow reactor. In some embodiments, the reaction chamber can be a showerhead reactor. In some embodiments, the reaction chamber can be a hot-wall reactor. In some embodiments, the reaction chamber can be a spatially-separated reactor. In some embodiments, the reaction chamber can be a single-wafer ALD reactor. In some embodiments, the reaction chamber can be a large-scale manufacturing single-wafer ALD reactor. In some embodiments, the reaction chamber can be a batch reactor for simultaneously manufacturing multiple substrates.

[0033] The reaction chamber can form part of an atomic layer deposition (ALD) assembly. The reaction chamber can form part of a chemical vapor deposition (CVD) assembly. The vapor deposition assembly can be an ALD or CVD deposition assembly, but in some process steps, MLD can also be used for certain parts of the deposition process flow. In some embodiments, the method is performed in a single reaction chamber of a combination tool, but other, previous, or subsequent manufacturing steps of the structure or device are performed in additional reaction chambers of the same combination tool. Optionally, the assembly including the reaction chamber can be provided with a heater to activate the reaction by raising the temperature of one or more substrates and / or reactants and / or precursors.

[0034] In this method, a first metal is deposited in the gap by a vapor deposition method to at least partially fill the gap. The vapor deposition method according to the present disclosure refers to the process of depositing a material from a gas phase onto a substrate. In the present disclosure, "gas" can include materials that are gases at normal temperature and pressure (NTP), evaporated solids, and / or evaporated liquids, and can consist of a single gas or a gas mixture depending on the context. One or more precursors for depositing the first metal (i.e., the first metal precursors) can be provided to the reaction chamber in the gas phase. The first metal precursors can be provided to the reaction chamber in the gas phase.

[0035] The term "inert gas" can refer to a gas that does not participate in a chemical reaction and / or does not become part of the layer to a perceptible extent. Exemplary inert gases include He and Ar and any combination thereof. In some cases, molecular nitrogen and / or hydrogen can be inert gases. Gases other than the process gases, i.e., gases that are not introduced through a precursor injector system, other gas distribution devices, etc., can be used, for example, to seal the reaction space and can include sealing gases.

[0036] In some embodiments, depositing the first metal includes a cyclic deposition process (i.e., a cyclic vapor deposition method). Generally, in the cyclic deposition process according to the present disclosure, such as atomic layer deposition (ALD) and molecular layer deposition (MLD), during each cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the substrate surface (e.g., a substrate surface that may include previously deposited material from a previous deposition cycle or other materials). In some embodiments, the precursor on the substrate surface does not readily react with additional precursors (i.e., the deposition of the precursor can be a partially or fully self-limiting reaction). Thereafter, another precursor or reactant can be introduced into the reaction chamber for converting the chemisorbed precursor into the desired material on the deposition surface. The second precursor or reactant is capable of further reacting with the precursor. During one or more cycles, e.g., during each step of each cycle, a purge step can be utilized to remove any excess precursor from the processing chamber and / or any excess reactant and / or reaction by-products from the reaction chamber. Thus, in some embodiments, the cyclic deposition process includes purging the reaction chamber after providing the first metal precursor into the reaction chamber. In some embodiments, the cyclic deposition process includes purging the reaction chamber after providing an additional reactant (e.g., a reducing agent) into the reaction chamber. In some embodiments, the cyclic deposition process includes purging the reaction chamber after providing the first metal precursor into the reaction chamber and after providing the additional reactant into the reaction chamber. Without limiting the present disclosure to any specific theory, ALD and MLD can be similar processes in terms of self-limiting reactions and a slower and more controllable layer growth rate compared to CVD. Generally, ALD is used to deposit inorganic materials, while in MLD, the precursors can be fully organic molecules.

[0037] The process can include one or more cyclic stages. In some embodiments, the process includes one or more non-cyclic (i.e., continuous) stages. In some embodiments, the deposition process includes a continuous flow of at least one precursor. In such embodiments, the process includes a continuous flow of a first polymer precursor or a second polymer precursor. In some embodiments, one or more precursors are continuously provided in the reaction chamber.

[0038] CVD processes are characterized by vapor deposition and are not self-limiting. They typically involve gas-phase reactions between two or more precursors and / or reactants. The precursors and reactants can be supplied to the reaction space or substrate simultaneously or in partially or fully separated pulses. However, CVD can be carried out with a single precursor or two or more precursors that do not react with each other. The single precursor can decompose into reactive components that deposit on the substrate surface. For example, the decomposition can be carried out by plasma or thermal methods. The substrate and / or reaction space can be heated to facilitate the reaction between the gaseous precursors and / or reactants. In some embodiments, the precursors and reactants are supplied until a layer of the desired thickness is deposited. In some embodiments, a cyclic CVD process can use multiple cycles to deposit a thin film of the desired thickness. In a cyclic CVD process, the precursors and / or reactants can be supplied to the reaction chamber in the form of non-overlapping or partially or fully overlapping pulses. In some embodiments, depositing a first metal includes a CVD process.

[0039] In some embodiments, the method according to the present disclosure includes a thermal deposition process. In thermal deposition, a temperature elevated relative to ambient temperature promotes a chemical reaction. Generally, in the absence of other external energy sources (such as plasma, free radicals, or other forms of radiation), the temperature elevation provides the energy required to form the target material. In some embodiments, the method according to the present disclosure includes a plasma-enhanced deposition method, such as PEALD or PECVD. For example, in some embodiments, deposition can be carried out by PEALD or PECVD.

[0040] As used herein, the term "comprising" means including certain features, but does not exclude the presence of other features, provided they do not render the claim infeasible. In some embodiments, the term "comprising" encompasses "consisting of".

[0041] As used herein, the term "consisting of" means that no other features are present in the device / method / product other than the features following the stated phrase. When the term "consisting of" is used to refer to a chemical compound, substance, or composition of matter, it means that the chemical compound, substance, or composition of matter contains only the listed components. Similarly, when the term "consisting essentially of" is used to refer to a chemical compound, substance, or composition of matter, it means that the chemical compound, substance, or composition of matter contains the listed components, but may also contain trace elements and / or impurities that do not significantly affect the characteristics of the chemical compound, substance, or composition of matter. Nevertheless, in some embodiments, the chemical compound, substance, or composition of matter can include other components as trace elements or impurities in addition to the listed components.

[0042] In addition, in the present disclosure, any two numbers of a variable can form a feasible range of the variable, and any indicated range may or may not include endpoints. Further, any value of the indicated variable (whether or not denoted by "about") can refer to an exact value or an approximate value, and includes equivalents, and can refer to an average value, a median value, a representative value, a majority value, etc. In addition, in the present disclosure, the terms "comprising", "consisting of", and "having" independently refer to "generally or broadly comprising", "including", "substantially consisting of", or "consisting of" in some embodiments. In the present disclosure, in some embodiments, the meaning of any defined term does not necessarily exclude the ordinary and customary meanings.

[0043] The term "substantially" as applied to a composition, method, or system generally means that additional components do not substantially change the nature and / or function of the composition, method, or system.

[0044] The term "substantially" as applied to a composition, method, or system generally means a proportion of a value, property, characteristic, etc., or conversely the lack thereof, i.e., at least about 70%, at least about 80%, at least about 90%, at least about 95%, at least about 97%, at least about 98%, at least about 99%, at least about 99.5%, at least about 99.9% or higher, or any proportion between about 70% and about 100%. In some embodiments, the term "substantially" means a proportion of about 90%, about 95%, about 97%, about 98%, about 99%, about 99.5%, or about 99.9%.

[0045] In the specification, it should be understood that the terms "on" or "above" can be used to describe a relative positional relationship. Another element, film, or layer can be directly on the layer, or another layer (intermediate layer) or element can be inserted therebetween, or a layer can be disposed on the layer but not completely cover the surface of the layer. Thus, unless the term "directly" is used alone, the terms "on" or "above" will be interpreted as relative concepts. Similarly, it should be understood that the terms "under", "below", or "beneath" will be interpreted as relative concepts.

[0046] The present disclosure is further explained by the following exemplary embodiments depicted in the accompanying drawings. The diagrams given herein are not meant to be actual views of any particular material, structure, or component, but are merely schematic representations describing embodiments of the present disclosure. It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the present disclosure. The structures, devices, and components depicted in the drawings may contain additional elements and details, which may be omitted for clarity.

[0047] For the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the methods and components described herein may not be described in detail. Additionally, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and / or physical couplings between various elements. Many alternative or additional functional relationships or physical connections may exist in the actual system, and / or may not exist in some embodiments.

[0048] Figure 1 is a block diagram of an exemplary embodiment of method 100 according to the present disclosure. In stage 102, as disclosed herein, a patterned substrate including gaps is provided in a reaction chamber. The gaps can form part of a partially fabricated semiconductor device. In some embodiments, the gaps are formed between two primary mandrels. The primary mandrels can be features for forming structures that can be narrower than those achievable by EUV lithography techniques, which aim for feature pitch dimensions from about 18 nm to about 14 nm. For example, in some embodiments, each mandrel defines a metal line in the final structure. In the present disclosure, the primary mandrels are formed by a patterning process prior to the method according to the present disclosure. The secondary mandrels in the present disclosure refer to the mandrels formed by this process. In some embodiments, the present method is used to increase the feature density on a semiconductor substrate, i.e., to reduce the pitch of the metal lines. Thus, the primary mandrels and the secondary mandrels define the line density. In some embodiments, the primary mandrels and the secondary mandrels have substantially the same composition. The advantage of such an embodiment is that any subsequent etching is uniform and the device manufacturing process is easier to optimize. As described above, the gaps according to the present disclosure include sidewalls, and the sidewalls are covered with spacer material. Various spacer materials are known in the art and are described in further detail below.

[0049] In block 104, the gaps are at least partially filled with a first metal by using a vapor deposition method. The gaps have sidewalls, and the sidewalls are covered with spacer material. Thus, the gap width is the distance between two adjacent primary mandrels covered by the spacer material. The vapor deposition method can be an ALD method, a CVD method, such as a cyclic CVD method, or a hybrid method having features of both ALD and CVD methods. In some embodiments, the gaps are substantially filled with the first metal. The gaps can be overfilled, and the excess first metal can be removed and the structure can be planarized by chemical mechanical polishing (CMP). In some embodiments, the deposition can be optimized such that no CMP stage is required.

[0050] In embodiments where the gaps are formed between two adjacent primary mandrels, depositing the first metal in the gaps creates secondary mandrels. The secondary mandrels are formed between the two primary mandrels, and the thickness of the spacer material determines the distance of the secondary mandrels to each primary mandrel. The width of the secondary mandrels is determined by the distance between the primary mandrels and the spacer material covering them.

[0051] As shown in selection box 106, in some embodiments, after depositing the first metal in the gap, the spacer material is removed. The etching method is selected based on the nature of the spacer material from dry and wet etching techniques known in the prior art. Removing the spacer material will expose the first mandrel and the secondary mandrel, which together will form a secondary gap. The width of the secondary gap is determined by the thickness of the spacer material. Fabrication of the target device can continue, for example, by etching the bottom of the secondary gap. In an embodiment where the first metal is molybdenum and the primary mandrel is formed of molybdenum (i.e., the second metal is molybdenum), the spacer material can advantageously be selected from silicon-containing materials such as silicon oxide and silicon nitride. Silicon oxide and silicon nitride form a suitable etch contrast with molybdenum, and the adhesion between these materials is better than some alternative material combinations.

[0052] Figure 2 a) through h) in are schematic diagrams of exemplary embodiments of the method according to the present disclosure. For clarity, several processing steps are omitted from the figures, and each panel may indicate the result after multiple processing steps.

[0053] Figure 2 a) in depicts a partially fabricated semiconductor device 200. In FIG. a) and subsequent figures, the bottommost portion is the surface of the silicon substrate layer 202 on which multiple material layers have been formed. Depending on the intended device structure, layer 202 can also be a different type of layer. The first layer on layer 202 is a metal layer, such as a ruthenium (Ru) layer 204, which will form metal lines after multiple processing steps. On top of the metal layer 204 is an optional adhesion layer 206, which can include, for example, titanium nitride (TiN). In an embodiment, the adhesion layer is used to improve the adhesion between the metal layer and the storage layer, which otherwise would be insufficient. The storage layer 208 is located on the adhesion layer, and the storage layer can include silicon, such as silicon oxide (SiO2) or silicon nitride (SiN). The storage layer is a layer used in applications where there is insufficient etch contrast between the target pattern layer 210 and the metal layer 204. The storage layer is used to maintain the patterning of the target pattern layer 210 (formed by the primary and secondary mandrels) after etching the target pattern layer. Figure 2 The next layer in the embodiment of is the target pattern layer 210, which can be a metal layer, such as a molybdenum layer. The target pattern layer 210 is covered by a hard mask 212. The hard mask can be formed of, for example, amorphous carbon, amorphous silicon, silicon oxide, or silicon nitride. In Figure 2 a) in, the hard mask 212 is not patterned. However, depending on the selected processing sequence, there can be additional layers on top of the hard mask 212, but they are omitted from the figure for simplicity.

[0054] In Figure 2 b) in, an initial pattern for forming the primary mandrel is formed in the hard mask 212.

[0055] In Figure 2 in c), a hard mask has been used to create a primary mandrel according to the present disclosure, and the target pattern layer 210, such as a molybdenum layer, is represented by a separate mandrel 210, and the hard mask 212 has been removed using conventional methods.

[0056] In Figure 2 in d), a spacer material 214 has been formed on the mandrel. For example, ALD or MLD can be used to deposit the spacer material. In some embodiments, the spacer material 214 is conformally deposited. Conformal deposition by ALD can result in a uniform thickness of the spacer material 214 throughout the structure. For example, the initially deposited spacer material 214 can be removed by dry etching. Transitioning from the processing stage shown in Figure 2 c) to the processing stage shown in Figure 2 d) may require multiple steps, including deposition, etching, CMP, or other cleaning steps. In some embodiments, the spacer material 214 includes silicon. In some embodiments, the spacer material 214 includes amorphous silicon. In some embodiments, the spacer material 214 consists of or consists essentially of amorphous silicon. In some embodiments, the spacer material 214 includes silicon oxide. In some embodiments, the spacer material 214 consists of or consists essentially of silicon oxide. In some embodiments, the spacer material 214 includes silicon nitride. In some embodiments, the spacer material 214 consists of or consists essentially of silicon nitride. In some embodiments, the spacer material 214 includes titanium. In some embodiments, the spacer material 214 includes titanium oxide. In some embodiments, the spacer material 214 consists of or consists essentially of titanium oxide. In some embodiments, the spacer material 214 includes titanium nitride. In some embodiments, the spacer material 214 consists of or consists essentially of titanium nitride. In some embodiments, the spacer material 214 includes titanium oxynitride. In some embodiments, the spacer material 214 consists of or consists essentially of titanium oxynitride. In some embodiments, the spacer material 214 includes tungsten. In some embodiments, the spacer material 214 includes tungsten carbide (WC). In some embodiments, the spacer material 214 consists of or consists essentially of tungsten carbide. In some embodiments, the spacer material 214 includes tungsten nitride. In some embodiments, the spacer material 214 consists of or consists essentially of tungsten nitride. In some embodiments, the spacer material 214 includes tungsten carbonitride. In some embodiments, the spacer material 214 consists of or consists essentially of tungsten carbonitride.

[0057] The composition and other properties of the spacer material 214 itself are not important as long as the sidewalls of the mandrel 210 can be uniformly covered with a desired thickness by it, and there is an etch contrast between the spacer material 214 on the one hand and the primary mandrel 210 and the secondary mandrel on the other hand. Thus, the spacer is used to define the distance (i.e., the pitch) between the primary mandrel and the secondary mandrel.

[0058] Figure 2 The stage depicted in d) above shows the gap to be filled in the present method. As described above, in the method according to the present disclosure, the sidewalls are covered with spacer material 214. In other words, each gap is lined with spacer material 214, such as amorphous silicon, silicon oxide, or silicon nitride. In some embodiments, for example Figure 2 in the embodiment depicted in d) above, the gap is formed between two primary mandrels 210.

[0059] Figure 2 d) above shows such an embodiment, where the gap includes a bottom, and the bottom includes a material different from the sidewalls. In some embodiments, the bottom of the gap includes silicon. In some embodiments, the bottom of the gap includes silicon oxide. In some embodiments, the bottom of the gap includes silicon nitride. In some embodiments, for example, in Figure 2 the embodiment of, the bottom of the gap is formed by a storage layer. The storage layer can be used in such applications where the materials of the primary mandrel and the optional secondary mandrel.

[0060] The sidewalls are formed of a metal (such as molybdenum) of the target patterning layer 210. Thus, in Figure 2 the embodiment of, the sidewalls include a second metal. In some embodiments, the sidewalls are formed of or consist essentially of the second metal. In some embodiments, the second metal exists as an elemental metal. In some embodiments, the sidewalls are formed of or consist essentially of only the elemental second metal. In Figure 2 the embodiment of, the primary mandrel 210 consists essentially of the second metal. Thus, the primary mandrel is formed essentially of the second metal. The second metal can be molybdenum. In some embodiments, the first metal is molybdenum and the second metal is molybdenum. Such an embodiment (where the first metal and the second metal are the same) may have advantages for further manufacturing steps of the target semiconductor device. In such an embodiment, the primary and secondary mandrels can have substantially or exactly the same composition, which can allow for uniform etching and simplify the design and reliability of downstream processing. For example, when the compositions of the primary and secondary mandrels are the same, the composition of the storage layer 208 may be easier to select.

[0061] The method according to the present disclosure further includes depositing a first metal in the gap by a vapor deposition method to at least partially fill the gap. In some embodiments, the vapor deposition method is a cyclic vapor deposition method. The result of such a deposition process is shown in Figure 2 e) above. Figure 2 e) above shows the primary mandrels (210, vertically hatched), secondary mandrels (216, horizontally hatched), and the spacer material (210, black) between each primary mandrel (210) and secondary mandrel (216) deposited according to the present invention.

[0062] In Figure 2 the embodiments, the thicknesses of the primary mandrel, the secondary mandrel, and the spacer are shown to be substantially equal. Thus, in Figure 2 the embodiments, the thickness of the spacer material is substantially equal to the width of the gap to be filled with the first metal. Further, the width of the primary mandrel is substantially equal to the thickness of the spacer material.

[0063] In some embodiments, the thicknesses of the primary mandrel and the secondary mandrel are substantially the same. In such embodiments, the primary mandrel and the secondary mandrel define metal lines of substantially equal width. The thickness of the spacer material 214 may be different from the thicknesses of the primary mandrel 210 and the secondary mandrel 216. Thus, in some embodiments, the spacer material is thicker than the widths of the primary mandrel and the secondary mandrel. In some embodiments, the spacer material is thinner than the widths of the primary mandrel and the secondary mandrel.

[0064] In some embodiments, the distance between the primary mandrels is from about 5 nm to about 60 nm, such as from about 10 nm to about 60 nm or from about 20 nm to about 60 nm, or from about 5 nm to about 30 nm or from about 5 nm to about 20 nm. In some embodiments, the distance between the primary mandrels is about 30 nm. In some embodiments, the distance between the primary mandrels is about 40 nm. In some embodiments, the distance between the primary mandrels is about 50 nm. In some embodiments, the distance between the primary mandrels is from about 30 to about 60 nm. In some embodiments, the distance between the primary mandrels is from about 40 to about 60 nm. In some embodiments, the distance between the primary mandrels is from about 20 to about 40 nm.

[0065] In some embodiments, the gap (i.e., the distance between adjacent layers of the spacer material 214) has a width-to-depth ratio ranging from about 1:1 to about 1:20.

[0066] In some embodiments, the thickness of the spacer material — which defines the distance between the metal lines in the final structure — is from about 1 nm to about 20 nm. For example, the thickness of the spacer material can range from about 5 nm to about 10 nm, such as about 6 nm or about 8 nm. Alternatively, for thin metal lines, thicknesses below 5 nm, such as 3 nm, can be contemplated. Conversely, forming thicker metal lines by the methods disclosed herein may be advantageous in some applications.

[0067] In some embodiments, the width of the primary mandrel 210 ranges from about 4 nm to about 15 nm, such as from about 5 nm to about 10 nm. For example, the width of the primary mandrel 210 can range from about 7 nm to about 9 nm. In an exemplary embodiment, the width of the primary mandrel 210 is about 7 nm, about 8 nm, about 10 nm, or about 12 nm.

[0068] The width of the deposited first metal 216 that forms the secondary mandrel is from about 4 nm to about 15 nm, such as from about 5 nm to about 10 nm, and is selected independently of the width of the primary mandrel 210. For example, the width of the primary mandrel 216 can range from about 7 nm to about 9 nm. In an exemplary embodiment, the width of the primary mandrel 210 is about 7 nm, about 8 nm, about 10 nm, or about 12 nm.

[0069] The height of the primary and secondary mandrels depends on the thickness of the target pattern layer 210. In some embodiments, the thickness of the target patterned layer 210 is from about 5 nm to about 60 nm, such as from about 10 nm to about 60 nm, such as about 15 nm, about 20 nm, or about 30 nm, about 40 nm, or about 50 nm. For example, the thickness of the target patterned layer 210 can be from about 5 nm to about 50 nm, or from about 5 nm to about 40 nm, or from about 5 nm to about 30 nm, or from about 30 nm to about 60 nm. In some embodiments, the gap has the same depth as the target pattern layer 210, i.e., from about 5 nm to about 60 nm.

[0070] There are various options for depositing the first metal. For example, halogen-containing metal precursors and metal-organic precursors are known in the art of depositing metals such as molybdenum.

[0071] In some embodiments, the first metal precursor is selected from metal-organic precursors and inorganic precursors. In some embodiments, the first metal precursor includes metal halides. For example, the first metal precursor can be selected from NbCl5, NbF5, TaCl5, TaF5, TaI5, TaBr5, MoCl5, MoCl6, MoF6, WCl5, WCl6, and WF6.

[0072] In some embodiments, the first metal precursor includes metal oxychlorides. In some embodiments, the first metal precursor includes oxychlorides selected from MoOCl4, MoO2Cl2, WOCl4, and WO2Cl2.

[0073] In some embodiments, the first metal can include molybdenum, and molybdenum can be deposited using a cyclic vapor deposition method, such as ALD. Thus, depositing the first metal in the gap can include contacting the substrate alternately and sequentially with a molybdenum precursor and a second gaseous reactant such as a reducing agent. In some embodiments, depositing the first metal can include depositing molybdenum by ALD, and the deposition method includes deposition cycles, and the deposition cycles include contacting the substrate with a gaseous molybdenum precursor and contacting the substrate with a second gaseous reactant such as a reducing agent. The reaction chamber can be purged after at least one of the molybdenum precursor and the second gaseous reactant.

[0074] In some embodiments, the deposition cycle for depositing a first metal (e.g., molybdenum) includes a first metal phase that includes contacting a substrate with a first gas-phase reactant that includes a molybdenum precursor. The terms "precursor" and "reactant" can refer to molecules (compounds or molecules containing a single element) that participate in a chemical reaction to produce another compound or element. A precursor typically includes at least a portion that is incorporated into the compound or element produced by the chemical reaction. The resulting compound or element can be deposited on the substrate. In some cases, the reactant is a precursor. In other cases, the compound or element produced by the chemical reaction does not include a portion of the reactant (the elements or groups within the reactant), and thus the reactant is not a precursor. In some embodiments, the precursor or reactant is provided as a mixture of two or more compounds. In the mixture, other compounds in addition to the precursor can be inert compounds or elements. In some embodiments, the precursor or reactant is provided in a composition. The composition can be a solution or a gas under standard conditions. In embodiments of the present disclosure, the first metal precursor is used to deposit the first metal in the gap. In some embodiments, the first metal is molybdenum, and accordingly, a molybdenum precursor is used.

[0075] In some embodiments, the molybdenum precursor can include molybdenum and a halogen, such as chloride. In some embodiments, the molybdenum precursor can include molybdenum, a halogen, and a chalcogen element, where the chalcogen element can include oxygen. In some embodiments, the molybdenum precursor includes at least one of molybdenum pentachloride (MoCl5) and molybdenum dioxide dichloride (MoO2Cl2). In some embodiments, the molybdenum precursor can be pulsed into the reaction chamber over a time period of less than 20 seconds or less than 10 seconds or less than 5 seconds or less than 1 second.

[0076] The excess first metal precursor (e.g., MoCl5 or MoO2Cl2) and reaction by-products (if any) can be removed from the substrate surface by purging with an inert gas. The excess second gas-phase reactant and any reaction by-products can be removed by means of the vacuum generated by the pumping system.

[0077] In the second stage of the deposition cycle, a first metal, such as molybdenum, is deposited using an inorganic first metal precursor. The deposition cycle can include a metallization stage in which the substrate is exposed to a second gaseous reactant, such as one or more reducing agents, which react with the molybdenum precursor or its derivatives present on the substrate to form the first metal, such as elemental molybdenum. Thus, in some embodiments of the present disclosure, the second stage of the deposition cycle includes contacting the semiconductor substrate with a reducing agent. The reducing agent can be selected from molecular hydrogen (H2), hydrogen radicals, hydrazine and hydrazine derivatives, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), germane (GeH4), digermane (Ge2H6), or diborane (B2H6). In some embodiments of the present disclosure, the reducing agent can include hydrogen (H2) or hydrogen radicals, atoms, or plasmas, i.e., excited hydrogen species generated using a hydrogen plasma (e.g., remote or direct plasma). In some embodiments, the reducing agent can include higher-order silanes having the general empirical formula Si x H (2x+2) . In some embodiments, the reducing agent can include higher-order germanes having the general empirical formula Ge x H (2x+2) . In some embodiments, the reducing agent can be pulsed into the reaction chamber for a period of less than 20 seconds, or less than 10 seconds, or less than 5 seconds, or less than 1 second. In some embodiments, the first metal precursor is MoO2Cl2 and the reducing agent is molecular hydrogen. In some embodiments, the first metal precursor is MoCl5 and the reducing agent is molecular hydrogen.

[0078] In some embodiments, the first metal precursor is a molybdenum precursor, and the molybdenum precursor includes molybdenum atoms and hydrocarbon ligands. In some embodiments, the molybdenum precursor includes a metal-organic compound containing molybdenum. Thus, the molybdenum precursor is a metal-organic precursor. A metal-organic precursor herein refers to a molybdenum precursor containing molybdenum atoms and hydrocarbon ligands, wherein the molybdenum atoms are not directly bonded to carbon atoms. In some embodiments, the metal-organic precursor contains one molybdenum atom that is not directly bonded to a carbon atom. In some embodiments, the metal-organic precursor contains two or more molybdenum atoms, none of which is directly bonded to a carbon atom. In some embodiments, the metal-organic precursor contains two or more metal atoms, at least one of which is not directly bonded to a carbon atom.

[0079] In some embodiments, the molybdenum precursor comprises an organometallic compound containing molybdenum. Thus, the molybdenum precursor is an organometallic precursor. An organometallic precursor herein refers to a molybdenum precursor containing molybdenum atoms and hydrocarbon ligands, wherein the molybdenum atoms are directly bonded to carbon atoms. In embodiments where the organometallic precursor contains two or more metal atoms, all of the metal atoms are directly bonded to carbon atoms. In some embodiments, the molybdenum precursor contains only molybdenum, carbon, and hydrogen. In other words, the molybdenum precursor does not contain oxygen, nitrogen, or other additional elements. In some embodiments, the molybdenum precursor includes at least two hydrocarbon ligands. In some embodiments, the molybdenum precursor includes at least three hydrocarbon ligands. In some embodiments, the molybdenum precursor includes four hydrocarbon ligands. In some embodiments, the molybdenum precursor includes a hydrocarbon ligand and a hydride ligand. In some embodiments, the molybdenum precursor includes a hydrocarbon ligand and two or more hydride ligands. In some embodiments, the molybdenum precursor includes two hydrocarbon ligands and two hydride ligands.

[0080] In some embodiments, the molybdenum precursor includes a cyclic moiety. For example, the molybdenum precursor may contain one or more benzene rings. In some embodiments, the molybdenum precursor includes two benzene rings. One or two of the benzene rings may contain hydrocarbon substituents. In some embodiments, each benzene ring of the molybdenum precursor contains an alkyl substituent. The alkyl substituent may be methyl, ethyl, or a straight-chain or branched alkyl containing three, four, five, or six carbon atoms. For example, the alkyl substituent of the benzene ring may be n-propyl or isopropyl. Additionally, the alkyl substituent may be in the n-, iso-, tert-, or sec- form of a butyl, pentyl, or hexyl moiety. In some embodiments, the molybdenum precursor includes bis(ethylbenzene)molybdenum, consisting of or consisting essentially of bis(ethylbenzene)molybdenum.

[0081] In some embodiments, the molybdenum precursor includes a cyclopentadienyl (Cp) ligand. For example, the molybdenum precursor may include MoCp2Cl2 or MoCp2H2, Mo(iPrCp)2Cl2, Mo(iPrCp)2H2, Mo(EtCp)2H2, or consisting of or consisting essentially of the same.

[0082] In some embodiments, the molybdenum precursor includes a carbonyl ligand. For example, the molybdenum precursor may include Mo(CO)6, Mo(1,3,5-cycloheptatriene)(CO)3, consisting of or consisting essentially of the same. Additionally, in some embodiments, the molybdenum precursor includes a nitrosyl ligand. For example, the molybdenum precursor may include MoCp(CO)2(NO), consisting essentially of or consisting of the same.

[0083] In embodiments using an organometallic or metal-organic first metal precursor, the metallization stage may include providing a reducing agent to the reaction chamber as described above. Alternatively, the metallization stage may include providing a halogenated reactant to the reaction chamber. The reactant may include a halogenated hydrocarbon. The halogenated hydrocarbon may contain one halogen atom. The halogenated hydrocarbon may contain one or more halogen atoms. The halogenated hydrocarbon may contain two halogen atoms. The halogenated hydrocarbon may contain two or more halogen atoms. The halogenated hydrocarbon may contain three halogen atoms. The halogenated hydrocarbon may contain three or more halogen atoms.

[0084] In some embodiments, the halogenated hydrocarbon contains at least two halogen atoms attached to different carbon atoms. The reactant may include a hydrocarbon containing at least two carbon atoms attached to each other. The reactant may contain three carbon atoms. Additionally, the reactant may contain four, five, or six carbon atoms. The reactant may include straight-chain, branched-chain, cyclic, and / or aromatic carbon chains. For example, the reactant may include bromoethane, propane, 2-methylpropane, 2,2-dimethylpropane (neopentane), n-butane, 2-methylbutane, 2,2-dimethylbutane, n-pentane, 2-methylpentane, 3-methylpentane, or n-hexane. In some embodiments, the halogenated hydrocarbon includes halogenated benzene. In some embodiments, the halogenated hydrocarbon includes a compound composed of a halogen atom and a hydrocarbon group.

[0085] In some embodiments, the reactant contains two or more halogen atoms, and at least two halogen atoms are attached to different carbon atoms. The halogen atoms may be the same halogen, such as bromine, iodine, fluorine, or chlorine. Alternatively, the halogen atoms may be different halogens, such as iodine and bromine, bromine and chlorine, chlorine and iodine. The reactant may include two halogen atoms attached to different carbon atoms. The reactant may contain three halogen atoms, each attached to a different carbon atom. The reactant may contain four halogen atoms, each attached to a different carbon atom. Alternatively, in embodiments where the reactant contains three, four, or more halogen atoms, some carbon atoms may be attached to two or three halogen atoms.

[0086] In some embodiments, two halogen atoms in the reactant are attached to adjacent carbon atoms of the hydrocarbon. Thus, the reactant may contain two adjacent carbon atoms, each having at least one halogen substituent. In some embodiments, each adjacent carbon atom has only one halogen substituent. Alternatively, one or both of the carbon atoms attached to the halogen may have two halogen atoms attached thereto. Embodiments can be envisioned where one or two carbon atoms attached to the halogen have three halogen atoms attached thereto. The positions of the two carbon atoms in the carbon chain may vary. In some embodiments, they are located at the ends of the carbon chain, but in some embodiments, they are away from the ends of the carbon chain. It will be apparent to those skilled in the art that the position of a given carbon atom in the carbon chain limits the number of available potential substituents.

[0087] For example, in embodiments where the reactant contains two carbon atoms, at least one halogen atom is attached to each carbon. If the two-carbon reactant contains two halogen atoms, then each of them is attached to a different carbon atom. In embodiments where the reactant contains two carbon atoms and three halogens, one of the carbon atoms is disubstituted with halogen. In embodiments where the reactant contains two carbon atoms and four halogens, both carbon atoms can be disubstituted with halogen. Alternatively, one carbon atom can have one halogen substituent while the second carbon atom can have three.

[0088] Similarly, in embodiments where the reactant contains three carbon atoms and two halogen atoms, each halogen atom is attached to a different carbon atom. Thus, there is no halogen atom attached to one of the carbon atoms. The two halogen atoms can be attached to adjacent carbon atoms (i.e., carbon atoms adjacent to each other in the carbon chain). Alternatively, there can be one carbon atom between the halogenated carbon atoms. For example, the reactant can contain 1,2-dihalopropane or 1,3-dihalopropane, such as 1,2-dichloropropane, 1,3-dichloropropane, 1,2-diiodopropane or 1,3-diiodopropane, 1,2-difluoropropane or 1,3-difluoropropane, or consist of or consist essentially of the same.

[0089] In embodiments where the reactant contains three carbon atoms and three halogen atoms, each carbon atom can have a halogen atom attached to it. Alternatively, any one of the three carbon atoms may have two halogen atoms attached to it, while one carbon atom - either at the end of the carbon chain or in the middle - may have no halogen. The disubstituted carbon atom can be at the end or in the middle of the carbon chain. As a further alternative, in some embodiments, the three-carbon reactant can contain four halogen atoms. In such embodiments, each carbon can have a halogen atom attached to it, and one carbon - either at the end of the carbon chain or in the middle - can have an additional halogen atom attached to it. As an even further alternative, two carbons can have two halogen atoms attached to them, while one carbon atom - either at the end of the carbon chain or in the middle - can have no halogen. In some embodiments, the reactant includes 1,2-dihaloalkanes or 1,2-dihaloalkenes or 1,2-dihaloalkynes or 1,2-dihaloarenes, where the halogen is attached to adjacent carbon atoms.

[0090] In some embodiments, the reactant has the general formula X a R b C—(CX c R” d ) n –CX a R’ b, where X is a halogen, R, R', and R'' are independently H or alkyl, a and b are independently 1 or 2, such that for each carbon atom, a + b = 3, n is 0, 1, 2, 3, 4, or 5, and where c and d are independently 0, 1, or 2, such that for each carbon atom, c + d = 2.

[0091] In some embodiments, the reactant has the general formula X a R b C–CX a R’ b , where X is a halogen, R and R' are independently H or alkyl, and a and b are independently 1, 2, or 3 such that for each carbon atom, a + b = 3.

[0092] In embodiments where the reactant contains four carbons, it can have two, three, four, five, or six halogen substituents attached to the carbon. For example, the reactant can have the formula CH3-CXH-CH2-CXH2, CH3-CH2-CXH-CXH2, CH3-CXH-CXH-CH3, or H2CX-CH2-CH2-CXH2. In embodiments where the four-carbon halogen contains three carbons, the reactant can have formulas such as H2CX-CXH-CH2-CXH2, H2CX-CXH-CXH-CH3, HCX2-CXH-CH2-CH3, HCX2-CH2-CXH-CH3, or HCX2-CH2-CH2-CXH2 or CH3-CXH-CX2-CH3. In the formulas, X represents a halogen. Examples of such reactants are 1,2-dihalobutane, 1,3-dihalobutane, and 1,4-dihalobutane.

[0093] In some embodiments, cyclic or aromatic reactants can be used. In some embodiments, the reactant includes a cyclic or aromatic compound. In some embodiments, the halogenated hydrocarbon contains an aryl group. In some embodiments, the halogenated hydrocarbon includes iodobenzene or 1-iodobutane. In some embodiments, the halogenated hydrocarbon includes bromobenzene or 1-bromobutane.

[0094] The reactants can include a dihalobenzene ring. The benzene ring can contain two or more halogens. The benzene ring can contain additional substituents, such as one or more alkyl groups as described above. The reactants can comprise, consist of, or consist essentially of a dihalobenzene, such as 1,2-dibromobenzene, 1,2-diiodobenzene, or 1,2-dichlorobenzene. The dihalobenzene can also be 1,3-dihalobenzene or 1,4-dihalobenzene. Additionally, trihalobenzenes such as 1,2,3- or 1,2,4-halobenzenes are possible. The aromatic reactant can contain four, five, or six halogens. For example, the cyclic reactant can include cyclopentane or cyclohexane. The cyclic reactant can contain two or more halogens. For example, cyclohexane can contain up to 12 identical or different halogens. The halogens can be in a cis or trans configuration. The halogens in cyclohexane can be located at carbon positions 1 and 2, 1 and 3, 1 and 4, or 1,2,3 or 1,2,4. Examples of cyclic reactants are 1,2-diiodocyclohexane, 1,3-diiodocyclohexane, 1,4-diiodocyclohexane, 1,2-dibromocyclohexane, 1,3-dibromocyclohexane, 1,4-dibromocyclohexane, 1,2-difluorocyclohexane, 1,3-difluorocyclohexane, 1,4-difluorocyclohexane.

[0095] In some embodiments, the reactant has the general formula X a R b C—CX a R’ b , where X is a halogen, R and R’ are independently H or an alkyl group, and a and b are independently 1 or 2, such that for each carbon atom, a + b = 3. In some embodiments, X is iodine. In some embodiments, X is bromine. In some embodiments, X is chlorine. In some embodiments, for two carbon atoms, a is 1. In some embodiments, for one carbon atom, a is 1 and for the other carbon atom, a is 2. In some embodiments, both R and R’ are H.

[0096] In some embodiments of the present invention, the first metal can be deposited to a certain thickness such that the gap substrate between the spacer materials 214 covering the sidewalls of the primary mandrel 210 is completely filled with the first metal. For example, in some embodiments, the first metal can include molybdenum deposited to a thickness between about 2 nm and 30 nm or between about 5 nm and 20 nm. In some embodiments, it may not be necessary to fill the gap with the first metal. The appropriate thickness depends on subsequent processing steps, and a partially filled gap may be sufficient as long as the target patterning of the underlying layer is achieved.

[0097] In some embodiments, during the deposition of the first metal, the substrate may be heated to a desired deposition temperature. Thus, a deposition method for depositing the first metal, such as ALD, may be carried out at a substrate temperature below about 500 °C, or below about 450 °C, or below about 400 °C, or below about 350 °C, or below about 300 °C, or below about 250 °C, or even below about 200 °C. In some embodiments, the deposition of the first metal may be carried out at a substrate temperature between 300 °C and 450 °C, or between 200 °C and 350 °C, or between 200 °C and 500 °C.

[0098] In further embodiments, the reaction chamber in which atomic layer deposition of the first metal occurs may be placed under vacuum using a pumping system fluidly connected to the reaction chamber. Thus, in some embodiments, the ALD method for depositing the first metal layer may be carried out at a reaction chamber pressure of less than 100 Torr, or less than 50 Torr, or less than 20 Torr, or less than 10 Torr.

[0099] In some embodiments, the first metal deposited in the gap by a cyclic vapor deposition method such as ALD may be deposited to completely fill the gap. In some embodiments, in a structure having an aspect ratio (height to width ratio) of about 2, or greater than about 2, or greater than about 5, or greater than about 10, or greater than about 25, or greater than about 30, the step coverage of the first metal may be equal to or greater than about 50%, or greater than about 80%, or greater than about 90%, or greater than about 95%, or greater than about 98%, or greater than about 99%, or even about 100%.

[0100] In some embodiments, the first metal 216 is deposited at least partially as elemental metal. In some embodiments, the first metal 216 is substantially deposited as elemental metal. For example, the first metal such as molybdenum may contain less than about 20 atomic % oxygen, less than about 10 atomic % oxygen, less than about 5 atomic % oxygen, or even less than about 2 atomic % oxygen. In further embodiments, the first metal may contain less than about 10 atomic % hydrogen, or less than about 5 atomic % hydrogen, or less than about 2 atomic % hydrogen, or even less than about 1 atomic % hydrogen. In some embodiments, the first metal may contain less than about 10 atomic % halogen, such as Cl, or less than about 5 atomic % halogen, less than about 1 atomic % halogen, or less than about 0.5 atomic % halogen. In additional embodiments, the first metal such as molybdenum may include less than about 10 atomic % carbon, or less than about 5 atomic % carbon, or less than about 2 atomic % carbon, or less than about 1 atomic % carbon, or less than about 0.5 atomic % carbon. The elemental composition of the deposited material may be measured by methods known to those skilled in the art of semiconductor material development.

[0101] In some embodiments, after the first metal has been deposited in the gap, the spacer material 214 is removed, and the deposited first metal forms a secondary mandrel. Figure 2 Figure f) in Figure 2 depicts a partially fabricated semiconductor device 200 after the spacer material 214 has been removed. In some embodiments, the deposited first metal forming the secondary mandrel and the primary mandrel transfer a pattern into the underlying layer. In some embodiments, the deposited first metal and the primary mandrel form an etch mask for etching the underlying material. The underlying material herein refers to any one or more materials on which the primary mandrel and the deposited first metal (“secondary mandrel”) are formed. For example, the underlying material may be a storage layer. In some embodiments, the primary mandrel 210 is formed of a second metal, and there is an etch contrast between the first and second metals on the one hand and the underlying layer on the other hand. Accordingly, the underlying layer is etched faster relative to the first and second metals. The metal line pattern to be formed is visible as the primary mandrel 210 and the secondary mandrel 216. The spacer material 214 can be removed by methods known in the art of semiconductor device fabrication. For example, a plasma-based etch method such as a wet etch or a dry etch method known in the art can be used.

[0102] In cases where the materials are the same or similar, the primary mandrel 210 and the secondary mandrel 216 formed by this method can have the same or similar etch properties. For example, as in the Figure 2 embodiment of Figure 2 , the primary mandrel can be formed of a second metal. Both the first metal and the second metal can be molybdenum, and both the primary mandrel 210 and the secondary mandrel 216 can consist essentially of elemental molybdenum.

[0103] Figure 2 Figures g) and h) in Figure 2 depict downstream processing steps of the semiconductor device manufacturing process according to the present disclosure. In Figure 2 Figure g) in Figure 2 , the etching continues towards forming the metal line, and the adhesion layer 206 and the storage layer 208 have been etched. Accordingly, the primary mandrel 210 and the secondary mandrel 216 have also been partially etched. During this process, the primary mandrel 210 and the secondary mandrel 216 have been partially etched. In Figure 2 Figure h) in Figure 2 , the etching process continues until the end, and the primary mandrel 210 and the secondary mandrel 216 have been completely etched away. In the absence of the mandrels 210, 216, the storage layer 208 continues to define the pattern.

[0104] Figure 3FIG. 0 is a schematic diagram of an embodiment of a semiconductor processing assembly 300 in accordance with the present disclosure. The semiconductor processing assembly 300 includes one or more reaction chambers 320 configured and arranged to hold a substrate, a precursor injector system 301 configured and arranged to provide a first metal precursor and a second reactant in a gas phase into the reaction chamber 320. The semiconductor processing assembly 300 further includes a first metal precursor source container 302 configured and arranged to contain the first metal precursor. The semiconductor processing assembly 300 further includes a second reactant source container 303 configured and arranged to contain the second reactant. The semiconductor processing assembly 300 is configured and arranged to provide the first metal precursor and the second reactant into the reaction chamber 320 via the precursor injector system 301 for depositing a first metal in the gaps of the substrate.

[0105] In some embodiments, the semiconductor processing assembly 300 further includes one or more additional precursor source containers 304, and the precursor injector system 301 is configured and arranged to provide one or more additional precursors in a gas phase into the reaction chamber 320. The processing assembly 300 may include optional additional source containers configured and arranged to contain additional reactants used in substrate processing. For example, another source container (not shown) may be configured and arranged to contain, for example, an etchant or a cleaner.

[0106] The semiconductor processing assembly 300 may be used to perform the methods described herein. In the illustrated example, the processing assembly 300 includes one or more reaction chambers 320, a precursor injector system 301, source containers 302, 303, 304, optional and additional source containers, an exhaust source 322, and a controller 330. The processing assembly 300 may include one or more additional gas sources (not shown), such as an inert gas source, a carrier gas source, and / or a purge gas source. Although three source containers 302-304 are shown, the processing assembly 300 may include any suitable number of source containers. The source containers 302-304 may be coupled to the reaction chamber 320 via lines 312-314, which may each include a flow controller, a valve, a heater, etc. In some embodiments, each of the source containers 302-304 may be independently heated or maintained at ambient temperature. In some embodiments, the source containers are heated such that the precursor or reactant reaches a temperature suitable for evaporation. The reaction chamber 320 may include any suitable reaction chamber, such as an ALD or CVD reaction chamber described herein. The exhaust source 322 may include one or more vacuum pumps.

[0107] The controller 330 includes electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in the processing assembly 300. Such circuitry and components are used to introduce precursors, reactants, and other gases from corresponding sources. The controller 330 can control the timing of gas pulse sequences, the temperature of the substrate and / or reaction chamber 320, the pressure within the reaction chamber 320, and various other operations to provide proper operation of the processing assembly 300. The controller 330 can include control software to control valves, either electrically or pneumatically, to control the flow of precursors, reactants, and other gases into and out of the reaction chamber 320. The controller 330 can include modules that perform specific tasks, such as software or hardware components.

[0108] Other configurations of the processing assembly 300 are possible, including different numbers and types of precursor and source containers. For example, the reaction chamber 320 can include more than one, such as two or four, deposition stations. For example, such a multi-station configuration may be advantageous if deposition and / or etching of various materials can be performed in the same reaction chamber. In addition, it should be understood that there are many arrangements of valves, conduits, precursor sources, and reactant sources that can be used to achieve the goal of selectively and in a coordinated manner supplying gases to the reaction chamber 320. In addition, for purposes of a schematic representation of the processing assembly 300, many components have been omitted for simplicity of illustration, and such components can include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0109] During operation of the processing assembly 300, a substrate, such as a semiconductor wafer (not shown), is transferred from, for example, a substrate handling system to the reaction chamber 320. Once the substrates are transferred to the reaction chamber 320 (i.e., they are provided in the reaction chamber 320), one or more gases from gas sources, such as precursors, reactants, carrier gases, and / or purge gases, are introduced into the reaction chamber 320 to perform the methods described herein.

[0110] In one aspect, a method of reducing the pitch of features in a semiconductor substrate is disclosed. The method of reducing the pitch of features in a semiconductor substrate includes providing a patterned substrate including gaps in a reaction chamber, wherein the gaps have sidewalls and the sidewalls are covered with spacer material. The method further includes depositing a first metal in the gaps by a chemical vapor deposition method to at least partially fill the gaps.

[0111] In one aspect, a method of patterning a target layer is disclosed. The method of patterning a target layer includes providing a patterned substrate including gaps in a reaction chamber, wherein the gaps have sidewalls and the sidewalls are covered with spacer material. The method further includes depositing a first metal in the gaps by a chemical vapor deposition method to at least partially fill the gaps.

[0112] In one aspect, a method of depositing a material in a gap is disclosed. The method of depositing a material in a gap includes providing a patterned substrate including a gap in a reaction chamber, wherein the gap has sidewalls and the sidewalls are covered with a spacer material. The method further includes depositing a first metal in the gap by a chemical vapor deposition method to at least partially fill the gap.

[0113] The method according to the present disclosure can be used to fabricate semiconductor devices. Accordingly, a method of fabricating a semiconductor device is disclosed.

[0114] In another aspect, a semiconductor processing component for performing the method according to the present disclosure is disclosed.

[0115] It should be understood that the configurations and / or methods described herein are exemplary in nature and these specific embodiments or examples should not be considered limiting as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Accordingly, the various acts shown may be performed in the order shown, in other orders, or in some cases omitted.

[0116] The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of various methods and components, as well as other features, functions, acts, and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. A method of forming a structure, the method comprising: providing a patterned substrate including a gap in a reaction chamber, the gap having sidewalls, wherein the sidewalls are covered with a spacer material; A first metal is deposited in the gap by a vapor deposition method to at least partially fill the gap.

2. The method according to claim 1, wherein: The gap is formed between the two primary mandrels.

3. The method according to claim 1 or 2, wherein: The spacer material includes silicon.

4. A method according to any one of the preceding claims, wherein: The vapor deposition method is a cyclic vapor deposition method.

5. A method according to any one of the preceding claims, wherein: The sidewalls include a second metal.

6. The method according to claim 5, wherein: The first metal and the second metal are the same.

7. A method according to any one of the preceding claims, wherein: The gap includes a bottom, and the bottom includes a different material than the sidewalls.

8. The method according to claim 7, wherein: The bottom is formed by a storage layer.

9. The method according to claim 7 or 8, wherein: The base includes silicon.

10. A method according to any one of the preceding claims, wherein: The first metal is at least partially deposited as elemental metal.

11. A method according to any one of the preceding claims, wherein: The gap has a width of about 5 nm to about 60 nm.

12. A method according to any one of the preceding claims, wherein: The gap has a depth of about 5 nm to about 60 nm.

13. A method according to any one of the preceding claims, wherein: The thickness of the spacer material is substantially equal to the width of the gap to be filled by the first metal.

14. A method according to any one of the preceding claims, wherein: The primary mandrel is substantially formed from the second metal.

15. A method according to any one of the preceding claims, wherein: After depositing the first metal in the gap, the spacer material is removed.

16. A method according to any one of the preceding claims, wherein: The deposited first metal and the primary mandrels define a pattern.

17. A method according to any one of the preceding claims, wherein: The deposited first metal and the primary mandrels form a mask for etching the underlying material.

18. A method of reducing a pitch of features on a semiconductor substrate, the method comprising: providing a patterned substrate including a gap in a reaction chamber, the gap having sidewalls, wherein the sidewalls are covered with a spacer material; A first metal is deposited in the gap by a vapor deposition method to at least partially fill the gap.

19. A method for patterning a target layer, the method comprising: providing a patterned substrate including a gap in a reaction chamber, the gap having sidewalls, wherein the sidewalls are covered with a spacer material; A first metal is deposited in the gap by a vapor deposition method to at least partially fill the gap.

20. A method of depositing a material in a gap, the method comprising: providing a patterned substrate including a gap in a reaction chamber, the gap having sidewalls, wherein the sidewalls are covered with a spacer material; A first metal is deposited in the gap by a vapor deposition method to at least partially fill the gap.

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