Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a semiconductor chip having a source electrode pad and mounted on a die pad via a die bonding material; a wiring electrically connected to the source electrode pad of the semiconductor chip; and a sealing body that seals the semiconductor chip and the wiring. The wiring and the source electrode pad are made of metals of different types from each other. A wiring bonding layer made of sintered metal is interposed between the source electrode pad and the wiring. The wiring is electrically connected to the source electrode pad via the wiring bonding layer.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-212400, filed on December 15, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Art

[0004] The technologies disclosed are listed below for the device.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-151554

[0006] There is a semiconductor device in which a semiconductor chip is mounted on a die pad, and a source electrode and a lead of the semiconductor chip are electrically connected by a metal plate made of a conductive resin and copper. For example, in the case of the semiconductor device disclosed in Patent Document 1, a source electrode and a source lead of the semiconductor chip are electrically connected via a conductive paste and a copper plate. Further, a gate electrode and a gate lead of the semiconductor chip are electrically connected via a bonding wire. Summary of the Invention

[0007] In the case of a semiconductor device in which an electrode pad and a lead of a semiconductor chip are electrically connected to each other via a wiring, it is necessary to improve the bonding reliability of a portion where the wiring and the electrode pad are electrically connected to each other. For example, when the electrode pad and the wiring are made of different types of metals from each other, the bonding strength can be reduced compared to the case where the electrode pad and the wiring are made of the same type of metal from each other.

[0008] Other objects and novel features will become apparent from the description of this specification and the drawings.

[0009] A semiconductor device according to one embodiment includes: a die pad; a lead spaced apart from the die pad; a semiconductor chip having a first electrode pad and mounted on the die pad via a die bonding material; a wiring electrically connected to each of the lead and the first electrode pad of the semiconductor chip; and a sealing body that seals the semiconductor chip, the die bonding material, and the wiring. The first electrode pad and the wiring are made of different types of metals from each other. A wiring bonding layer made of a sintered metal is disposed between the first electrode pad and the lead. The wiring is electrically connected to the first electrode pad via the wiring bonding layer.

[0010] A method of manufacturing a semiconductor device according to another embodiment includes the steps of: (a) preparing a die pad; (b) applying a first paste onto the die pad; (c) mounting a semiconductor chip having a first electrode pad on the first paste; (d) disposing a second paste including a plurality of metal particles on the first electrode pad of the semiconductor chip; (e) sintering the plurality of metal particles included in the second paste by heating the second paste to form a wiring bonding layer; and (f) wire-bonding a wire made of a metal different from the first electrode pad to the wiring bonding layer.

[0011] According to an embodiment, it is possible to improve the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a top surface view of a semiconductor device according to an embodiment.

[0013] Figure 2 is Figure 1 a bottom surface view of the semiconductor device shown.

[0014] Figure 3 is a transparent plan view showing the internal structure of the semiconductor device in which the Figure 1 shown encapsulant is removed.

[0015] Figure 4 is a cross-sectional view taken along Figure 3 center line A-A.

[0016] Figure 5 is an explanatory diagram schematically showing an example of a circuit included in the Figure 1 shown semiconductor device.

[0017] Figure 6 is showing Figure 5 an example of a main part cross-sectional view of a device structure of a field effect transistor shown.

[0018] Figure 7 is showing Figure 4 an enlarged cross-sectional view of each component of a semiconductor chip, a wiring bonding layer, and a lead shown.

[0019] Figure 8 is showing Figure 4 an enlarged cross-sectional view of each component of a semiconductor chip, a die bonding material, and a die pad shown.

[0020] Figure 9 is a flowchart showing an example of a method of manufacturing the Figures 1 to 4 shown semiconductor device.

[0021] Figure 10 is showing inFigure 9 An enlarged plan view of a component of a lead frame prepared in the lead frame preparation steps shown.

[0022] Figure 11 It is Figure 9 An enlarged cross-sectional view showing the state in which the paste for die bonding is applied to the die pad in the die bonding paste application step.

[0023] Figure 12 It is an enlarged cross-sectional view showing the state in which a semiconductor chip is mounted on Figure 11 the paste for die bonding shown.

[0024] Figure 13 It is Figure 9 An enlarged cross-sectional view showing the state in which the sintered metal paste is applied to the die pad in the sintered metal paste application step.

[0025] Figure 14 It schematically shows Figure 9 An explanatory view of the state in which the lead frame is heated in a vacuum furnace in the sintering step shown.

[0026] Figure 15 It schematically shows Figure 9 An enlarged cross-sectional view of the state in which a load and ultrasonic waves are applied to the wiring by a bonding tool in the wire bonding step shown. Detailed Description

[0027] (Description of Format and Basic Terms and Usages in this Application)

[0028] In this application, for convenience, the description of the embodiments is divided into multiple parts as needed, but unless otherwise explicitly stated, these parts are not independent and separate from each other, regardless of the order of description, and parts of a single example, where one part may be a detailed part of another part or a part or all of a modified example. Similarly, in principle, the description of similar parts is omitted. In addition, unless otherwise explicitly stated, each component in the embodiments is not necessary, and theoretically limited to that number, and it is not obvious from the context.

[0029] Similarly, in the description of embodiments and the like, with regard to materials, components, etc., stating that "X consists of A" does not exclude elements other than A, unless it is clearly indicated that this is not the case and it is obvious from the context that this is not the case. For example, with regard to components, it means that "X includes A as the main component (principal component)". For instance, referring to a "silicon member" does not limit it to pure silicon, but includes members such as SiGe (silicon-germanium) alloys or other multi-component alloys with silicon as the main component and other additives. In addition, unless otherwise specifically stated, referring to gold plating, copper plating layer, nickel plating, etc., includes not only pure substances but also members including gold, copper, nickel, etc. as the main component.

[0030] In addition, when referring to a specific numerical value or number, unless otherwise clearly stated, the theoretical upper limit is that value, and it is obvious from the context that this is not the case, it can be greater than or less than that specific numerical value.

[0031] In the drawings of the embodiments, the same or similar components are denoted by the same or similar symbols or reference numerals, and in principle, no repeated description is given.

[0032] In the drawings, when the cross-section becomes complex or when it is clearly distinguishable from the gap, shading, etc. can even be omitted in the cross-section. In this regard, even if the hole is closed on the plane, when the outline of the background is obvious from the description, etc., the outline of the background can be omitted. In addition, hatching or dot patterns can be applied not only to the cross-section but also to indicate the boundary of a non-empty area or a depicted area.

[0033] In the embodiments described below, as an example of a semiconductor device, a semiconductor device called a power device or a power semiconductor device incorporated into a power control circuit such as a power supply circuit is discussed. The semiconductor device described below is incorporated into a power conversion circuit and serves as a switching element.

[0034] <Semiconductor Device>

[0035] First, describe Figure 1 the package structure of the semiconductor device PKG1 shown. Figure 1 is a top view of the semiconductor device of this embodiment. In addition, Figure 2 is Figure 1 a bottom view of the semiconductor device shown. In addition, Figure 3 is a perspective plan view showing the internal structure of the semiconductor device with the package removed as shown in Figure 1 shown. In addition, Figure 4 is a cross-sectional view along the line A-A in Figure 3 shown.

[0036] Figures 1 to 4 Describes the X direction (refer to Figures 1 to 3) in the Y - direction or Z - direction (refer to Figure 4 ). The Y - direction is the side intersecting with the X - direction, and in the following description, the X - direction and the Y - direction are orthogonal to each other. The Z - direction is orthogonal to both the X - direction and the Y - direction. In other words, the Z - direction is the normal direction of the X - Y plane including the X - direction and the Y - direction. In the following description, "thickness" mainly means the length in the Z - direction. In addition, in the following description, "planar view" mainly means the view of the X - Y plane.

[0037] The semiconductor device PKG1 of this embodiment includes a semiconductor chip 10 (refer to Figure 3 and Figure 4 ), a die pad (metal plate, chip mounting component, heat sink) 20 on which the semiconductor chip 10 is mounted (refer to Figures 2 to 4 ), a plurality of leads (terminals) 30 as external terminals, and a plurality of wirings 12 (refer to Figure 3 ).

[0038] As Figure 3 shown, the die pad 20 has an upper surface (surface) 20t. The semiconductor chip 10 is mounted on the upper surface 20t of the die pad 20 via a die bonding material 11 (refer to Figure 4 ). A plurality of leads 30 are arranged along the side (chip side) 10s1 of the semiconductor chip 10 that extends in the X - direction among the plurality of sides 10s of the semiconductor chip 10. A plurality of electrode pads ( Figure 3 the gate electrode pad GE and the source electrode pad SE shown) arranged on the upper surface (chip surface, surface) 10t of the semiconductor chip 10 and the plurality of leads 30 are electrically connected to each other via a plurality of wirings respectively. As Figure 4 shown, the semiconductor chip 10 and the plurality of wirings 12 are sealed in a sealing body 40. In addition, the semiconductor chip 10, the upper surface 20t of the die pad 20, and the internal lead components (sealing components) 30M of the plurality of leads 30 (refer to Figure 4 ) are sealed by the sealing body 40. The sealing body (resin sealing body, resin, molding resin) 40 is arranged to contact the die pad 20 and the internal lead components 30M of the leads 30.

[0039] As Figure 4 shown, the semiconductor chip 10 has an upper surface (main surface, front surface, surface) 10t and a lower surface (main surface, rear surface, surface) 10b opposite to the upper surface 10t. As Figure 3As shown, in a plan view, the semiconductor chip 10 has four sides (chip sides) 10s. The four sides 10s are composed of a side 10s1 extending in the X direction, a side 10s2 opposite to the side 10s1, a side 10s3 intersecting with the sides 10s1 and 10s2 and extending in the Y direction, and a side 10s4 opposite to the side 10s3. The side 10s1 is located closest to each of the plurality of leads 30 among the four sides 10s of the semiconductor chip 10 and extends in the X direction. In Figure 3 In the example shown, the semiconductor chip 10 forms a rectangle in a plan view, and the long sides (sides 10s1 and 10s2) are arranged to extend along the X direction.

[0040] On the upper surface 10t of the semiconductor chip 10, gate electrode pads GE and source electrode pads SE are arranged. An insulating film (passivation film) having the upper surface 10t of the semiconductor chip 10 is provided with a plurality of openings. Each of the gate electrode pads GE and the source electrode pads SE is exposed from the insulating film at the openings. The area of the source electrode pad SE is larger than the area of the gate electrode pad GE. The gate electrode pad GE is an electrode pad connected to the gate electrode G of the transistor Q1 described later. Figure 5 The source electrode pad SE is an electrode pad connected to the source S of the transistor Q1 described later. Figure 5

[0041] For example, each of the gate electrode pads GE and the source electrode pads SE is mainly made of aluminum. The metal mainly made of aluminum includes not only pure aluminum but also aluminum alloys added with additive elements such as silicon and copper. When referring to a metal mainly made of aluminum, aluminum constitutes at least 90% by weight of the metal, preferably 95% by weight or more. The elements added to aluminum are not limited to copper and silicon, and there are various modification examples.

[0042] As Figure 4 shown, a drain electrode pad (drain electrode) DE is arranged on the lower surface 10b of the semiconductor chip 10. The drain electrode pad DE is an electrode pad connected to the drain D of the transistor Q1 described later. In Figure 5 the example shown, the entire lower surface 10b of the semiconductor chip 10 serves as the drain electrode pad DE. Figure 4

[0043] ​​The drain electrode pad DE is made of a metal film. Although details will be described later, it is preferable that, in the metal film constituting the drain electrode pad DE, the metal film located at the boundary surface with the die bonding material 11 is made of a metal that is easily bondable with the die bonding material 11. For example, in the case of the present embodiment, the die bonding material 11 is made of sintered copper. Therefore, it is preferable that a metal film made of one of gold, silver, copper, and nickel is formed at the portion of the drain electrode pad DE that contacts the die bonding material 11. On the other hand, if the die bonding material 11 is solder or a conductive resin (a resin body in which a plurality of conductive particles are mixed in a resin including a thermosetting resin), it is preferable that a metal film made of one of gold and silver is formed at the portion that contacts the die bonding material 11, and this metal film constitutes the drain electrode pad DE.

[0044] In the present embodiment, a vertical channel structure MOSFET is exemplified as an example of the transistor Q1. Therefore, the drain electrode pad DE is located on the lower surface 10b of the semiconductor chip 10, and the lower surface 10b is the opposite side of the surface on which the gate electrode pad GE and the source electrode pad SE are arranged. The drain electrode pad DE of the semiconductor chip 10 is electrically connected to the die pad 20 through the die bonding material 11.

[0045] Although not shown, as a modified example of the present embodiment, when a lateral channel structure MOSFET is used, the gate electrode pad GE, the source electrode pad SE, and the drain electrode pad DE are arranged on the upper surface 10t of the semiconductor chip 10.

[0046] As Figure 3 and 4 shown, the semiconductor device PKG1 has a die pad (metal plate, chip mounting component, heat sink) 20, and the semiconductor chip 10 is mounted on the die pad 20. Each of the die pad 20 and the plurality of leads 30 (see Figure 3 ) has a substrate 31 made of, for example, copper (Cu) or an alloy material mainly composed of copper (Cu). As Figure 4 shown, the die pad 20 has an upper surface (surface, main surface, chip mounting surface) 20t and a lower surface (surface, main surface, back surface, main surface) 20b opposite to the upper surface 20t, and the semiconductor chip 10 is mounted on the upper surface 20t via the die bonding material 11.

[0047] In the present embodiment, the die bonding material 11 is composed of a conductive material that electrically connects the drain electrode pad DE (see Figure 4 ) and the die pad 20. The die bonding material 11 is composed of a sintered metal, such as sintered copper or sintered silver. In the present embodiment, as Figure 3As shown, a wiring bonding layer WBL made of sintered metal is disposed on a source electrode pad SE. By using sintered metal as the die bonding material 11, it is possible to sinter the die bonding material 11 and the wiring bonding layer WBL in a single sintering process during the manufacturing process of a semiconductor device.

[0048] As a modified example of the die bonding material 11, a resin material including conductive particles or solder can be exemplified. A resin material including conductive particles is called a conductive resin or a conductive paste. Moreover, those using silver particles as the conductive particles are called silver paste.

[0049] As another modified example, in the case of applying a device structure in which no electrodes are disposed on the lower surface 10b of the semiconductor chip 10 (for example, a transistor having a lateral channel structure), the die bonding material 11 does not necessarily have to be conductive. In such a case, for example, an insulating resin adhesive can be used.

[0050] However, as described below, when performing a sintering process, high-temperature heat treatment is carried out. Therefore, from the viewpoint of preventing damage to the die bonding material 11 during the sintering process, it is preferable that the die bonding material 11 is sintered metal.

[0051] As Figure 2 shown, the die pad 20 has four sides 20s in a plan view. Specifically, the die pad 20 has a side 20s1 extending in the X direction, a side 20s2 disposed on the opposite side of the side 20s1, a side 20s3 extending in the Y direction and intersecting the side 20s1, and a side 20s4 disposed on the opposite side of the side 20s3 and intersecting the side 20s1.

[0052] The die pad 20 includes a main body part (portion) 20P1 including a region for mounting the semiconductor chip 10 (see Figure 3 ), a head part (portion) 20P2 provided with a side 20s2 disposed on the opposite side of the side 20s1 in a plan view, and a connecting part (portion) 20P3 connecting the main body part 20P1 and the head part 20P2. Each of the sides 20s1, 20s3, and 20s4 is a side of the main body part 20P1 of the die pad 20. The side 20s2 is a side of the head part 20P2 of the die pad 20.

[0053] The main body part 20P1 includes a region for mounting the semiconductor chip 10 (refer to Figure 3 ), and a region for contacting a jig to fix the die pad 20 during the process of bonding the wiring 12 to the semiconductor chip (a wire bonding process to be described later). The main body part 20P1 forms a quadrilateral in a plan view. In Figure 2In the illustrated example, the main body portion 20P1 forms a rectangle, and the side 20s1 is a long side. The semiconductor chip 10 is arranged in a plan view such that the side 10s1 of the semiconductor chip 10 and the side 20s1 of the die pad 20 extend along each other.

[0054] The head portion 20P2 is integrally formed with the main body portion 20P1 and the connecting portion 20P3, but the semiconductor chip 10 is not mounted on the head portion 20P2. The side 20s2 of the head portion 20P2 and its periphery are exposed from the sealing body 40. By integrally forming the head portion 20P2 and the main body portion 20P1 exposed from the sealing body 40, the heat dissipation characteristics of the semiconductor device PKG1 can be improved. The connecting portion 20P3 is a component for connecting the head portion 20P2 and the main body portion 20P1.

[0055] As Figure 2 and Figure 4 shown, the lower surface 20b of the die pad 20 is exposed from the sealing body 40. By exposing the lower surface 20b of the die pad 20 from the sealing body 40, the heat dissipation characteristics of the die pad 20 can be improved. In addition, when the die pad 20 is bonded to the terminals of a mounting substrate (not shown), the die pad 20 itself can be used as a drain terminal (or a collector terminal in the case of an IGBT).

[0056] From the perspective of increasing the heat capacity of the die pad 20 or from the perspective of increasing the cross-sectional area of the conduction path through which current flows, it is preferable that the thickness of the die pad 20 (i.e., the length in the Z direction) is thicker. In Figure 4 the illustrated example, the thickness of the die pad 20 is greater than the thickness of the semiconductor chip 10. In addition, the thickness of the die pad 20 (the distance from the upper surface 20t to the lower surface 20b) is greater than the thickness of the lead 30 (the distance from the upper surface 30t to the lower surface 30b). For example, in Figure 4 the illustrated example, the thickness of the die pad 20 is approximately 500 μm to 2000 μm.

[0057] In addition, the components (external components, exposed components) of the die pad 20 exposed from the sealing body 40 are covered with a metal film 22. Similarly, for each of the plurality of leads 30, the components (outer lead components 30X) exposed from the sealing body 40 are covered with a metal film 32. These metal films 22 and 32 are metal films used as connection materials to improve the wettability of solder when the semiconductor device PKG1 is mounted on a mounting substrate.

[0058] As Figure 3 and Figure 4 shown, the semiconductor device PKG1 has a plurality of leads 30 electrically connected to the semiconductor chip 10. As Figure 3As shown, in a plan view, each of the plurality of leads 30 faces the edge 20s1 of the die pad 20. However, as shown in FIG. Figure 4 As shown, in the Z direction, the lower surface 30b of the lead 30 is positioned higher than the upper surface 20t of the die pad 20. Figure 4 In the cross-sectional view shown, the lead 30 does not face the side 20s1 of the die pad 20. “The plurality of leads 30 and the side 20s1 of the die pad 20 face each other in a plan view” means that Figure 3 As shown, the plurality of leads 30 and the edge 20s1 of the die pad 20 appear to face each other in a plan view. Figure 4 As shown, there is a case where the end surface of the lead 30 and the end surface of the die pad 20 do not face each other. Although not shown, as a modified example of the present embodiment, a case where the end surface of the lead 30 and the end surface of the die pad 20 face each other is also included in the above-mentioned state of "the plurality of leads 30 and the side 20s1 of the die pad 20 face each other in a plan view".

[0059] The plurality of leads 30 include a lead for a source (source lead, source terminal) 30S, a lead for a drain (drain lead, drain terminal) 30D, and a lead for a gate (gate lead, gate terminal) 30G. Figure 3 In the example shown, the plurality of leads 30 are arranged along the X direction. Figure 3 In the example shown, in the X direction, the leads are arranged in the order of the lead 30G, the lead 30D, and the lead 30S. However, the arrangement order is not limited to Figure 3 In the illustrated pattern, for example, they may be arranged in the order of the lead 30G, the lead 30S, and the lead 30D.

[0060] like Figure 4 As shown, each of the plurality of leads 30 includes an inner lead part 30M sealed in a sealing body 40 and an outer lead part (external part, exposed part) 30X exposed from the sealing body 40. In the present embodiment, the outer lead part 30X is bent, and the tip portion of the outer lead part 30X is positioned lower than the inner lead part 30M. Figure 4 The shape of the outer lead member 30X shown is called a gull-wing shape.

[0061] like Figure 3 As shown in FIG. 1 , the die pad 20 is integrally formed with a lead 30D serving as a drain terminal. The lead 30D is Figure 5 The drain electrode D shown is electrically connected to an external connection terminal, which will be described later. The lead 30D is electrically connected to the drain electrode pad DE of the semiconductor chip 10 through the die pad 20 and the die bonding material 11 (see Figure 4)。In addition, since the lead 30D is connected to the die pad 20, it has the function of a suspension lead that supports the die pad 20 during the manufacturing process of the semiconductor device to be described later.

[0062] In addition, as Figure 3 shown, the gate electrode pad GE of the semiconductor chip 10 and the lead 30G are electrically connected to each other via a wiring (conductive member, metal wiring) 12 (specifically, the wiring 12G for the gate). Similarly, the source electrode pad SE of the semiconductor chip 10 and the lead 30S are electrically connected to each other via the wiring 12 (specifically, a plurality of wirings 12S for the source).

[0063] The wiring 12 is a conductive member that connects to each of the electrode pads on the upper surface 10t of the semiconductor chip 10 and the lead 30. Materials that can be used for the wiring 12 include metals mainly made of copper (Cu), gold (Au), silver (Ag), or aluminum (Al). In this embodiment, each of the multiple wirings 12 is a copper wire made of copper. As described above, each of the gate electrode pad GE and the source electrode pad SE is mainly made of aluminum. Therefore, the wiring 12 and the source electrode pad SE (or the gate electrode pad GE) are made of different types of metals.

[0064] Therefore, when attempting to directly bond the wiring 12 and the source electrode pad SE made of different metals, there is room for improvement in terms of electrical connection reliability (e.g., bonding strength or electrical characteristics) compared to bonding the same type of metals.

[0065] Therefore, in the case of this embodiment, as Figure 4 shown, the wiring bonding layer WBLS to which the wiring 12S is bonded is placed between the source electrode pad SE and the wiring 12S. In addition, as Figure 3 shown, the wiring bonding layer WBLG is placed between the gate electrode pad GE and the wiring 12G. The wiring bonding layers WBLS and WBLG are made of the same material and are manufactured by the same manufacturing method. Hereinafter, the wiring bonding layer WBLS located on the source electrode pad SE will be described as a representative example, but the term "wiring bonding layer WBL" can be used to collectively refer to the wiring bonding layers WBLS and WBLG.

[0066] Figure 4 The shown wiring bonding layer WBL is made of sintered metal. In the case of this embodiment, the wiring bonding layer WBL is made of sintered copper, which consists of multiple copper particles sintered together. As a modified example of the wiring bonding layer WBL, sintered silver consisting of multiple silver particles sintered together can also be used. Details of the wiring bonding layer WBL made of sintered metal will be described later.

[0067] AsFigure 3 As shown, one end of the wiring 12S for the source is bonded to the wiring bonding layer WBLS located on the source electrode pad SE of the semiconductor chip 10. On the other hand, the other end of the wiring 12S opposite to the aforementioned one end is bonded to the metal film 33 of the wiring bonding region 30W covering the lead 30S (see Figure 4 ). One end of the wiring 12G for the gate is bonded to the wiring bonding layer WBLG located on the gate electrode pad GE of the semiconductor chip 10. At the same time, the other end of the wiring 12G opposite to the aforementioned one end is bonded to the metal film (not shown) of the wiring bonding region 30W covering the lead 30G. The metal film 33 is made of, for example, nickel (Ni) or silver (Ag). By bonding the wiring 12 to the metal film 33 covering the wiring bonding region 30W, the bonding strength between the wiring 12 and the lead 30 can be improved. The metal film of the lead bonding region 30W covering the lead 30G is made of the same material as the Figure 4 shown metal film 33.

[0068] In addition, in a power semiconductor device, the current flowing through the wiring path connected to the source electrode pad SE is larger than the current flowing through the wiring path connected to the gate electrode pad GE. Therefore, in the Figure 3 shown example, multiple wirings 12S are connected to the source electrode pad SE. In addition, in the Figure 3 shown example, each of the multiple wirings 12S is thicker than the wiring 12G. In addition, when the wiring 12S is made of copper, the conductivity of the wiring 12S can be increased compared to when the wiring 12S is made of gold or aluminum. In addition, copper has the advantage of reducing the raw material cost compared to silver or gold.

[0069] Note that the shape and number of the wirings 12 are not limited to the Figure 3 shown embodiment, and there are various modification examples. For example, as Figure 3 shown, when the thicknesses of the wiring 12S and the wiring 12G are different, even if the raw materials of the wiring 12S and the wiring 12G are the same, it is necessary to use different wire bonding machines. Therefore, for example, the wiring 12S can be made of copper, while the wiring 12G can be made of a different material such as gold or aluminum. In this case, the wiring bonding layer WBLG located on the gate electrode pad GE may not be provided. Alternatively, in Figure 3 , the thickness of the wiring 12S is thicker than the thickness of the wiring 12G, but as a modification example, there may be a case where the wirings 12 of the same thickness are used. In this case, the wiring 12S and the wiring 12G can be connected by the same wire bonding machine.

[0070] The semiconductor chip 10, the die bonding material 11 (refer to Figure 4)、Each of the inner lead components 30M of the multiple leads 30, the wiring bonding layer WBL, and the multiple wirings 12 are sealed by a sealing body 40. The sealing body 40 is a resin body that seals the semiconductor chip 10 and the wirings 12. The sealing body 40 has an upper surface 40t (refer to Figure 1 and Figure 4 ) and a lower surface (mounting surface) 40b located on opposite sides of the upper surface 40t (refer to Figure 2 and Figure 4 ). In addition, as shown in Figure 1 and 2 , each of the upper surface 40t (refer to Figure 1 ) and the lower surface 40b (refer to Figure 2 ) of the sealing body 40 has a plurality of sides 40s at its periphery.

[0071] For example, the sealing body 40 is mainly composed of a thermosetting resin such as an epoxy resin. In this embodiment, in order to improve the characteristics of the sealing body 40 (e.g., expansion characteristics due to thermal effects), for example, filler particles such as silica (silicon dioxide; e.g., SiO2) particles are mixed into the resin material.

[0072] <Circuit Configuration Example>

[0073] Next, an example of the circuit configuration and transistor element structure included in the semiconductor device PKG1 shown in Figure 3 will be described. Figure 5 is an explanatory diagram schematically showing an example of the circuit included in the semiconductor device shown in Figure 1 . In addition, Figure 6 is a main part cross-sectional view showing an example of the element structure of the field-effect transistor shown in Figure 5 .

[0074] A semiconductor device for power control is called a power semiconductor device and includes semiconductor elements such as diodes, thyristors, or transistors. Transistors are used in various fields, but as in this embodiment, a transistor incorporated into a power control circuit where a large current of 1 A (ampere) or more flows and operates as a switching element is called a power transistor. As shown in Figure 5 , the semiconductor device PKG1 of this embodiment has a semiconductor chip 10 equipped with a transistor Q1, which is a power transistor. In the example shown in Figure 5 and Figure 6 , the transistor Q1 included in the semiconductor chip 10 is a field-effect transistor, specifically, a MOSFET (metal-oxide-semiconductor field-effect transistor). For example, in a power semiconductor device, a transistor is used as a switching element. A MOSFET used in a power semiconductor device is called a power MOSFET.

[0075] The above-mentioned MOSFET is described by the term that generally represents a field-effect transistor having a structure in which a gate electrode made of a conductive material is placed on a gate insulating film. Therefore, even when described as a MOSFET, it does not exclude a gate insulating film other than an oxide film. In addition, for example, even when described as a MOSFET, it does not exclude a gate electrode material other than metal, such as polysilicon.

[0076] As Figure 6 shown, Figure 5 the transistor Q1 shown is formed of an n-channel type field-effect transistor. Figure 6 is a main part cross-sectional view showing Figure 5 an example of the element structure of the field-effect transistor shown.

[0077] In Figure 6 the example shown, an n-type epitaxial layer EP is formed on the main surface WHt of a semiconductor substrate WH made of, for example, n-type single crystal silicon. The semiconductor substrate WH and the epitaxial layer EP constitute a drain region of the MOSFET (corresponding to Figure 5 the region of the drain D shown). This drain region is electrically connected to a drain electrode pad DE formed on the edge of the lower surface 10b of the semiconductor chip 10 (see Figure 4 ).

[0078] On the epitaxial layer EP, a channel formation region CH as a p+-type semiconductor region is formed, and on this channel formation region CH, a source region (corresponding to Figure 5 the region of the source S shown) SR as an n+-type semiconductor region is formed. The source region SR is electrically connected to a source electrode pad SE formed on the edge of the upper surface 10t of the semiconductor chip 10 (see Figure 4 ) through a lead wiring. In addition, in the semiconductor region stacked on the semiconductor substrate WH, a trench (opening, groove) TRQ is formed, which penetrates from the upper surface of the source region SR through the channel formation region CH and reaches inside the epitaxial layer EP.

[0079] In addition, a gate insulating film GI is provided on the inner wall of the trench TRQ. In addition, a gate electrode G is provided on the gate insulating film GI, and the gate electrode G is stacked so as to fill the trench TRQ. The gate electrode G is electrically connected to a gate electrode pad GE of the semiconductor chip 10 through a lead wiring.

[0080] In addition, since the transistor Q1 has a drain region and a source region SR disposed across the channel formation region CH in the thickness direction, a channel is formed in the thickness direction (hereinafter referred to as a vertical channel structure). In this case, compared with a field effect transistor in which a channel is formed along the main surface WHt, the occupied area of the element in the plan view can be reduced. Therefore, the planar size of the semiconductor chip 10 can be reduced.

[0081] In addition, in the case of the above-described vertical channel structure, since the channel width per unit area in the plan view can be increased, the on-resistance can be reduced. Note that Figure 6 is a diagram showing the element structure of a field effect transistor, and in the Figure 5 shown semiconductor chip 10, for example, a plurality (a large number) of transistors Q1 having the element structure as shown in Figure 6 are connected in parallel. This allows the construction of a power MOSFET through which a large current of more than, for example, 1 ampere can flow.

[0082] As described above, when a MOSFET is constructed by connecting a plurality of transistors Q1 having a vertical channel structure in parallel, the electrical characteristics (mainly the breakdown voltage characteristics, on-resistance characteristics, and capacitance characteristics) of the MOSFET vary according to the planar size of the semiconductor chip 10. For example, if the planar area of the semiconductor chip 10 increases, the number of cells (i.e., the number of elements) of the transistors Q1 connected in parallel increases, thereby reducing the on-resistance and increasing the capacitance.

[0083] It should be noted that although MOSFETs are exemplified as examples of power transistors provided in a power semiconductor device in Figure 5 and Figure 6 , various modified examples can be applied. For example, an insulated gate bipolar transistor (IGBT) can be provided instead of the MOSFET.

[0084] In addition, in the Figure 6 shown example, a transistor having a vertical channel structure is exemplarily described, but it can be replaced with a transistor having a horizontal channel structure. In this case, the drain electrode pad DE is disposed on the upper surface 10t of the semiconductor chip 10 (see Figure 3 ). Therefore, the drain electrode pad DE (see Figure 6 ) connected to the drain of the transistor having a horizontal channel structure and Figure 3 shown drain lead 30D are electrically connected to each other via a wiring (drain wiring) not shown. In addition, similar to Figure 4 , the region (lead bonding region) of the drain lead 30D connected to the drain wiring is covered with a metal film 33, and the drain wiring is connected to the drain lead 30D via the metal film 33.

[0085] <Details of the wiring bonding layer>

[0086] Next, Figure 3 and Figure 4 the details of the wiring bonding layer WBL shown will be described. Figure 7 is an enlarged cross-sectional view showing the components of each of the semiconductor chip, the wiring bonding layer, and the lead shown in Figure 4 . Although not shown in Figure 7 , between the source electrode pad SE and the semiconductor substrate 13, a wiring layer is formed that is electrically connected to the transistor Q1 (see Figure 5 ) formed on the semiconductor substrate 13 and the source electrode pad SE.

[0087] The semiconductor chip 10 has a semiconductor substrate 13, a source electrode pad SE disposed on the semiconductor substrate 13, and an insulating film 14 covering the source electrode pad SE.

[0088] In Figure 7 the example shown, the insulating film 14 is a laminated film of insulating films 14A and 14B. The insulating film 14A is an inorganic insulating film made of, for example, silicon oxide or silicon nitride. On the other hand, the insulating film 14B is an organic insulating film made of, for example, polyimide.

[0089] The insulating film 14 is formed to cover the source electrode pad SE, but has an opening formed in its component. The component of the source electrode pad SE is exposed from the insulating film 14 in the opening.

[0090] As illustrated using Figure 4 , when attempting to directly bond the wiring 12S made of a different metal to the source electrode pad SE, there is room for improvement in the electrical connection reliability at the bonding interface compared to bonding the same metal. For example, in the present embodiment, when the wiring 12 is made of copper and the source electrode pad SE is made of aluminum, copper is harder than aluminum, and the source electrode pad SE can be damaged by the external force applied during the bonding of the wiring 12. When the source electrode pad SE is damaged by the external force, there is a concern that the electrical characteristics of the damaged component of the source electrode pad SE may deteriorate (e.g., the resistance value increases). In addition, when the source electrode pad SE is damaged by the external force, there is a concern that the bonding strength between the wiring 12 and the source electrode pad SE may decrease.

[0091] Therefore, the inventors of the present invention have studied a method for preventing damage to the source electrode pad SE when bonding the wiring 12 by placing a layer for bonding the wiring 12, i.e., the wiring bonding layer WBL, on the source electrode pad SE.

[0092] Although not shown, first, a method of forming a metal plating film on the source electrode pad SE was studied, for example, by plating, and the wiring 12 was bonded to the metal plating film. In the case of this inspection example, since the wiring 12 is not directly bonded to the source electrode pad SE, it was found that damage to the source electrode pad SE can be suppressed if the thickness of the plated metal film is thick enough.

[0093] However, when forming a metal film by plating, the thicker the metal film, the more difficult it is to form the film.

[0094] In the case of this embodiment, a metal member made of sintered metal is used as the wiring bonding layer WBL. As Figure 7 shown, the wiring bonding layer WBL made of sintered metal is a sintered body in which a plurality of metal particles 51 are sintered together. Each of the plurality of metal particles 51 is a fine particle having a particle size in the sub-micron order. In addition, a large number of metal particles 51 can be treated as powder. Metal particles having a particle size in the nano order can also be used. This allows the plurality of metal particles to be sintered together at a lower temperature and a lower load. However, when using metal particles in the nano order, there is a risk that the component cost (i.e., the manufacturing cost of the semiconductor device) can become higher compared to using metal particles in the sub-micron order. Metal particles having a particle size in the micron order can also be used. This allows cost reduction. However, when using metal particles in the micron order, there is a risk that the reactivity (sinterability) is reduced compared to using metal particles in the sub-micron order.

[0095] When forming the sintered body, a binder material is mixed with the powder of the metal particles 51 to make a slurry. By shaping the slurry into a predetermined shape and then heating it, the plurality of metal particles 51 can be sintered together. The binder material evaporates during the heat treatment. The remaining sintered body becomes a porous body having voids 52 between the sintered metal particles 51.

[0096] As described above, since the sintered metal is formed from a paste-like raw material, the thickness of the wiring bonding layer WBL can be made thicker compared to the method of forming a metal film by plating. For example, in the case of this embodiment, the thickness of the wiring bonding layer WBL is about 60 μm. Since the thickness of the source electrode pad SE is about 5 μm, the thickness of the wiring bonding layer WBL is more than 10 times the thickness of the source electrode pad SE.

[0097] Therefore, the wiring bonding layer WBL made of sintered metal is likely to become thick, making it difficult for the external force applied during the bonding of the wiring 12 to be transmitted to the source electrode pad SE. In addition, the wiring bonding layer WBL, which is a porous body as described above, allows the external force applied during the bonding of the wiring 12 to be mitigated by the voids 52 in the wiring bonding layer WBL, making it difficult to be transmitted to the source electrode pad SE. In the present embodiment, a wire bonding WBL made of sintered metal is provided, and the wiring 12 is bonded to the wiring bonding layer WBL. This prevents or suppresses damage to the source electrode pad SE when bonding the wiring 12. By suppressing damage to the source electrode pad SE, the electrical connection reliability between the path electrical connection line 12 and the source electrode pad SE can be improved.

[0098] Each of the plurality of metal particles 51 is, for example, a copper particle. That is, the wiring bonding layer WBL is made of sintered copper. As described above, when bonding the wiring 12 made of copper, it is particularly preferable that the wiring bonding layer WBL is made of sintered copper.

[0099] However, as a modification example, each of the plurality of metal particles 51 can be, for example, a silver particle. In other words, the wiring bonding layer WBL can be made of sintered silver. Even when the WBL is made of sintered silver, it is possible to bond the wiring 12 and the wiring bonding layer WBL. However, compared with silver, copper is a metal with a hardness (Vickers hardness) more than twice that of silver. Therefore, sintered copper is preferably used as the material for the wiring bonding layer WBL for bonding the copper wiring 12.

[0100] In the case of the present embodiment, as Figure 7 shown, a metal film 60 is disposed between the wiring bonding layer WBL and the source electrode pad SE. A metal film 62 made of one of gold, silver, copper, and nickel is formed at a portion of the metal film 60 in contact with the wiring bonding layer WBL.

[0101] In Figure 7 the example shown, the metal film 60 is a laminated film composed of a metal film 61 formed on the source electrode pad SE and a metal film 62 formed on the metal film 61. The metal film 61 is, for example, a nickel film made of nickel. The metal film 62 is, for example, a gold film made of gold. For the following reasons, it is preferable to dispose the metal film 60 between the wiring bonding layer WBL and the source electrode pad SE.

[0102] That is, considering the characteristics of the electrical connection path between the source electrode pad SE and the wiring 12S, it is preferable to reduce the impedance in the electrical connection path between the wiring bonding layer WBL made of sintered metal and the source electrode pad SE. In this embodiment, the wiring bonding layer WBL is sintered on the source electrode pad SE to form a sintered body. At this time, the lower surface WBLb of the wiring bonding layer WBL is sintered to the underlying layer facing the lower surface WBLb (in the Figure 7 example shown is the metal film 62).

[0103] When the wiring bonding layer WBL is made of sintered copper, the underlying layer is preferably a metal that is easily sintered with copper. This is because sintering the sintered copper over the entire underlying layer can reduce the resistance value at the interface between the sintered copper and the underlying layer. Therefore, it is preferable that a metal film 62 made of one of gold, silver, copper, and nickel is formed at the bonding interface with the wiring bonding layer WBL.

[0104] As a modified example of this embodiment, there may be a case where the wiring bonding layer WBL is directly sintered on the source electrode pad SE. However, from the viewpoint of improving the bonding reliability of the path for electrically connecting the wiring bonding layer WBL and the source electrode pad SE to each other, it is preferable that a metal film 62 made of any one of gold, silver, copper, and nickel adheres to the lower surface WBLb of the wiring bonding layer WBL.

[0105] The metal film 61 shown in Figure 7 can be omitted. In the Figure 7 example shown, since the metal film 61 made of nickel is provided as the underlying layer of the metal film 62, it serves as an antioxidant film for preventing oxidation of the portion of the source electrode pad SE exposed from the insulating film 14.

[0106] <Details of the die bonding material>

[0107] Next, the peripheral structure of the die bonding material shown in Figure 8 will be described. Figure 4 The die bonding material 11 is composed of sintered metal in the case of this embodiment as shown in Figure 8 is an enlarged cross-sectional view showing each component of the semiconductor chip, die bonding material, and die pad shown in Figure 4 .

[0108] As shown in Figure 8 , in the case of this embodiment, the die bonding material 11 is composed of sintered metal. As shown in Figure 8As shown, the die bonding material 11 is a sintered body in which a plurality of metal particles 53 are sintered together. Each of the plurality of metal particles 53 is a fine particle having a particle size in the sub-micron order. In addition, a large number of metal particles 53 can be treated as powder. Metal particles with a particle size in the nano order can also be used. This allows the plurality of metal particles to be sintered together at a lower temperature and with a lower load. However, when using metal particles with a particle size in the nano order, there is a risk that the component cost (i.e., the manufacturing cost of the semiconductor device) can be higher compared to metal particles with a particle size in the sub-micron order. Metal particles with a particle size in the micron order can also be used. This can reduce the cost. However, when using metal particles with a particle size in the micron order, there is a risk that the reactivity (sinterability) is reduced compared to metal particles with a particle size in the sub-micron order. In addition, the die bonding material 11 as a sintered body is a porous body including voids 54 between the sintered metal particles 53. As Figure 8 shown, in the case where the die bonding material 11 is composed of sintered metal, the wiring bonding layer WBL (refer to Figure 7 ) can be sintered together with the die bonding material 11 during the sintering process.

[0109] In the case of this embodiment, the die bonding material 11 is composed of sintered copper same as the Figure 7 shown wiring bonding layer WBL. In other words, Figure 8 each of the plurality of metal particles 53 shown is a copper particle.

[0110] As a modified example of this embodiment, there may be a case where the wiring bonding layer WBL and the die bonding material 11 are made of different materials from each other. For example, one of the wiring bonding layer WBL and the die bonding material 11 may be made of sintered copper, while the other may be made of sintered silver. However, when performing the sintering process in batches, the sintering process temperature is treated at the same temperature. Therefore, from the perspective of aligning the sintered states of the wiring bonding layer WBL and the die bonding material 11, it is preferable that the wiring bonding layer WBL and the die bonding material 11 are made of the same material.

[0111] In addition, as another modified example of this embodiment, the die bonding material 11 can be made of, for example, solder or conductive resin. In this modified example, since the die bonding material 11 is hardened first and then the wiring bonding layer WBL is sintered, the sintering temperature of the wiring bonding layer WBL needs to be such that the already hardened die bonding material 11 does not remelt or suffer thermal damage.

[0112] Therefore, in terms of reducing the limitation on the sintering temperature, it is preferable that the wiring bonding layer WBL and the die bonding material 11 are made of sintered metal, and particularly preferably, they are made of the same material.

[0113] As Figure 8As shown, a metal film 65 made of one of gold, silver, copper, and nickel is formed at a portion of the drain electrode pad DE that contacts the die bonding material 11. In Figure 8 the example shown, the drain electrode pad DE is a laminated film of a metal film 63, a metal film 64, and a metal film 65 in sequence from the edge of the semiconductor substrate 13.

[0114] The metal film 63 is a titanium film made of titanium, and this titanium film has good adhesion to the semiconductor substrate 13 made of silicon. The metal film 64 is, for example, a nickel film made of nickel. In addition, the metal film 65 is, for example, a silver film made of silver.

[0115] If the die bonding material 11 is made of sintered silver, it is preferable that the metal film 65 is made of one of gold, silver, and copper. On the other hand, if the die bonding material 11 is made of sintered silver, it is preferable that the metal film 65 is made of one of gold, silver, copper, and nickel.

[0116] By placing the metal film 65 made of one of the above metals on a portion of the drain electrode pad DE that contacts the die bonding material 11 made of sintered metal, it is possible to easily sinter the die bonding material 11 and the drain electrode pad DE.

[0117] However, as described above, if the die bonding material 11 is made of solder or conductive resin, the metal film 65 is preferably made of gold or silver. When solder is bonded to the metal film 65 made of gold or silver, a good connection state of the bonding interface can be obtained.

[0118] In addition, if the die bonding material 11 is made of conductive resin, the electrical connection reliability can be improved by adhering various metal particles (for example, silver particles) included in the conductive particles to the metal film 65 made of gold or silver. Also, if the die bonding material 11 is conductive resin, the adhesion strength between the drain electrode pad DE and the die bonding material 11 is determined by the adhesion strength between the resin included in the conductive resin and the drain electrode pad DE.

[0119] In Figure 8 the example shown, the die bonding material 11 is directly bonded to the upper surface 20t of the die pad 20 made of copper or copper alloy. However, as Figure 8 a modified example, on the upper surface 20t of the die pad 20, a metal film (not shown) made of, for example, silver can be arranged, and the die bonding material 11 can be bonded to this metal film made of silver. In particular, when the die bonding material 11 is made of sintered silver, solder, or conductive resin, it is preferable to insert a metal film made of gold or silver between the die bonding material 11 and the die pad 20.

[0120] The wiring bonding layer WBL and the die bonding material 11 both include, for example, a sintered metal as described above, but their thicknesses are different from each other. That is, Figure 7 The thickness TWBL of the wiring bonding layer WBL shown is greater than the thickness T11 of the die bonding material 11.

[0121] As described above, the wiring bonding layer WBL is provided to prevent or suppress damage to the source electrode pad SE when bonding Figure 7 the wiring 12 shown. On the other hand, Figure 8 For the die bonding material 11 shown, as long as it realizes the functions of fixing the semiconductor chip 10 on the die pad 20 and electrically connecting the semiconductor chip 10 and the die pad 20, its thickness T11 can be thin. Therefore, preferably, the thickness TWBL of the wiring bonding layer WBL is greater than the thickness T11 of the die bonding material 11.

[0122] For example, the thickness TWBL of the wiring bonding layer WBL is about 60 μm. In addition, Figure 8 The thickness T11 of the die bonding material 11 shown (in other words, the separation distance between the lower surface 10b of the semiconductor chip 10 and the upper surface 20t of the die pad 20) is, for example, about 30 μm.

[0123] As described above, as a modification example of this embodiment, in the case where the die bonding material shown is solder or a conductive resin, it is not necessary to increase the thickness of the die bonding material 11, and preferably, the thickness TWBL of the wiring bonding layer WBL is greater than the thickness T11 of the die bonding material 11. Figure 4

[0124]

[0124] <Method of manufacturing a semiconductor device>

[0125] Next, a method of manufacturing the Figures 1 to 4 semiconductor device shown will be described. Figure 9 is a flowchart showing an example of the manufacturing process of the semiconductor device according to this embodiment. In the Figure 9 example shown, the method of manufacturing the semiconductor device of this embodiment includes a lead frame preparation process, a semiconductor chip mounting process, a wire bonding process, a packaging process, a solder film formation process, and a dicing process.

[0126] <Lead frame preparation step>

[0127] First, in the Figure 9 lead frame preparation step shown, the Figure 10 lead frame LF shown is prepared. Figure 10 is an enlarged plan view showing the components of the lead frame prepared in the Figure 9 lead frame preparation step shown.

[0128] As Figure 10 shown, the lead frame LF prepared in this step includes a plurality of device forming sections LFd connected to a frame section (frame member) LFf. Figure 10 Eight device forming sections LFd are shown. Each of the plurality of device forming sections LFd corresponds to Figure 1 one semiconductor device PKG1 shown. The lead frame LF is a so-called multi-unit substrate having a plurality of device forming sections LFd arranged in a matrix form. Therefore, using the lead frame LF including a plurality of device forming sections LFd allows mass production of a plurality of semiconductor devices PKG1 (refer to Figure 1 ), thereby improving manufacturing efficiency. Note that Figure 10 an example is shown in which a plurality of device forming sections LFd in two rows are arranged along the X direction, but there are various modified examples of the arrangement of the device forming sections LFd. For example, a single row or more than three rows can be used.

[0129] The lead frame LF is mainly made of copper (Cu). Each of the plurality of device forming sections LFd is connected to the frame section LFf. The frame section LFf serves as a support section that supports each component formed in the device forming section LFd until Figure 9 the dividing step shown.

[0130] In addition, as Figure 3 shown, a die pad 20 and a plurality of leads 30 are formed in the device forming section LFd. The die pad 20 is connected to the frame section LFf via one of the plurality of leads 30 and is supported by the frame section LFf. In addition, each of the plurality of leads 30 is connected to the frame section LFf and is supported by the frame section LFf.

[0131] Focusing on one of the plurality of device forming sections LFd, this step can be represented as a die pad preparation step, that is, a step for preparing a die pad having an upper surface 20t.

[0132] In addition, each of the plurality of leads 30 is interconnected via a tie bar LFT1. In Figure 10 the example shown, each of the plurality of die pads 20 is interconnected via a tie bar LFT2. As Figure 10 shown, the tie bar LFT2 is located on opposite sides of the plurality of leads 30 via the die pad 20 in the device forming section LFd and includes a side 20s2 opposite to the side 20s1 facing the plurality of leads 30.

[0133] As Figure 7 and Figure 9 shown, a groove T21 is formed in the die pad 20. During the lead frame preparation process, the groove T21 is formed by pressure processing using a die.

[0134] Among the multiple leads 30, each of the leads 30 corresponding to the Figure 3 shown source lead 30S and gate lead 30G has a lead bonding region 30W. In the lead frame preparation step, a metal film 33 is formed on the lead bonding region 30W so as to cover the upper surface 30t. The metal film 33 is made of silver and can be formed, for example, by plating.

[0135] As described above, a metal film made of, for example, silver can be formed on the upper surface 20t of the die pad 20. In this case, for example, the metal film 33 can be formed simultaneously while forming the metal film on the die pad 20.

[0136] <Die bonding step>

[0137] Next, in Figure 9 the shown die bonding step, as Figure 3 shown, the semiconductor chip 10 is mounted on the die pad 20. As Figure 9 shown, the die bonding step includes a die bonding paste application step and a semiconductor chip mounting step. Figure 11 is an enlarged cross-sectional view showing the state in which the die bonding paste is applied to the die pad in Figure 9 the die bonding paste application step. Figure 12 is an enlarged cross-sectional view showing the state in which the semiconductor chip is mounted on Figure 11 the shown die bonding paste.

[0138] In the die bonding paste application step, as Figure 11 shown, for example, a die bonding paste (die bonding paste) 11P is applied to the upper surface 20t of the die pad 20. The die bonding paste 11P has an adhesive 53B and a plurality of metal particles 53 mixed in the adhesive 53B.

[0139] In the present embodiment, each of the plurality of metal particles 53 is, for example, a copper particle. As a modified example, each of the plurality of metal particles 53 can be a silver particle. The adhesive 53B is an organic solvent that holds each of the plurality of metal particles 53 by its adhesiveness. As Figure 11 shown, the paste 11P as a whole has a paste-like property and can be formed on the die pad 20.

[0140] Although not shown in Figure 9 , after the die bonding paste application step and before the semiconductor chip mounting step, a drying step can be performed to dry Figure 11The paste 11P shown. In the drying step, for example, in a heating furnace where the lead frame LF is placed, heat treatment is performed at 120 degrees Celsius for about 10 minutes. If this drying step is performed, a part of the adhesive 53B evaporates, increasing the density of the various metal particles 53, thus making it easier to sinter the various metal particles 53 (see Figure 9 in the sintering treatment step shown. Figure 11 ) together.

[0141] In the semiconductor chip mounting step, as Figure 12 shown, the semiconductor chip 10 having a source electrode pad SE is mounted on the paste 11P for die bonding. In this step, the lower surface 10b of the semiconductor chip 10 is pressed against the paste 11P. At this time, due to the adhesiveness of the adhesive 53B included in the paste 11P, the lower surface 10b of the semiconductor chip 10 is adhered to the paste 11P.

[0142] As in this embodiment, when Figure 4 the die bonding material 11 shown is made of sintered metal, in this step, sintering is not performed, and the paste 11P is sintered in the sintering treatment step shown in Figure 9 .

[0143] On the other hand, as a modification example of this embodiment, when Figure 4 the die bonding material 11 shown is made of solder or conductive resin, the die bonding step includes a curing step of the die bonding material, as shown by the dotted line in Figure 9 . In the die bonding material step, the paste (solder paste or conductive resin paste) as the raw material of the die bonding material is cured.

[0144] In the case of curing the solder paste, in the die bonding material curing step, the solder paste is heated above the melting point of the solder included therein and then cooled (referred to as reflow processing). On the other hand, in the case of curing the conductive resin paste, in the die bonding material curing step, the conductive resin paste is heated above the curing temperature of the thermosetting resin included therein and maintained at a high temperature to cure the thermosetting resin (referred to as curing baking processing).

[0145] In these modification examples, when the die bonding step is completed, the semiconductor chip 10 is fixed to the die pad 20 via the die bonding material 11.

[0146] <Wire Bonding Layer Formation Step>

[0147] Next, Figure 9 the wire bonding layer formation step shown includes a sintered metal paste application step and a sintering treatment step. Figure 13 is shown in Figure 9An enlarged cross-sectional view of the state in which a paste for sintering metal is applied to a die pad during the sintered metal paste application process. Figure 14 Schematically shows the state in Figure 9 An explanatory diagram showing the state of heating a lead frame in a vacuum furnace during the sintering process shown.

[0148] In the sintered metal paste application step, for example, as shown in Figure 13 A paste (paste for sintering metal) WBLP, which is a raw material for a wiring bonding layer, is applied to the source electrode pad SE of the semiconductor chip 10. The paste for the wiring bonding layer 11P includes an adhesive 51B and a plurality of metal particles 51 mixed in the adhesive 51B.

[0149] In the present embodiment, each of the plurality of metal particles 51 is, for example, a copper particle. As a modified example, there may be a case where each of the plurality of metal particles 51 is a silver particle. The adhesive 51B is an organic solvent that holds each of the plurality of metal particles 51 by its adhesiveness. The paste WBLP as a whole has a paste-like property and can be formed thickly on the source electrode pad SE, as shown in Figure 13 shown.

[0150] In the present embodiment, the thickness of the paste WBLP applied to the source electrode pad SE is, for example, 60 μm or more. Therefore, in the method of applying the paste WBLP, for example, compared with the method of forming a metal film by plating, it is possible to make the Figure 7 thickness TWBL of the wiring bonding layer WBL shown thicker.

[0151] Various methods can be used to apply the paste WBLP. For example, as a method of applying the paste WBLP, a method can be exemplified in which the paste WBLP is directly dispensed onto the source electrode pad SE using a dispenser (not shown in the figure) and then formed. Or a method can be exemplified in which the paste WBLP is directly applied to the source electrode pad SE using a printing coating device (not shown in the figure) while being formed into a plate shape. Or a method can be exemplified in which, as shown in Figure 13 shown, the paste WBLP pre-formed into a plate shape is arranged on the source electrode pad SE.

[0152] Although not shown in Figure 9 , after the sintered paste application step and before the sintering treatment step, a drying step can be performed in which the applied paste WBLP (refer to Figure 13) is dried. In the drying step, for example, when the lead frame LF is placed in a heating furnace (not shown in the figure), heat treatment is performed at 120 degrees Celsius for about 10 minutes. When this drying step is carried out, a part of the adhesive 51B evaporates, increasing the density of the various metal particles 51, thus making it easier to sinter the various metal particles 51 (refer to Figure 9 ) together in the sintering treatment step shown in Figure 13 .

[0153] Next, in the sintering treatment step shown in Figure 9 , as shown in Figure 14 , for example, the lead frame LF is placed in a vacuum furnace 70 and heated in a reduced-pressure atmosphere. In the example shown in Figure 14 , the vacuum furnace 70 is equipped with a sealed space connected to a vacuum pump 71, and a reduced-pressure state can be created by discharging the gas in the sealed space to the outside with the vacuum pump 71. In addition, a heater 72 is arranged inside the vacuum furnace 70 and can heat the temperature inside the sealed space. It should be noted that there are various modified examples of the method for heating the lead frame LF placed inside the vacuum furnace 70. For example, in the example shown in Figure 14 , the heater can be incorporated into the stage 73 and the pressing jig 74.

[0154] The reason for performing this step in a reduced-pressure atmosphere is to suppress the growth of the oxide film formed on the sintered metal surface during the sintering process. In particular, when sintering copper, since it is easier to form an oxide film compared to sintering silver, it is preferable to perform the sintering treatment step in a reduced-pressure atmosphere.

[0155] As a modified example of this embodiment, there is a method of performing the sintering treatment step in an inert gas atmosphere such as nitrogen. Alternatively, as another modified example, there is a method of performing the sintering treatment step in a reducing atmosphere using, for example, formic acid. From the perspective of preventing the growth of the oxide film formed on the sintered metal, the modified examples performed in an inert gas atmosphere or a reducing atmosphere are also effective.

[0156] However, when the sintering treatment step is performed in a reduced-pressure atmosphere, the effect of promoting the evaporation of the adhesive 51B shown in Figure 13 can be obtained. In this regard, it is particularly preferable to perform the sintering treatment step in a reduced-pressure atmosphere.

[0157] In the sintering treatment step, as shown in Figure 14As schematically shown by the white arrow, under pressure application, the lead frame LF is heated while being clamped between the stage 73 and the pressing jig 74. The heating temperature and time vary depending on the type of metal used. However, for example, in the case of forming sintered copper, it is heated at 260 degrees Celsius for 5 minutes under a pressure of 10 MPa.

[0158] In this step, from the perspective of more easily controlling the sintering state of the die bonding material 11 and the wiring bonding layer WBL, as already described, it is particularly preferable that the die bonding material 11 and the wiring bonding layer WBL are made of the same sintered metal.

[0159] Figure 11 The various metal particles 53 shown are sintered and bonded together through this step. At this time, as Figure 8 shown, one part of the various metal particles 53 is sintered to the die pad 20, and the other part is sintered to the drain electrode pad DE.

[0160] Similarly, Figure 13 the various metal particles 51 shown are sintered and bonded together through this step. At this time, as Figure 7 shown, one part of the various metal particles 51 is sintered to the source electrode pad SE (specifically, sintered to the metal film 62 formed on the source electrode pad SE).

[0161] It should be noted that although Figure 13 an example of the state where the paste WBLP is applied to the source electrode pad SE is shown, in the case of forming the wiring bonding layer WBLG on the gate electrode pad GE shown in Figure 3 , in this step, the paste WBLP (refer to Figure 13 ) that will become the raw material for the wiring bonding layer WBLG is applied to the gate electrode pad GE.

[0162] <Cleaning Step>

[0163] Next, before the wiring bonding step shown in Figure 9 , there may be a step of cleaning the wiring bonding layer formed in the wiring bonding layer forming step shown in Figure 9 as a cleaning treatment step. In the cleaning step, the wiring bonding layer is cleaned using a cleaning material to remove the oxide film formed on the surface of the wiring bonding layer, and thus expose the unoxidized metal on the surface. The cleaning material used in this embodiment is closer to neutral than acidic. Therefore, it is possible to reduce damage to the wiring bonding layer. On the other hand, if it is desired to ensure the removal of the oxide film, an acidic cleaning material can be used.

[0164] The pickling step includes the steps of removing the oxide film with an acidic solution such as sulfuric acid, washing away the acidic solution with water, and drying to remove the residual moisture.

[0165] If the oxide film can be removed by the pickling step, Figure 9 the sintering step shown can be carried out in an atmospheric environment. In addition, by carrying out the sintering step under reduced pressure, in an inert gas atmosphere, or in a reducing atmosphere, if the thickness of the oxide film formed on the surface of the wiring bonding layer between the sintering step and the wiring bonding step is negligibly thin, the pickling step can be omitted.

[0166] However, as described above, since the sintered metal is a porous body, there are cases where the cleaning liquid does not completely cover the metal surface. In addition, there can be a long lag between the wiring bonding layer formation step and the wiring bonding step. In such cases, there is a risk of oxide film growth on the surface of the sintered metal. Therefore, from the perspective of connecting the wiring 12 and the wiring bonding layer WBL in a good connection state as Figure 7 shown, it is particularly preferable to carry out the sintering step under reduced pressure, in an inert gas atmosphere, or in a reducing atmosphere, and to carry out the pickling step before the wiring bonding step.

[0167] <Wiring Bonding Step>

[0168] Next, in Figure 9 the wiring bonding step shown, as Figure 3 shown, a plurality of electrode pads (gate electrode pads GE and source electrode pads SE) of the semiconductor chip 10 and a plurality of leads 30 are electrically connected to each other via wiring (metal wiring) 12. Figure 15 is a magnified cross-sectional view schematically showing the state of applying a load and ultrasonic waves to the wiring by a bonding tool in Figure 9 the wiring bonding step shown.

[0169] In this step, the gate electrode pad GE of the semiconductor chip 10 and the lead 30G are electrically connected to each other via the wiring 12G (and the wiring bonding layer WBLG). In addition, in this step, the source electrode pad SE of the semiconductor chip 10 and the lead 30S are electrically connected to each other via the wiring 12S and the wiring bonding layer WBLS.

[0170] Various modification examples can be applied to the method of connecting the wiring 12. The wedge bonding method using a bonding tool called a wedge tool can be exemplified.

[0171] In the present embodiment, a metal film 33 made of silver is formed in the lead bonding region 30W (refer to Figure 4) One end of the wiring 12 is bonded to one of the gate electrode pad GE and the source electrode pad SE, and the other end of the wiring 12 is bonded to the metal film 33 formed in the wiring bonding region 30W.

[0172] In this embodiment, in the wiring bonding step, as Figure 15 shown, the wiring 12 made of a metal different from the source electrode pad SE is bonded to the wiring bonding layer WBL. As an example, as described above, the source electrode pad SE is mainly made of aluminum, and the wiring 12S is made of copper.

[0173] In the wiring bonding step, in order to ensure that the wiring 12 and the wiring bonding layer WBL are firmly bonded, as Figure 15 schematically shown, the wiring 12 and the wiring bonding layer WBL are bonded in a state where ultrasonic waves USW and a load F1 are applied to the wiring 12. In addition, in the wiring bonding step, in order to ensure that the wiring 12 and the wiring bonding layer WBL are firmly bonded, the wiring 12 is bonded to the wiring bonding layer WBL in a heated state.

[0174] At this time, when the wiring 12 is directly bonded to Figure 15 the source electrode pad SE shown, or is bonded to Figure 15 the metal film 60 shown, the force transmitted to the source electrode pad SE through the rigid wiring 12 may damage the source electrode pad SE.

[0175] On the other hand, in this embodiment, as already described, since the paste raw material is molded, the wiring bonding layer WBL made of sintered metal can be thicker than the method of forming a metal film by plating. Therefore, the external force when bonding the wiring 12 is less likely to be transmitted to the source electrode pad SE.

[0176] In addition, the wiring bonding layer WBL made of sintered metal is a porous body. Therefore, the external force when bonding the wiring 12 is alleviated by the voids 52 of the wiring bonding layer WBL, making it difficult to be transmitted to the source electrode pad SE. In the case of this embodiment, a wiring bonding layer WBL made of sintered metal is provided, and the wiring 12 is bonded to the wiring bonding layer WBL. As a result, when bonding the wiring 12, it is possible to prevent or suppress damage to the source electrode pad SE. By suppressing damage to the source electrode pad SE, it is possible to improve the electrical connection reliability of the path for electrically connecting the wiring 12 and the source electrode pad SE.

[0177] In this section, the step of electrically connecting the source electrode pad SE and the wiring 12S is described as an example, but the step of electrically connecting Figure 3 the gate electrode pad GE and the wiring 12G shown is similar.

[0178] In addition, in the case of this embodiment, the cleaning step is not performed after the wire bonding step. However, as an example of a modification, the above-described acid cleaning step may be performed after the wire bonding step. Since the wire bonding step is performed in a heated state, an oxide film may be formed on the wire bonding layer WBL during the wire bonding step, and the oxide film may grow. If the pickling step is performed after the wire bonding step, it is possible to remove the oxide film, thereby suppressing an increase in the resistance value of the wire bonding layer WBL.

[0179] <Sealing step>

[0180] Next, in Figure 9 the sealing step shown, the semiconductor chip 10, the components of the die pad 20, and the components of each of the plurality of leads 30 ( Figure 3 the inner lead portion 30M shown in Figure 4 ) the wire bonding layer WBL, and the plurality of wirings 12 are sealed with an insulating resin to form Figure 4 the sealed body 40 shown.

[0181] In this step, for example, a molding die including an upper die (first die) and a lower die (second die) is used to form the package body 40 by a so-called transfer molding method. By placing the lead frame LF, the Figure 10 die pad 20 and the plurality of leads 30 (refer to Figure 4 ) of the device forming component LFd shown in

[0182] the inner lead portion 30M are positioned in the cavity of the molding die. Then, the lead frame LF is clamped between the upper die and the lower die. In this state, when the softened (plasticized) thermosetting resin (insulating resin) is pressed into the cavity of the molding die, the insulating resin is molded according to the shape of the cavity. Figure 4 At this time, the components of the upper surface 20t of the die pad 20 adjacent to the edge 20s2 and the lower surface 20b of the die pad 20 are in close contact with the molding die. Therefore, as

[0183] shown, after this step, the components of the upper surface 20t and the lower surface 20b of the die pad 20 are exposed from the sealed body 40.

[0184] In addition, although the sealing body 40 is mainly composed of an insulating resin, it is possible to improve the function (e.g., warpage deformation resistance) of the sealing body 40 by mixing particles such as silica (silicon dioxide; SiO2) into the thermosetting resin.

[0185] <Solder film forming step>

[0186] Although not shown in Figure 9 when forming the Figure 4 shown metal film 32, as a solder film forming step, the lead frame LF is immersed in a plating solution (not shown), and a metal film ( Figure 4 shown metal film 32) is formed on the surface of the metal component (outer component) exposed from the sealing body 40. For example, a metal film 22 formed on the lower surface 20b of the die pad 20 shown in Figure 4 is preformed in the lead frame preparation step. As a method for forming the metal film 22, plating can be exemplified, for example.

[0187] In this step, for example, by the solder dipping method, a metal film 32 made of solder (refer to Figure 4 ) is formed on each exposed component of the plurality of leads 30 ( Figure 4 shown outer lead component 30X). Although not shown, the solder dipping method includes placing the Figure 10 shown lead frame LF in a solder bath including molten solder. At this time, only the components of the plurality of leads 30 are selectively immersed in the molten solder, and most of the sealing body 40 is not immersed in the molten solder. This allows a metal film 32 made of solder (refer to Figure 4 ) to be formed on each of the plurality of leads 30.

[0188] <Dividing step>

[0189] Next, Figure 9 the dividing step shown in Figure 10 includes a lead cutting process for cutting the tip components of the plurality of leads 30 shown in Figure 10 and a tie bar cutting step for cutting the tie bar LFT1 shown in Figure 4 . In the case of this embodiment, the dividing step includes a lead forming step for bending the outer lead component 30X of the lead 30, as shown in Figure 4 . For example, in this embodiment, the dividing step is performed in the order of the lead cutting step, the lead forming step, and the tie bar cutting step.

[0190] In the lead cutting step, multiple leads 30 are separated from the frame section LFf, thereby separating each of the multiple leads 30. In this step, the tip components of the multiple leads 30 are cut by a stamping process (cutting process) using a punch and a die (not shown). The newly formed tip surface in this step is not covered by the metal film 32.

[0191] In the lead forming step, the outer lead portion 30X of the lead 30 is formed by a stamping process using a punch and a die (not shown in the figure). In Figure 4 the example shown, the outer lead portion 30X is formed in a gull-wing shape.

[0192] In the tie bar cutting step, the Figure 10 shown tie bar Lft1 is cut. Further, in the tie bar cutting step, the tie bar Lft2 is cut, and each of the multiple die pads 20 connected via the tie bar Lft2 is divided. After this step, the multiple leads 30 are connected via the frame section LFf. Further, the multiple die pads 20 are connected via the drain lead 30D and the frame section LFf, and the drain lead 30D serves as a suspension lead (see Figure 3 ).

[0193] To cut the tie bars Lft1 and Lft2, a stamping process (cutting process) using a punch and a die (not shown in the figure) can be used. This step is performed after the solder film forming step, so the newly formed edges in this step are not covered by the metal film 32. By this step, Figure 10 the shown device forming section LFd is individualized, and the Figure 1 shown semiconductor device is obtained.

[0194] Through the above process, the Figures 1 to 4 shown semiconductor device PKG1 is obtained. Thereafter, tests such as electrical tests and visual inspections are performed as needed, and those tests determined to be defect-free are conveyed to the next step, such as the packaging of the semiconductor device.

[0195] Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its gist.

Claims

1. A semiconductor device, comprising: Die pad; a lead, spaced apart from the die pad; a semiconductor chip mounted on the die pad via a die bonding material, the semiconductor chip comprising a first electrode pad; a wiring electrically connected to each of the lead of the semiconductor chip and the first electrode pad; as well as a sealing body, sealing the semiconductor chip, the die bonding material and the wiring, wherein the first electrode pad and the wiring are made of different types of metal from each other, wherein a wiring bonding layer made of sintered metal is disposed between the first electrode pad and the lead, and The wiring is electrically connected to the first electrode pad via the wiring bonding layer.

2. The semiconductor device according to claim 1, wherein the wiring is made of copper, and The first electrode pad is mainly made of aluminum.

3. The semiconductor device according to claim 2, wherein the wire bonding layer is made of sintered copper.

4. The semiconductor device according to claim 3, wherein a first metal film is disposed between the wiring bonding layer and the first electrode pad, and A metal film made of one of gold, silver, copper, and nickel is formed at a portion of the first metal film in contact with the wire bonding layer. 5 . The semiconductor device according to claim 1 , wherein the die bonding material is made of a sintered metal.

6. The semiconductor device according to claim 5, wherein the wiring is made of copper, wherein the first electrode pad is mainly made of aluminum, and Wherein each of the wire bonding layer and the die bonding material is made of sintered copper.

7. The semiconductor device according to claim 5, The semiconductor chip has: a first surface, facing the die pad, a second surface, opposite to the first surface, and a second electrode pad formed on the second surface, wherein the first metal film is disposed between the wiring bonding layer and the first electrode pad, wherein a metal film made of one of gold, silver, copper and nickel is formed at a portion of the first metal film in contact with the wiring bonding layer, and A metal film made of one of gold, silver, copper and nickel is formed at a portion of the second electrode pad that is in contact with the die bonding material. 8 . The semiconductor device according to claim 5 , wherein a thickness of the wire bonding layer is greater than a thickness of the die bonding material.

9. The semiconductor device according to claim 1, wherein the semiconductor chip includes a power transistor made of one of a power MOSFET and an IGBT, and The first electrode pad is electrically connected to the source of the power MOSFET or the emitter of the IGBT.

10. A method for manufacturing a semiconductor device, comprising the steps of: (a) preparing a lead frame including a die pad; (b) applying a first slurry onto the die pad; (c) mounting a semiconductor chip on the first paste, the semiconductor chip having a first electrode pad; (d) disposing a second paste including a plurality of metal particles on the first electrode pad of the semiconductor chip; (e) sintering the plurality of metal particles included in the second paste by heating, thereby forming a wiring bonding layer; as well as (f) bonding a wire to the wire bonding layer, the wire being made of a metal different from that of the first electrode pad.

11. The method according to claim 10, wherein the first slurry is made of the same material as the second slurry, and Wherein in the step (e), by heating the first slurry, the plurality of metal particles included in the first slurry are sintered, thereby forming a die bonding material for fixing the semiconductor chip on the die pad.

12. The method according to claim 11, wherein each of the plurality of metal particles is a copper particle, and After the step (e) and before the step (f), the wiring bonding layer is cleaned by using an acidic cleaning material.

13. The method according to claim 10, wherein in the step (f), the wiring and the wiring bonding layer are bonded to each other under the condition that ultrasonic waves and a load are applied to the wiring.

14. The method according to claim 10, wherein the wiring is made of copper, and The first electrode pad is mainly made of aluminum.

15. The method of claim 13, wherein each of the plurality of metal particles is copper.

16. The method according to claim 10, wherein the step (e) is performed under one of a reduced pressure treatment atmosphere, an inert gas atmosphere, and a reducing atmosphere.

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