Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes a semiconductor layer having an N-type drift region, a P-type body region on the N-type drift region, and an N-type source region on the P-type body region; an insulating layer on the semiconductor layer; a first opening disposed in the insulating layer; a second opening disposed in the semiconductor layer and extending from the N-type source region to the P-type body region so as to overlap the first opening in a plan view; an insulating film disposed on a sidewall of the second opening; a first metal layer disposed on the insulating layer, the semiconductor layer of the first opening, the insulating film, and the semiconductor layer of the second opening; and a second metal layer disposed on the first metal layer.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-212241, filed on December 15, 2023 (including the specification, drawings, and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2008-42056

[0006] A technology for miniaturizing semiconductor devices is being developed.

[0007] However, when manufacturing electrodes, there is a problem that the barrier metal breaks, causing a reaction between the semiconductor layer and the material forming the electrodes.

[0008] Other problems and novel features will become clear from the description of the present specification and the drawings. Summary of the Invention

[0009] According to one embodiment, a semiconductor device has a structure in which sidewalls of a source region and a body region are covered with an insulating film to prevent reaction with electrodes.

[0010] According to this embodiment, a highly reliable semiconductor device can be provided. Brief Description of the Drawings

[0011] Figure 1 A diagram including a method for manufacturing an electrode of a semiconductor device showing the prior art;

[0012] Figure 2 A diagram including a method for manufacturing an electrode of a semiconductor device showing the present disclosure;

[0013] Figure 3 A schematic diagram of a semiconductor device of the present disclosure;

[0014] Figure 4 A schematic diagram of another semiconductor device of the present disclosure; and

[0015] Figure 5 A diagram including a method for manufacturing a semiconductor device showing the present disclosure. Detailed Description of the Embodiments

[0016] [Embodiment]

[0017] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention according to the claims is not limited to the following embodiments. In addition, not all configurations described in the embodiments must be means for solving the problems. For clarity, some parts are appropriately omitted or simplified in the following description and drawings. In each figure, the same elements are denoted by the same reference numerals, and redundant descriptions thereof are appropriately omitted.

[0018] (Semiconductor device according to the first embodiment)

[0019] Figure 1 A figure showing a method for manufacturing an electrode of a semiconductor device of the prior art is included. Figure 2 A figure showing a method for manufacturing an electrode of a semiconductor device of the present disclosure is included. Figure 3 It is a schematic diagram of a semiconductor device of the present disclosure. Hereinafter, with reference to Figures 1 - 3 the semiconductor device according to the first embodiment will be described.

[0020] As Figure 1 shown in (a) of

[0021] the semiconductor device of the prior art includes a semiconductor layer, which includes an N-type drift region 108, a P-type body region 107 on the N-type drift region 108, and an N-type source region 106 on the P-type body region 107. The semiconductor device is provided on a semiconductor substrate (such as a silicon substrate for example), and the semiconductor layer uses the components of the semiconductor substrate. A trench is formed in the semiconductor layer, and an embedded insulating film 103, a shielding electrode 102, and a gate electrode 101 are embedded in the trench. An insulating layer 104 is formed on the semiconductor layer. Sidewalls 105 for self-aligned contact (SAC-SW) are provided on the sidewalls of the insulating layer 104. In the present specification, the insulating layer 104 may include SAC-SW.

[0022] The N-type drift region 108 is formed as N-type to allow electron flow. When the semiconductor device is turned on and a positive voltage is applied to the gate electrode 101, the P-type body region 107 forms a channel and allows electron flow. A small amount of P-type impurities (such as boron (B)) are introduced into the P-type body region 107. When the semiconductor device is turned on, the N-type source region 106 injects electrons. N-type impurities are introduced into the N-type source region 106. The N-type source region 106 has more N-type impurities than the N-type drift region 108.

[0023] For example, the semiconductor device according to the above embodiment may have a configuration in which the conductivity type (P-type or N-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. is reversed. Therefore, when one of the N-type and P-type conductivity types is the first conductivity type and the other is the second conductivity type, the first conductivity type may be P-type and the second conductivity type may be N-type, or conversely, the first conductivity type may be N-type and the second conductivity type may be P-type.

[0024] The embedded insulating film 103 is formed to insulate the shielding electrode 102 and the gate electrode 101 from the semiconductor layer. The embedded insulating film 103 can be used as the field plate insulating film 121 and the gate insulating film 122. The embedded insulating film 103 on the side surface of the shielding electrode 102 serves as the field plate insulating film 121, and the embedded insulating film 103 on the side surface of the gate electrode 101 serves as the gate insulating film 122.

[0025] The gate electrode 101 is made of, for example, polysilicon. Applying a voltage to the gate electrode 101 allows the semiconductor device to control the current between the source and the drain. The shielding electrode 102 is an electrode to which a ground potential or the same voltage as the gate electrode can be applied. The shielding electrode 102 is made of polysilicon. The shielding electrode 102 helps to control the semiconductor device.

[0026] SAC 109 is a technique for forming an electrode by introducing impurities in a self-aligned manner. SAC 109 allows for element miniaturization beyond the limits of lithography. Here, it is used to form the second opening 116 in the N-type source region 106. The source electrode is formed in the second opening 116. Therefore, the second opening 116 is formed to penetrate the N-type source region 106 and extend to the middle of the P-type body region 107.

[0027] As Figure 1 shown in (b) of [], the SAC-SW 105 is retracted by performing wet etching to form the first opening 115 in the insulating layer 104. In this process, the silicon on the source region 106 is exposed.

[0028] As Figure 1As shown in (c) thereof, P-type impurities such as boron are introduced into the opening at a high concentration. To obtain an ohmic contact, a first metal layer 110 made of titanium (Ti) is formed, and a barrier metal 111 made of titanium nitride (TiN) is formed on the first metal layer.

[0029] As Figure 1 As shown in (d) thereof, heat treatment is performed in this state, and the first metal layer reacts with the semiconductor layer to form a silicide. In particular, when the first metal layer is titanium, titanium silicide is formed.

[0030] As the device is miniaturized, the cohesion 112 of titanium silicide occurs. Depending on the titanium silicide formation conditions, the cohesion of titanium silicide occurs at the side surface of the semiconductor layer and at the bottom of the N-type source region 106 and the P-type body region 107. Since the thickness of the titanium film between the sidewall portion and the bottom of the N-type source region 106 and the P-type body region 107 is different, the degree of cohesion of titanium silicide is different, resulting in stress generation. Therefore, the barrier metal 111 made of titanium nitride on the sidewall of the semiconductor layer breaks.

[0031] Then, as Figure 1 As shown in (e) thereof, when tungsten (W) plug 113 as the second metal layer is embedded in the opening using tungsten fluoride, fluorine enters from the sidewall of the semiconductor layer not covered by the barrier metal and reacts with the semiconductor layer, resulting in the formation of wormholes 114.

[0032] The semiconductor device of the present disclosure is a technology for preventing such wormholes 114. Since this process is the same as Figure 1 the same, the details of this technology before forming the SAC 109 are omitted. As Figure 2 As shown in (a) thereof, after forming the second opening 116 for embedding the source electrode in the insulating layer 104 and the semiconductor layer, the SAC-SW 105 is retracted. Retracting the SAC-SW 105 allows the formation of a first opening 115 in the insulating layer 104 and the sidewall that overlaps the second opening 116 in the plan view. A first opening 115 that overlaps the second opening 116 in the plan view is formed in the insulating layer 104 and the sidewall. Then, an insulating film 117 is disposed in the first opening 115 and the second opening 116.

[0033] Next, as Figure 2 As shown in (b) thereof, the insulating film 117 on the upper surface of the semiconductor layer is removed by performing anisotropic etching while retaining the insulating layer 117 on the side surface of the semiconductor layer to form an insulating film 117 on the sidewall of the semiconductor layer.

[0034] A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate of such films can be used for the insulating film 117. The insulating film 117 can be the same silicon oxide film as that of the SAC-SW. Using a silicon nitride film as the insulating film 117 allows subsequent processing without reducing the film thickness, so that the film thickness can be reduced. By forming the insulating film 117 into a multilayer structure including a silicon oxide film and a silicon nitride film, the reduction in film thickness and the stress caused by the silicon nitride film can be alleviated.

[0035] Then, as shown in (c) of Figure 2 , a P-type impurity such as boron is implanted into the second opening 116 at a high concentration to provide titanium as the first metal layer and titanium nitride as the barrier metal. The titanium of the first metal layer reacts with the silicon (Si) of the semiconductor layer to form titanium silicide 118 on the upper surfaces of the source region and the P-type body region.

[0036] As shown in (d) of Figure 2 , at the sidewall of the semiconductor layer, the insulating film 117 contacts the titanium, but the titanium and the silicon do not contact, so no titanium silicide is formed and no cohesion 112 occurs. The titanium as the first metal layer only reacts with the silicon contacting the semiconductor layer on the upper surface of the semiconductor layer.

[0037] As shown in (e) of Figure 2 , when tungsten as the second metal layer is embedded, due to the difference in cohesion, no stress is generated, so the barrier metal does not break and no wormholes are formed. In this way, a highly reliable semiconductor device can be obtained.

[0038] As shown in Figure 3 , silicide 119 is formed on the upper surface of the N-type source region, and silicide 118 is formed on the upper surface of the P-type body region. At the side surfaces of the N-type source region 106 and the P-type body region 107, the insulating film 117 contacts the first metal layer 110, but the first metal layer 110 and the semiconductor layer do not contact, so no silicide is formed and no cohesion 112 and stress caused by the difference in cohesion occur.

[0039] Here, titanium is used for the first metal layer. However, cobalt (Co) can also be used. The same titanium nitride is used for the barrier metal. By using cobalt, the wire can be made thinner and the increase in resistance due to cohesion can be suppressed. When using cobalt, the first metal layer is formed before introducing the P-type impurity into the second opening. Preferably, the P-type impurity is introduced after forming cobalt silicide to suppress the generation of spikes in the cobalt silicide.

[0040] (Semiconductor device according to the second embodiment)

[0041] Figure 4 is a schematic diagram of another semiconductor device of the present disclosure. Hereinafter, reference will be made toFigure 4 Describe a semiconductor device according to the second embodiment.

[0042] The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that the SAC-SW 105 is not formed. That is, in the semiconductor device according to the second embodiment, an opening is formed in the insulating layer 104 using conventional lithography.

[0043] As Figure 4 shown, an insulating film 117 is formed on the sidewalls of the insulating layer 104 and the semiconductor layer. Therefore, in the semiconductor device according to the second embodiment, the barrier metal does not break and no wormholes are formed. In addition, the insulating film is removed from the upper surfaces of the insulating layer 104 and the semiconductor layer. Therefore, in the first metal layer and the semiconductor layer, silicide 119 is formed on the upper surface of the N-type source region, and silicide 118 is formed on the upper surface of the P-type body region. In this way, a highly reliable semiconductor device can be obtained.

[0044] (Method for manufacturing a semiconductor device according to the first embodiment)

[0045] Figure 5 Includes a diagram showing a method for manufacturing a semiconductor device of the present disclosure. Hereinafter, reference will be made to Figure 5 Describe a method for manufacturing a semiconductor device according to the first embodiment.

[0046] As Figure 5 shown in the upper figure above, a semiconductor layer is formed, in which an N-type drift region 108, a P-type body region 107 on the N-type drift region 108, and an N-type source region 106 on the P-type body region 107 are formed. Next, a gate electrode 101, a shielding electrode 102, and an embedded insulating film 103 are formed in the semiconductor layer. The embedded insulating film 103 has a field plate insulating film 121 and a gate insulating film 122. An insulating layer 104 is formed on the semiconductor layer and the gate electrode 101. Next, sidewalls 105 are formed on the side surfaces of the insulating layer 104. A second opening 116 extending from the N-type source region 106 to the P-type body region 107 is formed in the semiconductor layer.

[0047] As Figure 5 shown in the lower figure below, the sidewalls 105 are retracted to form a first opening 115 in the insulating layer 104. In the cross-sectional view, the first opening 115 overlaps with the second opening 116. Next, an insulating film 117 is formed on the insulating layer 104, the sidewalls 105, and the semiconductor layer. Next, the insulating film 117 is removed from the semiconductor layer while the insulating film 117 on the sidewalls of the semiconductor layer remains as it is. The insulating film 17 is removed by using, for example, anisotropic etching.

[0048] Next, a P-type impurity is implanted into the semiconductor layer and activated by heat treatment. Next, a first metal layer 110 is formed on the insulating layer 104, sidewalls 105, and the semiconductor layer. The first metal layer 110 also covers the insulating film 117. The first metal layer 110 is, for example, a titanium-containing material, and the titanium-containing material is a laminate of titanium and titanium nitride. A titanium-containing metal layer is formed and heated to form a silicide 118 of the semiconductor layer and titanium.

[0049] A second metal layer 113 is formed on the first metal layer 110. The second metal layer 113 is a tungsten-containing material. After forming the second metal layer 113, a wiring layer 120 made of aluminum copper (Al-Cu) is formed to complete the semiconductor device.

[0050] A third metal layer may be provided between the first metal layer 110 and the second metal layer 113. For example, if cobalt is used for the first metal layer 110, a titanium-containing material is used for the third metal layer, and a tungsten-containing material is used for the second metal layer 113. After forming cobalt, heating is performed to form a silicide. The titanium-containing material is a laminate of titanium and titanium nitride and serves as a barrier metal for tungsten.

[0051] In this way, a highly reliable semiconductor device can be obtained.

[0052] In the above, the invention of the present inventor has been described in detail based on the embodiments. However, the present invention is not limited to the above embodiments and various modifications can be made without departing from the gist of the present invention.

Claims

1. A semiconductor device, comprising: A semiconductor layer, comprising an N-type drift region, a P-type body region on the N-type drift region, and an N-type source region on the P-type body region; an insulating layer on the semiconductor layer; A first opening is provided in the insulating layer; a second opening disposed in the semiconductor layer and extending from the N-type source region to the P-type body region to overlap with the first opening in a plan view; an insulating film disposed on a side wall of the second opening; A first metal layer is disposed on the insulating layer, the semiconductor layer of the first opening, the insulating film, and the semiconductor layer of the second opening; as well as The second metal layer is disposed on the first metal layer.

2. The semiconductor device according to claim 1, wherein the insulating layer comprises side walls, wherein the second opening is formed by the sidewall in a self-aligned manner, and Wherein the first opening is formed by retracting the side wall.

3. The semiconductor device according to claim 1, wherein the first metal layer comprises titanium, wherein the second metal layer comprises tungsten, and The titanium forms silicide in a region in contact with the semiconductor layer.

4. The semiconductor device according to claim 1, wherein the third metal layer is disposed between the first metal layer and the second metal layer, wherein the first metal layer comprises cobalt, wherein the second metal layer comprises tungsten, wherein the third metal layer comprises titanium, and The cobalt forms silicide in a region in contact with the semiconductor layer.

5. The semiconductor device according to claim 1, wherein a trench is provided in the semiconductor layer, and The embedded insulating film, the shielding electrode and the gate electrode are arranged in the groove.

6. A method for manufacturing a semiconductor device, comprising: forming a semiconductor layer, in which an N-type drift region, a P-type body region on the N-type drift region, and an N-type source region on the P-type body region are formed; forming a field plate insulating film, a gate insulating film, a shielding electrode and a gate electrode in the semiconductor layer; forming an insulating layer on the gate electrode and the semiconductor layer; forming side walls on side surfaces of the insulating layer; forming a second opening in the semiconductor layer, the second opening extending from the N-type source region to the P-type body region; retracting the sidewall to form a first opening in the insulating layer, the first opening overlapping the second opening in plan view; forming an insulating film on the insulating layer, the sidewalls and the semiconductor layer; removing the insulating film on the semiconductor layer while leaving the insulating film on the side surface of the semiconductor layer as it is; injecting P-type impurities into the semiconductor layer; activating the P-type impurities; forming a first metal layer on the insulating layer and the semiconductor layer; as well as A second metal layer is formed on the first metal layer. 7 . The method for manufacturing a semiconductor device according to claim 6 , comprising forming silicide by performing heating after forming the first metal layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the first metal layer comprises titanium, and The second metal layer includes tungsten.

9. The method for manufacturing a semiconductor device according to claim 7, wherein the third metal layer is disposed between the first metal layer and the second metal layer, Wherein the first metal layer comprises cobalt, wherein the second metal layer comprises tungsten, and wherein the third metal layer comprises titanium.

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