Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a first wafer and a second wafer. The first wafer includes a first substrate, a stress adjusting structure and a first bonding structure. The stress adjustment structure is disposed on the first substrate, and the first bonding structure is disposed on the stress adjustment structure. The stress adjusting structure comprises a first oxide layer and a second oxide layer which are sequentially arranged on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer. The second wafer includes a second substrate and a second bonding structure. The second bonding structure is disposed on the second substrate, wherein the second bonding structure is bonded to the first bonding structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly to a bonded semiconductor component and a method for manufacturing the same. Background Art

[0002] A three-dimensional integrated circuit (3D IC) refers to a technology that transforms traditional two-dimensional chips into three-dimensional stacked chips by using wafer level bonding and through silicon via (TSV) technology. Since 3D ICs can effectively utilize space, shorten the circuit transmission distance, and provide extremely low resistance connections, they have gradually become the mainstream technology for components such as power converters, low-noise amplifiers, radio frequency (RF), or millimeter wave (MMW).

[0003] However, there are still problems to be improved in current 3D ICs. For example, in 3D ICs, the upper and lower wafers can be configured as the same or different wafers. For example, both can be logic wafers, or one is a logic wafer and the other is a dynamic random access memory (DRAM) wafer. Due to the different manufacturing processes of different wafers, warping of different degrees is likely to occur due to different stresses accumulated in the manufacturing process, which affects the alignment during bonding, and further affects the properties of the subsequent fabricated 3D ICs. Summary of the Invention

[0004] According to an embodiment of the present invention, a semiconductor component is provided, which includes a first wafer and a second wafer. The first wafer includes a first substrate, a stress adjustment structure, and a first bonding structure. The stress adjustment structure is disposed on the first substrate, and the first bonding structure is disposed on the stress adjustment structure. The stress adjustment structure includes a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer. The second wafer includes a second substrate and a second bonding structure. The second bonding structure is disposed on the second substrate, wherein the second bonding structure is bonded to the first bonding structure.

[0005] Another embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the steps of: providing a first wafer, wherein the first wafer includes a first substrate, a stress adjustment structure disposed on the first substrate, and a first bonding structure disposed on the stress adjustment structure, the stress adjustment structure includes a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer; providing a second wafer, wherein the second wafer includes a second substrate and a second bonding structure disposed on the second substrate; and bonding the second bonding structure to the first bonding structure.

[0006] Compared with the prior art, the semiconductor device of the present invention includes a stress adjustment structure. By controlling the stress provided by the stress adjustment structure, it is beneficial to improve the flatness of the bonding surfaces of the upper and lower wafers and / or make the bonding surfaces of the upper and lower wafers more conformable, which is beneficial to reducing the alignment error and improving the bonding quality, and further improving the properties of the semiconductor device. Description of the Drawings

[0007] Figure 1 、 Figure 2 and Figure 3 are schematic cross-sectional views of the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0008] Figure 4 is Figure 3 an enlarged view of part A in

[0009] Figure 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

[0010] Figure 6 is a graph showing the misalignment experimental results of a comparative example and a semiconductor device according to an embodiment of the present invention;

[0011] Figure 7 is Figure 6 another misalignment experimental result graph of the semiconductor devices of the comparative example and the embodiment in

[0012] Symbol Description

[0013] 1, 1a: Semiconductor device

[0014] 10, 10a: First wafer

[0015] 20, 20a: Second wafer

[0016] 110: First substrate

[0017] 130, 130a: First interconnect structure

[0018] 132, 232: Intermetal dielectric layer

[0019] 134.234: Metal interconnection

[0020] 150,250: Stress adjustment structure

[0021] 152,252: First oxide layer

[0022] 154,254: Second oxide layer

[0023] 156,256: Metal layer

[0024] 170: First bonding structure

[0025] 172: First bonding dielectric layer

[0026] 174: First bonding conductor

[0027] 210: Second substrate

[0028] 230,230a: Second interconnect structure

[0029] 270: Second bonding structure

[0030] 272: Second bonding dielectric layer

[0031] 274: Second bonding conductor

[0032] A: Portion

[0033] D1: Horizontal direction

[0034] D2: Vertical direction

[0035] S0: Bonding surface

[0036] S1,S2: Bonding surface

[0037] T1: Thickness

[0038] t1: First sub - thickness

[0039] t2: Second sub - thickness

[0040] t3: Third sub - thickness

[0041] W1: Width Detailed implementation manner

[0042] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. To make the content of the present invention clearer and easier to understand, the following drawings may be schematic diagrams in a simplified form, and the elements therein may not be drawn to scale. Moreover, the number and size of the elements in the drawings are only for illustration and do not limit the present invention. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, back, bottom, top, etc., are only with reference to the directions in the drawings. Therefore, the directional terms used are for explanation and do not limit the present invention. In addition, in the following embodiments, the same or similar elements will be denoted by the same or similar reference numerals.

[0043] In the following description of "the first feature is formed on or above the second feature", it may mean that "the first feature is in direct contact with the second feature", or it may mean that "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact.

[0044] The present invention uses terms such as first, second, etc. to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish one element, region, layer, and / or section from another element, region, layer, and / or section, and they do not imply or represent any previous ordinal number of the element itself, nor represent the arrangement order of one element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, region, layer, and / or section discussed below may also be referred to by the term of the second element, region, layer, and / or section. These terms in the claims may not be the same as those in the specification, and may be replaced by first, second, third... in accordance with the order of the element declarations in the claims.

[0045] Please refer to Figures 1 to 3 , which is a schematic cross-sectional view of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 In, first, a first wafer 10 is provided. The first wafer 10 includes a first substrate 110, a first interconnect structure 130 disposed on the first substrate 110, a stress adjustment structure 150 disposed on the first interconnect structure 130, and a first bonding structure 170 disposed on the stress adjustment structure 150. The stress adjustment structure 150 includes a first oxide layer 152 and a second oxide layer 154 sequentially disposed on the first substrate 110, and a metal layer 156 disposed in the first oxide layer 152 and the second oxide layer 154. The first refractive index of the first oxide layer 152 is different from the second refractive index of the second oxide layer 154.

[0046] For example, the first wafer 10 can be fabricated in the following manner. First, a first substrate 110 can be provided. The first substrate 110 can be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon on insulator (SOI) substrate. Active components (not shown in the figure) or passive components (not shown in the figure), such as transistors, diodes, capacitors, inductors, resistors, etc., but not limited thereto, can be formed on the first substrate 110 according to actual requirements.

[0047] Next, a metal interconnect fabrication process can be performed to form a first interconnect structure 130 on the first substrate 110. For example, a stop layer (not shown in the figure) and a metal interlayer dielectric layer 132 can be sequentially formed on the surface of the first substrate 110, and then one or more photolithography and etching fabrication processes can be performed to remove part of the metal interlayer dielectric layer 132 and part of the stop layer to form contact holes (not shown in the figure). Then, a conductive material is filled into each contact hole and a planarization fabrication process such as chemical mechanical polishing is used to form metal interconnects 134 electrically connecting the active components (not shown in the figure) or passive components (not shown in the figure) on the first substrate 110. The material of the metal interlayer dielectric layer 132 can include silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, plasma-enhanced oxides, or other suitable dielectric materials. The conductive material for forming the metal interconnects 134 can include a barrier layer (not shown in the figure) and a metal layer (not shown in the figure). The material of the barrier layer can include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. The material of the metal layer can include aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), or a combination thereof, but not limited thereto. Subsequently, the above fabrication process can be repeated and multiple sets of the first interconnect structure 130 composed of the metal interlayer dielectric layer 132 and the metal interconnects 134 can be formed on the first substrate 110 according to the requirements of the fabrication process to complete the back-end-of-the-line (BEOL) fabrication process. Other circuit components such as capacitors, inductors, resistors, embedded memories, etc. can also be included in the first interconnect structure 130, but are not shown in the figure for simplicity.

[0048] Next, the stress adjustment structure 150 may be formed on the first interconnect structure 130. For example, a stop layer (not shown), a first oxide layer 152, and a second oxide layer 154 may be sequentially formed on the surface of the first interconnect structure 130, and one or more photolithography and etching processes may be performed to remove a portion of the second oxide layer 154, a portion of the first oxide layer 152, and a portion of the stop layer to form contact holes (not shown), and then a conductive material is filled into each contact hole and a planarization process such as chemical mechanical polishing is performed to form a metal layer 156 disposed in the first oxide layer 152 and the second oxide layer 154. The material of the first oxide layer 152 may include, for example, a plasma enhanced oxide, and the material of the second oxide layer 154 may include, for example, another plasma enhanced oxide, and the refractive indexes of the two plasma enhanced oxides are different. In addition, the materials of the first oxide layer 152 and the second oxide layer 154 may be different from the material of the intermetallic dielectric layer 132, or one of the materials of the first oxide layer 152 and the second oxide layer 154 may be the same as the material of the intermetallic dielectric layer 132. The conductive material forming the metal layer 156 can be selected from the conductive materials applicable to the metal interconnect 134 described above, which will not be described in detail herein.

[0049] Next, a first bonding structure 170 may be formed on the stress adjustment structure 150. For example, a stop layer (not shown) and a first bonding dielectric layer 172 may be sequentially formed on the surface of the stress adjustment structure 150, and then one or more photolithography and etching processes are performed to remove a portion of the first bonding dielectric layer 172 and a portion of the stop layer to form contact holes (not shown), and then conductive materials are filled into each contact hole and a planarization process such as chemical mechanical polishing is performed to form a first bonding conductor 174 disposed in the first bonding dielectric layer 172. At this point, the production of the first wafer 10 is completed.

[0050] The material of the first bonding dielectric layer 172 includes a dielectric material that can be wafer-level bonded with a bonding dielectric layer of another wafer (e.g., the second bonding dielectric layer 272 of the second wafer 20 hereinafter), such as silicon dioxide, tetraethoxysilane (TEOS), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or plasma-enhanced oxide, but is not limited thereto. In addition, the material of the first bonding dielectric layer 172 may be different from the material of the first oxide layer 152 and different from the material of the second oxide layer 154, or the material of the first bonding dielectric layer 172 may be the same as the material of one of the first oxide layer 152 and the second oxide layer 154. The conductive material forming the first bonding conductor 174 may include a metal material suitable for wafer-level bonding, such as copper (Cu), but is not limited thereto.

[0051] Then, if Figure 2As shown, a second wafer 20 is provided, where the second wafer 20 includes a second substrate 210, a second interconnect structure 230 disposed on the second substrate 210, and a second bonding structure 270 disposed on the second interconnect structure 230.

[0052] For example, the second wafer 20 can be fabricated in the following manner. First, the second substrate 210 can be provided. The second substrate 210 can be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate. Active elements (not shown) or passive elements (not shown), such as transistors, diodes, capacitors, inductors, resistors, etc., but not limited thereto, can be formed on the second substrate 210 according to actual requirements.

[0053] Next, a metal interconnect fabrication process can be performed to form the second interconnect structure 230 on the second substrate 210. For example, a stop layer (not shown) and an inter-metal dielectric layer 232 can be sequentially formed on the surface of the second substrate 210, and then one or more photolithography and etching fabrication processes can be performed to remove a portion of the inter-metal dielectric layer 232 and a portion of the stop layer to form contact holes (not shown). Then, a conductive material is filled into each contact hole and a planarization fabrication process such as chemical mechanical polishing is used to form metal interconnects 234 electrically connecting the active elements (not shown) or passive elements (not shown) on the second substrate 210. The conductive material for the metal interconnects 234 can be selected from the conductive materials applicable to the metal interconnects 134 described above, and the material for the inter-metal dielectric layer 232 can be selected from the materials applicable to the inter-metal dielectric layer 132 described above, which will not be elaborated here. Subsequently, the above fabrication process can be repeated and multiple sets of the second interconnect structure 230 composed of the inter-metal dielectric layer 232 and the metal interconnects 234 can be formed on the second substrate 210 according to the requirements of the fabrication process to complete the back-end fabrication process. Other circuit elements such as capacitors, inductors, resistors, embedded memories, etc. can also be included in the second interconnect structure 230, which are not shown in the figure for simplicity.

[0054] Next, the second bonding structure 270 can be formed on the second interconnect structure 230. For example, a stop layer (not shown) and a second bonding dielectric layer 272 can be sequentially formed on the surface of the second interconnect structure 230, and then one or more photolithography and etching fabrication processes can be performed to remove a portion of the second bonding dielectric layer 272 and a portion of the stop layer to form contact holes (not shown). Then, a conductive material is filled into each contact hole and a planarization fabrication process such as chemical mechanical polishing is used to form second bonding conductors 274 disposed in the second bonding dielectric layer 272. The material for the second bonding dielectric layer 272 and the conductive material for the second bonding conductors 274 can refer to the relevant descriptions of the first bonding dielectric layer 172 and the first bonding conductors 174 respectively, which will not be elaborated here. Thus, the fabrication of the second wafer 20 can be completed.

[0055] Next, the second bonding structure 270 is bonded to the first bonding structure 170. As Figure 3 shown, the first wafer 10 is flipped so that its back side faces upward, and then, a bonding process, such as hybrid bonding technology, is performed to bring the first bonding conductors 174 embedded in the first bonding dielectric layer 172 and the second bonding conductors 274 embedded in the second bonding dielectric layer 272 into face-to-face contact with each other. Then, a heat treatment step is carried out to promote the formation of a bond between the first bonding dielectric layer 172 and the second bonding dielectric layer 272, and the atomic diffusion of the metal in the solid state is used to bond the second bonding conductor 274 and the first bonding conductor 174. Thus, the fabrication of the semiconductor device 1 can be completed. In some embodiments, before the bonding process, the first bonding structure 170 and the second bonding structure 270 can be subjected to surface treatment to remove impurities attached to the surface and / or modify the surface to improve the bondability. The temperature of the heat treatment step can be between 100°C and 400°C.

[0056] Although not shown in the figures, the method of fabricating a semiconductor device may further include other fabrication processes for manufacturing 3D ICs. For example, a dielectric layer can be formed on the back side of the first wafer 10, and a plug fabrication process can be performed to form a plurality of plugs (also referred to as through silicon vias (TSVs)) in the dielectric layer and the first substrate 110 to electrically connect the metal interconnects 134, and a plurality of metal pads can be formed on the dielectric layer and electrically connected to the plurality of plugs. The plurality of metal pads can be used as bonding pads for the entire 3D IC to output / input externally.

[0057] The above-mentioned various film layers, such as the intermetal dielectric layer 132, the metal interconnects 134, the first oxide layer 152, the second oxide layer 154, the metal layer 156, the first bonding dielectric layer 172, the first bonding conductors 174, the intermetal dielectric layer 232, the metal interconnects 234, the second bonding dielectric layer 272, the second bonding conductors 274, etc., can be formed by any suitable method, such as but not limited to molecular-beam epitaxy (MBE), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), etc.

[0058] Please also refer to Figure 3and Figure 4 , Figure 3 is a cross-sectional schematic view showing a semiconductor device 1 according to an embodiment of the present invention, Figure 4 which Figure 3 is an enlarged view of a portion A in . The semiconductor device 1 includes a first wafer 10 and a second wafer 20. The first wafer 10 includes a first substrate 110, a stress adjustment structure 150, and a first bonding structure 170, and optionally includes a first interconnect structure 130. The first interconnect structure 130 is disposed on the first substrate 110, the stress adjustment structure 150 is disposed on the first interconnect structure 130 (i.e., the stress adjustment structure 150 is disposed on the first substrate 110 through the first interconnect structure 130), and the first bonding structure 170 is disposed on the stress adjustment structure 150. The stress adjustment structure 150 includes a first oxide layer 152 and a second oxide layer 154 sequentially disposed on the first substrate 110, and a first refractive index of the first oxide layer 152 is different from a second refractive index of the second oxide layer 154.

[0059] In this embodiment, the stress adjustment structure 150 includes two oxide layers (i.e., a bilayer structure). However, this is only an example, and the present invention is not limited thereto. In other embodiments, the number of oxide layers in the stress adjustment structure 150 may be greater than or equal to three, and the refractive indices of the multiple oxide layers may gradually change along the vertical direction D2, so that the stress adjustment structure 150 can provide a gradually changing stress.

[0060] The second wafer 20 includes a second substrate 210 and a second bonding structure 270, and optionally includes a second interconnect structure 230. The second bonding structure 270 is disposed on the second interconnect structure 230 (i.e., the second bonding structure 270 is disposed on the second substrate 210 through the second interconnect structure 230), wherein the second bonding structure 270 is bonded to the first bonding structure 170. Further, the first wafer 10 has a bonding surface S1, the second wafer 20 has a bonding surface S2, and the bonding surface S1 and the bonding surface S2 are bonded to form a bonding surface S0.

[0061] The first interconnect structure 130 may include multiple inter-metal dielectric layers 132 and metal interconnects 134 disposed in the inter-metal dielectric layers 132. Herein, the number of the inter-metal dielectric layers 132 is only an illustration and can be flexibly adjusted according to actual requirements. The stress adjustment structure 150 may further include a metal layer 156 disposed in the first oxide layer 152 and the second oxide layer 154. The first bonding structure 170 may include a first bonding dielectric layer 172 and a first bonding conductor 174 penetrating through the first bonding dielectric layer 172, and the first bonding conductor 174 is in direct contact with the metal layer 156. In other words, the stress adjustment structure 150 and the first bonding structure 170 of the present invention are directly adjacent to each other. It can also be regarded that the present invention changes the inter-metal dielectric layer closest to the bonding structure in a general interconnect structure from a single-layer structure (single material) to a multi-layer structure (double-layer or more than double-layer structure; two or more materials), and can provide the effect of stress adjustment.

[0062] The second interconnect structure 230 may include multiple inter-metal dielectric layers 232 and metal interconnects 234 disposed in the inter-metal dielectric layers 232. Herein, the number of the inter-metal dielectric layers 232 is only an illustration and can be flexibly adjusted according to actual requirements. The second bonding structure 270 may include a second bonding dielectric layer 272 and a second bonding conductor 274 penetrating through the second bonding dielectric layer 272, and the second bonding conductor 274 is bonded (in direct contact) with the first bonding conductor 174.

[0063] In the present invention, the first oxide layer 152 and the second oxide layer 154 have different compressive stresses or tensile stresses due to the first refractive index being different from the second refractive index. According to an embodiment of the present invention, when the refractive index is larger, the compressive stress is larger. For example, when the refractive index of the first oxide layer 152 or the second oxide layer 154 is 1.455, the magnitude of the compressive stress may be 61 Mpa; when the refractive index of the first oxide layer 152 or the second oxide layer 154 is 1.461, the magnitude of the compressive stress may be 126 Mpa; when the refractive index of the first oxide layer 152 or the second oxide layer 154 is 1.475, the magnitude of the compressive stress may be 185 Mpa. However, the foregoing refractive indices and the magnitudes of the compressive stresses are only illustrations, and the present invention is not limited thereto. The refractive indices of the materials forming the first oxide layer 152 and the second oxide layer 154 can be adjusted according to actual requirements, so that the first oxide layer 152 and the second oxide layer 154 can provide different compressive stresses or tensile stresses.

[0064] According to the present invention, through different numerical combinations of the first refractive index and the second refractive index, and in combination with different thickness combinations of the first oxide layer 152 and the second oxide layer 154, the stress provided by the overall stress adjustment structure 150 can be controlled, which is beneficial to improving the flatness of the bonding surfaces S1 and S2 of the first wafer 10 and the second wafer 20 or making the bonding surfaces S1 and S2 of the first wafer 10 and the second wafer 20 fit more closely, thereby being beneficial to reducing the alignment error and improving the properties of the semiconductor element 1. For example, when the stress adjustment structure 150 is not provided on the first wafer 10 (that is, Figure 3 the first oxide layer 152 and the second oxide layer 154 in

[0065] Figure 4 are replaced by the intermetal dielectric layer 132), the bonding surface S1 may have a warpage that is slightly concave upward or slightly convex downward due to the process stress. By providing the stress adjustment structure 150, the bonding surface S1 can be made flatter. For another example, when the bonding surface S2 of the second wafer 20 has a warpage that is slightly concave downward due to the process stress, the stress provided by the stress adjustment structure 150 can be controlled to cause the bonding surface S1 of the first wafer 10 to have a warpage that is slightly convex downward, so that the concave and convex of the bonding surfaces S1 and S2 can be matched to fit more closely.

[0066] In

[0067] , the stress adjustment structure 150 has a thickness T1 in the vertical direction D2, and the thickness T1 can be 2000 angstroms to 4000 angstroms. The first oxide layer 152 has a first sub-thickness t1 in the vertical direction D2, and the second oxide layer 154 has a second sub-thickness t2 in the vertical direction D2, and the ratio (t2 / t1) of the second sub-thickness t2 to the first sub-thickness t1 can be 0.25 to 4. For example, the first sub-thickness t1 can be 20% to 80% of the thickness T1 (that is, 20%×T1 ≤ t1 ≤ 80%×T1), and the second sub-thickness t2 can be 20% to 80% of the thickness T1 (that is, 20%×T1 ≤ t2 ≤ 80%×T1). The first refractive index can be 1.455 to 1.475. The absolute value of the difference between the second refractive index and the first refractive index can be 0.006 to 0.02 (that is, 0.006 ≤ |second refractive index - first refractive index| ≤ 0.02). When the ratio of the second sub-thickness t2 to the first sub-thickness t1 and the first refractive index and the second refractive index satisfy the above relationships, the effect of reducing the alignment error can be more significant.

[0066] According to an embodiment of the present invention, the second refractive index can be greater than the first refractive index. Thus, in the first oxide layer 152 and the second oxide layer 154, the second oxide layer 154 closer to the first bonding structure 170 can provide a greater compressive stress, which is beneficial to strengthening the tightness of the bonding surfaces S1 and S2.

[0067] According to an embodiment of the present invention, the thickness T1 may be equal to the sum of the first sub-thickness t1 and the second sub-thickness t2 (i.e., T1 = t1 + t2). When the stress adjustment structure 150 further includes a stop layer (not shown) disposed between the first oxide layer 152 and the first interconnect structure 130, the thickness T1 may be equal to the sum of the first sub-thickness t1, the second sub-thickness t2, and the thickness of the stop layer in the vertical direction D2.

[0068] The metal layer 156 has a third sub-thickness t3 in the vertical direction D2, and the third sub-thickness t3 may be equal to the thickness T1 (i.e., t3 = T1). The metal layer 156 has a width W1 in the horizontal direction D1, and the width W1 may be fixed along the vertical direction D2. The aforementioned vertical direction D2 may be parallel to the normal direction of the first substrate 110 (not shown), and the horizontal direction D1 may be perpendicular to the vertical direction D2.

[0069] According to an embodiment of the present invention, the third sub-thickness t3 may be equal to the sum of the first sub-thickness t1 and the second sub-thickness t2 (i.e., t3 = t1 + t2). When the stress adjustment structure 150 further includes a stop layer (not shown) disposed between the first oxide layer 152 and the first interconnect structure 130, the third sub-thickness t3 may be equal to the sum of the first sub-thickness t1, the second sub-thickness t2, and the thickness of the stop layer in the vertical direction D2.

[0070] Figure 5FIG. is a cross-sectional schematic view of a semiconductor device 1a according to another embodiment of the present invention. The semiconductor device 1a includes a first wafer 10a and a second wafer 20a. The first wafer 10a includes a first substrate 110 and a first bonding structure 170, and optionally includes a first interconnect structure 130a. The second wafer 20a includes a second substrate 210, a stress adjustment structure 250, and a second bonding structure 270, and optionally includes a second interconnect structure 230a. The stress adjustment structure 250 includes a first oxide layer 252 and a second oxide layer 254 sequentially disposed on the second substrate 210, and a metal layer 256 disposed in the first oxide layer 252 and the second oxide layer 254, and a first refractive index of the first oxide layer 252 is different from a second refractive index of the second oxide layer 254. The main difference between the semiconductor device 1a and the semiconductor device 1 is that the stress adjustment structure 150 of the semiconductor device 1 is disposed on the upper first wafer 10, while the stress adjustment structure 250 of the semiconductor device 1a is disposed on the lower second wafer 20a. In addition, the number of inter-metal dielectric layers 132 in the first interconnect structure 130a is different from the number of inter-metal dielectric layers 132 in the first interconnect structure 130, and the number of inter-metal dielectric layers 232 in the second interconnect structure 230a is different from the number of inter-metal dielectric layers 232 in the second interconnect structure 230. By disposing the stress adjustment structure 250 on the second wafer 20a, it is beneficial to improve the flatness of the bonding surface S2, or to cause the bonding surface S2 to warp in the opposite direction to the bonding surface S1, so that the bonding surfaces S1 and S2 are more closely attached. Other details of the semiconductor device 1a can be referred to the related description of the semiconductor device 1. In addition, the semiconductor devices 1 and 1a are described by taking only one of the upper wafer (i.e., the first wafers 10 and 10a) and the lower wafer (i.e., the second wafers 20 and 20a) having a stress adjustment structure (i.e., the stress adjustment structures 150 and 250) as an example. However, the present invention is not limited thereto. In other embodiments, stress adjustment structures can be disposed on both the upper wafer and the lower wafer, thereby facilitating the improvement of the flatness of the bonding surfaces of the upper wafer and the lower wafer. In addition, since the semiconductor devices 1 and 1a are applied to wafer-level bonding, the first wafers 10 and 10a and the second wafers 20 and 20a can both be product wafers, each having a plurality of corresponding dies, or one of the first wafers 10 and 10a and the second wafers 20 and 20a is a product wafer and the other is an interposer.

[0071] Please refer to Figure 6 and Figure 7 , Figure 6 FIG. is a graph showing the results of a misalignment experiment of a semiconductor device according to a comparative example and an embodiment of the present invention. Figure 7 FIG. is Figure 6 another graph showing the results of a misalignment experiment of the semiconductor devices of the comparative example and the embodiment in FIG.Figure 6 and Figure 7 In, the structure of the semiconductor element according to an embodiment of the present invention can be referred to Figure 3 the semiconductor element 1 in. The difference between the comparative example and the embodiment is that in the comparative example, the inter-metal dielectric layer of the first interconnect structure is used to replace the first oxide layer and the second oxide layer. Figure 6 In, the vertical axis represents the cumulative probability, and the horizontal axis represents the normalized misalignment of the first wafer and the second wafer in the X direction (for example, the horizontal direction D1). Figure 7 In, the vertical axis represents the cumulative probability, and the horizontal axis represents the normalized misalignment of the first wafer and the second wafer in the Y direction (for example, another horizontal direction perpendicular to the horizontal direction D1). As can be seen from Figure 6 it, the normalized misalignment of the comparative example in the X direction is about 1, while the normalized misalignment of the embodiment in the X direction is about 0.625. As can be seen from Figure 7 it, the normalized misalignment of the comparative example in the Y direction is about 1.5, while the normalized misalignment of the embodiment in the Y direction is about 0.05. Compared with the comparative example, the embodiment according to the present invention can significantly reduce the misalignment, which is beneficial to reducing the alignment error.

[0072] Compared with the prior art, the semiconductor element of the present invention includes a stress adjustment structure. By controlling the stress provided by the stress adjustment structure, it is beneficial to improve the flatness of the bonding surfaces of the upper and lower wafers and / or make the bonding surfaces of the upper and lower wafers more conformable, which is beneficial to reducing the alignment error and improving the bonding quality, and further can improve the properties of the semiconductor element.

[0073] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: The first wafer comprises: first base; A stress adjustment structure is disposed on the first substrate, wherein the stress adjustment structure comprises a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer; and A first bonding structure is disposed on the stress adjustment structure; as well as The second wafer comprises: Second base; as well as The second bonding structure is disposed on the second substrate, wherein the second bonding structure is bonded to the first bonding structure. 2 . The semiconductor device as claimed in claim 1 , wherein the stress adjustment structure has a thickness in a vertical direction, and the thickness is 2000 angstroms to 4000 angstroms. 3 . The semiconductor device as claimed in claim 1 , wherein the first oxide layer has a first sub-thickness in a vertical direction, the second oxide layer has a second sub-thickness in the vertical direction, and a ratio of the second sub-thickness to the first sub-thickness is 0.25 to 4. The semiconductor device as claimed in claim 1 , wherein the first refractive index is 1.455 to 1.

475. 5 . The semiconductor device as claimed in claim 1 , wherein an absolute value of a difference between the second refractive index and the first refractive index is 0.006 to 0.

02. The semiconductor device as claimed in claim 1 , wherein the second refractive index is greater than the first refractive index.

7. The semiconductor device as described in claim 1, wherein the stress adjustment structure has a thickness in the vertical direction, and the stress adjustment structure further includes a metal layer arranged in the first oxide layer and the second oxide layer, and the metal layer has a third sub-thickness in the vertical direction, and the third sub-thickness is equal to the thickness. 8 . The semiconductor device as claimed in claim 7 , wherein the metal layer has a width in a horizontal direction, and the width is constant along the vertical direction. 9 . The semiconductor device as claimed in claim 7 , wherein the first bonding structure comprises a first bonding dielectric layer and a first bonding conductor penetrating through the first bonding dielectric layer, and the first bonding conductor directly contacts the metal layer. 10 . The semiconductor device as claimed in claim 9 , wherein a material of the first bonding dielectric layer is different from a material of the first oxide layer and different from a material of the second oxide layer.

11. A method for manufacturing a semiconductor device, comprising: A first wafer is provided, wherein the first wafer comprises a first substrate, a stress adjustment structure disposed on the first substrate, and a first bonding structure disposed on the stress adjustment structure, the stress adjustment structure comprises a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer; Providing a second wafer, wherein the second wafer comprises a second substrate and a second bonding structure disposed on the second substrate; and The second bonding structure is bonded to the first bonding structure. 12 . The method of claim 11 , wherein the stress adjustment structure has a thickness in a vertical direction, the thickness being 2000 angstroms to 4000 angstroms. 13 . The method of claim 11 , wherein the first oxide layer has a first sub-thickness in a vertical direction, the second oxide layer has a second sub-thickness in the vertical direction, and a ratio of the second sub-thickness to the first sub-thickness is 0.25 to 4. The method of claim 11 , wherein the first refractive index is 1.455 to 1.

475. 15 . The method of claim 11 , wherein an absolute value of a difference between the second refractive index and the first refractive index is 0.006 to 0.

02. The method of claim 11 , wherein the second refractive index is greater than the first refractive index.

17. The method of claim 11, wherein the stress adjustment structure has a thickness in a vertical direction, the stress adjustment structure further comprises a metal layer disposed in the first oxide layer and the second oxide layer, the metal layer having a third sub-thickness in the vertical direction, the third sub-thickness being equal to the thickness. 18 . The method of claim 17 , wherein the metal layer has a width in a horizontal direction, and the width is constant along the vertical direction. 19 . The method of claim 17 , wherein the first bonding structure comprises a first bonding dielectric layer and a first bonding conductor is disposed through the first bonding dielectric layer, and the first bonding conductor directly contacts the metal layer. 20 . The method of claim 19 , wherein a material of the first bonding dielectric layer is different from a material of the first oxide layer and different from a material of the second oxide layer.

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