Preparation method of high-power C Band SOA

Abstract

The invention relates to a preparation method of a high-power C Band SOA, and belongs to the field of chip preparation. According to the method, the SOA chip with high saturation output power is obtained by using active region materials of a compressive strain quantum well and a tensile strain barrier and adopting a gradient waveguide structure. According to the invention, active region materials of a compressive strain quantum well and a tensile strain barrier are used, and a gradual change type small-angle taper RWG waveguide structure is adopted, so that an SOA chip (17dBm at 500mA and 19dBm at 750mA) with high saturation output power is obtained, and 70% of light spot ovality and coupling loss in a 2dB range are ensured.

Description

Technical Field

[0001] The present invention belongs to the field of chip preparation, and specifically relates to a method for preparing a high-power C Band SOA. Background Art

[0002] When an optical signal propagates in an optical fiber, a semiconductor optical amplifier (SOA) can increase the output power and maintain a sufficiently high signal level. However, the SOA has the phenomenon of gain saturation. Only when operating in an (approximate) linear state, the signal can be amplified clearly and without distortion. But in the saturation state, due to the mode effect, the signal waveform will be distorted. Therefore, it is crucial to design an SOA with low PDG and high saturated output power.

[0003] The gain saturation of the SOA is caused by too high an injection carrier concentration or too high an input optical intensity. After reaching the gain saturation point, the gain of the SOA decreases as the injection carrier concentration increases; or given an unsaturated DC bias, when the input power is continuously increased to a certain value, the gain of the SOA decreases. When actually used for power amplification, we are more concerned about the saturated output power, that is, the output power corresponding to a 3 dB gain drop. Its theoretical formula is:

[0004]

[0005] In the above formula, refers to the photon energy, A refers to the cross-sectional area of the active layer, refers to the output coupling coefficient, refers to the carrier lifetime, refers to the mode field confinement factor, and refers to the differential gain. To increase the saturated output power, it is possible to increase the cross-sectional area of the active layer (reduce the optical power per unit area), reduce the mode field confinement factor and the differential gain (when it is small to a certain extent, the mode field expands laterally on both sides, which is equivalent to increasing the active area), and at the same time, try to reduce the saturation of the spontaneous emission power in the gain medium of the SOA on the output power of the SOA.

[0006] There are mainly two commonly used methods to increase the saturated output power: one is to directly increase the current, which is the most intuitive method. However, after the output power of the SOA is saturated, it will no longer increase but decrease instead. And too high a current will generate too much heat, making the SOA unstable, increasing the load of the cooling system and affecting the lifespan of the SOA. The other is to improve the waveguide structure, appropriately extend the length of the waveguide and increase the width of the waveguide to increase the area of the gain region, thereby improving the gain. However, if the waveguide is extended too long, the latter half of the waveguide will be saturated, resulting in losses; if the waveguide is too wide, multimode laser is likely to be generated, making the SOA unstable, and an overly wide waveguide will also bring additional losses. Therefore, the taper structure with a gradually changing waveguide width is widely used to improve the saturated output power and stability of the SOA. However, if the output end is too wide, the spot ellipticity will become worse, generating excessive coupling losses, which limits the practical use of the tapered SOA. Therefore, the coupling efficiency also needs to be considered when designing the waveguide. Summary of the Invention

[0007] The purpose of the present invention is to provide a method for fabricating a high-power C Band SOA. By using an active region material with compressive strained quantum wells and tensile strained barriers, and adopting a gradually changing small-angle taper RWG waveguide structure, an SOA chip with high saturated output power (17 dBm @ 500 mA, 19 dBm @ 750 mA) can be obtained, and a spot ellipticity of 70% and a coupling loss within 2 dB are ensured.

[0008] To achieve the above purpose, the technical solution of the present invention is: a method for fabricating a high-power C Band SOA, by using an active region material with tensile strained quantum wells and lattice-matched barriers, and adopting a gradually changing waveguide structure to obtain an SOA chip with high saturated output power.

[0009] Furthermore, the method includes waveguide design and epitaxial design; among them,

[0010] For waveguide design, a gradually changing waveguide structure is adopted;

[0011] For epitaxial design, from bottom to top are the substrate, the first N-InP buffer layer, the InGaAsP high-refractive index layer, the second N-InP buffer layer, the first InGaAsP SCH layer, the MQW layer, the second InGaAsP SCH layer, the electron blocking layer, the InP upper cladding layer, the etch stop layer, the highly doped P-InP layer, the ohmic contact layer InGaAs, and the InP protective layer.

[0012] Furthermore, the gradually changing waveguide structure is a gradually changing small-angle taper RWG waveguide structure.

[0013] Furthermore, in the tapered waveguide structure, the ridge width at the light incident end is 0.6 - 2.2 μm, and the ridge width at the light output end is 3 - 5 μm.

[0014] Furthermore, the thickness of the first N-InP buffer layer is 0.8 - 1.2 μm, the thickness of the InGaAsP high refractive index layer is 100 - 200 nm, the thickness of the second N-InP buffer layer is 1.0 - 2.0 μm, the thickness of the first InGaAsP SCH layer is 70 - 110 nm, the thickness of the MQW layer is 40 - 80 nm, the thickness of the second InGaAsP SCH layer is 60 - 100 nm, the thickness of the electron blocking layer is 5 - 10 nm, the thickness of the InP upper cladding layer is 80 - 120 nm, the thickness of the etch stop layer is 10 - 40 nm, the thickness of the highly doped P-InP layer is 2 - 3 μm, the thickness of the ohmic contact layer InGaAs is 200 - 300 nm, and the thickness of the InP protective layer is 10 - 30 nm.

[0015] Furthermore, the preparation process of the SOA chip is as follows:

[0016] First, use HCl to remove the surface InP protective layer of the epitaxial wafer, then deposit SiO2 for the ridge waveguide mask, then perform ridge waveguide lithography, then after etching the exposed SiO2 to remove the photoresist, perform ridge etching, then remove the SiO2 mask, then grow a 300 - 400 nm SiO2 passivation layer, then perform lithography and etching for the ridge waveguide window opening and scribing lanes to obtain the scribing lanes and the exposed ohmic contact layer, then perform lithography for the ID and pads and deposit thin gold on the P side, and after stripping the gold layer, obtain the gold electrodes and the metal ID. Then perform electroplating 1 to increase the gold layer thickness in the area except for the ID, then perform electroplating 2 to raise the height of the pad area to avoid damaging the ridge. Then perform thinning, and after thinning, deposit metal on the N side to obtain the preliminary un-cleaved chip array. Then perform bar cleavage and coat antireflection films on both sides. After the preliminary LIV test, perform cleavage to obtain the required SOA chip.

[0017] Furthermore, the ridge etching is divided into two steps: cladding etching and ridge waveguide etching.

[0018] Furthermore, the prepared SOA chip needs to be tested for the saturated output power.

[0019] Furthermore, for the saturated output power test, that is, starting from an injected optical power of -30 dBm, obtain a set of data of output and gain for each increase of 1 dB, and they correspond one by one. The output power corresponding to a 3 dB drop in gain is the saturated output power.

[0020] Furthermore, the prepared SOA chip ensures a spot ellipticity of 70% and a coupling loss within 2 dB.

[0021] Compared with the prior art, the present invention has the following beneficial effects: The high-power SOA chip of the present invention not only improves the saturated output power but also reduces the coupling loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is the waveguide design structure of the present invention.

[0023] Figure 2 It is the epitaxial design structure of the present invention.

[0024] Figure 3 It is a schematic diagram of the preparation process of the SOA chip of the present invention.

[0025] Figure 4 It is a schematic diagram of the saturated output power test.

[0026] Figure 5 It is the spot pattern of the near-light end and the far-light end of the tapered waveguide structure.

[0027] Figure 6 It is the data of the amplification test and the saturated output power test. DETAILED DESCRIPTION OF THE INVENTION

[0028] The technical solution of the present invention will be specifically described below with reference to the drawings.

[0029] The present invention provides a method for preparing a high-power C Band SOA. By using an active region material with compressive strained quantum wells and tensile strained barriers and adopting a tapered waveguide structure, an SOA chip with a high saturated output power (17 dBm @ 500 mA, 19 dBm @ 750 mA) is obtained, and a spot ellipticity of 70% and a coupling loss within 2 dB are ensured.

[0030] The following is the specific implementation process of the present invention.

[0031] As Figures 1-3 shown, a method for preparing a high-power C Band SOA of the present invention focuses on the tapered waveguide design, which specifically includes the following contents:

[0032] Waveguide design:

[0033] Referring to Figure 1 , the tapered waveguide structure used in this application has a ridge width of about 0.6 - 2.2 um at the light input end and about 3 - 5 um at the light output end, which can not only ensure single-mode output but also increase the saturated output power.

[0034] Epitaxial design:

[0035] Referring to Figure 2, from bottom to top are substrate, N-InP buffer layer (0.8 - 1.2 μm), InGaAsP high refractive index layer (100 - 200 nm), N-InP buffer layer (1.0 - 2.0 μm), InGaAsP SCH layer (70 - 110 nm), MQW layer (40 - 80 nm), InGaAsP SCH layer (60 - 100 nm), electron blocking layer (5 - 10 nm), InP upper cladding layer (80 - 120 nm), etch stop layer (10 - 40 nm), highly doped P-InP layer (2 - 3 μm), ohmic contact layer InGaAs (200 - 300 nm), and finally InP protection layer (10 - 30 nm, this layer is removed first in the preparation of SOA chip).

[0036] SOA chip preparation process:

[0037] See Figure 3 , first use HCl to remove the surface InP of the epitaxial wafer, then deposit ridge waveguide mask SiO2, then perform ridge waveguide lithography, then etch the exposed SiO2, after removing the photoresist, perform ridge etching, ridge etching is divided into two steps, cladding etching and ridge waveguide etching, then remove the SiO2 mask, then grow a 300 - 400 nm SiO2 passivation layer, then perform lithography and etching for ridge waveguide window opening and scribing channels, and then the scribing channels and the exposed ohmic contact layer can be obtained. Then perform lithography for ID and pads, then deposit thin gold on the P side, and after stripping the gold layer, a thinner gold electrode and metal ID can be obtained. Then perform electroplating 1, increase the gold layer thickness for the area except ID, then perform electroplating 2, raise the pads area to avoid damaging the ridge, then perform thinning, after thinning perform N side metal deposition, and then a preliminary un-cleaved chip array can be obtained. Then perform bar strip cleavage, coat antireflection films on both sides, and after preliminary LIV testing perform cleavage, and then the required SOA chip can be obtained.

[0038] Saturated output power test:

[0039] See Figure 4 , start with the injected optical power of -30 dBm, and get a set of output and gain data for every 1 dB increase. They correspond one by one. The output power corresponding to the 3 dB decrease in gain is the saturated output power.

[0040] Figure 5 It is the spot pattern of the near optical end and far optical end of the tapered waveguide structure. Figure 6 They are the test data of amplification test and saturated output power test.

[0041] The above are the preferred embodiments of the present invention. All changes made according to the technical solutions of the present invention and whose functional effects do not exceed the scope of the technical solutions of the present invention belong to the protection scope of the present invention.

Claims

1. A method for preparing a high-power C Band SOA, characterized in that: By using active region materials of compressive strain quantum wells and tensile strain barriers and adopting a gradient waveguide structure, an SOA chip with high saturation output power is obtained.

2. The method for preparing a high-power C Band SOA according to claim 1, characterized in that: Including waveguide design and epitaxial design; among them, Waveguide design adopts a gradual waveguide structure; The epitaxial design, from bottom to top, is substrate, first N-InP buffer layer, InGaAsP high fold layer, second N-InP buffer layer, first InGaAsP SCH layer, MQW layer, second InGaAsP SCH layer, electron blocking layer, InP upper cladding layer, etching stop layer, highly doped P-InP layer, ohmic contact layer InGaAs, and InP protective layer.

3. The method for preparing a high-power C Band SOA according to claim 1, characterized in that: The tapered waveguide structure is a tapered small-angle taper RWG waveguide structure.

4. The method for preparing a high-power C Band SOA according to claim 1, characterized in that: In the gradient waveguide structure, the ridge width at the light input end is 0.6 to 2.2 um, and the ridge width at the light output end is 3 to 5 um.

5. The method for preparing a high-power C Band SOA according to claim 2, characterized in that: The thickness of the first N-InP buffer layer is 0.8-1.2 μm, the thickness of the InGaAsP high fold layer is 100-200 nm, the thickness of the second N-InP buffer layer is 1.0-2.0 μm, the thickness of the first InGaAsP SCH layer is 70-110 nm, the thickness of the MQW layer is 40-80 nm, the thickness of the second InGaAsPSCH layer is 60-100 nm, the thickness of the electron blocking layer is 5-10 nm, the thickness of the InP upper cladding layer is 80-120 nm, the thickness of the etching stop layer is 10-40 nm, the thickness of the highly doped P-InP layer is 2-3 μm, the thickness of the ohmic contact layer InGaAs is 200-300 nm, and the thickness of the InP protective layer is 10-30 nm.

6. The method for preparing a high-power C Band SOA according to claim 4, characterized in that: The SOA chip preparation process is as follows: First, use HCl to remove the surface InP protective layer of the epitaxial wafer, then deposit SiO2 on the ridge waveguide mask, then perform ridge waveguide lithography, then etch the exposed SiO2 to remove the photoresist, perform ridge corrosion, remove the SiO2 mask, and then grow a 300-400nm SiO2 passivation layer, then perform ridge waveguide window opening, scribe line lithography and etching to obtain scribe lines and exposed ohmic contact layers, then perform ID and pad lithography and P-side thin gold deposition, and after stripping the gold layer, obtain the gold electrode and metal ID, and then perform electroplating 1 to increase the gold layer thickness in areas other than the ID, and then perform electroplating 2 to raise the pad area to avoid crushing the ridge, and then perform thinning, and after thinning, perform N-side metal deposition to obtain a preliminary uncleaved chip array, and then perform bar cleavage and anti-reflection film coating on both sides, and perform debonding after preliminary LIV testing to obtain the required SOA chip.

7. The method for preparing a high-power C Band SOA according to claim 6, characterized in that: Ridge etching is divided into two steps, cladding etching and ridge waveguide etching.

8. The method for preparing a high-power C Band SOA according to claim 6, characterized in that: The prepared SOA chip needs to be tested for saturated output power.

9. The method for preparing a high-power C Band SOA according to claim 8, characterized in that: The saturated output power test starts with the injected optical power of -30dBm, and obtains an output and gain data for each 1dB increase. The two correspond one to one. The output power corresponding to a 3dB drop in gain is the saturated output power.

10. A method for preparing a high-power C Band SOA according to any one of claims 1 to 9, characterized in that: The prepared SOA chip ensures a light spot ellipticity of 70% and a coupling loss within the range of 2dB.

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