GmC dynamic amplifier with high linearity, high temperature and power supply voltage stability

Abstract

The invention discloses a GmC dynamic amplifier with high linearity, high temperature and power supply voltage stability, and relates to an integrated circuit technology. The amplifier comprises an amplifier main body part and a bias part for providing voltage bias for the main body part. Wherein the main body part of the amplifier adopts two differential pairs with asymmetric transistor width-to-length ratios, so that the linearity of transconductance of the amplifier is improved, and the linearity of the amplifier is improved when the input amplitude is relatively large; besides, a constant transconductance bias circuit is adopted in the bias part, transconductance of a transistor of the constant transconductance bias circuit is slightly affected by temperature and power voltage condition changes, and due to the effect of a current mirror, transconductance of a differential pair of the main body part and gain of the main body part also have high temperature and power voltage stability. The linearity of the dynamic GmC amplifier is higher than that of a traditional GmC amplifier, the gain can be kept relatively unchanged within a certain temperature and power supply voltage range, the advantages of low noise and low power consumption of the dynamic GmC amplifier are played, the defects of the dynamic GmC amplifier are overcome, the dynamic GmC amplifier can be used as a residual amplifier of a high-speed high-precision low-power-consumption assembly line SAR ADC, and the dynamic GmC amplifier can be used as a high-speed high-precision low-power-consumption assembly line SAR ADC. The method is widely applied to the high-precision and advanced fields such as medical imaging, biological detection, Internet of Things, instruments and meters, industrial process control and the like.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and particularly to a dynamic amplifier. Background Art

[0002] In the past few decades, the semiconductor industry has developed rapidly, the technology of digital circuits has become increasingly powerful, and the integration degree of chips has been continuously improved. Due to its high speed, high precision, high reliability, and the increasingly perfect EDA technology, digital circuits are widely used in fields such as medical treatment, aerospace, measurement, communication, and audio and video processing, and have occupied a dominant position. However, in people's daily lives, most of the signals they come into contact with, such as sound, are analog signals. Therefore, digital signal devices must be able to communicate effectively with the analog environment. Such devices that can achieve interconnection between the digital world and the analog world are called data converters, which are mainly divided into analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Among them, ADCs are widely used in many electronic devices, such as the ADC that converts electrocardiogram signals into digital signals in an electrocardiograph. The performance of the ADC directly affects the signal quality after the analog signal enters the digital system, and thus may affect the performance of the entire digital system.

[0003] At present, ADCs can be divided into high-precision ADCs and high-speed ADCs according to the high or low input frequency. High-speed ADCs are mainly used in communication, satellite images and other scenarios, and time-interleaved or pipelined architectures can be adopted. High-precision ADCs are mainly applied in sensors, medical detection, audio, industrial detection and other fields. Due to their high-precision characteristics, sigma-delta or successive approximation register (SAR) ADCs are mainly used. Among them, sigma-delta ADCs rely on oversampling and quantization noise shaping technologies, and can achieve a maximum accuracy of 24 bits or 32 bits. However, due to their oversampling characteristics, the higher the accuracy, the higher the order of shaping and the higher the sampling rate required. Therefore, it is difficult to achieve a high signal bandwidth. Secondly, sigma-delta ADCs will exhibit the phenomenon of idle tones under certain input conditions, which will cause harmonics in the output spectrum, and the noise shaping function depends on the memory ability of the circuit. In some scenarios, such as multiplexing multiple sensors with one ADC, it is not suitable for use. On the contrary, SAR ADCs do not have the memory of the circuit and have the characteristics of sampling and converting one by one. They can be applied in multiplexing scenarios, and the digital codeword output does not need to be processed by a decimation filter like sigma-delta. Although the maximum accuracy of SAR ADCs is not as good as that of sigma-delta ADCs, they have a high degree of digitization and a simple structure. Their speed, power consumption and area are improved with the progress of CMOS technology and the reduction of transistor feature size. Moreover, SAR ADCs can be combined with pipelined ADCs to obtain pipelined SAR ADCs, which can increase the sampling rate while maintaining the original accuracy.

[0004] The residue amplifier is a crucial module in a pipelined SAR ADC. The errors introduced by the previous-stage ADC can be resolved by setting inter-stage redundancy or the redundancy of the next-stage ADC. Due to the amplification of the residue amplifier, the corresponding input-referred errors of the next-stage ADC will be suppressed, while the errors introduced by the residue amplifier will directly manifest in the output codewords of the next stage. Traditional residue amplifiers generally adopt a switched-capacitor structure as feedback. Since the gain error depends on the gain of the operational amplifier, the operational amplifier usually adopts a cascode structure to increase the gain. This structure is a static amplifier with high power consumption and limited output swing. The limited output swing will result in a small residue gain, and this type of operational amplifier requires a high supply voltage and cannot be used in advanced processes with reduced power rails. Moreover, for advanced processes, due to the short-channel effect, the intrinsic gain of the transistors is low, and the gain of a single-stage operational amplifier is limited. Therefore, using a multi-stage operational amplifier is an inevitable choice. However, for a multi-stage operational amplifier, stability is a problem, which can be solved by methods such as Miller compensation and introducing dead zones in a ring amplifier, but this will increase the circuit complexity. The closed-loop amplifier consumes a certain amount of power to charge the feedback capacitor and the load. And within a certain settling time, the higher the settling degree, the smaller the time constant. The smaller the time constant means the higher the noise bandwidth. Therefore, there is a design trade-off between settling error and noise.

[0005] In summary, the closed-loop amplifier has a design trade-off between settling error and noise, the problem of loop stability, and the problem of low energy efficiency for a static closed-loop amplifier. The open-loop amplifier based on GmC integral charging can avoid these problems. The equivalent circuit of this amplifier is to use a voltage-controlled current source with a transconductance of Gm to charge a capacitor to achieve the amplification function. Since it is an open-loop system, there is no stability problem of the closed-loop system. Secondly, since there is no settling, the time constant is very large, the noise bandwidth is very small, and the noise introduced to the system is very small. Moreover, since this operational amplifier only works during amplification, the power consumption is very low and the energy efficiency is high, which can be an option for low-power, high-precision, or high-speed ADCs. However, the two inevitable problems of the open-loop amplifier based on GmC integral charging are that its gain is greatly affected by temperature and supply voltage, and its linearity is relatively low when the input swing is large. Summary of the Invention

[0006] In view of the problems that the gain of the traditional open-loop amplifier based on GmC integral charging is affected by temperature and supply voltage and the low linearity, the present invention provides a GmC dynamic amplifier with high linearity, high temperature, and supply voltage stability, which can reduce the variation of the gain with temperature and supply voltage conditions and improve the linearity when the input signal amplitude is high.

[0007] The technical solution adopted by the present invention to solve the above technical problems is a GmC dynamic amplifier with high linearity, high temperature and power supply voltage stability, which is characterized in that it includes an amplifier main body part and a bias part.

[0008] The amplifier main body part includes two differential pairs with asymmetric width-to-length ratios formed by the first to fourth transistors M1, M2, M3, M4, the eleventh, twelfth, fourteenth and fifteenth transistors M11, M12, M14, M15 for reset, the thirteenth and sixteenth transistors M13, M16 for preventing the differential pair current from being affected by the output voltage, the fifth and sixth transistors M5, M6 for controlling whether the amplification unit is in the amplification phase or the reset phase, the seventh and eighth transistors M7, M8 for increasing the output impedance of the tail current source so as to improve the common-mode rejection ratio of the operational amplifier, and the ninth and tenth transistors M9, M10 for current replication.

[0009] The bias part is composed of a constant transconductance bias circuit and three transistors connected in series with current sources. The constant transconductance bias circuit is composed of the seventeenth to twenty-eighth transistors M17~M28 and a resistor R1, and can provide a voltage bias Vbn_cs_tail for the amplifier main body part. The twenty-ninth transistor M29 is connected in series with the current source I1 to provide a voltage bias Vbp_cas for the constant transconductance bias circuit. The thirtieth transistor M30 is connected in series with the current source l2 to provide a voltage bias Vbn_cas for the amplifier main body part. The thirty-first transistor is connected in series with the current source l3 to provide a voltage bias Vbn_cas_tail for the amplifier main body part.

[0010] The main body part has positive and negative input terminals Vip and Vin, positive and negative output terminals Voutp and Voutn, an enable control terminal CLK, an enable control terminal Bias voltage terminals Vbn_cas, Vbn_cas_tail, and Vbn_cs_tail, power supply terminal, and ground level terminal. Among them, the positive input terminal Vip is connected to the gates of the first transistor and the third transistor M1, M3, the negative input terminal Vin is connected to the gates of the second transistor and the fourth transistor M2, M4, the positive output terminal Voutp is connected to the drain of the fifteenth transistor, the negative output terminal Voutn is connected to the drain of the fourteenth transistor, the enable control terminal CLK is connected to the gates of the fifth, sixth, twelfth, fourteenth, and fifteenth transistors M5, M6, M12, M14, M15, the bias voltage terminal Vbn_cas is connected to the gates of the thirteenth and sixteenth transistors M13, M16, the bias voltage terminal Vbn_cas_tail is connected to the gates of the seventh and eighth transistors M7, M8, and the bias voltage terminal Vbn_cs_tail is connected to the gates of the ninth and tenth transistors M9, M10; the sources of the ninth and tenth transistors M9, M10 are both connected to the ground level terminal, and the drains are respectively connected to the sources of the seventh and eighth transistors M7, M8; the drains of the seventh and eighth transistors M7, M8 are respectively connected to the sources of the fifth and sixth transistors M5, M6; the drain of the fifth transistor M5 and the sources of the first and second transistors M1, M2 are connected, and the drain of the sixth transistor M6 and the sources of the third and fourth transistors M3, M4 are connected; the drains of the first and third transistors M1, M3 are both connected to the source of the thirteenth transistor M13, and the drains of the second and fourth transistors M2, M4 are both connected to the source of the sixteenth transistor M16; the source and drain of the eleventh transistor M11 are respectively connected to the source of the thirteenth transistor M13 and the source of the sixteenth transistor M16, and the gate of the eleventh transistor is connected to the enable control terminal connected; the source and drain of the twelfth transistor M12 are respectively connected to the source of the sixteenth transistor M16 and the source of the thirteenth transistor M13; the drain of the thirteenth transistor M13 and the drain of the fourteenth transistor M14 are connected, and the drain of the sixteenth transistor M16 and the drain of the fifteenth transistor M15 are connected. The sources of the fourteenth and fifteenth transistors are both connected to the power supply terminal. The first to eleventh transistors M1~M11, the thirteenth and sixteenth transistors M13, M16 in the main body are N-type MOS transistors, and the twelfth, fourteenth, and fifteenth transistors M12, M14, M15 are P-type MOS transistors; the width-to-length ratios of the fourteenth and fifteenth transistors are equal, the width-to-length ratios of the thirteenth and sixteenth transistors are equal, the width-to-length ratios of the fifth and sixth transistors are equal, the width-to-length ratios of the seventh and eighth transistors are equal, the width-to-length ratios of the ninth and tenth transistors are equal, the width-to-length ratio of the first transistor is 5.4 times that of the second transistor, and the width-to-length ratio of the fourth transistor is 5.4 times that of the third transistor.

[0011] The bias section has bias voltage output terminals Vbn_cas_tail, Vbn_cs_tail, and Vbn_cas, as well as a power supply terminal and a ground level terminal, where Vbn_cs_tail is connected to the gate of the seventeenth transistor M17, Vbn_cas_tail is connected to the gate and drain of the thirty-first transistor M31, and Vbn_cas is connected to the gate and drain of the thirtieth transistor. The source of the twenty-ninth transistor M29 is connected to the power supply terminal, and both the drain and the gate are connected to the positive terminal of the first current source I1. The negative terminal of the first current source I1 is connected to the ground level. The source of the thirtieth transistor M30 is connected to the power supply terminal, and both the drain and the gate are connected to the positive terminal of the second current source I2. The negative terminal of the second current source I2 is connected to the ground level. The source of the thirty-first transistor M31 is connected to the ground level terminal, and both the drain and the gate are connected to the negative terminal of the third current source I3. The positive terminal of the third current source I3 is connected to the power supply terminal. The source of the twenty-eighth transistor M28 is connected to the power supply terminal, the gate is connected to the drain of the twenty-seventh transistor M27 and the gate of the twenty-first transistor M21, and the drain is connected to the source of the twenty-seventh transistor M27. The gate of the twenty-seventh transistor M27 is connected to the gate of the twenty-second transistor M22 and the drain of the twenty-ninth transistor M29, and the drain is connected to the drain of the twenty-sixth transistor M26. The drain of the twenty-sixth transistor M26 is connected to the drain of the twenty-seventh transistor M27, the gate is connected to the gate and drain of the twenty-third transistor M23, and the source is connected to the drain of the twenty-fifth transistor M25. The gate of the twenty-fifth transistor M25 is connected to the gate and drain of the twenty-fourth transistor M24, and the source is connected to the resistor R1. The two ends of the resistor R1 are respectively connected to the source of the twenty-fifth transistor M25 and the ground level terminal. The source of the twenty-first transistor M21 is connected to the power supply terminal, and the drain is connected to the source of the twenty-second transistor M22. The gate of the twenty-second transistor M22 is connected to the drain of the twenty-ninth transistor M29. The drain and the gate of the twenty-third transistor M23 are both connected to the drain of the twenty-second transistor M22, and the source is connected to the drain of the twenty-fourth transistor M24. The gate and the drain of the twenty-fourth transistor M24 are both connected to the source of the twenty-third transistor M23, and the source is connected to the ground level terminal. The source of the twentieth transistor M20 is connected to the power supply terminal, the gate is connected to the drain of the twenty-seventh transistor M27, and the drain is connected to the source of the nineteenth transistor M19. The gate of the nineteenth transistor M19 is connected to the drain of the twenty-ninth transistor M29, and the drain is connected to the drain of the eighteenth transistor and the gate of the seventeenth transistor. The gate of the eighteenth transistor M18 is connected to the drain of the thirty-first transistor M31, and the source is connected to the drain of the seventeenth transistor M17. The source of the seventeenth transistor M17 is connected to the ground level terminal.The seventeenth, eighteenth, twenty-third, twenty-fourth, twenty-sixth, twenty-fifth, and thirty-first transistors of the bias section are N-type MOS transistors, and the nineteenth, twentieth, twenty-first, twenty-second, twenty-seventh, twenty-eighth, twenty-ninth, and thirtieth transistors are P-type MOS transistors.

[0012] As described above, the GmC dynamic amplifier circuit with high linearity, high temperature, and power supply voltage stability provided by the present invention adopts two differential pairs with asymmetric transistor aspect ratios in the amplifier main body. The offset voltages of the two differential pairs are opposite to each other, that is, the input voltages corresponding to the maximum transconductance of the two differential pairs are opposite to each other. As Figure 1 shown, by connecting the drain ends of the transistors corresponding to the two differential pairs, the differential output currents of the two differential pairs can be added, which is equivalent to adding the transconductances of the two differential pairs, and a differential circuit with a constant transconductance can be obtained within a certain differential input range, thereby improving the linearity of the amplifier when the input amplitude is relatively large; secondly, the eleventh, twelfth, fourteenth, and fifteenth transistors are also introduced in the main body to reset the amplifier and reduce the influence of the residual charge of one amplification operation on the next amplification; thirdly, the thirteenth and sixteenth transistors are introduced in the main body to reduce the influence of the output voltages Voutp and Voutn on the drain currents of the first to fourth transistors; then, the seventh and eighth transistors are also introduced in the main body to increase the output impedance of the tail current source and reduce the influence of the input common-mode voltage on the magnitude of the tail current source, that is, the transconductance of the differential pair; in addition, the bias section of the present invention also adopts a constant transconductance bias circuit. The transconductance of the transistors in this circuit is less affected by temperature and power supply voltage conditions. Through the current mirror, the current of the constant transconductance bias circuit is copied to the main body as the current of the tail current source. Therefore, the transconductance of the differential pair in the main body and the gain of the main body also have high temperature and power supply voltage stability. Description of the Drawings

[0013] Figure 1 is a graph showing the relationship between the transconductance of an asymmetric differential pair and a composite structure including two complementary asymmetric differential pairs and the input signal.

[0014] Figure 2 is a circuit diagram of a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability.

[0015] Figure 3 is a circuit diagram of a conventional GmC dynamic amplifier.

[0016] Figure 4 is a circuit diagram of the simulation environment for testing a conventional GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability, as well as a timing diagram of the switches in the circuit diagram.

[0017] Figure 5 are the input-output transfer characteristic curves of a common GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability.

[0018] Figure 6 is a graph showing the variation of the gain of a common GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability with the differential input voltage.

[0019] Figure 7 is the spectrum of the output signal of a common GmC dynamic amplifier after being sampled.

[0020] Figure 8 is the spectrum of the output signal of a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability after being sampled.

[0021] Figure 9 is the gain distribution diagram of a common GmC dynamic amplifier when the differential input is 1 mV, the power supply voltage fluctuates by ±10%, and the temperature ranges from -40°C to 120°C.

[0022] Figure 10 is the gain distribution diagram of a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability when the differential input is 1 mV, the power supply voltage fluctuates by ±10%, and the temperature ranges from -40°C to 120°C. Detailed implementation mode

[0023] Example 1 Refer to Figure 1 and Figure 2 .

[0024] This embodiment is a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability. The key module for achieving high linearity refers to the principle shown in Figure 1 . Figure 1 shows a graph of the relationship between the transconductance and the input signal of two asymmetric differential pairs and a composite structure containing two complementary asymmetric differential pairs. It can be seen that if the aspect ratios of the two transistors of the differential pair are different, then the differential pair will have an input offset, and the graph of gm versus the differential input voltage will shift to the left or right. The amount and direction of the shift depend on the aspect ratios of the two transistors. When two asymmetric differential pairs with the same aspect ratios of the two transistors but opposite positions relative to the input terminal are combined, as shown in Figure 1 , the gms of these two complementary differential pairs will add up. If the ratio of the aspect ratios of the two transistors of the asymmetric differential pair is set reasonably, a composite transconductance structure with gm not varying with the input within a certain input range can be obtained.

[0025] For a GmC dynamic amplifier, the gain is equal to where gm is the transconductance of the input differential pair, T is the integration time, that is Figure 2 the pulse width of the enabling control input CLK in Figure 1 and C is the size of the load capacitor. Therefore, using the composite structure including two complementary asymmetric differential pairs as the GmC dynamic amplifier can obtain a GmC dynamic amplifier with a gain that does not change with input variations within a certain differential input range, thereby improving the linearity of the GmC amplifier. As Figure 2 shown, the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability includes an amplifier main body part and a bias part.

[0026] The amplifier main body part includes two differential pairs with different aspect ratios formed by the first to fourth transistors M1, M2, M3, M4, the eleventh, twelfth, fourteenth, and fifteenth transistors M11, M12, M14, M15 for reset, the thirteenth and sixteenth transistors M13, M16 for preventing the differential pair current from being affected by the output voltage, the fifth and sixth transistors M5, M6 for controlling whether the amplification unit is in the amplification phase or the reset phase, the seventh and eighth transistors M7, M8 for increasing the output impedance of the tail current source and thus improving the common-mode rejection ratio of the operational amplifier, and the ninth and tenth transistors M9, M10 for current replication.

[0027] The bias part is composed of a constant transconductance bias circuit and three transistors connected in series with current sources. The constant transconductance bias circuit consists of the seventeenth to twenty-eighth transistors M17~M28 and a resistor R1, and can provide a voltage bias Vbn_cs_tail for the amplifier main body part. The twenty-ninth transistor M29 is connected in series with the current source I1 to provide a voltage bias Vbp_cas for the constant transconductance bias circuit. The thirtieth transistor M30 is connected in series with the current source I2 to provide a voltage bias Vbn_cas for the amplifier main body part. The thirty-first transistor is connected in series with the current source I3 to provide a voltage bias Vbn_cas_tail for the amplifier main body part.

[0028] The main body part has positive and negative input terminals Vip and Vin, positive and negative output terminals Voutp and Voutn, an enabling control terminal CLK, and an enabling control terminal Bias voltage terminals Vbn_cas, Vbn_cas_tail, and Vbn_cs_tail, power supply terminal, and ground level terminal. Among them, the positive input terminal Vip is connected to the gates of the first transistor and the third transistor M1, M3, the negative input terminal Vin is connected to the gates of the second transistor and the fourth transistor M2, M4, the positive output terminal Voutp is connected to the drain of the fifteenth transistor, the negative output terminal Voutn is connected to the drain of the fourteenth transistor, the enable control terminal CLK is connected to the gates of the fifth, sixth, twelfth, fourteenth, and fifteenth transistors M5, M6, M12, M14, M15, the bias voltage terminal Vbn_cas is connected to the gates of the thirteenth and sixteenth transistors M13, M16, the bias voltage terminal Vbn_cas_tail is connected to the gates of the seventh and eighth transistors M7, M8, and the bias voltage terminal Vbn_cs_tail is connected to the gates of the ninth and tenth transistors M9, M10; the sources of the ninth and tenth transistors M9, M10 are both connected to the ground level terminal, and the drains are respectively connected to the sources of the seventh and eighth transistors M7, M8; the drains of the seventh and eighth transistors M7, M8 are respectively connected to the sources of the fifth and sixth transistors M5, M6; the drain of the fifth transistor M5 and the sources of the first and second transistors M1, M2 are connected, and the drain of the sixth transistor M6 and the sources of the third and fourth transistors M3, M4 are connected; the drains of the first and third transistors M1, M3 are both connected to the source of the thirteenth transistor M13, and the drains of the second and fourth transistors M2, M4 are both connected to the source of the sixteenth transistor M16; the source and drain of the eleventh transistor M11 are respectively connected to the source of the thirteenth transistor M13 and the source of the sixteenth transistor M16, and the gate of the eleventh transistor is connected to the enable control terminal connected; the source and drain of the twelfth transistor M12 are respectively connected to the source of the sixteenth transistor M16 and the source of the thirteenth transistor M13; the drain of the thirteenth transistor M13 and the drain of the fourteenth transistor M14 are connected, and the drain of the sixteenth transistor M16 and the drain of the fifteenth transistor M15 are connected. The sources of the fourteenth and fifteenth transistors M14, M15 are both connected to the power supply terminal. The first to eleventh transistors M1~M11, the thirteenth and sixteenth transistors M13, M16 of the main body are N-type MOS transistors, and the twelfth, fourteenth, and fifteenth transistors M12, M14, M15 are P-type MOS transistors; the width-to-length ratios of the fourteenth and fifteenth transistors are equal, the width-to-length ratios of the thirteenth and sixteenth transistors are equal, the width-to-length ratios of the fifth and sixth transistors are equal, the width-to-length ratios of the seventh and eighth transistors are equal, the width-to-length ratios of the ninth and tenth transistors are equal, the width-to-length ratio of the first transistor is 5.4 times that of the second transistor, and the width-to-length ratio of the fourth transistor is 5.4 times that of the third transistor.

[0029] The bias section has bias voltage output terminals Vbn_cas_tail, Vbn_cs_tail, and Vbn_cas, as well as a power supply terminal and a ground level terminal. Among them, Vbn_cs_tail is connected to the gate of the seventeenth transistor M17, Vbn_cas_tail is connected to the gate and drain of the thirty-first transistor M31, and Vbn_cas is connected to the gate and drain of the thirtieth transistor. The source of the twenty-ninth transistor M29 is connected to the power supply terminal, and both the drain and the gate are connected to the positive terminal of the first current source I1. The negative terminal of the first current source I1 is connected to the ground level. The source of the thirtieth transistor M30 is connected to the power supply terminal, and both the drain and the gate are connected to the positive terminal of the second current source I2. The negative terminal of the second current source I2 is connected to the ground level. The source of the thirty-first transistor M31 is connected to the ground level terminal, and both the drain and the gate are connected to the negative terminal of the third current source I3. The positive terminal of the third current source I3 is connected to the power supply terminal. The source of the twenty-eighth transistor M28 is connected to the power supply terminal, the gate is connected to the drain of the twenty-seventh transistor M27 and the gate of the twenty-first transistor M21, and the drain is connected to the source of the twenty-seventh transistor M27. The gate of the twenty-seventh transistor M27 is connected to the gate of the twenty-second transistor M22 and the drain of the twenty-ninth transistor M29, and the drain is connected to the drain of the twenty-sixth transistor M26. The drain of the twenty-sixth transistor M26 is connected to the drain of the twenty-seventh transistor M27, the gate is connected to the gate and drain of the twenty-third transistor M23, and the source is connected to the drain of the twenty-fifth transistor M25. The gate of the twenty-fifth transistor M25 is connected to the gate and drain of the twenty-fourth transistor M24, and the source is connected to the resistor R1. Both ends of the resistor R1 are respectively connected to the source of the twenty-fifth transistor M25 and the ground level terminal. The source of the twenty-first transistor M21 is connected to the power supply terminal, and the drain is connected to the source of the twenty-second transistor M22. The gate of the twenty-second transistor M22 is connected to the drain of the twenty-ninth transistor M29. The drain and the gate of the twenty-third transistor M23 are both connected to the drain of the twenty-second transistor M22, and the source is connected to the drain of the twenty-fourth transistor M24. The gate and the drain of the twenty-fourth transistor M24 are both connected to the source of the twenty-third transistor M23, and the source is connected to the ground level terminal. The source of the twentieth transistor M20 is connected to the power supply terminal, the gate is connected to the drain of the twenty-seventh transistor M27, and the drain is connected to the source of the nineteenth transistor M19. The gate of the nineteenth transistor M19 is connected to the drain of the twenty-ninth transistor M29, and the drain is connected to the drain of the eighteenth transistor and the gate of the seventeenth transistor. The gate of the eighteenth transistor M18 is connected to the drain of the thirty-first transistor M31, and the source is connected to the drain of the seventeenth transistor M17. The source of the seventeenth transistor M17 is connected to the ground level terminal.The seventeenth, eighteenth, twenty-third, twenty-fourth, twenty-sixth, twenty-fifth, and thirty-first transistors of the bias section are N-type MOS transistors, and the nineteenth, twentieth, twenty-first, twenty-second, twenty-seventh, twenty-eighth, twenty-ninth, and thirtieth transistors are P-type MOS transistors.

[0030] As described above, the GmC dynamic amplifier circuit with high linearity, high temperature, and power supply voltage stability provided by the present invention adopts Figure 1 the composite structure shown, which includes two complementary asymmetric differential pairs, to improve the linearity of the amplifier when the input amplitude is large; secondly, the main body part also introduces the eleventh, twelfth, fourteenth, and fifteenth transistors to reset the amplifier, and at the same time reduce the influence of the residual charge of one amplification operation on the next amplification; thirdly, the main body part introduces the thirteenth and sixteenth transistors, which can reduce the influence of the output voltages Voutp and Voutn on the drain currents of the first to fourth transistors; then, the main body part also introduces the seventh and eighth transistors, which improve the output impedance of the tail current source and reduce the influence of the input common-mode voltage on the size of the tail current source, that is, the transconductance of the differential pair; in addition, the bias section of the present invention also adopts a constant transconductance bias circuit, which is composed of the seventeenth to twenty-eighth transistors M17~M28, as Figure 2 shown, due to the action of the replicated current of the current mirror composed of the twenty-first, twenty-second, twenty-seventh, and twenty-eighth transistors M21, M22, M27, and M28, the currents of the twenty-fifth transistor M25 and the twenty-fourth transistor M24 are equal. Assuming that the currents of M24 and M25 are both equal to I, the aspect ratio of M24 is the aspect ratio of M25 is the overdrive voltage of M24 is (V ov ) M24 , the overdrive voltage of M25 is (V ov ) M25 , the resistance value of the resistor R1 is R, the mobility of n-type carriers is u n , the unit capacitance value of the gate oxide layer is C ox , then the following equation holds:

[0031]

[0032] After calculation, the following formula can be obtained from the above formula

[0033]

[0034] Since the transconductance of the transistor is equal to Therefore, the transconductance of the twenty-fourth transistor M24 can be derived from the above formula, as shown in the following formula:

[0035]

[0036] Therefore, the transconductance of the twenty-fourth transistor only depends on and R, and is not affected by temperature and power supply voltage. The current mirror formed by the twentieth, twenty-eighth, seventeenth, ninth, and tenth transistors M20, M28, M17, M9, and M10 copies the current of the constant transconductance bias circuit to the main body circuit as the current of the tail current sources M9 and M10. Assuming that the current amplification factor of the current mirror is N, then the current of M9 and M10 is NI. Assuming that the aspect ratio of the first transistor is The current of NmI of the tail current source flows to one transistor in the differential pair, where m depends on the aspect ratio of the transistors in the differential pair. For M1, then the transconductance of M1 is equal to the following formula:

[0037]

[0038] Therefore, the transconductance of the first transistor M1 only depends on N, m, and R, and is not affected by temperature and power supply voltage. Since N, m, and R are fixed values, the transconductance of the first transistor M1 is fixed. Similarly, the transconductances of transistors M2, M3, and M4 can also be obtained as fixed. For a GmC dynamic amplifier, the gain is equal to where C can be made of metal MIM or MOM capacitors, and its capacitance is less affected by temperature and power supply voltage. And T can be kept constant by applying a CLK signal whose pulse width is not affected by temperature and power supply voltage, such as a divided frequency signal of an external clock or the output signal of a DLL. Therefore, the high temperature and power supply voltage stability of the gain of the GmC dynamic amplifier can be ensured. In addition, in order to ensure the accuracy of current mirror current replication, the seventh, eighth, eighteenth, nineteenth, twenty-second, twenty-third, twenty-sixth, and twenty-seventh transistors are added. These transistors are all common-gate transistors, which can shield the influence of the voltage at the output end of the current mirror on the drain voltage of the common-source transistor of the current mirror. In this way, the drain voltages of the common-source transistors in the input and output branches of the current mirror are equal, and the accuracy of current replication is improved.

[0039] See Embodiment 2 Figures 3 to 10 .

[0040] Embodiment 2 is a simulation of a general GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability. Through the simulation results, the two amplifiers can be compared to prove the advantages of the present invention over the general structure.

[0041] The structure of the general GmC dynamic amplifier is as Figure 3As shown, it has positive and negative input terminals Vip and Vin, positive and negative output terminals Voutp and Voutn, an enable control terminal CLK, and an enable control terminal a power supply terminal and a ground level terminal. Among them, the positive input terminal Vip is connected to the gate of the first transistor M1, the negative input terminal Vin is connected to the gate of the second transistor M2, the positive output terminal Voutp is connected to the drain of the seventh transistor, the negative output terminal Voutn is connected to the drain of the sixth transistor, the enable control terminal CLK is connected to the gates of the third, eighth, ninth, and fifteenth transistors M3, M8, M9, M15, the drain and the gate of the thirteenth transistor are both connected to the positive terminal of the second current source I2, and the gates of the sixth and seventh transistors M6, M7, the drain and the gate of the twelfth transistor are both connected to the negative terminal of the third current source I3, and the gates of the eleventh and fourth transistors M11, M4, the drain of the eleventh transistor is connected to the gates of the tenth and fifth transistors M10, M5; the source of the thirteenth transistor is connected to the power supply terminal, the negative terminal of the second current source I2 is connected to the ground level terminal, the positive terminal of the third current source is connected to the power supply terminal, the source of the twelfth transistor is connected to the ground level terminal, the positive terminal of the first current source I1 is connected to the power supply terminal, the source of the eleventh transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is connected to the ground level terminal, the source and the drain of the fifth transistor are respectively connected to the ground level terminal and the source of the fourth transistor, the drain of the fourth transistor is connected to the source of the third transistor, the drain of the third transistor is connected to the sources of the first and second transistors, the drains of the first and second transistors are respectively connected to the sources of the sixth and seventh transistors, the source and the drain of the fourteenth transistor are respectively connected to the drains of the first and second transistors, the gate of the fourteenth transistor is connected to the enable control terminal connected, the source and the drain of the fifteenth transistor are respectively connected to the drains of the second and first transistors, the drains of the sixth and seventh transistors are respectively connected to the drains of the eighth and ninth transistors, and the sources of the eighth and ninth transistors are both connected to the power supply terminal. The first to seventh transistors M1~M7, the tenth, eleventh, twelfth, and fourteenth transistors M10, M11, M12, M14 are N-type MOS transistors, and the eighth, ninth, thirteenth, and fifteenth transistors M8, M9, M13, M15 are P-type MOS transistors; the width-to-length ratios of the eighth and ninth transistors are equal, the width-to-length ratios of the sixth and seventh transistors are equal, and the width-to-length ratios of the first and second transistors are equal.

[0042] The simulation environment circuit diagram for testing ordinary GmC dynamic amplifiers and GmC dynamic amplifiers with high linearity, high temperature, and power supply voltage stability, as well as the timing diagram of the switches in the circuit diagram, are as Figure 4As shown, this structure simulates the situation where a GmC dynamic amplifier is applied inside a pipelined SAR ADC as a residue amplifier. Here, C1 and C2 are equivalent to the CDAC of the previous-stage SAR ADC, and C3 and C4 are equivalent to the CDAC of the next-stage SAR ADC. The bottom plate of C1 is connected to two switches, and the other ends of the two switches are respectively connected to VCM + RES / 2 and VCM. The bottom plate of C2 is connected to two switches, and the other ends of the two switches are respectively connected to VCM - RES / 2 and VCM. Here, VCM represents the common-mode voltage, usually equal to half of the power supply voltage, and RES represents the residue after the previous-stage SAR ADC completes quantization. The top plates of C1 and C2 are respectively connected to VCM through a switch, and are respectively connected to the negative input terminal and the positive input terminal of the GmC dynamic amplifier. The bottom plates of C3 and C4 are respectively connected to the positive output terminal and the negative output terminal of the GmC dynamic amplifier through a switch, and the top plates are both connected to VCM. The control timing of the above-mentioned switches is as Figure 4 shown in the right half. This timing simulates the situation of a normal pipelined SAR ADC working. When φ1 and φ 1e are at high level, the previous-stage SAR ADC samples the input signal on the bottom plate. That is to say, the bottom plates of C1 and C2 are connected to the input signal source, and the top plates are connected to VCM. The voltage value of the capacitor tracks the change of the input signal. For the sake of convenience here, we assume that the input signals at both positive and negative terminals are VCM, and the differential input signal is 0. Then φ 1e becomes low level, the top plates of C1 and C2 are disconnected from VCM. Then φ1 becomes low level, and the bottom plates of C1 and C2 are disconnected from the input signal. In this way, the voltage of the input signal at the moment when φ 1e becomes low level is stored in C1 and C2. Then the SAR ADC starts quantization. The quantization process is equivalent to connecting the bottom plates of C1 and C2 to the voltages corresponding to the quantized codewords. Since the difference between the voltage corresponding to the codeword and the differential input signal is the residue RES of the ADC, and the differential input signal is 0, when φ2 becomes high level, the bottom plates of C1 and C2 are respectively connected to VCM + RES / 2 and VCM - RES / 2. According to the charge conservation of the capacitor, the differential input of the GmC dynamic amplifier is equal to RES at this time. Then CLK becomes high level, triggering the amplification process of the GmC dynamic amplifier. After a period of time, CLK returns to low level, and the amplification process ends. At this time, the output differential voltage of the GmC dynamic amplifier is equal to RES multiplied by the gain of the amplifier. At the same time, φ2 becomes low level, and the output differential voltage of the GmC dynamic amplifier is stored on the CDAC of the next-stage SAR ADC, that is, C3 and C4.

[0043] Example 2 involves three simulations. The process library used in the simulations is TSMC180nm. The first simulation is the measurement of the transfer characteristic curves of a general GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability, as well as the relationship between the gain and the input signal. In this simulation, the process corner is set to tt, the temperature is set to 27 degrees Celsius, and the power supply voltage is set to the normal value of 5V. The measurement method is to set RES in Figure 4 to a DC signal and give the control signal according to the timing diagram of Figure 4 . Measure the output differential voltage of the GmC dynamic amplifier when φ2 becomes low. Continuously change the magnitude of the DC signal RES and measure the output differential voltage corresponding to each RES. At the same time, obtain the gain by dividing the output voltage by RES. During the simulation, the GmC in Figure 4 can be replaced with the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability shown in Figure 2 or the general GmC dynamic amplifier shown in Figure 3 to obtain their respective simulation results. Through this simulation, the input-output transfer characteristic curves of the general GmC dynamic amplifier and the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability, as well as the image of the gain varying with the differential input voltage, are obtained, as shown in Figure 5 and Figure 6 .

[0044] Figure 5 shows the input-output transfer characteristic curves of the general GmC dynamic amplifier and the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability. The abscissa is the magnitude of the differential input voltage, and the ordinate is the magnitude of the differential output voltage. The red dashed line represents the input-output transfer characteristic curve of the general GmC dynamic amplifier, and the green solid line represents the input-output transfer characteristic curve of the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability. It can be seen that when the differential input voltage is relatively large and its absolute value exceeds 60mV, the input-output transfer characteristic curve of the general GmC dynamic amplifier begins to bend, showing a certain degree of non-linearity, and the gain begins to decrease. However, the input-output transfer characteristic curve of the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability still maintains a certain degree of linearity, indicating that the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability has higher linearity than the general GmC dynamic amplifier.

[0045] Figure 6Shows the images of the gain of a general GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability varying with the differential input voltage. The abscissa is the magnitude of the differential input voltage, and the ordinate is the gain. The red dashed line represents the image of the gain of the general GmC dynamic amplifier varying with the differential input voltage, and the green solid line represents the image of the gain of the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability varying with the differential input voltage. It can be seen that the gain of the general GmC dynamic amplifier is the largest when the differential input voltage is 0, and it decreases sharply as the absolute value of the input voltage increases, showing non-linearity; while the gain of the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability can remain relatively unchanged within the differential input voltage range of -40mV to 40mV, showing a certain degree of linearity. This indicates that the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability has a higher linearity than the general GmC dynamic amplifier.

[0046] The second simulation of Example 2 is the measurement of the spectrum of the output signal of a general GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability after being sampled when the input signal is a sine signal. In this simulation, the process corner is set to tt, the temperature is set to 27 degrees Celsius, and the power supply voltage is set to the normal value of 5V. The measurement method is to Figure 4 set the RES in Figure 4 to a sine signal with an amplitude of 60mV and a frequency of 3*2M / 1024Hz, give the control signal according to the Figure 4 timing diagram, set the frequency of the control signal to 2M, let the amplifier amplify 1024 times, measure the output differential voltage of the GmC dynamic amplifier each time φ2 becomes low, so as to obtain 1024 sampling points of the output differential voltage. Perform a fast Fourier transform on these sampling points to obtain the spectrum of the output signal after being sampled. During the simulation, the GmC in Figure 2 can be replaced with the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability shown in Figure 3 or the general GmC dynamic amplifier shown in Figure 7 and Figure 8 respectively to obtain their respective simulation results. The spectra of the output signals of the general GmC dynamic amplifier and the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability obtained by simulation are shown in

[0047] Figure 7 Shows the spectrum of the output signal of the general GmC dynamic amplifier after being sampled. It can be seen that in addition to the component with the largest power presented by the input signal, there is also a harmonic component with a relatively high power, indicating that the sine input signal has serious distortion after passing through the general GmC dynamic amplifier;Figure 8 The spectrum after sampling the output signal of a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability is shown. It can be seen that the power of the harmonic components has been significantly reduced compared to that of a conventional GmC dynamic amplifier. Through the analysis of the spectrum, the THD of the conventional GmC dynamic amplifier is 49.3 dB, while that of the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability is 70.5 dB. Therefore, the distortion degree of the signal after passing through the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability is 21.2 dB less than that after passing through the conventional GmC dynamic amplifier. Since harmonic distortion is caused by the non-linearity of the amplifier, it can be said that the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability has higher linearity than the conventional GmC dynamic amplifier.

[0048] The third simulation of Example 2 is the measurement of the sensitivity of a conventional GmC dynamic amplifier and a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability to temperature and power supply voltage. In this simulation, the process corner is set to tt, and the measurement method is to Figure 4 set the RES in it to a DC signal of 1 mV, and give the control signal according to the Figure 4 timing diagram. Measure the output differential voltage of the GmC dynamic amplifier when φ2 becomes low. Continuously change the magnitudes of the temperature and power supply voltage. The temperature change range is from -40 °C to 120 °C, and the power supply voltage range is ±10% floating, that is, from 4.5 V to 5.5 V. Measure the output differential voltage corresponding to various conditions, and obtain the gain by dividing the output voltage by RES. During the simulation, the GmC in Figure 4 can be replaced with Figure 2 the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability shown in Figure 3 or the conventional GmC dynamic amplifier shown in Figure 9 and Figure 10 respectively to obtain their respective simulation results. The gain data of the conventional GmC dynamic amplifier and the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability obtained from the simulation are plotted as histograms, as shown in

[0049] Figure 9 The gain distribution diagram of the conventional GmC dynamic amplifier is shown when the differential input is 1 mV, the power supply voltage is ±10% floating, and the temperature ranges from -40 °C to 120 °C. It can be seen that the standard deviation of the gain distribution is 1.9, and the distribution ranges from 13 to 19.5, indicating that the gain fluctuates greatly with the temperature and power supply voltage conditions, which shows that the gain of the conventional GmC dynamic amplifier is greatly affected by the temperature and power supply voltage conditions. Figure 10The gain distribution diagram of a GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability is shown when the differential input is 1 mV, the power supply voltage fluctuates by 10% up and down, and the temperature ranges from -40°C to 120°C. It can be seen that the standard deviation of the gain distribution is 262 m, and the distribution is only in the range of 15.1 to 16.3, indicating that the gain fluctuates less with temperature and power supply voltage conditions, which shows that the gain of the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability is less affected by temperature and power supply voltage conditions and has high temperature and power supply voltage stability.

[0050] If the GmC dynamic amplifier with high linearity, high temperature, and power supply voltage stability is used as the residue amplifier of a pipelined SAR ADC, since the gain of this residue amplifier is still affected by the process corner, it is necessary to correct the gain of this operational amplifier once by adjusting the resistor R1 in the bias part or other methods after the ADC leaves the factory. Since the process corner of each chip is fixed after production, only one correction is required, and calibration is not required for each subsequent operation, ensuring the convenience of ADC use. The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. For example, if there is a startup problem of no current after the constant transconductance bias unit in the bias part is powered on, it can be solved by adding a startup circuit. If the range of differential input is relatively large, exceeding 60 mV, it can be solved by adding more asymmetric differential pairs. Due to the advantages of low power consumption, low noise, high linearity, high temperature, and power supply voltage stability of this amplifier, it can ensure the high precision and low power consumption of the ADC, and at the same time has the ability to adapt to sudden environmental conditions, and is widely used in high-tech fields such as medical imaging, biological detection, Internet of Things, instrumentation, and industrial process control.

Claims

1. A GmC dynamic amplifier with high linearity and high temperature and power supply voltage stability, characterized in that: It includes the amplifier main body and the bias part. The main part of the amplifier includes two differential pairs with asymmetric width-to-length ratios formed by first to fourth transistors M1, M2, M3, and M4, eleventh, twelfth, fourteenth, and fifteenth transistors M11, M12, M14, and M15 for resetting, thirteenth and sixteenth transistors M13 and M16 for preventing the differential pair current from being affected by the output voltage, fifth and sixth transistors M5 and M6 for controlling whether the amplifying unit is in the amplification phase or the reset phase, seventh and eighth transistors M7 and M8 for increasing the output impedance of the tail current source and thus increasing the common-mode rejection ratio of the operational amplifier, and ninth and tenth transistors M9 and M10 for replicating the current. The bias part is composed of a constant transconductance bias circuit and three transistors connected in series with a current source. The constant transconductance bias circuit is composed of the seventeenth to twenty-eighth transistors M17-M28 and the resistor R1, which can provide a voltage bias Vbn_cs_tail for the main part of the amplifier. The twenty-ninth transistor M29 is connected in series with the current source I1 to provide a voltage bias Vbp_cas for the constant transconductance bias circuit. The thirtieth transistor M30 is connected in series with the current source I2 to provide a voltage bias Vbn_cas for the main part of the amplifier. The thirty-first transistor is connected in series with the current source I3 to provide a voltage bias Vbn_cas_tail for the main part of the amplifier.

2. The GmC dynamic amplifier with high linearity and high temperature and power supply voltage stability according to claim 1, characterized in that: The main body has positive and negative input terminals Vip and Vin, positive and negative output terminals Voutp and Voutn, an enable control terminal CLK, an enable control terminal Bias voltage terminals Vbn_cas, Vbn_cas_tail, and Vbn_cs_tail, a power supply terminal, and a ground level terminal. The positive input terminal Vip is connected to the gates of the first and third transistors M1 and M3, the negative input terminal Vin is connected to the gates of the second and fourth transistors M2 and M4, the positive output terminal Voutp is connected to the drain of the fifteenth transistor, the negative output terminal Voutn is connected to the drain of the fourteenth transistor, the enable control terminal CLK is connected to the gates of the fifth, sixth, twelfth, fourteenth, and fifteenth transistors M5, M6, M12, M14, and M15, the bias voltage terminal Vbn_cas is connected to the gates of the thirteenth and sixteenth transistors M13 and M16, the bias voltage terminal Vbn_cas_tail is connected to the gates of the seventh and eighth transistors M7 and M8, and the bias voltage terminal Vbn_cs_tail is connected to the gates of the ninth and tenth transistors M9 and M10; The sources of the ninth and tenth transistors M9 and M10 are connected to the ground level terminal, and the drains are connected to the sources of the seventh and eighth transistors M7 and M8 respectively; The drains of the seventh and eighth transistors M7 and M8 are connected to the sources of the fifth and sixth transistors M5 and M6 respectively; The drain of the fifth transistor M5 is connected to the sources of the first and second transistors M1 and M2, and the drain of the sixth transistor M6 is connected to the sources of the third and fourth transistors M3 and M4; The drains of the first and third transistors M1, M3 are connected to the source of the thirteenth transistor M13, and the drains of the second and fourth transistors M2, M4 are connected to the source of the sixteenth transistor M16; The source and drain of the eleventh transistor M11 are connected to the source of the thirteenth transistor M13 and the source of the sixteenth transistor M16 respectively, and the gate of the eleventh transistor is connected to the enable control terminal. connect; The source and drain of the twelfth transistor M12 are connected to the source of the sixteenth transistor M16 and the source of the thirteenth transistor M13 respectively; The drain of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14 , and the drain of the sixteenth transistor M16 is connected to the drain of the fifteenth transistor M15 . Sources of the fourteenth transistor M14 and the fifteenth transistor M15 are both connected to the power supply terminal.

3. The GmC dynamic amplifier with high linearity and high temperature and power supply voltage stability according to claim 2, characterized in that: The first to eleventh transistors M1 to M11, the thirteenth and sixteenth transistors M13 and M16 of the main body are N-type MOS transistors, the twelfth, fourteenth and fifteenth transistors M12, M14 and M15 are P-type MOS transistors; the fourteenth and The width-to-length ratio of the fifteenth transistor is equal, the width-to-length ratio of the thirteenth and sixteenth transistors are equal, the width-to-length ratio of the fifth and sixth transistors are equal, the width-to-length ratio of the seventh and eighth transistors are equal, the width-to-length ratio of the ninth and tenth transistors are equal, the width-to-length ratio of the first transistor is 5.4 times the width-to-length ratio of the second transistor, and the width-to-length ratio of the fourth transistor is 5.4 times the width-to-length ratio of the third transistor.

4. The GmC dynamic amplifier with high linearity and high temperature and supply voltage stability according to claim 1, It is characterized in that The bias part has bias voltage output terminals Vbn_cas_tail, Vbn_cs_tail, and Vbn_cas, as well as a power supply terminal and a ground level terminal, wherein Vbn_cs_tail is connected to the gate of the seventeenth transistor M17, Vbn_cas_tail is connected to the gate and drain of the thirty-first transistor M31, and Vbn_cas is connected to the gate and drain of the thirtieth transistor. The source of the twenty-ninth transistor M29 is connected to the power supply terminal, and the drain and the gate are both connected to the positive terminal of the first current source I1. The negative terminal of the first current source I1 is connected to the ground level. The source of the thirtieth transistor M30 is connected to the power supply terminal, and the drain and the gate are both connected to the positive terminal of the second current source I2. The negative terminal of the second current source I2 is connected to the ground level. The source of the thirty-first transistor M31 is connected to the ground level terminal, and the drain and gate are both connected to the negative terminal of the third current source I3. The positive terminal of the third current source I3 is connected to the power supply terminal. The source of the twenty-eighth transistor M28 is connected to the power supply terminal, the gate is connected to the drain of the twenty-seventh transistor M27 and the gate of the twenty-first transistor M21, and the drain is connected to the source of the twenty-seventh transistor M27. The gate of the twenty-seventh transistor M27 is connected to the gate of the twenty-second transistor M22 and the drain of the twenty-ninth transistor M29 , and the drain of the twenty-sixth transistor M26 is connected to the drain of the twenty-sixth transistor M26 . The drain of the twenty-sixth transistor M26 is connected to the drain of the twenty-seventh transistor M27 , the gate is connected to the gate and drain of the twenty-third transistor M23 , and the source is connected to the drain of the twenty-fifth transistor M25 . The gate of the twenty-fifth transistor M25 is connected to the gate and drain of the twenty-fourth transistor M24 , and the source of the twenty-fifth transistor M25 is connected to the resistor R1 . Two ends of the resistor R1 are connected to the source of the twenty-fifth transistor M25 and the ground level terminal respectively. The source of the twenty-first transistor M21 is connected to the power supply terminal, and the drain is connected to the source of the twenty-second transistor M22. A gate of the twenty-second transistor M22 is connected to a drain of the twenty-ninth transistor M29 . The drain and gate of the twenty-third transistor M23 are connected to the drain of the twenty-second transistor M22 , and the source is connected to the drain of the twenty-fourth transistor M24 . The gate and drain of the twenty-fourth transistor M24 are connected to the source of the twenty-third transistor M23 , and the source is connected to the ground level terminal. The source of the twentieth transistor M20 is connected to the power supply terminal, the gate is connected to the drain of the twenty-seventh transistor M27, and the drain is connected to the source of the nineteenth transistor M19. The gate of the nineteenth transistor M19 is connected to the drain of the twenty-ninth transistor M29 , and the drain is connected to the drain of the eighteenth transistor and the gate of the seventeenth transistor. The gate of the eighteenth transistor M18 is connected to the drain of the thirty-first transistor M31 , and the source of the eighteenth transistor M18 is connected to the drain of the seventeenth transistor M17 . A source of the seventeenth transistor M17 is connected to the ground level terminal.

5. The GmC dynamic amplifier with high linearity and high temperature and power supply voltage stability according to claim 4, characterized in that: The seventeenth, eighteenth, twenty-third, twenty-fourth, twenty-sixth, twenty-fifth and thirty-first transistors of the bias part are N-type MOS tubes, and the nineteenth, twentieth, twenty-first, twenty-second, twenty-seventh, twenty-eighth, twenty-ninth and thirtieth transistors are P-type MOS tubes.

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