Variable-gain high-linearity differential amplifier circuit and receiver

Abstract

The present application provides a variable gain high linearity differential amplifier circuit and receiver, the circuit comprising: a main amplification stage comprising a differential pair and a negative feedback network disposed between an input and an output of the differential pair, the differential pair docking a differential input signal; and the calibration stage reversely accesses the differential input signal to the output end of the main amplification stage to form a signal counteracting path. According to the invention, low-distortion and high-gain amplification driving capability of signals can be realized, and the method can be widely applied to a wireless communication signal link receiver system.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication electronic circuits, and particularly to a variable gain high linearity differential amplifier circuit and a receiver. Background Art

[0002] With the development of wireless communication technology, the technical requirements for high linearity intermediate frequency amplifiers are getting higher and higher, mainly manifested in improving linearity, reducing noise figure, increasing bandwidth, and achieving miniaturization and integration.

[0003] The intermediate frequency amplifier of the receiver mainly greatly boosts the signal output by the mixer to meet the needs of the demodulation circuit. For the intermediate frequency amplifier, not only high gain, low noise, low distortion are required, but also sufficient bandwidth, good frequency response, large dynamic range and other performances. Especially for the low distortion performance requirements of the input signal by the high-speed high-resolution ADC, as the front-end unit before the ADC input, the performance of the intermediate frequency amplifier directly affects the performance indicators of the high-resolution ADC.

[0004] Traditional differential negative feedback amplifiers more or less face certain problems, such as high power consumption, low dynamic range, low linearity, and difficulty in input-output matching or the requirement for an additional input-output matching network. Summary of the Invention

[0005] In view of the above problems existing in the prior art, the present invention proposes a variable gain high linearity differential amplifier circuit and a receiver, mainly solving the problems of high power consumption and low linearity of traditional differential negative feedback amplifiers.

[0006] In order to achieve the above object and other objects, the technical solution adopted by the present invention is as follows.

[0007] The present application provides a variable gain high linearity differential amplifier circuit, the circuit comprising: a main amplification stage, which includes a differential pair and a negative feedback network disposed between the input and output of the differential pair, the differential pair receiving a differential input signal; a calibration stage, which reversely connects the differential input signal to the output end of the main amplification stage to form a signal cancellation path.

[0008] In an embodiment of the present application, the feedback gain of the negative feedback network is adjustable.

[0009] In an embodiment of the present application, the differential pair includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is connected to the source of the second NMOS transistor and grounded. The gate of the first NMOS transistor serves as a first input terminal, the gate of the second NMOS transistor serves as a second input terminal, the drain of the first NMOS transistor serves as a first output terminal, and the drain of the second NMOS transistor serves as a second output terminal. A negative feedback network is respectively provided between the first input terminal and the first output terminal and between the second input terminal and the second output terminal. The first input terminal receives a first input signal, and the second input terminal receives a second input signal, where the first input signal and the second input signal form the differential input signal.

[0010] In an embodiment of the present application, the negative feedback network includes a first sub-network and a second sub-network. The first sub-network includes a first programmable resistor and a first capacitor. One end of the first programmable resistor is connected to the first output terminal, the other end is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first input terminal. The second sub-network includes a second programmable resistor and a second capacitor. One end of the second programmable resistor is connected to the second output terminal, the other end is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the second input terminal.

[0011] In an embodiment of the present application, the calibration stage includes a first programmable transconductance differential transistor, a second programmable transconductance differential transistor, and a third programmable resistor. The gate of the first programmable transconductance differential transistor is connected to the second input signal, the drain is connected to the first output terminal, and the source is connected to the source of the second programmable transconductance differential transistor and the first end of the third programmable resistor. The gate of the second programmable transconductance differential transistor is connected to the first input signal, and the drain is connected to the second input signal. The second end of the third programmable resistor is grounded.

[0012] In an embodiment of the present application, the first programmable transconductance differential transistor and the second programmable transconductance differential transistor form multiple groups of differential structures, and the on-off state of each group of differential structures is controlled by a switching transistor. The bias current of each switching transistor is controlled by a preset first control signal, or the transconductance of the calibration stage is adjusted by adjusting the aspect ratio of the differential structure, so that the calibration stage outputs an intermodulation cancellation signal with a corresponding amplitude.

[0013] In an embodiment of the present application, the programmable resistor includes a resistor array composed of multiple parallel resistor branches. The resistor branch includes a first resistor, a second resistor, a third resistor, and a fifth NMOS transistor. One end of the first resistor serves as one end of the programmable resistor, and the other end is connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor is connected to one end of the second resistor, and the other end of the second resistor serves as the other end of the programmable resistor. The gate of the fifth NMOS transistor is connected to one end of the third resistor, and the other end of the third resistor is connected to a preset second control signal.

[0014] In an embodiment of the present application, a feeding balun is further provided at the output end of the main amplification stage.

[0015] The present application also provides a receiver, including the aforementioned variable gain high linearity differential amplifier circuit.

[0016] As described above, a variable gain high linearity differential amplifier circuit and a receiver provided by the present application have the following beneficial effects.

[0017] By adding a calibration stage branch to the main amplification stage in the present application, the entire variable gain differential amplifier achieves higher linearity and lower distortion within the full gain dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a conventional differential amplification circuit.

[0019] Figure 2 It is a circuit schematic diagram of the variable gain high linearity differential amplifier circuit in an embodiment of the present application.

[0020] Figure 3 It is a schematic diagram of the implementation structure of the variable negative feedback resistor arrays VRF and VRc in the negative feedback network in an embodiment of the present application.

[0021] Figure 4 It is a circuit schematic diagram of the calibration stage in an embodiment of the present application.

[0022] Figure 5 It is a schematic diagram of the results of the third-order intermodulation intercept point of the amplifier output corresponding to different values of the control code CTR<4:1> in the calibration stage circuit of an embodiment of the present application.

[0023] Figure 6 It is a schematic diagram of the results of the third-order intermodulation intercept point of the differential amplifier output at different gains in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0025] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0026] The inventor has found through research that:

[0027] Traditional differential negative feedback amplifiers more or less face certain problems, such as high power consumption, low dynamic range, low linearity, and great difficulty in input-output matching or the requirement for an additional input-output matching network, etc. As Figure 1 shown in the common-source amplifier, it has a high input impedance and an output impedance determined by the output load resistors LOAD1 and LOAD2. An additional compensation circuit is required to match the input-output impedance; the load resistor affects the signal swing, and high power consumption is also required to improve linearity. Therefore, it is necessary to design a feedback matching amplifier with low power consumption, high linearity, and variable gain.

[0028] This application proposes a variable-gain high-linearity differential amplifier circuit and a receiver. The technical solution of this application will be elaborated in detail below in combination with specific embodiments.

[0029] Please refer to Figure 2 , Figure 2 which is the circuit schematic diagram of the variable-gain high-linearity differential amplifier circuit in an embodiment of this application. The circuit includes: a main amplification stage, which includes a differential pair and a negative feedback network disposed between the input and output of the differential pair, and the differential pair receives a differential input signal; a calibration stage, which reversely connects the differential input signal to the output end of the main amplification stage to form a signal cancellation path. Through programmable linearization compensation design for the intermodulation signals generated by the main amplification stage in the calibration stage, the third-order intermodulation calibration is maximally eliminated, achieving the minimization of the distortion after linear amplification of the input signal at different gains.

[0030] In one embodiment, the differential pair includes a first NMOS transistor and a second NMOS transistor. The source of the first NMOS transistor is connected to the source of the second NMOS transistor and grounded. The gate of the first NMOS transistor serves as a first input terminal, the gate of the second NMOS transistor serves as a second input terminal, the drain of the first NMOS transistor serves as a first output terminal, and the drain of the second NMOS transistor serves as a second output terminal. The negative feedback network is respectively provided between the first input terminal and the first output terminal and between the second input terminal and the second output terminal. The first input terminal receives a first input signal, and the second input terminal receives a second input signal, wherein the first input signal and the second input signal form the differential input signal.

[0031] In one embodiment, the negative feedback network includes a first sub-network and a second sub-network. The first sub-network includes a first programmable resistor and a first capacitor. One end of the first programmable resistor is connected to the first output terminal, the other end is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first input terminal. The second sub-network includes a second programmable resistor and a second capacitor. One end of the second programmable resistor is connected to the second output terminal, the other end is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the second input terminal.

[0032] In one embodiment, the calibration stage includes a first programmable transconductance differential transistor, a second programmable transconductance differential transistor, and a third programmable resistor. The gate of the first programmable transconductance differential transistor is connected to the second input signal, the drain is connected to the first output terminal, and the source is connected to the source of the second programmable transconductance differential transistor and the first end of the third programmable resistor. The gate of the second programmable transconductance differential transistor is connected to the first input signal, and the drain is connected to the second input signal. The second end of the third programmable resistor is grounded.

[0033] In one embodiment, the first programmable transconductance differential transistor and the second programmable transconductance differential transistor form multiple groups of differential structures, and the on-off state of each group of differential structures is controlled by a switching transistor. The bias current of each switching transistor is controlled by a preset first control signal, or the transconductance of the calibration stage is adjusted by adjusting the aspect ratio of the differential structure, so that the calibration stage outputs an intermodulation cancellation signal with a corresponding amplitude. Specifically, the calibration stage is composed of differential programmable NMOS transistors NM3 (i.e., the first programmable transconductance differential transistor) / NM4 (i.e., the second programmable transconductance differential transistor) and a source-level variable feedback resistor array VR C1 constitutes.

[0034] In one embodiment, the programmable resistor includes a resistor array composed of multiple parallel resistor branches. The resistor branches include a first resistor, a second resistor, a third resistor, and a fifth NMOS transistor. One end of the first resistor serves as one end of the programmable resistor, and the other end is connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor is connected to one end of the second resistor, and the other end of the second resistor serves as the other end of the programmable resistor. The gate of the fifth NMOS transistor is connected to one end of the third resistor, and the other end of the third resistor is connected to a preset second control signal.

[0035] In one embodiment, a feeding balun is further provided at the output end of the main amplification stage, and the gain of the negative feedback network of the main amplification stage is adjustable.

[0036] Specifically, the main amplification stage is composed of differential amplification NMOS transistors NM1 / NM2, an output load balun T1 (which can also be an inductor), a variable negative feedback resistor array VR F1 / VR F2 and capacitors C1 / C2.

[0037] The differential input positive terminal signal INP and the negative terminal signal INN are respectively connected to the gates of the differential pair MOS transistors NM1 and NM2 of the main amplification stage. At the same time, INP and INN of this differential signal are also respectively connected to the gates of the MOS transistors NM4 and NM3 of the IM3 calibration stage. The drains of the corresponding input differential pair transistors NM1 and NM3 of the two-stage amplification unit are connected, and the drains of the MOS transistors NM2 and NM4 are connected. The sources of NM1 and NM2 are connected and then grounded, and the sources of the NM3 and NM4 networks are connected and then connected to one end of the variable feedback resistor VR C1 and then grounded. Through the above connections, a calibration path is formed by superimposing two intermodulation signals with opposite phases.

[0038] The programmable resistor array VR F1 forms a series negative feedback network (i.e., the first sub-network) with the capacitor C1. One end of VR F1 is connected to the negative terminal of the secondary coil of the load balun (named LDN), and the other end is connected to the positive terminal of the capacitor C1. The negative terminal of the capacitor C1 is connected to the gates of the MOS transistors NM1 and NM4. The programmable resistor array VR F2 forms a series negative feedback network (i.e., the second sub-network) with the capacitor C2. VR F2One end is connected to the positive terminal of the secondary coil of the load balun (named LDP), and the other end is connected to the positive electrode of capacitor C1. The negative electrode of capacitor C1 is connected to the gates of MOS transistors NM2 and NM3. The input and output ports of the two negative feedback networks are respectively connected to the gate and drain of the amplification transistor to form negative feedback between the input and output signals, which is beneficial to broadening the flatness of the signal bandwidth; by adjusting the resistance value of the variable resistor, the gain can be adjusted. LDP and LDN are the secondary ports of the amplifier load balun, and after being coupled and transformed, they are output to the primary coil and finally output to the subsequent stage signal. The output differential signal lines are OUTP and OUTN. When used as a single-ended output, either OUTP or OUTN can be grounded, and the other end is used as a single-ended output to drive the subsequent stage circuit.

[0039] In one embodiment, since the intermodulation signal generated by the main amplification stage through amplification is much smaller than the output signal, and the gain of the input signal is much greater than the amplification gain of the calibration stage, the influence of the calibration path on the gain of the main amplification stage is small. By adjusting the gain of the programmable calibration stage amplification unit, the superposition of the IM3 intermodulation signal generated by the main amplification stage and the intermodulation signals with different powers generated by the calibration stage can be achieved, so as to optimize IM3.

[0040] In one embodiment, the implementation structure of the variable negative feedback resistor arrays VRF and VRc in the negative feedback network is as Figure 3 shown. In this solution, 8-bit digital control bits ctrl<8:1> are used to control 8 groups of switching resistors with different resistance values respectively to achieve the control and switching of the resistance size. The digital control method of the resistor array is an equal-proportion weight, realizing 8 different resistance value combinations. Each group of switching resistors consists of 3 resistors and an NMOS transistor. For example, the first group of switching resistors controlled by ctrl<1> consists of resistor R1, resistor R2, resistor Rg1, and NM1; one end of resistor R1 is connected to the output terminal named RESN, and the other end is connected to the source electrode of NMOS transistor NM1; one end of resistor R2 is connected to the output terminal named RESP, and the other end is connected to the drain electrode of NMOS transistor NM1; one end of resistor Rg1 is connected to the gate of NMOS transistor NM1, and the other end is connected to the external control level ctrl<1>; when ctrl<1> is at a high level, NM1 is turned on and the resistor is connected to the network. When ctrl<1> is at a low level, NM1 is in the off state, and the control resistor is not connected to the network.

[0041] In one embodiment, the implementation diagram of the programmable IM3 calibration stage circuit is as Figure 4As shown, it mainly consists of four groups of common-source amplifiers with different width-to-length ratios. The differential input transistors of the four groups of common-source amplifiers are designed according to the binary weight ratio. The four groups of amplifiers are controlled by four control lines CTR<4:1>, realizing 16 combinations of width-to-length ratios. The transistor with a width-to-length ratio controlled by CTR<1> is gm, the transistor with a width-to-length ratio controlled by CTR<2> is 2*gm, the transistor with a width-to-length ratio controlled by CS<3> is 4*gm, and the transistor with a width-to-length ratio controlled by CS<4> is 8*gm. The CTR<1> control signal of the first group of amplifiers is connected to the gate of NMC1. The drain of NMC1 is connected to the sources of NM3-1 and NM4-1. The gates of NM3-1 and NM4-1 are respectively connected to the input signals INN and INP. The drains of NM3-1 and NM4-1 are respectively connected to the connection lines LDN and LDP. The CTR<2> control signal of the second group of amplifiers is connected to the gate of NMC2. The drain of NMC2 is connected to the sources of NM3-2 and NM4-2. The gates of NM3-2 and NM4-2 are respectively connected to the input signals INN and INP. The drains of NM3-2 and NM4-2 are respectively connected to the connection lines LDN and LDP. The CTR<3> control signal of the third group of amplifiers is connected to the gate of NMC3. The drain of NMC3 is connected to the sources of NM3-3 and NM4-3. The gates of NM3-3 and NM4-3 are respectively connected to the input signals INN and INP. The drains of NM3-3 and NM4-3 are respectively connected to the connection lines LDN and LDP. The CTR<4> control signal of the third group of amplifiers is connected to the gate of NMC4. The drain of NMC4 is connected to the sources of NM3-4 and NM4-4. The gates of NM3-4 and NM4-4 are respectively connected to the input signals INN and INP. The drains of NM3-4 and NM4-4 are respectively connected to the connection lines LDN and LDP. The sources of the NMC1, NMC2, NMC3, and NMC4 control switch transistors are connected together and then connected to one end of the variable resistor VRc and then to ground. By controlling CTR<4:1>, the IM3 calibration stage circuit can achieve different amplification gains, eliminate the intermodulation signals of the main amplification stage, and find the optimal linear region.

[0042] In one embodiment, Figure 5This is the result of the third-order intermodulation intercept point of the amplifier output corresponding to different values of the control code CTR<4:1> in the calibration-level circuit in an embodiment of the present application. It can be seen from the results that when the calibration function is not configured, that is, CTR<4:0> is 0 (decimal), the third-order intermodulation intercept point value of the amplifier output is approximately 32 dBm within the working range; when the calibration function is enabled and the calibration control bit CTR<4:1> increases from 1 to 8, the output third-order intermodulation intercept point shows an increasing change, and when the calibration control bit CTR<4:1> increases from 9 to 15, the output third-order intermodulation intercept point shows a decreasing change. When CTR<4:1> is 8, the optimal value is reached, and the optimal state can exceed 41 dBm in the full frequency band, which is 9 dB higher than before calibration. Therefore, the differential amplifier in the embodiment of the present application has very low intermodulation distortion characteristics.

[0043] In one embodiment, Figure 6 This is the result of the third-order intermodulation intercept point of the output of the differential amplifier in the embodiment of the present application at different gains. It can be obtained from the results that the third-order intermodulation intercept point of this amplifier changes by approximately 3 dB within the 8 dB variable gain change range and maintains good linearity within the gain range.

[0044] The above implementation results show that: A variable-gain high-linearity differential amplifier circuit proposed in the present application has excellent linear amplification performance, can achieve large dynamic range, low distortion, and high-linearity driving amplification ability for receiver signals, meets the requirements of high-precision and high-resolution ADC driving, and can be widely applied to the receiver system of wireless communication signal links.

[0045] The present application also provides a receiver, which includes the variable-gain high-linearity differential amplifier circuit in the foregoing embodiment. The specific structure of the amplifier circuit will not be elaborated here. Other architectures in the receiver and the cooperation relationship with the differential amplifier circuit are well known in the art and will not be elaborated here.

[0046] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A variable gain high linearity differential amplifier circuit, characterized in that: The circuit comprises: a main amplifier stage, comprising a differential pair and a negative feedback network disposed between an input and an output of the differential pair, the differential pair being coupled to a differential input signal; The calibration stage connects the differential input signal in reverse to the output terminal of the main amplification stage to form a signal cancellation path.

2. The variable gain high linearity differential amplifier circuit according to claim 1, characterized in that: The feedback gain of the negative feedback network is adjustable.

3. The variable gain high linearity differential amplifier circuit according to claim 1 or 2, characterized in that: The differential pair includes a first NMOS transistor and a second NMOS transistor, the source of the first NMOS transistor is connected to the source of the second NMOS transistor and is grounded, the gate of the first NMOS transistor serves as a first input terminal, the gate of the second NMOS transistor serves as a second input terminal, the drain of the first NMOS transistor serves as a first output terminal, the drain of the second NMOS transistor serves as a second output terminal, and the negative feedback network is respectively provided between the first input terminal and the first output terminal and between the second input terminal and the second output terminal; The first input terminal is connected to a first input signal, and the second input terminal is connected to a second input signal, wherein the first input signal and the second input signal constitute the differential input signal.

4. The variable gain high linearity differential amplifier circuit according to claim 3, characterized in that: The negative feedback network includes a first sub-network and a second sub-network, the first sub-network includes a first programmable resistor and a first capacitor; one end of the first programmable resistor is connected to the first output end, the other end is connected to one end of the first capacitor, and the other end of the first capacitor is connected to the first input end; The second sub-network includes a second programmable resistor and a second capacitor; one end of the second programmable resistor is connected to the second output end, the other end is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the second input end.

5. The variable gain high linearity differential amplifier circuit according to claim 3, characterized in that: The calibration stage includes a first programmable transconductance differential transistor, a second programmable transconductance differential transistor and a third programmable resistor; the gate of the first programmable transconductance differential transistor is connected to the second input signal, the drain is connected to the first output terminal, the source is connected to the source of the second programmable transconductance differential transistor and connected to the first terminal of the third programmable resistor; the gate of the second programmable transconductance differential transistor is connected to the first input signal, and the drain is connected to the second input signal; the second terminal of the third programmable resistor is grounded.

6. The variable gain high linearity differential amplifier circuit according to claim 5, characterized in that: The first programmable transconductance differential transistor and the second programmable transconductance differential transistor form a plurality of groups of differential structures, and the on / off state of each group of the differential structures is controlled by a switch tube, and the bias current of each switch tube is controlled by a preset first control signal, or the transconductance of the calibration stage is adjusted by adjusting the width-to-length ratio of the differential structure, so that the calibration stage outputs an intermodulation cancellation signal of a corresponding amplitude.

7. The variable gain high linearity differential amplifier circuit according to claim 4 or 5, characterized in that: The programmable resistor includes a resistor array composed of multiple parallel resistor branches, wherein the resistor branches include a first resistor, a second resistor, a third resistor and a fifth NMOS tube; one end of the first resistor serves as one end of the programmable resistor, and the other end is connected to the drain of the fifth NMOS tube, the source of the fifth NMOS tube is connected to one end of the second resistor, and the other end of the second resistor serves as the other end of the programmable resistor; the gate of the fifth NMOS tube is connected to one end of the third resistor, and the other end of the third resistor is connected to a preset second control signal.

8. The variable gain high linearity differential amplifier circuit according to claim 4 or 5, characterized in that: The output end of the main amplifier stage is also provided with a feeding balun.

9. A receiver, characterized in that: It comprises the variable gain high linearity differential amplifier circuit as described in any one of claims 1-8.

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