IIR filter

Abstract

The invention provides an IIR (Infinite Impulse Response) filter, which is characterized in that a current filtering result is calculated on the basis of N input data, N feedforward coefficients, N-1 feedback coefficients and N-1 previous feedback filtering results, N is the order of the IIR filter, and N is greater than or equal to 2; the integer part and the partial decimal in the previous filtering result are fed back to be used for calculating the current filtering result, the bit number of the partial decimal fed back in the previous filtering result is W, the value of the last bit of the partial decimal fed back in the previous filtering result is fixed to be 1, and W is a natural number larger than or equal to 1. Therefore, not only can the calculation amount be reduced, but also the offset of the final filtering result caused by intercepting the decimal part of the specific bit width of the previous filtering result for feedback can be reduced.

Description

[Technical field]

[0001] The present invention relates to the field of filtering operations, and in particular to an IIR (Infinite Impulse Response) filter. [Background technology]

[0002] The output of an IIR filter depends not only on the current input and past input values, but also on past output values.

[0003] The filtering result output by the IIR filter is:

[0004]

[0005] where b n is the nth feedforward coefficient, a m is the mth feedback coefficient, N is the order of the IIR filter, N is greater than or equal to 2, y k is the current filtering result, i.e., the kth filtering result, x k is the current input data, i.e. the kth input data, x k-n is the current input data x k The previous nth input data, y k-m is the mth filtering result before the current filtering result. m , b n ,y k and x k All are floating point numbers.

[0006] Specific:

[0007]

[0008] in is the signed fixed-point integer of the current filtering result (i.e. the integer part), is the unsigned fixed-point decimal (i.e. the decimal part) of the current filtering result. is the integer part of the mth filter result before the current filter result, is the fractional part of the previous m-th filtering result.

[0009] In an existing solution, when feeding back the previous filtering result, the integer part of the previous filtering result can be Feedback is performed to feed back all the fractional parts of the previous filtering results. However, this requires more calculations.

[0010] In another existing solution, when feeding back the previous filtering result, the integer part of the previous filtering result can be Feedback is performed by intercepting a part of the decimal of the previous filtering result and feeding it back. However, this approach will cause the final filtering result to be offset.

[0011] Therefore, it is urgent to propose a new technical solution to solve the above problems. [Summary of the invention]

[0012] One of the purposes of the present invention is to provide an IIR filter, which can not only reduce the amount of calculation and reduce the resource overhead of hardware, but also reduce the offset of the final filtering result caused by intercepting the fractional part of the specific bit width of the previous filtering result for feedback.

[0013] According to one aspect of the present invention, the present invention provides an IIR filter, which calculates a current filtering result based on N input data and N feedforward coefficients, N-1 feedback coefficients and fedback N-1 previous filtering results, wherein N is the order of the IIR filter, N is greater than or equal to 2, the integer part and part of the decimals in the previous filtering result are fed back to calculate the current filtering result, the number of bits of the part of the decimals fed back in the previous filtering result is W bits, the value of the last 1 bit of the part of the decimals fed back in the previous filtering result is fixed to 1, and W is a natural number greater than or equal to 1.

[0014] Compared with the prior art, the present invention fixes the value of the last 1 bit of the decimal part of the previous filtering result that is fed back to 1, which can not only reduce the amount of calculation and reduce the hardware resource overhead, but also reduce the offset in the final filtering result caused by intercepting the decimal part of a specific bit width of the previous filtering result for feedback.

Brief Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0016] Figure 1 A schematic diagram comparing different sampling principles of the IIR filter of the present invention and two existing IIR filters when feeding back previously filtered data;

[0017] Figure 2Schematic diagram of the effects of the IIR filter scheme proposed by the present invention and the two existing IIR filter schemes, where float is the existing scheme of feeding back all decimals in the previous filtered data, Directly Intercept is the existing scheme of intercepting part of the decimals in the previous filtered data for feedback, and Ours is the scheme adopted by the present invention;

[0018] Figure 3 A partial structural diagram of the IIR filter in the present invention;

[0019] Figure 4 FIG. 4 is another partial structural diagram of the IIR filter in the present invention. [Specific implementation method]

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "coupled" and other terms indicating electrical connection should be understood in a broad sense; for example, it can be a direct electrical connection, or it can be indirectly electrically connected through an intermediate medium, and the intermediate medium can be an electronic component, a functional circuit, etc. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0022] The present invention provides an IIR filter, which can not only reduce the amount of calculation and the resource overhead of hardware, but also reduce the offset of the final filtering result caused by intercepting the decimal part of the specific bit width of the previous filtering result for feedback, that is, improve the offset problem, improve the accuracy of the fixed-point operation of the IIR filter, and reduce the average error.

[0023] The IIR filter in the present invention calculates the current filtering result based on N input data and N feedforward coefficients, N-1 feedback coefficients and N-1 previous filtering results fed back, wherein N is the order of the IIR filter, and N is greater than or equal to 2. The integer part and part of the decimals in the previous filtering result are fed back to calculate the current filtering result, the number of bits of the part of the decimals fed back in the previous filtering result is W bits, the value of the last 1 bit of the part of the decimals fed back in the previous filtering result is fixed to 1, and W is a natural number greater than or equal to 1. The number of bits of all decimals of the previous filtering result is greater than W.

[0024] Figure 1 The present invention is a schematic diagram comparing the different sampling principles of the IIR filter and the two existing IIR filters when feeding back the previous filter data. Compared with the existing solution 2, the present invention feeds back one more decimal in the previous filter data, and the value of the last bit is fixed to 1, that is, only a small amount of computing resources is added (an additional "1" is added), which can reduce the offset of the final filter result caused by intercepting the decimal part of the specific bit width of the previous filter result for feedback, improve the accuracy of the IIR filter fixed-point operation, and reduce the average error. Compared with the existing solution 2, the present invention does not feed back all the decimals in the previous filter data, which can reduce the amount of calculation and reduce the resource overhead of hardware. Figure 2 The schematic diagram of the effect of using the IIR filter scheme proposed by the present invention and the two existing IIR filter schemes, where float is the existing scheme of feeding back all decimals in the previous filtered data, Directly Intercept is the existing scheme of intercepting part of the decimals in the previous filtered data for feedback, and Ours is the scheme adopted by the present invention. Although only one more bit of decimal is fed back, and the value of the last bit is fixed to 1, compared with the existing scheme 2, the scheme in the present invention can obviously reduce the offset of the final filtering result caused by intercepting the decimal part of the specific bit width of the previous filtering result for feedback, improve the accuracy of the fixed-point operation of the IIR filter, and reduce the average error.

[0025] In the present invention, the current filtering result output by the IIR filter is:

[0026]

[0027] where b n is the nth feedforward coefficient, a m is the mth feedback coefficient, N is the order of the IIR filter, N is greater than or equal to 2, y k is the current filtering result, i.e., the kth filtering result, x k is the current input data, i.e. the kth input data, x k-n is the current input data x k The previous nth input data, y k-m is the mth filtering result before the current filtering result. m , b n ,y k and x k All are floating point numbers.

[0028] Specific:

[0029]

[0030] in is the signed fixed-point integer of the current filtering result (i.e. the integer part), is the unsigned fixed-point decimal (i.e. the decimal part) of the current filtering result. is the integer part of the mth filter result before the current filter result, is the fractional part of the previous m-th filtering result.

[0031] Figure 3 A partial structural diagram of the IIR filter in the present invention; Figure 4 FIG. 4 is another partial structural diagram of the IIR filter in the present invention.

[0032] like Figure 3 and 4 As shown, the IIR filter includes:

[0033] A first register group 110, used for caching N feed-forward coefficients;

[0034] The second register group 120 is used to receive and shift buffer N input data input in sequence;

[0035] A first multiplication module 130 and a first addition module 140, wherein the first multiplication module 130 performs multiplication operation on each input data in the second register group 120 and the corresponding feedforward coefficient in the first register group 110 to obtain a plurality of feedforward product data, and the first addition module 140 adds the plurality of feedforward product data obtained by the first multiplication module 130 to obtain feedforward cumulative filtering data;

[0036] The third register group 160 is used to cache N-1 feedback coefficients;

[0037] The fourth register group 170 is used to receive and sequentially shift and cache N-1 previous filtering results fed back, wherein only a part of the decimals in each previous filtering result is fed back and cached, and the value of the last 1 bit of the part of the decimals fed back in each previous filtering result is fixed to 1;

[0038] A second multiplication module 180 and a second addition module 190, wherein the second multiplication module 180 multiplies each previous filtering result of the feedback in the fourth register group 170 by the corresponding feedback coefficient in the third register group 180 to obtain a plurality of feedback product data, and the second addition module 190 adds the plurality of feedback product data obtained by the second multiplication module 180 to obtain feedback accumulation filtering data;

[0039] The third adding module (not shown) adds the feedforward accumulated filtering data and the feedback accumulated filtering data to obtain a current filtering result, and feeds back the current filtering result as a previous filtering result to the fourth register group.

[0040] Among them, Figure 3 and 4 In the example, N is 7, and in other examples, N can be other values.

[0041] More specifically, the first register group 110 includes a plurality of first registers 111, each first register 111 being used for one of the N feedforward coefficients;

[0042] The second register group 120 includes a plurality of second registers 121, the plurality of second registers respectively correspond to the plurality of first registers, and the plurality of second registers are sequentially arranged to form a first shift register, the first second register in the first shift register sequentially receives input data, and each time a new input data is received, each second register in the first shift register shifts the input data cached therein to the next second register, the first second register in the first shift register caches the new input data, and the last second register in the second shift register outputs or deletes the input data cached therein,

[0043] The third register group 160 includes a plurality of third registers 161, each third register being used for one of the N-1 feedback coefficients;

[0044] The fourth register group 170 includes multiple fourth registers 171, and the multiple fourth registers correspond to multiple third registers respectively. The multiple fourth registers are arranged in sequence to form a second shift register. The first fourth register in the second shift register receives the feedback of previous filtering results in sequence. Each time a new previous filtering result is received, each fourth register in the second shift register shifts the previous filtering result cached therein to the next fourth register. The first fourth register in the second shift register caches the new previous filtering result, and the last fourth register in the second shift register outputs or deletes the previous filtering result cached therein. The previous filtering result cached in each fourth register has only W decimal places, and the value of the last decimal place is fixed to 1.

[0045] More specifically, the first multiplication module 130 includes a plurality of first multiplication units 131, each of which corresponds to a first register and a second register, and each of which performs a multiplication operation on a feedforward coefficient cached in a corresponding first register and an input data cached in a corresponding second register to obtain a feedforward product data.

[0046] The first adding module 140 includes a plurality of first adding units, wherein the first adding units add a plurality of feedforward product data obtained by each first multiplying unit 131 to obtain feedforward accumulated data;

[0047] The second multiplication module 180 includes a plurality of second multiplication units 181, each of which corresponds to a third register and a fourth register, and each of which performs multiplication operation on the feedback coefficient cached in the corresponding third register and the previous result data cached in the corresponding fourth register to obtain a feedback product data.

[0048] The second adding module 190 includes a plurality of second adding units, and the second adding units add a plurality of feedback product data obtained by the second multiplying units to obtain feedback accumulated data.

[0049] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0050] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify and vary the above embodiments within the scope of the present invention.

Claims

1. An IIR filter, characterized in that: The current filtering result is calculated based on N input data and N feedforward coefficients, N-1 feedback coefficients and N-1 previous filtering results of the feedback, where N is the order of the IIR filter, N is greater than or equal to 2, The integer part and part of the decimal in the previous filtering result are fed back for calculating the current filtering result. The number of bits of the partial decimal fed back in the previous filtering result is W bits, and the value of the last bit of the partial decimal fed back in the previous filtering result is fixed to 1, and W is a natural number greater than or equal to 1.

2. The IIR filter according to claim 1, characterized in that It includes: The first register group is used to cache N feed-forward coefficients; The second register group is used to receive and shift buffer N input data input in sequence; A first multiplication module and a first addition module, wherein the first multiplication module multiplies each input data in the second register group by the corresponding feedforward coefficient in the first register group to obtain a plurality of feedforward product data, and the first addition module adds the plurality of feedforward product data obtained by the first multiplication module to obtain feedforward cumulative filtering data; The third register group is used to cache N-1 feedback coefficients; A fourth register group is used to receive and sequentially shift and cache N-1 previous filtering results fed back, wherein only a part of the decimals in each previous filtering result is fed back and cached, and the value of the last 1 bit of the part of the decimals fed back in each previous filtering result is fixed to 1; a second multiplication module and a second addition module, wherein the second multiplication module multiplies each previous filtering result of the feedback in the fourth register group by the corresponding feedback coefficient in the third register group to obtain a plurality of feedback product data, and the second addition module adds the plurality of feedback product data obtained by the second multiplication module to obtain feedback accumulation filtering data; The third adding module adds the feedforward accumulated filtering data and the feedback accumulated filtering data to obtain a current filtering result, and feeds the current filtering result back to the fourth register group as a previous filtering result.

3. The IIR filter according to claim 2, characterized in that The first register group includes a plurality of first registers, each first register being used for one of the N feedforward coefficients; The second register group includes a plurality of second registers, each of which corresponds to a plurality of first registers. The plurality of second registers are arranged in sequence to form a first shift register. The first second register in the first shift register receives input data in sequence. Each time a new input data is received, each second register in the first shift register shifts the input data cached therein to the next second register. The first second register in the first shift register caches the new input data, and the last second register in the second shift register outputs or deletes the input data cached therein. The third register group includes a plurality of third registers, each third register being used for one of the N-1 feedback coefficients; The fourth register group includes multiple fourth registers, and the multiple fourth registers correspond to multiple third registers respectively. The multiple fourth registers are arranged in sequence to form a second shift register. The first fourth register in the second shift register receives the feedback of previous filtering results in sequence. Each time a new previous filtering result is received, each fourth register in the second shift register shifts the previous filtering result cached therein to the next fourth register. The first fourth register in the second shift register caches the new previous filtering result, and the last fourth register in the second shift register outputs or deletes the previous filtering result cached therein. The previous filtering result cached in each fourth register has only W decimal places, and the value of the last decimal place is fixed to 1.

4. The IIR filter according to claim 3, characterized in that The first multiplication module includes a plurality of first multiplication units, each of which corresponds to a first register and a second register, and each of which performs a multiplication operation on a feedforward coefficient cached in a corresponding first register and input data cached in a corresponding second register to obtain a feedforward product data. The first adding module includes a plurality of first adding units, wherein the first adding units add a plurality of feedforward product data obtained by the first multiplying units to obtain feedforward accumulated data; The second multiplication module includes a plurality of second multiplication units, each of which corresponds to a third register and a fourth register, and each of which multiplies the feedback coefficient cached in the corresponding third register with the previous result data cached in the corresponding fourth register to obtain a feedback product data. The second adding module includes a plurality of second adding units, and the second adding units add a plurality of feedback product data obtained by the second multiplying units to obtain feedback accumulated data.

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