Efficient architecture for long arrival SERDES based on high performance DSP

Abstract

The invention relates to an efficient architecture for long arrival SERDES based on high performance DSP. A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) due to dispersion associated with a long arrival transmission medium. In some embodiments, the SERDES includes a second filter configured to shape the ISI. The SERDES also includes a third filter coupled in parallel with the second filter and configured to reduce ISI due to reflections associated with both near zero delay and long delay.

Description

Technical Field

[0001] This specification generally relates to high-speed serial communication links, and more particularly, to an efficient architecture for a long-reach serializer-deserializer (SERDES) based on high-performance digital signal processing (DSP). Background Art

[0002] A serializer-deserializer (SERDES) based on high-speed digital signal processing (DSP) requires sophisticated algorithms to operate over populated and low-cost channels while maintaining high efficiency to reduce power usage and chip area. This is particularly true for highly integrated large application specific integrated circuits (ASICs). Conventional DSP receivers may have a long feed-forward equalizer (FFE) with many taps (controlled filter coefficients) and a short 1-2 tap decision feedback equalizer (DFE). Practical channels have reflections that require equalization at long delays, which in turn drives an increase in the FFE or DFE length. The input to the FFE typically has attenuated high-frequency content, requiring more active taps to equalize the reflections. These factors increase the power and area of the DSP. The complexity of these circuits results in longer delays to obtain timing-related information (e.g., received symbols and expected values to compare), thus causing a margin loss in highly integrated environments where jitter tolerance is required. Sometimes, a separate shorter FFE is dedicated to the timing recovery path to achieve reasonable but sub-optimal signal quality with lower delay. However, this approach can add redundancy and complexity. For low bit error rate applications, a low-power low-area architecture with reflection cancellation and fast timing recovery while still maintaining noise shaping similar to FFE-DFE is desired.

[0003] For applications with long reach transmission channels, the insertion loss increases, which can cause a loss of performance margin for DSP-based SERDESs that use FFE to shape the signal to reduce inter-symbol interference (ISI). Generally, ISI refers to the situation where signal overlap occurs, causing individual pulses (symbols) to interfere with each other. This interference occurs when the duration of the impulse response of the channel is longer than the symbol period. As a result, the tail of one pulse spills over into the subsequent time slots allocated for other pulses, which can lead to symbol detection errors. On high-loss channels in long reach transmission media, a large amount of ISI must be reduced, which requires more FFE taps, which will increase power and device area. Even with additional taps, the trade-off between ISI and noise results in residual ISI (specifically, those near-zero delay ISI) being left. A DFE can be used to perform ISI cancellation without noise enhancement. Unlike a feed-forward equalizer (FFE) that only uses previously received symbols to form an estimate of the current symbol, a DFE uses both previously received symbols and previous decisions (estimates) about the transmitted symbols. However, the process is limited to post-cursor (or positive delay) ISI. Accordingly, there is a need for an improved high-speed DSP for long reach SERDESs that reduces these residual ISIs without noise enhancement and reduces the hardware cost of the FFE tap count. SUMMARY OF THE INVENTION

[0004] In one aspect, the present disclosure provides an apparatus that includes: a first filter configured to process an input signal to reduce inter-symbol interference (ISI) associated with channel dispersion through a long reach transmission medium; a second filter serially coupled to the first filter and configured to modify the shape of the ISI; and a third filter coupled in parallel with the second filter and configured to cancel the ISI associated with both long delay reflections and near-zero delay reflections.

[0005] In another aspect, the present disclosure provides a system that includes: an analog-to-digital converter (ADC) configured to provide a digital signal converted from an analog signal transmitted through a transmission medium; a first filter configured to reduce inter-symbol interference (ISI) of the digital signal associated with dispersion in the transmission medium; a second filter configured to modify the spectral shape of the ISI; and a third filter configured to cancel the ISI associated with reflections at various time points in the transmission medium; wherein the transmission medium includes a long reach transmission medium, and the second filter is implemented in a serializer-deserializer SERDES together with the first filter and in parallel with the third filter.

[0006] In another aspect, the present disclosure provides a receiver that includes: a feed-forward equalizer (FFE) configured to equalize signal dispersion associated with a transmission medium; a filter configured to reduce both long-delay reflections and near-zero-delay reflections attributed to inter-symbol interference (ISI) in the transmission medium; a partial response finite impulse response (PRFIR) filter configured to add controlled ISI based on a transfer function; and an interpolator coupled to the FFE and configured to output a phase adjustment signal to the PRFIR filter, wherein the transmission medium includes a serializer-deserializer (SERDES) long reach transmission medium. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A further understanding of the nature and advantages of particular embodiments may be realized by reference to the remaining portions of the specification and drawings, wherein like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to denote one of a plurality of like components. When a reference numeral is referred to without stating an existing sub-label, it is intended to refer to all such plurality of like components.

[0008] Figure 1 is a block diagram illustrating an example of a serializer-deserializer (SERDES) link implementing high performance digital signal processing (DSP) of the present technology.

[0009] Figure 2 is a block diagram illustrating an example of a high performance DSP system according to various aspects of the present technology.

[0010] Figure 3 is a block diagram illustrating an example of a high performance DSP system according to various aspects of the present technology.

[0011] Figure 4 is a block diagram illustrating an example of a high performance DSP system according to various aspects of the present technology.

[0012] Figure 5 is a block diagram illustrating an example of a high performance DSP-based long reach SERDES according to various aspects of the present technology.

[0013] Figure 6 is an electronic system in which some aspects of the present technology are implemented. DETAILED DESCRIPTION

[0014] The following detailed description is intended to be illustrative of various configurations of the technology and is not intended to represent the only configurations in which the technology may be practiced. The accompanying drawings are incorporated herein and constitute a part of the detailed description, which include specific details for a thorough understanding of the technology. However, the technology is not limited to the specific details set forth herein and may be practiced without those specific details. In some instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the technology.

[0015] The following description is presented to enable a person skilled in the art to make and use the invention and to incorporate it in the context of a particular application. Various modifications and the various uses in different applications will be apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0016] In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the practice of the invention may not necessarily be limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form (rather than in detail) to avoid obscuring the description.

[0017] The reader is cautioned to note all papers and documents that are filed concurrently with this specification and that are open to public inspection with this specification, and the contents of all such papers and documents are hereby incorporated by reference into this text. Unless specifically stated otherwise, all features disclosed in this specification (including any appended claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose. Thus, unless specifically stated otherwise, each disclosed feature is only an example of a generic series of equivalent or similar features.

[0018] Furthermore, any element in a claim of the technology that does not explicitly state "means for" performing a specific function, or "step for" performing a specific function, is not to be construed as a "means" or "step" clause as in paragraph 6 of section 112 of title 35, United States Code. In particular, the use of "step of" or "act of" in the claims herein is not intended to invoke the provisions of paragraph 6 of section 112 of title 35, United States Code.

[0019] When an element is referred to herein as being "connected" or "coupled" to another element (including but not limited to electrical or communication connection or coupling), it will be understood that the element can be directly connected to the other element, or there can be intermediate elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it should be understood that there are no intermediate elements in the "direct" connection between the elements. However, the existence of a direct connection does not exclude other connections in which intermediate elements may be present.

[0020] When an element is referred to herein as being "disposed" relative to another element in some manner (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it will be understood that the element can be directly disposed relative to the other element (e.g., directly disposed on the other element), or there can be intermediate elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it should be understood that there are no intermediate elements in the "direct" instance. However, the existence of a direct disposition does not exclude other instances in which intermediate elements may be present.

[0021] Similarly, when an element is referred to herein as being "joined" to another element, it will be understood that the element can be directly joined to the other element (without any intermediate elements) or there can be intermediate elements between the joined elements. In contrast, when an element is referred to as being "directly joined" to another element, it should be understood that there are no intermediate elements in the "direct" joining between the elements. However, the existence of a direct joining does not exclude other forms of joining in which intermediate elements may be present.

[0022] Likewise, when an element is referred to herein as a "layer", it will be understood that the layer can be a single layer or can include multiple layers. For example, a conductive layer can include multiple different conductive materials or multiple different conductive material layers, and a dielectric layer can include multiple dielectric materials or multiple dielectric material layers. When a layer is described as being coupled or connected to another layer, it will be understood that the coupled or connected layers can include intermediate elements that are present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it should be understood that there are no intermediate elements between the layers. However, the existence of directly coupled or connected layers does not exclude other connections in which intermediate elements may be present.

[0023] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are for explanatory purposes only and are not limited to any fixed direction or orientation. Rather, these terms are only used to indicate the relative position and / or orientation between various parts of an object and / or component.

[0024] In addition, the methods and processes described herein may be described in a particular order for ease of illustration. However, it should be understood that unless otherwise specified, intermediate processes may occur before and / or after any part of the described processes, and various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0025] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and unless otherwise indicated, the use of "and" and "or" means "and / or". In addition, the use of the terms "including" and "having" and other forms, such as "includes", "included", "has", "have", "had", should be regarded as non-exclusive. In addition, unless otherwise specifically stated, terms such as "element" or "component" cover both elements and components that include a single unit and elements and components that include more than one unit.

[0026] As used herein, the phrase "at least one of" before a list of items (where the terms "and" or "or" separate any of the items in the list) modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each of the listed items; rather, the phrase allows the meaning of including at least one of any of the items and / or at least one of any combination of the items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In examples where it is intended to select "at least one of each of A, B, and C" or alternatively "at least one of A, at least one of B, and at least one of C", it will be described explicitly as such.

[0027] The present technology is directed to an efficient architecture for a serializer-deserializer (SERDES) based on high-performance digital signal processing (DSP). The disclosed technology provides a low-power, low-area architecture for low bit error rate (BER) applications that has reflection cancellation and fast timing recovery while maintaining the noise shaping of a similar feed-forward equalizer (FFE) and decision feedback equalizer (DFE). Instead of a single-stage FFE, the disclosed solution implements the FFE as a cascaded combination of three filters and an optional interpolator. In some embodiments, the three filters include a receive (RX)-FFE filter, a reflection canceller (RC) finite impulse response (FIR) filter, and a noise shaping partial response (PR) FIR filter.

[0028] A short RX-FFE filter implemented at low latency targets the unit tap equalization response. The equalization response has less dynamic range across the channel and allows for more aggressive bit-width reduction in downstream stages. The short RX-FFE filter output is provided for timing recovery and can be easily sliced to the expected value of the symbol, and provides low latency timing error for clock and delay recovery (CDR) without implementing the delays of long FFE or DFE. The output is also quantized and used as input to a floating tap structure to cancel reflections. This signal has been equalized by the RX-FFE, resulting in fewer active taps to cancel reflections. The quantized input has a narrow bit-width, resulting in low-cost delay lines and trivial multipliers, leading to low total power and chip area. To obtain the benefits of noise shaping, the RX FFE output is conveyed through a noise shaping filter and a DFE filter to trim inter-symbol interference (ISI). To obtain even faster timing recovery, an interpolator can be inserted at the FFE output. The interpolator operates on a well-equalized input, resulting in a cost savings in the bit resolution of the associated multipliers while still maintaining all other capabilities.

[0029] A serializer-deserializer (commonly known as SERDES) is a key component in high-speed digital communication systems and computing. It plays a crucial role in facilitating the transfer of data between chips or devices, especially where high data rates and efficiency are essential. The serializer in SERDES takes a parallel data stream (where multiple bits are transmitted simultaneously over different channels) and converts it into a single high-speed serial data stream. This process not only involves combining the data streams but typically also includes encoding and adding clock information to ensure that the receiver can correctly recover the original data. Conversely, the deserializer performs the opposite function. The deserializer takes a high-speed serial data stream and converts it back into a parallel data stream. This process includes clock recovery, decoding, and aligning the incoming data to ensure that it matches the original transmitted parallel data. A general aspect includes a serializer-deserializer (SERDES)-based apparatus for processing a serial data stream in a high-speed data communication system. The apparatus also includes a first filter configured to process an input signal to reduce inter-symbol interference (ISI) associated with channel dispersion through a long reach transmission medium. The apparatus also includes a second filter serially coupled to the first filter and configured to shape the ISI. The apparatus also includes a third filter coupled in parallel with the second filter and configured to cancel the ISI associated with both long-delay reflections and near-zero-delay reflections. Other embodiments of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0030] Embodiments may include one or more of the following features. The apparatus, wherein the first filter may include a feedforward equalizer configured to include a calibration circuit to calibrate a timing offset of an input signal received from an analog-to-digital converter (ADC) to provide a first intermediate signal for a serializer-deserializer (SERDES). The second filter may include a partial response finite impulse response (PRFIR) filter configured to introduce controlled ISI based on a transfer function that includes at least one term associated with a sum and a positive delay added corresponding to a negative delay implemented in a third filter. The apparatus may include an interpolator configured to adjust a phase of the first intermediate signal output from the first filter to output a second intermediate signal based on a phase adjustment signal. The apparatus may include a phase detector configured to detect a phase angle of the second intermediate signal from the interpolator and a loop filter configured to generate the phase adjustment signal. The third filter may include a quantizer and a reflection cancellation finite impulse response (RCFIR) filter serially coupled to the quantizer, and the third filter is coupled in parallel to the interpolator and the first filter with the PRFIR filter. The RCFIR filter is configured to use a plurality of floating taps located from a near-zero negative delay timing point to a positive delay timing point including a long delay timing point to cancel reflections. The apparatus may include a fourth filter coupled in parallel with the RCFIR filter and configured to remove residual ISI attributed to analog noise. The apparatus may include a delay matching circuit coupled to the PRFIR filter and followed by an adder, the delay matching circuit configured to enable reduction of negative delay ISI performed in the RCFIR filter, and the adder configured to combine a positive output of the second filter with corresponding negative outputs of the third and fourth filters and generate an output signal. The apparatus may include a fifth filter coupled to the adder, the fifth filter may include a decision feedback equalizer (DFE) configured to process the output signal to remove the controlled ISI added by the second filter. Embodiments of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.

[0031] Another general aspect includes a system for a long-reach SERDES based on a high-performance DSP. The system also includes an analog-to-digital converter (ADC) configured to provide a digital signal converted from an analog signal transmitted through a transmission medium. The system also includes a first filter configured to reduce inter-symbol interference (ISI) associated with dispersion in the transmission medium in the digital signal. The system also includes a second filter configured to alter the spectral shape of the ISI. The system also includes a third filter configured to eliminate ISI associated with reflections at various timing points in the transmission medium. The system also includes, where the transmission medium may include a long-reach transmission medium, and the second filter is implemented in a serializer-deserializer (SERDES) together with the first filter and in parallel with the third filter.

[0032] Embodiments may include one or more of the following features. The system, where the first filter may include a feed-forward equalizer (FFE) having offset calibration to provide a first intermediate signal with equalized dispersion. The second filter may include a partial response finite impulse response (PRFIR) filter configured to introduce a controlled ISI based on a transfer function and add the controlled ISI to the first intermediate signal. The third filter may include a quantizer serially coupled to a reflection cancellation finite impulse response (RCFIR) filter. The RCFIR filter is configured to reduce reflections using a plurality of floating taps located from a near-zero negative delay time point to a positive delay time point including a long delay time point, where the taps associated with negative delays in the RCFIR filter are modeled by modifying the taps with longer delays in the PRFIR filter. The system may include a fourth filter coupled in parallel with the third filter and configured to reduce residual ISI attributed to long-tailed analog noise. The system may further include a delay matching circuit adder coupled to the PRFIR filter and followed by an adder, the delay matching circuit configured to provide a controlled positive delay ISI through the PRFIR filter to enable reduction of the negative delay ISI performed in the RCFIR filter, the system may include a decision feedback equalizer to remove the controlled ISI added by the PRFIR filter. Embodiments of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.

[0033] Another general aspect includes a serializer-deserializer (SERDES) receiver. The receiver also includes a feed-forward equalizer (FFE) configured to equalize signal dispersion associated with a transmission medium. The receiver also includes a filter configured to reduce both long-delay reflections and near-zero-delay reflections attributed to inter-symbol interference (ISI) in the transmission medium. The receiver also includes a partial response finite impulse response (PRFIR) filter configured to add controlled ISI based on a transfer function. The receiver also includes an interpolator coupled to the FFE and configured to output a phase adjustment signal to the PRFIR filter, where the transmission medium can include a serializer-deserializer (SERDES) long reach transmission medium.

[0034] Embodiments can include one or more of the following features. The receiver, where the filter can include a quantizer and a reflection cancellation finite impulse response (RCFIR) filter coupled in series, the filter being coupled in parallel with the PRFIR filter, where the transfer function includes a contribution from added positive-delay ISI that corresponds to negative-delay ISI processed by the RCFIR filter. The receiver can include an adder coupled to the PRFIR filter and the RCFIR filter and a decision feedback equalizer (DFE) coupled to the adder, the adder being configured to process outputs from both the PRFIR filter and the RCFIR filter, the DFE being configured to remove the controlled ISI added by the PRFIR filter. Embodiments of the described techniques can include hardware, a method or process, or computer software on a computer-accessible medium.

[0035] Figure 1 is a block diagram illustrating an example of a SERDES link 100 of a high-performance DSP in which the present technique is implemented. The SERDES link 100 includes a transmitter device 110, a transmission medium 115, and a receiver device 120. The transmitter device 110 includes a transmit (TX) data source 112 and a transmitter circuit 114. The TX data source provides data (e.g., electrical data or optical data) to be transmitted to the receiver device 120. The transmitter circuit 114 includes digital-to-analog circuitry adapted to process the data, e.g., amplifying and noise canceling to prepare the data for transmission over the transmission medium 115. In some embodiments, the transmitter circuit 114 can also include electro-optic circuitry. The transmission medium 115 can be an optical transmission medium consisting of an optical cable and optical components or an electrical transmission medium consisting of twisted pair or coaxial cable and associated circuitry.

[0036] The receiver device 120 includes an analog front end (AFE) circuit 122, an analog-to-digital converter (ADC) circuit 124, a receiver (RX) DSP block 126, and an RX data processing block 128. The AFE circuit 122 may include a low-noise amplifier, a filter, and a variable gain amplifier, and is responsible for amplifying and noise-reducing the analog signal received from the transmission medium 115. The ADC circuit 124 converts the analog output signal of the AFE circuit 122 into a digital signal, which can be processed by the RX DSP block 126. The RX DSP block 126 includes a clock and data recovery (CDR) circuit for synchronizing with a digital data stream that may have timing variations and extracting a clean clock signal from the digital data stream. The last stage is the RX data processing block 128, which further processes the output data from the RX DSP block 126 to recover the original data for presentation on an output device, e.g., for display on a display device. In some embodiments, the SERDES link 100 may include an optional forward error correction (FEC) block (not shown for simplicity), which may be implemented in the transmitter device 110 (e.g., in the TX data source 112) or the receiver device 120 (e.g., the RX data processing block 128). The SERDES link 100 shows TX and RX only in one direction. A similar link may be used in the opposite direction. The RX DSP block 126 is the basis of the receiver device 120, and the present technology provides an efficient implementation architecture for it as discussed herein.

[0037] Figure 2 is a block diagram illustrating an example of a high-performance DSP system 200 according to various aspects of the present technology. The high-performance DSP system 200 includes a DSP device 220, an ADC 210, and an ADC clock controller 212. The ADC 210 is similar to Figure 1 the ADC circuit 124 and can receive analog data 202 from an AFE circuit (e.g., Figure 1 122) and convert it into digital data for processing by the DSP system 200. The ADC clock controller 212 provides and controls the clock signal for the ADC 210.

[0038] The DSP device 220 includes an ADC calibration circuit 222, an FFE circuit 224, an interpolator 226, a phase detector (PD) 228, a CDR circuit 230, and an RX FFE circuit 232, a delay matching circuit 234, a reflection canceller 236, a summing (or adder) circuit 238, and a DFE circuit 240. In some embodiments, some components of the DSP device 220 may be implemented in software and / or firmware. The ADC calibration circuit 222 may be a gain skew calibration circuit and is responsible for calibrating the timing offset (skew) and gain errors of the ADC 210. The FFE circuit 224 is used to cancel the effects associated with the transmission medium (e.g., Figure 1The associated channel is dispersed and may include an equalizer with offset calibration. Channel dispersion in telecommunications and signal processing refers to the phenomenon in which different frequency components of a signal arrive at the receiver at different times. The causes of channel dispersion can include different modes of the transmission medium, material-dependent dispersion, different polarization states, and phase velocity variations in the transmission medium. The frequency components of the signal undergo this time spreading as it travels through the channel, and this can cause significant problems in information transmission, especially at high data rates over long distances. The FFE circuit 224 can be implemented as a symbol-spaced FIR filter to reduce distortion caused by, for example, channel loss impairment. In some aspects, the FFE circuit 224 can be implemented using a multi-tap filter that forms a certain number of delayed versions of the input signal, and the delayed versions are added back to the signal with appropriate weights. In some embodiments, the FFE circuit 224 can include offset calibration for calibrating the timing or voltage offset of the digital signal received from the ADC calibration circuit 222. The PD 228 can detect the phase angle of the interpolator output signal and provide it to the CDR circuit 230. The CDR circuit 230 can include a loop filter and control logic and generate an interpolator phase adjustment signal 231 and a control signal 233 used by the ADC clock controller 212.

[0039] The output of the interpolator 226 includes the original signal transmitted by the transmitter device (e.g., Figure 1 of 110) plus the edge reflection effect caused by the transmission medium (e.g., Figure 1 of 115), and is ready for the next stage (including the RX-FFE 232 and the reflection canceller 236) to cancel the edge reflection effect. The RX-FFE 232 is a short equalizer implemented with low latency and can target partial response that requires noise shaping. The RX-FFE 232 includes a noise shaping filter that can change the spectral shape of the signal and can be characterized by a polynomial transfer function similar to l+αD+βD 2 where D is the delay or latency variable and α and β are the parameters of the transfer function. The value of α is typically between 0 and 1 to implement a low-pass filter to reduce noise. The reflection canceller 236 consists of a quantizer (Q) and a subsequent FIR filter with a floating tap structure (also known as a Q-FIR filter). The quantized input to the FIR has a narrow bit width, resulting in a low-cost delay line and a simple multiplier, leading to low total power consumption and chip area. In other words, using a Q filter in front of the FIR filter allows the use of an FIR with a lower number of bits, and the possible outputs for different values of Q bits (2, 3, and 4) are given in Table 250. The reflection canceller 236 can effectively cancel the effects of channel impairment, e.g., cancel the Figure 1115) Reflection signals that may occur when transmitting signals. The output signal from the RX-FFE 232 is delayed by the delay matching circuit 234 and combined with the signal output of the reflection canceller 236 by the summing circuit 238 for timing recovery. The delay matching circuit 234 resolves the difference between the processing delays of the Q / FIR 236 and the RX-FFE 232 path, so that the output of the summing circuit 238 is correct. The output signal from the summing circuit 238 is conveyed to the DFE circuit 240, which is a noise shaping filter for suppressing quantization noise. The DFE circuit 240 subtracts the term αD + βD introduced by the RX-FFE using an estimate of the transmitted symbol derived from the signal at its input. 2 . In this way, the noise shaping benefit of the RX-FFE is achieved without compromising the inter-symbol interference (ISI) introduced by it. The DSP output signal 242 is a signal that has cancelled the channel dispersion and reflection effects. The DSP output signal is sent to the RX data processing circuit (e.g., Figure 1 128) to recover the original data transmitted by the transmitter device (e.g., Figure 1 110).

[0040] Figure 3 is a block diagram illustrating an example of a high-performance DSP device 300 according to various aspects of the present technology. The DSP device 300 includes an ADC calibration circuit 310 and an FFE circuit 320, a PD 322, a delay matching circuit 330, a reflection canceller 334, a summing circuit 332, an RX-FFE 336, an interpolator 338, and a DFE circuit 340. In some embodiments, some components of the DSP device 300 may be implemented in software and / or firmware. The ADC calibration circuit 310 may be a gain skew calibration circuit and is responsible for calibrating the timing offset and gain error of the ADC 210. The FFE circuit 320 is a passive equalizer for cancelling channel dispersion and includes offset calibration. The FFE circuit 320 may be implemented as a symbol-interval FIR filter to reduce distortion caused by, for example, channel loss degradation. In some aspects, the FFE circuit 320 may be implemented using a multi-tap filter that forms a certain number of delayed versions of the input signal, which are added back to the input signal with appropriate weights. In some embodiments, the FFE circuit 320 may include offset calibration for calibrating the timing offset of the digital signal received from the ADC calibration circuit 310. The PD 322 may detect a phase angle signal 324 associated with the output signal from the FFE circuit 320. The phase angle signal 324 may be provided to a CDR circuit (e.g., Figure 2 230).

[0041] The output of the FFE 320 includes that transmitted by the transmitter device (e.g., Figure 1the original signal transmitted by the transmitter device (e.g., Figure 1 plus the edge reflection effect caused by the transmission medium (e.g., Figure 2 which has been eliminated. The reflection canceller 334 consists of a Q filter followed by a FIR filter with a floating tap structure and is similar to Figure 2 the reflection canceller 236. The quantized input to the FIR filter has a narrow bit width, resulting in a low-cost delay line and a simple multiplier, leading to low total power and chip area. In other words, using a Q filter in front of the FIR filter (also known as a Q-FIR filter) allows the use of a FIR with a lower number of bits, and the possible outputs for different values of Q bits (2, 3, and 4) are given in Table 350. The delay matching 330 addresses the processing delay of the reflection canceller 334 such that the output of the summing circuit 332 is correct. Through the summing circuit 332, the output of the delay matching circuit 330 is combined with the output of the reflection canceller 334. The output signal from the summing circuit 332 is conveyed into the RX-FFE 336, which is similar to 2 the RX-FFE 232 discussed above. For example, the RX-FFE 336 similarly includes a noise shaping filter, which can change the spectral shape of the signal and can be characterized by a polynomial transfer function: 1 + αD + βD Figure 2 where D is the delay or delay variable and α and β are the parameters of the transfer function. The value of α is typically between 0 and 1 to implement a low-pass filter to reduce noise. The output of the RX-FFE 336 is conveyed to the interpolator 338, which can help achieve faster timing recovery. The interpolator 338 can use a phase adjustment signal 335, which is provided, for example, by a CDR circuit (e.g., Figure 2 the 230) discussed above. The output of the interpolator 338 is sent to the DFE circuit 340, which is a noise shaping filter for suppressing quantization noise and has a similar transfer function to Figure 1 the DFE circuit 240 discussed above. The output of the DSP device 300 is a signal with channel dispersion and reflection effects eliminated and is sent to the RX data processing circuit (e.g., Figure 1 the 128) to recover the original data transmitted by the transmitter device (e.g.,

[0042] Figure 4 the 110).is a block diagram illustrating an example of a high-performance DSP according to various aspects of the present technology. The DSP device 400 includes an ADC calibration circuit 410 and an FFE circuit 420, a PD 422, a number of (e.g., three) echo canceller stages 430 (430-1, 430-2, and 430-3), an RX-FFE circuit 436, an interpolator 438, and a DFE circuit 440. In some embodiments, some components of the DSP device 400 may be implemented in software and / or firmware. The ADC calibration circuit 410 may be a gain skew calibration circuit and is responsible for calibrating the timing offset and gain error of the ADC (e.g., Figure 2 of 210). The FFE circuit 420 is a passive equalizer for canceling channel dispersion and may include offset calibration. The FFE circuit 420 may be implemented as a symbol-spaced FIR filter to reduce distortion caused by, for example, channel loss impairment. In some aspects, the FFE circuit 420 may be implemented using a multi-tap filter that forms a number of delayed versions of the input signal, and the delayed versions are added back to the signal with appropriate weights. In some embodiments, the FFE circuit 420 may include offset calibration for calibrating the timing offset of the digital signal received from the ADC calibration circuit 410. The PD 422 may detect a phase angle signal 424 associated with the output signal from the FFE circuit 420. The phase angle signal 424 may be provided to a CDR circuit (e.g., Figure 2 of 230).

[0043] The output of the FFE circuit 420 includes the original signal transmitted by a transmitter device (e.g., Figure 1 of 110) plus the edge reflection effects caused by the transmission medium (e.g., Figure 1 of 115) that have been canceled. The echo canceller stages 430 may cancel the edge reflection effects. Each of the echo canceller stages 430 consists of a Q-FIR filter 432, a delay match 433, and a summing circuit 434, as described above with respect to Figure 2As discussed. The delay matching 433 resolves the delay of the Q / FIR filter 432 such that the output of the echo canceller stage 430 is correct. The purpose of using multiple echo canceller stages 430 is to provide an implementation of an iterative echo cancellation algorithm. Generally speaking, the output of the first Q / FIR filter 432 is a coarser estimate of the echo, and this output is used as the input to the second Q / FIR stage. The estimate of the echo from the second Q / FIR is expected to be a better estimate (better performance) of the echo, and so on. There will be a point beyond which the estimate does not get better or "converges". Three stages are shown as a balance between the quality of the estimate of the echo and the complexity of the echo canceller stage 430. More or fewer stages are possible. The output signal from the echo canceller stage 430 is conveyed into the RX-FFE circuit 436, which is similar to the Figure 2 RX-FFE 232 discussed above. For example, the RX-FFE circuit 436 similarly includes a noise shaping filter, which can change the spectral shape of the signal and can be characterized by the polynomial transfer function: l + αD + βD 2 where D is a delay or latency variable and α and β are parameters of the transfer function. The value of α is typically between 0 and 1 to implement a low pass filter to reduce noise. The output of the RX-FFE circuit 436 is conveyed to an interpolator 438, which can help achieve faster timing recovery. The interpolator 438 can use a phase adjustment signal 435, which is provided, for example, by a CDR circuit (such as Figure 2 the 230 discussed above). The output of the interpolator 438 is sent to a DFE circuit 440, which is a noise shaping filter for suppressing quantization noise and has a similar transfer function to the Figure 2 DFE circuit 240 discussed above. The output of the DSP device 400 is a signal with the channel dispersion and echo effects removed, and this signal is sent to the RX data processing circuit (such as Figure 1 the 128 discussed above) to recover the original data transmitted by the transmitter device (such as Figure 1 the 110 discussed above).

[0044] Figure 5It is a block diagram illustrating an example of a high-performance DSP-based long-reach SERDES 600 according to various aspects of the present technology. The high-performance DSP-based long-reach SERDES 600 is configured as a digital signal processor (DSP) that processes digital signals converted from an analog interface 610 via a long-reach transmission medium. For example, the transmission medium includes solid materials such as optical fibers or coaxial cables and free space such as radio links in various frequency bands. A long-reach transmission medium refers to a medium that can carry signals over a relatively long distance without substantial loss of integrity or data. In telecommunications and networking, "long reach" is generally contrasted with "short reach" or "proximal" media that are designed for shorter, often local distances. Using an optical fiber used in long-distance telecommunications networks and undersea cable systems as an example, long reach means enabling signal transmission over distances of tens to hundreds of kilometers. For satellite communications, signals can be relayed via satellites in geostationary orbits or other orbits, enabling signal transmission over continental or intercontinental distances. The DSP includes an FFE filter 624, an interpolator 626, a CDR circuit 630, a partial response FIR (PRFIR) filter 632, a delay matching circuit 633, a quantizer 635, a reflection cancellation FIR (RCFIR) filter 636, a tail cancellation FIR (TCFIR) filter 637, an adder 638, and a DFE filter 646. In some embodiments, some components of the DSP may be implemented in software and / or firmware.

[0045] and Figure 2Similar to the FFE circuit 224 in [reference], the FFE filter 624 is an equalizer used to cancel inter-symbol interference (ISI) in the input signal 621 (a sampled digital signal converted by the ADC from an analog signal from the analog interface 610) caused by channel dispersion associated with a long-reach transmission medium. In an embodiment, the FFE filter 624 is configured to be a symbol-spaced filter to reduce distortion caused by channel dispersion associated with the transmission medium. The FFE filter 624 can be implemented as a multi-tap filter, where each tap refers to a filter coefficient for compensating the channel response at different time points to form a certain number of delayed versions of the input signal 621, and the delayed versions are added back to the signal with appropriate weights. An adaptive scheme (e.g., using the least mean square (LMS) algorithm) is used to continuously adjust the coefficients during operation. For example, the FFE filter 624 uses 12 taps that are added to the input digital signal, e.g., by convolving the input signal 621 with a predetermined filter response defined by the coefficients of the 12 taps to mitigate the ISI associated with the transmission medium. For a long-reach transmission medium, the channel insertion loss becomes much larger, resulting in a large amount of ISI, which requires more FFE taps. However, for a high-speed communication system, adding taps means faster hardware, more stringent synchronization requirements, and more complex adaptive processing. In an embodiment, the number of taps in the FFE filter 624 remains the same, and an alternative approach is used to provide efficient digital signal processing and a cost-effective solution to reduce the performance loss caused in the long-reach SERDES 600. In some embodiments, the FFE filter 624 can be implemented using a calibration circuit to calibrate the timing or voltage offset of the input signal 621 to generate a first intermediate signal, which is a dispersion equalization signal for the downstream of the long-reach SERDES 600.

[0046] The DSP-based SERDES 600 may further include an interpolator 626 that is used to adjust the phase of the sampling clock of the first intermediate signal in very fine increments using a phase adjustment signal 631 to generate a second intermediate signal. The interpolator 626 helps to obtain a faster timing recovery loop. Since the first intermediate signal is a well-balanced input to the interpolator 626, it results in a cost savings in the bit resolution of the associated multiplier while still maintaining all other capabilities. In the timing recovery loop, the CDR circuit 630 may employ a phase detector (PD) to detect the phase angle of the second intermediate signal, i.e., the output signal of the interpolator. The CDR circuit 630 may further include a loop filter (LF) and predetermined control logic for generating the phase adjustment signal 231 of the interpolator 626. The phase adjustment signal 631 is used to insert intermediate samples between the original samples according to a specific interpolation method to increase the sampling rate. The CDR circuit 630 may also generate an analog control signal 622 via a clock controller that is used to control the ADC to convert the analog signal from the analog interface 610.

[0047] After the timing recovery process by the CDR circuit 630, the output of the interpolator 626 contains the original signal transmitted by the transmitter device (e.g., Figure 1 110), where the channel dispersion effect is mitigated by the FFE filter 624 and the channel reflection effect caused by the transmission medium (e.g., Figure 1 115) is retained. The next stage of the DSP-based SERDES includes a partial response FIR (PRFIR) filter 632 and a reflection cancellation FIR (RCFIR) filter 636, configured to cancel the channel reflection effect. The PRFIR filter 632 is serially coupled to the FFE filter 624 via the interpolator 626. A partial response finite impulse response (PRFIR) filter is a specialized type of FIR filter that is mainly used in digital communication systems to shape the transmitted signal and facilitate more efficient signal detection at the receiver. The concept of "partial response" in this context refers to the principle that, based on some form of ISI, it may make it easier to detect and decode the signal in certain cases by intentionally introducing controlled intersymbol interference (ISI) in the transmitted signal. In an embodiment, the PRFIR filter 632 is implemented as a noise shaping filter at low latency and may target the partial response to be noise shaped, e.g., reshaping the filter spectral response or more generally changing the spectral shape of the intersymbol interference (ISI). The PRFIR filter intentionally introduces a known or controlled ISI pattern so that the entire system (the transmitter and receiver together) can more effectively handle the signal degradation caused by the long-reach transmission medium. In a particular embodiment, the PRFIR filter 632 is configured to change the spectral shape by modifying the signal transfer function. For example, it may be achieved by introducing something similar to l + αD + βD2 The characterized polynomial transfer function is used to introduce controlled ISI to change the shape of the inter-symbol interference, where D is a delay or latency variable and α and β are parameters of the transfer function. The value of α is typically between 0 and 1 and is used to implement a low-pass filter to reduce the noise attributed to ISI. Therefore, using the reshaped signal spectrum, the channel energy of most signals in the frequency band can be placed where the noise or interference is minimal. Through these processing schemes, the PRFIR filter 632 can be designed to intentionally introduce controlled ISI through terms in the transfer function (e.g., αD + βD 2 ). When combined with an appropriate detection technique (e.g., maximum likelihood sequence estimation), the entire SERDES system can achieve better performance than without controlled ISI.

[0048] In an embodiment of the present technology, to efficiently mitigate the ISI associated with channel reflections, an RCFIR path is provided to be coupled in parallel to the PRFIR filter 632. The RCFIR path includes a quantizer 635 serially coupled in front of the RCFIR filter 636. The RCFIR filter 636 is configured to eliminate or minimize reflections or echoes at various time points, including both long-delay reflections and near-zero reflections attributed to impedance mismatches or discontinuities in the transmission channel. The quantizer 635 provides an algorithm for mapping a continuous or large set of values into a finite range, such that a large-scale digital signal is quantized using a finite number of discrete values. By placing the quantizer 635 in front of the RCFIR filter 636, the quantized input is provided to the RCFIR filter 635, which has a narrow bit width, resulting in a low-cost delay line and a simple multiplier, leading to low total power consumption and chip area. In other words, the RCFIR filter 635 can use a lower number of bits. For example, when using PAM4 signal modulation, the output of the quantizer 635 can be 2 bits, with possible values of 3, 1, -1, -3; or when using the NRZ modulation mode, the Q bit can be 1 bit, with values of 1, -1.

[0049] In an embodiment, the RCFIR filter 636 is configured to have a floating tap structure in which each tap coefficient can be dynamically positioned or allocated depending on specific requirements. By optimizing tap selection, the RCFIR filter 636 can effectively eliminate the effects of channel impairments, such as reflected signals that may occur when transmitting a signal along a transmission medium. For long reach transmission media, the insertion loss becomes much larger, and adding taps in the RCFIR filter 636 can avoid the power and area increases associated with taps in the FFE filter 624. Generally, the taps in an RCFIR filter can cover and be associated with a larger delay corresponding to a later time of the echo from an impedance discontinuity. These reflections (which can be classified as long delay and near-zero delay reflections) interact with the original signal in different ways, resulting in various forms of ISI. Long delay reflections have a substantial delay relative to the original signal (often amounting to several symbol durations), typically caused by impedance mismatches in the transmission medium located far from the transmitter or receiver (e.g., cables in a wired network or atmospheric conditions in a wireless network). This delay means that the reflected signal can interfere not only with the immediately following symbol but also with several subsequent symbols, causing the signal to trail over time. In the present disclosure, unlike existing filters having taps for eliminating most long delay reflections, additional taps are added to specifically extend the RCFIR filter 636 to eliminate reflections or echoes attributable to shorter delays having ISI. Shorter delay reflections are echoes received at an earlier time or near the main pulse. Shorter delay reflections are also referred to as near-zero delay reflections. Near-zero delay reflections are caused by impedance mismatches near the transmitter or receiver. These near-zero delay reflections can be caused by imperfect connections, sudden changes in transmission line characteristics, or other factors that cause a portion of the signal to be reflected almost immediately. These near-zero delay reflections cause more signal distortion than the trailing phenomenon experienced by long delay reflections. These can cause constructive or destructive interference, resulting in signal amplitude and phase variations.

[0050] In some embodiments, the RCFIR filter 636 is configured to reduce reflections at various time points using a plurality of floating taps located from near-zero negative delay time points to positive delay time points including long delay time points. Near-zero delay includes both positive and negative delays. Negative delay ISI is also referred to as "precursor ISI", the symbol at a time point before the main signal pulse. Effectively, the taps associated with the negative delay in the RCFIR path can be modeled by modifying the taps with longer delay times in the PRFIR path. In some embodiments, the output from the RCFIR filter 636 for such negative delay is achieved by adding (positive) delay in other paths (e.g., the PRFIR filter). For example, the RCFIR filter 636 includes 20 floating taps for handling 40 input multiplexed lines. The taps start from delay -7, where the negative delay represents the symbol at a position 7 unit intervals before the main pulse, and the maximum reach is at the farthest symbol position at 152 after the main pulse. In some embodiments, the PRFIR path includes a delay matching circuit 633 subsequent to the PRFIR filter 632. The delay matching circuit 633 resolves the difference in processing delays between the RCFIR path and the PRFIR path such that the outputs of the PRFIR filter 632 and the RCFIR filter 636 can be correctly combined in timing. In Figure 5 the embodiment shown in, the delay matching circuit 633 is configured to achieve precursor ISI cancellation by including terms attributable to the added positive delay in the transfer function in the PRFIR path, where the added positive delay term corresponds to the negative delay implemented in the path of the RCFIR filter 636. Additionally, the taps can be set every 4 symbols, thus providing downsampling or reduced rate processing. In some embodiments, the extension to lower delays (shorter delays and near-zero delays) can also be done using fixed delay taps. In some embodiments, the possible floating tap positions can be shared with the reflection taps to achieve a more efficient embodiment for channels that do not require 100% of both taps.

[0051] In another embodiment, the long reach SERDES 600 further includes a TCFIR filter 637 coupled in parallel with the RCFIR filter 636. The TCFIR filter 637 is configured with taps similar to those of the RCFIR filter 636 and is configured to reduce or eliminate the trailing effects or long-duration reflections or echoes in the long reach transmission medium and to ensure that the lengthening effect of the signal pulse tail does not interfere with subsequent symbols. These trailing effects or long-duration reflections are often due to residual ISI caused by long-tailed interference from analog noise in the input signal resulting from increased insertion loss. In an implementation, the TCFIR filter 637 includes 16 taps, each tap being configured to process eight consecutive symbol durations. The long reach SERDES 600 further includes an adder 638 configured to combine all paths from the PRFIR filter 632, the RCFIR filter 636, and the TCFIR filter 637. Note that, as Figure 5 shown, there is a positive sign in the input from the PRFIR filter 632, while there is a negative sign in each of the inputs from the RCFIR filter 636 or the TCFIR filter 637. This indicates that the output of the PRFIR filter 632 (including the original signal that cancels the dispersive ISI) is processed by the adder 638 to remove the effects of the reflected ISI provided by the RCFIR filter 636 or any residual ISI provided by the TCFIR filter 637. The PRFIR filter 636 adds the controlled ISI represented by αD + βD 2 Thus, the output of the adder 638 can be expressed as 1 + αD + βD 2 - RCFIR - TCFIR. In some implementations, a half least significant bit (LSB) can be added during the adder process to facilitate a data rounding operation (performed in the rounding circuit 642) in the next step of signal processing to reduce quantization noise. After the rounding operation, a saturation operation may also be required in the saturation circuit 644 for systems that use fixed-point arithmetic to ensure that the signal is within the representable range.

[0052] The output signal 641 from the adder 638 is conveyed into a DFE filter 646, which is configured as a noise shaping filter that utilizes both the current decision and past decisions (symbol estimates) to compensate for the channel-induced ISI associated with the long reach transmission medium. The DFE filter 646 corrects the postcursor ISI by feedback decisions. In an embodiment, the DFE 646 subtracts the term αD + βD introduced by the PRFIR filter 632 from the estimate of the transmitted symbol derived from the signal at its input 2。In this way, the noise shaping benefits of the PRFIR filter 632 are achieved without degrading the controlled ISI introduced by it. The output signal 642 of the DSP-based SERDES 600 is a signal in which the channel dispersion and reflection effects are cancelled. The DSP output signal 642 is further sent to the RX data processing circuit (e.g., Figure 1 128 of) to recover the original data transmitted by the transmitter device (e.g., Figure 1 110 of).

[0053] In some embodiments, the DSP-based long reach SERDES 600 may include a coupling canceller configured to cancel some of the analog effects of interference between different channels to clean the signal before performing the channel equalization process in the FFE filter 632. In some embodiments, the coupling canceller may be implemented in the FFE filter 632. In the present disclosure, the DSP configuration includes an extension of the floating taps in the RCFIR filter for covering ISI mitigation near the main pulse, which enables the DSP-based SERDES to handle long-range operating environments (e.g., transceivers and high-speed switch applications > 200 Gb / s or faster).

[0054] Figure 6 is an electronic system in which some aspects of the present technology are implemented. The electronic system 500 can be a network switch of a data center or an enterprise network and / or can be a part thereof. The electronic system 500 may include various types of computer-readable media and interfaces for various other types of computer-readable media. The electronic system 500 includes a bus 508, one or more processing units 512, a system memory 504 (and / or buffer), a ROM 510, a permanent storage device 502, an input device interface 514, an output device interface 506, and one or more network interfaces 516, or subsets and variations thereof.

[0055] The bus 508 collectively represents all the system, peripheral, and chipset buses that communicatively connect the numerous internal devices of the electronic system 500. In one or more embodiments, the bus 508 communicatively connects one or more processing units 512 with the ROM 510, the system memory 504, and the permanent storage device 502. From these various memory units, the one or more processing units 512 retrieve the instructions to be executed and the data to be processed in order to perform the processes of the present disclosure. In different embodiments, the one or more processing units 512 can be a single processor or a multi-core processor. In one or more aspects, the one or more processing units 512 can execute the software components of the present technology.

[0056] The ROM 510 stores static data and instructions required by one or more processing units 512 and other modules of the electronic system 500. On the other hand, the permanent storage device 502 can be a read-write memory device. The permanent storage device 502 can be a non-volatile memory unit that stores instructions and data even when the electronic system 500 is powered off. In one or more embodiments, a mass storage device (e.g., a magnetic disk or an optical disk and its corresponding disk drive) can be used as the permanent storage device 502.

[0057] In one or more embodiments, a removable storage device (e.g., a floppy disk, a flash drive, and its corresponding disk drive) can be used as the permanent storage device 502. Similar to the permanent storage device 502, the system memory 504 can be a read-write memory device. However, different from the permanent storage device 502, the system memory 504 can be a volatile readable memory, e.g., a random access memory (RAM). The system memory 504 can store each of the instructions and data that one or more processing units 512 may need during runtime. In one or more embodiments, the processes of the present disclosure are stored in the system memory 504, the permanent storage device 502, and / or the ROM 510. From these various memory units, one or more processing units 512 retrieve instructions to execute the processes of one or more embodiments.

[0058] The bus 508 is also connected to an input device interface 514 and an output device interface 506. The input device interface 514 enables a user to transfer information to the electronic system 500 and select commands. For example, input devices that can be used with the input device interface 514 may include an alphanumeric keyboard and a pointing device (also referred to as a "cursor control device"). For example, the output device interface 506 can enable the display of images generated by the electronic system 500. For example, output devices that can be used with the output device interface 506 may include a printer and a display device, e.g., a liquid crystal display, a light-emitting diode display, an organic light-emitting diode display, a flexible display, a flat panel display, a solid-state display, a projector, or any other device for outputting information. One or more embodiments may include a device that serves as both an input device and an output device, e.g., a touch screen. In these embodiments, the feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and the input from the user includes sound, voice, or tactile input, which can be received in any form.

[0059] Finally, as Figure 6As shown, bus 508 also couples electronic system 500 to one or more networks and / or to one or more network nodes via one or more network interfaces 516. In this manner, electronic system 500 can be part of a network of computers (e.g., a local area network, a wide area network, an intranet, or a network of networks such as the Internet). Any or all components of electronic system 500 can be used in conjunction with the present disclosure.

[0060] Implementations within the scope of the present disclosure can be implemented, in part or in whole, using a tangible computer-readable storage medium (or multiple tangible computer-readable storage media of one or more types) that encodes one or more instructions. The tangible computer-readable storage medium can also be non-transitory in nature. A computer-readable storage medium can be any storage medium that can be read from, written to, or otherwise accessed by a general or special purpose computing device that includes any processing electronics and / or processing circuitry capable of executing instructions. By way of example and not limitation, the computer-readable medium can include any volatile semiconductor memory such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. The computer-readable medium can also include any non-volatile semiconductor memory such as ROM, PROM, EPROM, EEPROM, NVRAM, flash memory, nvSRAM, FeRAM, FeTRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, racetrack memory, FJG, and Millipede memory.

[0061] Although the foregoing is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents can be used. Accordingly, the above description and the accompanying illustrations should not be regarded as limiting the scope of the invention as defined by the appended claims.

Claims

1. A device comprising: a first filter configured to process an input signal to reduce inter-symbol interference (ISI) associated with channel dispersion through a long-reach transmission medium; a second filter coupled in series to the first filter and configured to change the shape of the ISI; and A third filter is coupled in parallel with the second filter and is configured to cancel ISI associated with both long delay reflections and near zero delay reflections.

2. The device of claim 1 , wherein the first filter comprises a feed-forward equalizer configured to include a calibration circuit to calibrate a timing offset of the input signal received from an analog-to-digital converter (ADC) to provide a first intermediate signal for a serializer-deserializer (SERDES).

3. The apparatus of claim 2 , wherein the second filter comprises a partial response finite impulse response (PRFIR) filter configured to introduce controlled ISI based on a transfer function, wherein the transfer function contains at least one term associated with an added positive delay corresponding to a negative delay implemented in the third filter. 4 . The device of claim 3 , further comprising an interpolator configured to adjust a phase of the first intermediate signal output from the first filter to output a second intermediate signal based on a phase adjustment signal.

5. The device of claim 4, further comprising a phase detector configured to detect a phase angle of the second intermediate signal from the interpolator and a loop filter configured to generate the phase adjustment signal.

6. The device of claim 4, wherein the third filter comprises a quantizer and a reflection canceller finite impulse response (RCFIR) filter coupled in series to the quantizer, the third filter being coupled to the interpolator and the first filter in parallel with the PRFIR filter.

7. The device of claim 6, wherein the RCFIR filter is configured to eliminate reflections using a plurality of floating taps located from a near-zero negative delay timing point to a positive delay timing point including a long delay timing point.

8. The device of claim 7, further comprising a fourth filter coupled in parallel with the RCFIR filter and configured to remove residual ISI due to analog noise.

9. The device of claim 8, further comprising a delay matching circuit coupled to the PRFIR filter and followed by an adder, the delay matching circuit being configured to enable reduction of negative delay ISI performed in an RCFIR filter, the adder being configured to combine a positive output of the second filter with corresponding negative outputs of the third and fourth filters and produce an output signal.

10. The device of claim 9, further comprising a fifth filter coupled to the adder, the fifth filter comprising a decision feedback equalizer (DFE) configured to process the output signal to remove the controlled ISI added by the second filter.

11. A system comprising: an analog-to-digital converter ADC configured to provide a digital signal converted from an analog signal transmitted via a transmission medium; a first filter configured to reduce inter-symbol interference (ISI) of the digital signal associated with dispersion in the transmission medium; a second filter configured to change the spectral shape of the ISI; and a third filter configured to eliminate ISI associated with reflections at various timing points in the transmission medium; Wherein the transmission medium comprises a long reach transmission medium, and the second filter is implemented in a serializer-deserializer (SERDES) together with the first filter and in parallel with the third filter.

12. The system of claim 11, wherein the first filter comprises a feed-forward equalizer (FFE) having an offset calibration to provide a first intermediate signal having an equalized dispersion.

13. The system of claim 11, wherein the second filter comprises a partial response finite impulse response (PRFIR) filter configured to introduce controlled ISI based on a transfer function and to add the controlled ISI to the first intermediate signal.

14. The system of claim 11, wherein the third filter comprises a quantizer coupled in series with a reflection canceller finite impulse response (RCFIR) filter.

15. A system according to claim 13, wherein the RCFIR filter is configured to reduce reflections using multiple floating taps located at positive delay time points ranging from near-zero negative delay time points to including long delay time points, wherein the taps associated with negative delays in the RCFIR filter are modeled by modifying taps with longer delays in the PRFIR filter.

16. The system of claim 15, further comprising a fourth filter coupled in parallel with the third filter and configured to reduce residual ISI due to long-tail analog noise.

17. The system of claim 16, further comprising a delay matching circuit coupled to the PRFIR filter and followed by an adder, the delay matching circuit configured to provide a controlled positive delay ISI through the PRFIR filter to enable reduction of negative delay ISI performed in an RCFIR filter, the system further comprising a decision feedback equalizer to remove the controlled ISI added by the PRFIR filter.

18. A receiver comprising: a feed-forward equalizer (FFE) configured to equalize signal dispersion associated with a transmission medium; a filter configured to reduce both long delay reflections and near zero delay reflections due to inter-symbol interference (ISI) in the transmission medium; a partial response finite impulse response (PRFIR) filter configured to add controlled ISI based on a transfer function; and An interpolator is coupled to the FFE and configured to output a phase adjustment signal to the PRFIR filter, wherein the transmission medium comprises a serializer-deserializer (SERDES) long reach transmission medium.

19. The receiver of claim 18, wherein the filter comprises a quantizer and reflection eliminator finite impulse response (RCFIR) filter coupled in series, the filter being coupled in parallel with the PRFIR filter, wherein the transfer function includes a contribution from added positive delay ISI corresponding to negative delay ISI processed by the RCFIR filter.

20. The receiver of claim 19, comprising an adder coupled to the PRFIR filter and the RCFIR filter and a decision feedback equalizer (DFE) coupled to the adder, the adder being configured to process outputs from both the PRFIR filter and the RCFIR filter, the DFE being configured to remove the controlled ISI added by the PRFIR filter.

Images