Signal rapid detection circuit and method

Abstract

The invention belongs to the technical field of electronics, and relates to a signal rapid detection circuit and method. In the signal rapid detection circuit, a sampling clock of a sampling comparator circuit for sampling an input signal DIN and a threshold amplitude V1 is CK1, and a sampling clock of a sampling comparator circuit for sampling the input signal DIN and the threshold amplitude V2 is CK2; the signal detection circuit receives the judgment signals D1 and D2 and outputs a detection signal SD; the Mueller-Muller phase discriminator receives the judgment signals D1 and D2, and outputs a phase too early / too late signal EL; and the control state machine receives the signals SD and EL, outputs a phase control code to the phase interpolator circuit so as to adjust the phases of the sampling clocks CK1 and CK2, and outputs a voltage control code to the digital-to-analog conversion circuit so as to adjust the reference amplitudes V1 and V2. According to the invention, no extra load is introduced to the input end of the receiver circuit, the bandwidth is increased, and the realization of a higher-rate receiver circuit is facilitated.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and particularly to the field of high-speed interface integrated circuits, and relates to a signal fast detection circuit and method. Background Art

[0002] In high-speed serial communication, in order to effectively reduce power consumption, the link needs to be turned off when idle. When a burst data packet arrives, the link needs to be awakened in a very short time to start data reception. This requires the receiving end to detect the signal state in the link so as to adjust the working mode of the receiving end.

[0003] The existing signal fast detection methods are as Figure 1 shown, including a receiver circuit 101 and a signal detection circuit 102. The receiver circuit 101 is composed of a sampling comparator circuit 103, a clock recovery circuit 104 and a phase interpolator circuit 105. The signal detection circuit 102 is connected in parallel with the high-speed data receiver at the receiving end and is a branch independent of the high-speed path. The signal detection circuit 102 can adopt a typical structure of a power detector and a comparator, and includes capacitors 106, 107, NMOS transistors 108, 109, capacitors 110, resistors 111 and a comparator circuit 112. The high-frequency input signals VIP and VIN are AC-coupled to the input pair of transistors, and the voltage at the drain of the NMOS transistor drops due to charge accumulation. The detected amplitude VDETECT is transmitted to the comparator circuit and compared with the reference amplitude VREF. The detection signal SDB changes from the "1" level to the "0" level, and the signal is detected.

[0004] However, in the prior art, the signal detection circuit is directly connected to the high-speed data path, introducing additional load, resulting in a decrease in bandwidth, which is not conducive to the implementation of a high-rate receiver circuit. Moreover, an additional comparator is used in the signal detection circuit, and the offset of the comparator circuit itself will lead to a decrease in detection accuracy. Summary of the Invention

[0005] In order to simplify the circuit design and solve the problem of signal fast detection in the prior art, the present invention proposes a signal fast detection circuit and method.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A signal fast detection circuit includes a sampling comparator circuit, a signal detection circuit, a Mueller-Muller phase detector, a control state machine, a phase interpolator circuit, and a digital-to-analog conversion circuit. The sampling comparator circuit samples the input signal DIN and the threshold amplitude V1 to obtain a decision signal D1, and samples the input signal DIN and the threshold amplitude V2 to obtain a decision signal D2. The input end of the signal detection circuit is connected to the decision signals D1 and D2, and the output end is connected to the first input end of the control state machine. The input end of the Mueller-Muller phase detector is connected to the decision signals D1 and D2, and the output end is connected to the second input end of the control state machine. The first output end of the control state machine is connected to the input end of the phase interpolator circuit, and the output end of the phase interpolator circuit is connected to the sampling comparator circuit. The second output end of the control state machine is connected to the input end of the digital-to-analog conversion circuit, and the output end of the digital-to-analog conversion circuit is connected to the sampling comparator circuit.

[0008] Further, the sampling clock for the sampling comparator circuit to sample the input signal DIN and the threshold amplitude V1 is CK1; the sampling clock for the sampling comparator circuit to sample the input signal DIN and the threshold amplitude V2 is CK2. The signal detection circuit receives the decision signals D1 and D2 and outputs a detection signal SD. The Mueller-Muller phase detector receives the decision signals D1 and D2 and outputs a phase early / late signal EL. The control state machine receives the detection signal SD and the phase early / late signal EL, and outputs a phase control code PICODE to the phase interpolator circuit to adjust the phases of the sampling clocks CK1 and CK2. The control state machine outputs a voltage control code DACCODE to the digital-to-analog conversion circuit to adjust the magnitudes of the reference amplitudes V1 and V2.

[0009] A signal fast detection method implemented by using the signal fast detection circuit according to claim 1 includes the following steps:

[0010] The sampling comparator circuit samples the input signal DIN and the threshold amplitude V1 to obtain a decision signal D1, and the sampling clock is CK1;

[0011] The sampling comparator circuit samples the input signal DIN and the threshold amplitude V2 to obtain a decision signal D2, and the sampling clock is CK2;

[0012] The signal detection circuit receives the decision signals D1 and D2 and outputs a detection signal SD;

[0013] The Mueller-Muller phase detector receives the decision signals D1 and D2 and outputs a phase early / late signal EL;

[0014] The control state machine receives the detection signal SD and the early / late phase signal EL, and outputs the phase control code PICODE to the phase interpolation circuit to adjust the phases of the sampling clocks CK1 and CK2. The control state machine outputs the voltage control code DACCODE to the digital-to-analog conversion circuit to adjust the magnitudes of the reference amplitudes V1 and V2.

[0015] Furthermore, the signal fast detection method includes a signal detection mode and a normal data reception mode, which are controlled by the control state machine.

[0016] Furthermore, the signal detection mode includes:

[0017] The sampling clocks CK1 and CK2 have a difference of 0.5UI, and the reference amplitudes V1 and V2 are of the same magnitude and are set between the signal amplitude and the noise amplitude. When there is no signal, the noise amplitude is less than the reference amplitude, and the output of the sampling comparator circuit is at 0 level. When there is a signal, the signal amplitude is greater than the reference amplitude, and the output of the sampling comparator circuit is at 1 level. By using sampling clocks with a difference of 0.5UI, it is ensured that at least one path samples to the center of the eye diagram.

[0018] Furthermore, the normal data reception mode includes:

[0019] The sampling clocks CK1 and CK2 have the same phase, are located at the center of the eye diagram, and are controlled by the MMCDR. The reference amplitudes V1 and V2 are respectively set at the threshold amplitude and the signal amplitude to enable the normal operation of the MMCDR loop.

[0020] A receiver, characterized by comprising the above-mentioned signal fast detection circuit.

[0021] The beneficial effects of the present invention are:

[0022] A signal fast detection method proposed by the present invention can avoid introducing additional load at the input end of the receiver circuit, increase the bandwidth, and is beneficial to the implementation of a higher-speed receiver circuit. Compared with the existing technical solutions, the comparator of the data path is reused without introducing an additional comparator circuit, simplifying the circuit design. Description of the Drawings

[0023] Figure 1 It is a signal fast detection method of the prior art.

[0024] Figure 2 It is a signal fast detection method proposed by the present invention.

[0025] Figure 3 It is a schematic diagram of the signal fast detection principle proposed by the present invention.

[0026] Figure 4 It is a logic block diagram depicting the working process of the present invention.

[0027] Description of Main Component Symbols:

[0028] CK, CK1, CK2: Sampling Clocks

[0029] PICODE: Phase Control Code

[0030] DACCODE: Voltage Control Code

[0031] VIP: Positive Terminal of Input Differential Voltage Signal

[0032] VIN: Negative Terminal of Input Differential Voltage Signal

[0033] SD, SDB: Detection Signals

[0034] VREF, V1, V2: Reference Amplitudes

[0035] VDETECT: Detection Amplitude

[0036] D1, D2: Decision Signals

[0037] EL: Phase Too Early / Too Late Signal Detailed Implementation Manner

[0038] In combination with the accompanying drawings, the present invention will be further described below.

[0039] The present invention proposes a signal fast detection method. The receiver can adopt a typical structure of baud rate sampling, as Figure 2 shown. The receiver circuit consists of a sampling comparator circuit 201, a signal detection circuit 202, a Mueller-Muller phase detector 203, a control state machine 204, a phase interpolator circuit 205, and a digital-to-analog conversion circuit 206. The sampling comparator circuit 201 samples the input signal DIN and the threshold amplitude V1 to obtain the decision signal D1, with the sampling clock being CK1, and samples the input signal DIN and the threshold amplitude V2 to obtain the decision signal D2, with the sampling clock being CK2. The signal detection circuit 202 receives the decision signals D1 and D2 and outputs the detection signal SD. The Mueller-Muller phase detector 203 receives the decision signals D1 and D2 and outputs the phase too early / too late signal EL. The control state machine 204 receives the detection signal SD and the phase too early / too late signal EL, outputs the phase control code PICODE to the phase interpolator circuit 205 to adjust the phases of the sampling clocks CK1 and CK2, and the control state machine 204 outputs the voltage control code DACCODE to the digital-to-analog conversion circuit 206 to adjust the magnitudes of the reference amplitudes V1 and V2.

[0040] The circuit is divided into two modes: signal detection mode and normal data reception mode, and is controlled by the control state machine 204. When working in the signal detection mode, the sampling clocks CK1 and CK2 differ by 0.5UI (UI stands for Unit Interval, the unit time interval), and the reference amplitudes V1 and V2 are of the same magnitude and are set between the signal amplitude and the noise amplitude. When no signal arrives, the noise amplitude is less than the reference amplitude, and the output of the sampling comparator circuit is at the 0 level. When a signal arrives, the signal amplitude is greater than the reference amplitude, and the output of the sampling comparator circuit is at the 1 level. The sampling clocks with a difference of 0.5UI can ensure that at least one path samples the center of the eye diagram. When working in the normal data reception mode, the sampling clocks CK1 and CK2 have the same phase and are located at the center of the eye diagram, and are controlled by MMCDR. The reference amplitudes V1 and V2 are respectively set at the threshold amplitude and the signal amplitude to ensure the normal operation of the MMCDR loop. Among them, MMCDR refers to Mueller - Muller Clock Data Recovery, and the sampling phase of the clock is controlled by the Mueller - Muller phase detector.

[0041] Figure 3 This is a schematic diagram of the signal fast - detection principle proposed by the present invention. For sampling 301, the circuit works in the signal detection mode. The reference amplitudes V1 and V2 are of the same magnitude, the sampling clocks CK1 and CK2 differ by 0.5UI, and there is no signal in the circuit. The light - colored area is noise. At this time, the decision signals D1 = 0 and D2 = 0, and no signal is detected. For sampling 302, at this time, the decision signal D1 = 1 and D2 = 0, and a signal is detected. For sampling 303, the circuit works in the normal data reception mode. The reference amplitudes V1 and V2 are respectively set at the threshold amplitude and the signal amplitude. The decision signals D1 and D2 are respectively sent to the Mueller - Muller phase detector as the decision data signal and the decision error signal. The sampling clocks CK1 and CK2 have the same phase and are located at the center of the eye diagram and are controlled by MMCDR.

[0042] Figure 4 This is a logic block diagram depicting the working process of the present invention. After starting, the phases of the sampling clocks CK1 and CK2 and the reference amplitudes V1 and V2 are set. Detection of D1 and D2 is repeated until D1 = 1 or D2 = 1, at which point the fast signal detection ends. The phases of the sampling clocks CK1 and CK2 and the reference amplitudes V1 and V2 are reset to meet the requirements of the MMCDR loop, and at this time, normal data reception begins.

[0043] Comparison Figure 2 and Figure 1It can be shown that, compared with the prior art solutions, the signal fast detection method proposed in the embodiments of the present invention does not introduce additional load at the input end of the receiver circuit, increases the bandwidth, and is beneficial to the implementation of a receiver circuit with a higher rate. On the other hand, the signal fast detection method proposed in the embodiments of the present invention does not add an additional comparator circuit. By only relying on multiplexing the comparator circuit in the existing data path and reconfiguring its sampling clock and reference amplitude, the function of signal detection is achieved.

[0044] Further, in the method proposed in the embodiments of the present invention, the receiver circuit can adopt a baud rate sampling structure or an oversampling structure.

[0045] Further, in the method proposed in the embodiments of the present invention, the receiver circuit structure can be extended to more interleaved channels, such as a two-way time interleaved structure, a four-way time interleaved structure, etc.

[0046] Further, in the method proposed in the embodiments of the present invention, the detected signal can be an arbitrary code pattern signal, such as a preamble signal with alternating 0s and 1s, a PRBS signal, etc.

[0047] The specific embodiments of the present invention disclosed above are intended to help understand the content of the present invention and implement it accordingly. Those of ordinary skill in the art can understand that various substitutions, changes, and modifications are possible without departing from the spirit and scope of the present invention. The present invention should not be limited to the content disclosed in the embodiments of this specification, and the protection scope of the present invention is subject to the scope defined by the claims.

Claims

1. A fast signal detection circuit, characterized in that: The invention comprises a sampling comparator circuit, a signal detection circuit, a Mueller-Muller phase detector, a control state machine, a phase interpolator circuit and a digital-to-analog conversion circuit; the sampling comparator circuit samples an input signal DIN and a threshold amplitude V1 to obtain a decision signal D1, and samples an input signal DIN and a threshold amplitude V2 to obtain a decision signal D2; the input end of the signal detection circuit is connected to the decision signals D1 and D2, and the output end is connected to the first input end of the control state machine; the input end of the Mueller-Muller phase detector is connected to the decision signals D1 and D2, and the output end is connected to the second input end of the control state machine; the first output end of the control state machine is connected to the input end of the phase interpolator circuit, and the output end of the phase interpolator circuit is connected to the sampling comparator circuit; the second output end of the control state machine is connected to the input end of the digital-to-analog conversion circuit, and the output end of the digital-to-analog conversion circuit is connected to the sampling comparator circuit.

2. The signal fast detection circuit according to claim 1, characterized in that: The sampling clock of the sampling comparator circuit for sampling the input signal DIN and the threshold amplitude V1 is CK1; the sampling clock of the sampling comparator circuit for sampling the input signal DIN and the threshold amplitude V2 is CK2; the signal detection circuit receives the decision signals D1 and D2, and outputs the detection signal SD; The Mueller-Muller phase detector receives the decision signals D1 and D2, and outputs the phase early / late signal EL; the control state machine receives the detection signal SD and the phase early / late signal EL, and outputs the phase control code PICODE to the phase interpolator circuit to adjust the phase of the sampling clocks CK1 and CK2; the control state machine outputs the voltage control code DACCODE to the digital-to-analog conversion circuit to adjust the size of the reference amplitudes V1 and V2.

3. A fast signal detection method implemented by the fast signal detection circuit of claim 1, characterized in that: The following steps are involved: The sampling comparator circuit samples the input signal DIN and the threshold amplitude V1 to obtain a decision signal D1, and the sampling clock is CK1; The sampling comparator circuit samples the input signal DIN and the threshold amplitude V2 to obtain a decision signal D2, and the sampling clock is CK2; The signal detection circuit receives the decision signals D1 and D2 and outputs a detection signal SD; The Mueller-Muller phase detector receives the decision signals D1 and D2 and outputs a phase early / late signal EL; The control state machine receives the detection signal SD and the phase early / late signal EL, outputs the phase control code PICODE to the phase interpolator circuit to adjust the phase of the sampling clocks CK1 and CK2, and outputs the voltage control code DACCODE to the digital-to-analog conversion circuit to adjust the size of the reference amplitudes V1 and V2.

4. The signal rapid detection method according to claim 3, characterized in that: It includes signal detection mode and normal data receiving mode, which are controlled by the control state machine.

5. The signal rapid detection method according to claim 4, characterized in that: The signal detection mode includes: the sampling clocks CK1 and CK2 differ by 0.5UI, the reference amplitudes V1 and V2 are of the same size and are set between the signal amplitude and the noise amplitude; when there is no signal, the noise amplitude is smaller than the reference amplitude, and the output of the sampling comparator circuit is 0 level; when there is a signal, the signal amplitude is greater than the reference amplitude, and the output of the sampling comparator circuit is 1 level, and the sampling clocks with a difference of 0.5UI are used to ensure that at least one sampling is performed to the center of the eye diagram.

6. The signal rapid detection method according to claim 4, characterized in that: The normal receiving data mode includes: sampling clocks CK1 and CK2 have the same phase, are located in the center of the eye diagram, are controlled by MMCDR, and reference amplitudes V1 and V2 are respectively set at the threshold amplitude and signal amplitude for normal operation of the MMCDR loop.

7. A receiver, characterized in that: It comprises the signal rapid detection circuit as claimed in claim 1 or 2.

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