System and method for probabilistic quadrature amplitude modulation (QAM)

Abstract

The invention relates to a system and method for probabilistic quadrature amplitude modulation (QAM). An apparatus may include a transmitter and one or more processors. The one or more processors may identify, by a low density parity check (LDPC) encoder, a target code rate for which data is encoded. The one or more processors may receive, by the LDPC encoder, a first set of information bits. The one or more processors may receive, by the LDPC encoder, a second set of information bits from an output of a shaping encoder. The one or more processors may adjust a code rate of an LDPC code to a second code rate that is higher than the target code rate to cause the LDPC encoder to encode the data at the target code rate. The one or more processors may encode the data using the LDPC code. The transmitter may transmit the encoded data.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to each of U.S. Provisional Patent Application No. 63 / 610,530, filed Dec. 15, 2023, the entire contents of which are incorporated herein by reference for all purposes. Field of the Invention

[0003] The present disclosure generally relates to systems and methods for improving the encoding process of a communication system and / or performing probabilistic encoding modulation to improve the performance of quadrature amplitude modulation (QAM) through constellation shaping of signals / codes. Background of the Invention

[0004] Error correction codes enable information data to be exchanged in a reliable manner between a transmitter communication system and a receiver communication system. The transmitter communication system encodes the information data to obtain a codeword. A codeword is the encoded information data. The transmitter communication system transmits the codeword to the receiver communication system. Due to noise in the communication channel, the transmission received by the receiver communication system may not be the same as the transmitted codeword. Encoding the information data allows the receiver communication system with an appropriate decoding process to recover the information data from the received transmission despite such noise. For example, the transmitter communication system transmits parity bits to the receiver communication system. The parity bits allow the receiver communication system to verify whether the received transmission is a valid codeword and, if the received transmission is not a valid codeword, correct errors in the transmission. In one method, generating parity bits involves a complex process. Summary of the Invention

[0005] In one aspect, the present application relates to a method that includes: identifying, by a low density parity check (LDPC) encoder of a first device, a target code rate for which data is to be encoded; receiving, by the LDPC encoder of the first device, a first set of information bits; receiving, by the LDPC encoder of the first device, a second set of information bits from an output of a shaping encoder; adjusting, by one or more processors of the first device, a code rate of an LDPC code to a second code rate higher than the target code rate to cause the LDPC encoder to encode the data at the target code rate; encoding, by the one or more processors of the first device, the data using the LDPC code; and transmitting, by the one or more processors of the first device, the encoded data.

[0006] In another aspect, the present disclosure relates to a device comprising: a transmitter and one or more processors, wherein the one or more processors are configured to: identify, by a low-density parity-check (LDPC) encoder, a target code rate for encoding data; receive, by the LDPC encoder, a first set of information bits; receive, by the LDPC encoder, a second set of information bits from an output of a shaping encoder; adjust the code rate of the LDPC code to a second code rate higher than the target code rate so that the LDPC encoder encodes the data at the target code rate; and encode the data using the LDPC code, and the transmitter is configured to transmit the encoded data.

[0007] In another aspect, the present disclosure relates to an apparatus comprising: a receiver configured to receive encoded data; and one or more processors configured to: receive, by a low-density parity-check (LDPC) decoder, a log-likelihood ratio (LLR) value corresponding to the encoded data from the encoded data based on a shaping code; decode, by the LDPC decoder, the LLR value using an LDPC code; and apply, by the shaping decoder, the shaping code to the decoded LLR value to obtain the decoded data corresponding to the encoded data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description taken in conjunction with the accompanying drawings, in which like reference characters identify corresponding elements throughout the text. In the drawings, like reference numerals generally indicate identical, functionally similar and / or structurally similar elements.

[0009] Figure 1 is a diagram depicting an example communication environment having a communication system in accordance with one or more embodiments.

[0010] Figure 2 is a schematic block diagram of a computing system according to an embodiment.

[0011] Figure 3A , Figure 3B and Figure 3C is a graph depicting an LDPC coded modulation system using a uniformly distributed QAM constellation and the information theoretical limit of the uniformly distributed QAM constellation.

[0012] Figure 4A and Figure 4B is a diagram depicting geometric constellation shaping in accordance with one or more embodiments.

[0013] Figure 5A and Figure 5B is a diagram depicting probabilistic constellation shaping in accordance with one or more embodiments.

[0014] Figure 6 is a diagram depicting an example LDPC coded modulation system including a shaping encoder and an LDPC encoder according to one or more embodiments.

[0015] Figure 7A and Figure 7B is a diagram depicting an example shaping code according to one or more embodiments.

[0016] Figure 8 is a diagram depicting probability constellation shaping using a prefix-free code according to one or more embodiments.

[0017] Figure 9 is a diagram depicting an example LDPC coded demodulation system including an LDPC decoder and a shaping decoder according to one or more embodiments.

[0018] Figure 10 is a diagram depicting an example LDPC coded demodulation system including an LDPC decoder and a shaping decoder according to one or more embodiments.

[0019] Figure 11 is a flowchart showing a process for encoding and / or decoding data using a shaping code and an LDPC code according to an embodiment.

[0020] Figure 12 is a diagram depicting example simulation results using an LDPC coded modulation system according to one or more embodiments.

[0021] Figure 13 is a diagram depicting example simulation results using an LDPC coded modulation system according to one or more embodiments.

[0022] Figure 14 is a diagram depicting example simulation results using an LDPC coded modulation system according to one or more embodiments.

[0023] Figure 15 is a diagram depicting example simulation results using an LDPC coded modulation system according to one or more embodiments.

[0024] Figure 16 is a diagram depicting example simulation results using an LDPC coded modulation system according to one or more embodiments.

[0025] Figure 17 is a diagram depicting example simulation results using an LDPC coded modulation system according to one or more embodiments.

[0026] Details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. Detailed Description

[0027] Numerous different embodiments or examples are provided below to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature communicating or communicatively coupling with a second feature may include embodiments in which the first feature communicates directly with the second feature or is directly coupled to the second feature, and may also include embodiments in which additional features may be interposed between the first and second features such that the first feature communicates or is indirectly coupled to the second feature indirectly. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Referring to Figure 1 , FIG. illustrates an example communication environment 100 including communication systems (or communication devices) 105, 108 according to one or more embodiments. In one embodiment, communication system 105 includes baseband circuitry 110 and transmitter circuitry 120, and communication system 108 includes baseband circuitry 150 and receiver circuitry 140. In one aspect, communication system 105 is regarded as a transmitter communication system, and communication system 108 is regarded as a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. In one or more embodiments, these components are embodied as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, communication systems 105, 108 include more, fewer, or different components than those Figure 1 shown in. For example, each of communication systems 105, 108 includes transceiver circuitry to allow two-way communication between communication systems 105, 108 or with other communication systems. In some embodiments, each of communication systems 105, 108 may have a configuration similar to that of computing system 2000 as Figure 2 shown in.

[0029] The baseband circuitry 110 of communication system 105 is circuitry that generates baseband data 115 for transmission. The baseband data 115 contains information data (e.g., signals) at baseband frequencies for transmission. In one method, the baseband circuitry 110 includes an encoder 130 that encodes data and generates or outputs parity bits. In one aspect, the baseband circuitry 110 (or encoder 130) obtains a generator matrix or parity-check matrix, or uses a previously generated generator matrix or a previously generated parity-check matrix, and encodes the information data by applying the information data to the generator matrix or parity-check matrix to obtain a codeword. In some embodiments, the baseband circuitry 110 stores one or more generator matrices or one or more parity-check matrices that conform to any IEEE 802.11 standard for WLAN communication. The baseband circuitry 110 retrieves the stored generator matrix or the stored parity-check matrix in response to detecting information data to be transmitted, or in response to receiving an instruction to encode the information data. In one method, the baseband circuitry 110 generates parity bits according to a portion of the generator matrix or using the parity-check matrix, and appends the parity bits to the information bits to form a codeword. The baseband circuitry 110 generates baseband data 115 that contains the codeword for communication system 108, and provides the baseband data 115 to the transmitter circuitry 120.

[0030] The transmitter circuitry 120 of communication system 105 includes or corresponds to circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits a wireless signal 125 according to the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna (not shown). In this configuration, the transmitter circuitry 120 upconverts the baseband data 115 from the baseband circuitry 110 to a carrier signal to generate a wireless signal 125 at an RF frequency (e.g., 10 MHz to 60 GHz), and transmits the wireless signal 125 through the antenna.

[0031] The receiver circuitry 140 of communication system 108 is circuitry that receives the wireless signal 125 from communication system 105 and obtains baseband data 145 from the received wireless signal 125. In one configuration, the receiver circuitry 140 is coupled between the baseband circuitry 150 and an antenna (not shown). In this configuration, the receiver circuitry 140 receives the wireless signal 125 through the antenna, and downconverts the wireless signal 125 at the RF frequency according to the carrier signal to obtain baseband data 145 from the wireless signal 125. Then, the receiver circuitry 140 provides the baseband data 145 to the baseband circuitry 150.

[0032] The baseband circuitry 150 of the communication system 108 includes or corresponds to circuitry that receives baseband data 145 from the receiver circuitry 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry 150 includes a decoder 160 that extracts information and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain the information data generated by the baseband circuitry 110 of the communication system 105.

[0033] In some embodiments, each of the baseband circuitry 110 (including the encoder 130), the transmitter circuitry 120, the receiver circuitry 140, and the baseband circuitry 150 (including the decoder 160) can be one or more processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any combination thereof.

[0034] Figure 2 is a schematic block diagram of a computing system according to an embodiment. The illustrated example computing system 2000 includes one or more processors 2010 in direct or indirect communication with a memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 having a network interface port for connecting to a network (not shown), and other components such as input / output (“I / O”) components 2050. Generally, the processor 2010 will execute instructions (or computer programs) received from the memory. The illustrated processor 2010 incorporates or is connected to a cache memory 2020. In some examples, instructions are read from the memory 2060 into the cache memory 2020 and executed by the processor 2010 from the cache memory 2020. The computing system 2000 may not necessarily contain Figure 2 all of these components shown in Figure 2 and may contain

[0035] More specifically, the processor 2010 can be any logic circuitry that processes instructions such as those obtained from the memory 2060 or the cache 2020. In many implementations, the processor 2010 is a microprocessor unit or a dedicated processor. The computing device 2000 can be based on any processor or set of processors capable of operating as described herein. The processor 2010 can be a single-core or multi-core processor. The processor 2010 can be multiple different processors.

[0036] The memory 2060 can be any device suitable for storing computer-readable data. The memory 2060 can be a device with fixed storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD ROM, DVD-ROM, or optical disk). The computing system 2000 can have any number of memory devices 2060.

[0037] The cache memory 2020 is generally a form of computer memory placed near the processor 2010 to achieve fast read times. In some embodiments, the cache memory 2020 is part of the processor 2010 or on the same chip as the processor 2010. In some embodiments, there are multiple levels of cache 2020, e.g., L2 and L3 cache layers.

[0038] The network interface controller 2030 manages the exchange of data via a network interface (sometimes referred to as a network interface port). The network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some embodiments, some of the tasks of the network interface controller are handled by one or more of the processors 2010. In some embodiments, the network interface controller 2030 is part of the processor 2010. In some embodiments, the computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some embodiments, the computing system 2000 has multiple network interface controllers 2030. In some embodiments, each network interface is a connection point for a physical network link (e.g., a Category 5 Ethernet link). In some embodiments, the network interface controller 2030 supports wireless network connections, and the interface port is wireless (e.g., radio) receiver or transmitter (e.g., for any of the IEEE 802.11 protocols, near field communication "NFC", Bluetooth, ANT, or any other wireless protocol). In some embodiments, the network interface controller 2030 implements one or more network protocols, such as Ethernet. Generally, the computing device 2000 exchanges data with other computing devices via the network interface over a physical or wireless link. The network interface can be directly linked to another device or linked to another device via an intermediate device, e.g., a network device that connects the computing device 2000 to a data network such as the Internet, e.g., a hub, bridge, switch, or router.

[0039] The computing system 2000 may include or interface with one or more input or output (“I / O”) devices. Input devices include, but are not limited to, keyboards, microphones, touchscreens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include, but are not limited to, video displays, speakers, refreshable braille terminals, lights, MIDI devices, and 2-D or 3-D printers.

[0040] Other components may include an I / O interface, an external serial device port, and any additional coprocessors. For example, the computing system 2000 may include an interface (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., a portable flash drive or an external media drive). In some embodiments, the computing device 2000 includes additional devices such as a coprocessor; for example, a math coprocessor may assist the processor 2010 with high-precision or complex calculations.

[0041] The component 2050 may be configured to connect to external media, the display 2070, the input device 2080, or any other component in the computing system 2000 or a combination thereof. The display 2070 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a flat panel display, a solid state display, a cathode ray tube (CRT) display, a projector, a printer, or any other presently known or later developed display device for outputting the determined information. The display 2070 may act as an interface for a user to view the operation of the processor 2010 or, specifically, as an interface for interfacing with software stored in the memory 2060.

[0042] The input device 2080 may be configured to allow a user to interact with any of the components of the computing system 2000. The input device 2080 may be multiple pads, a keyboard, a cursor control device (e.g., a mouse), or a joystick. Additionally, the input device 2080 may be a remote control, a touchscreen display (which may be a combination of the display 2070 and the input device 2080), or any other device operable to interact with the computing system 2000, such as any device operable to act as an interface between the user and the computing system 2000.

[0043] In one aspect, a parity check matrix defines a set of equations satisfied by any valid codeword. Parity check matrices can be used to encode low-density parity check ("LDPC") codes, described by Richardson and Urbanke in IEEE Transactions on Information Theory, Vol. 47, No. 2 (February 2001). Typically, many wireless and wired communication systems use LDPC as a forward error correction coding scheme.

[0044] In one aspect, constellation shaping is an energy efficiency enhancement method used in digital signal modulation. Constellation shaping can improve traditional modulation techniques such as amplitude and phase shift keying (APSK) and quadrature amplitude modulation (QAM) by modifying the continuous uniform distribution of data symbols to match channel characteristics.

[0045] Figure 3A , Figure 3B and Figure 3C is a graph depicting an LDPC coded modulation system using a uniformly distributed QAM constellation and the information theoretical limit of the uniformly distributed QAM constellation. Figure 3A The constellation structure 300 for 1024QAM (where constellation size M=1024) is shown, where there are 4 different partitions (eg, divisions or subdivisions) 301, 302, 303, 304 depending on the real and imaginary dimensions, so that the decoder can exploit this simple partitioning scheme. Figure 3B A block diagram of an LDPC coded modulation system 320 is shown that includes an LDPC encoder 322 and a pulse amplitude modulation (PAM) symbol mapper (or "PAM mapper") 324. The LDPC encoder 322 can receive multiple binary values ​​(e.g., values ​​in the F2 field) from a source and generate a codeword of length N at its output. The PAM mapper 324 can map each log2M value (from an M-ary signal constellation (e.g., 1024QAM)) into an analog waveform for transmission. The LDPC coded modulation system 320 can be an LDPC-BICM system combined with conventional QAM (with a uniformly distributed QAM constellation). BICM refers to a binary interleaved coded modulation system, which is a model of the coded modulation system on which most communication systems are based. The system 320 may leave gaps in the limits of what can be achieved, such as Figure 3C As shown in . Figure 3C The spectral efficiency of various modulation schemes is shown, including binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 16-QAM, 64-QAM, 256-QAM, 1024-QAM and 4096-QAM, which are represented by lines 357, 356, 355, 354, 353, 352 and 351, respectively.Figure 3C The limit of the spectral efficiency of the channel (Shannon limit) is also shown, which is indicated by line 351, and the gap 352 between the Shannon limit and QAM (e.g., 4096-QAM) is 1.53 dB.

[0046] The Shannon limit (or Shannon capacity) refers to the maximum rate of error-free data that can be theoretically transmitted over a channel under the condition that the link is subject to random data transmission errors for a specific noise level. The Shannon limit is the fundamental limit of the channel, and this limit can be achieved when the distribution of the code matches the optimal distribution of the given channel. The Shannon limit is achieved when the mutual information is maximized, and the mutual information is maximized when the input distribution matches the optimal distribution. For example, for a Gaussian white noise (AWGN) channel, the mutual information is maximized when the codebook also has a Gaussian distribution, and the maximum mutual information is the Shannon limit. The Shannon limit may not change with the distribution, but is a fixed number for a given channel (while the actual rate may depend on the distribution).

[0047] By matching the probability with the input distribution, increasing the block length (to have a larger block length), and / or using Gaussian random codes, the maximum achievable transmission rate can be improved. The achievable capacity may also be limited by the finite-length performance. For example, the Polyanskiy bound can provide a bound on the energy required for each bit in a communication system, which is the baseline of the finite-length performance. The capacity of BICM may depend on a uniform codebook, a large block length, and / or random codes. A communication system using a QAM constellation with a uniform distribution may result in a loss of up to πe / 6 (≈1.53 dB) close to the Shannon limit. If a communication system uses a codebook constructed with a uniform distribution (and does not introduce a distribution to the codebook), there is a 1.53 dB gap for a specific channel. To reduce this gap, the communication system can perform constellation shaping to benefit from being away from the uniform QAM. For example, there are roughly two methods of constellation shaping: geometric constellation shaping (see Figure 4A and Figure 4B ) and probabilistic constellation shaping (see Figure 5A and Figure 5B ).

[0048] Figure 4A and Figure 4B Figures 400 and 450 depict geometric constellation shaping according to one or more embodiments. Geometric constellation shaping aims to shape the constellation lattice to be close to the Gaussian geometry so that the constellation can have a Gaussian distribution with a large M. For example, points can be placed at unequal distances (e.g., by changing the distance between points), but with a uniform probability. Although it is not easy to track when RF impairments are significant, geometric constellation shaping is deployed in some wired systems and / or standards.

[0049] Figure 5A andFigure 5B is a diagram depicting probability constellation shaping according to one or more embodiments. Figure 5A Shows diagram 500 depicting a trellis of constellations weighted with different probabilities. Figure 5B Shows diagram 550 depicting the probability distribution on the trellis, where curve 551 indicates an ideal mapping (e.g., Gaussian mapping). Figure 5B Also shows that a trellis with a large length (e.g., a trellis at or near ±60) is mapped to a small probability.

[0050] In one aspect, a communication system (e.g., an LDPC coded modulation / demodulation system) may include a shaping encoder configured to apply a constellation shaping scheme (e.g., probability constellation shaping) to QAM. For example, if the shaping encoder generates an amplitude block of length n from an input bit block of length (k s -n s ), where k s >n s , then the shaping rate (or compression rate) Rs can be defined as follows: s Since the shaping rate R

[0051]

[0052] is less than 1 (Rs < 1), the shaping encoder of the communication system will serve as forward error correction (FEC). Thus, the constellation shaping performed by the shaping encoder will negatively impact the overall code rate. For example, assuming the desired code rate = 5 / 6, if the shaping encoder applies probability QAM to a conventional communication system (e.g., LDPC coded modulation system 320), then the overall code rate will be less than 5 / 6. s To address this issue, according to some aspects, embodiments in the present disclosure relate to a technique of using a shaping encoder with LDPC (e.g., a probability shaping encoder) to apply constellation shaping to QAM modulation with different rates to achieve a shaping gain of 1.53 dB. The shaping gain may refer to (1) an increase in the information rate (e.g., the average entropy per symbol) achieved by constellation shaping compared to a uniformly distributed constellation; or (2) an improvement in the energy efficiency of the information rate achieved by constellation shaping compared to a uniformly distributed constellation.

[0053] In some embodiments, the LDPC coded modulation system may include a shaping encoder, an adjustable encoder, and / or a symbol mapper. In some embodiments, the symbol mapper may be a PAM symbol mapper. In some embodiments, the modulation system may be implemented in the baseband circuitry or transmitter circuitry of the communication system.

[0054]

[0055] ​In some embodiments, a shaping encoder may include an amplitude shaper and an Amp2Bits (Amplitude to Bits) converter. The amplitude shaper may receive input data (e.g., input binary values) and apply probability constellation shaping to QAM symbols to produce amplitudes corresponding to the QAM symbols (e.g., the amplitudes in the n s dimensions, represented by ). The Amp2Bits converter may convert the shaped amplitudes into binary values. For example, the shaping rate R s of the amplitude shaper may be 0.95, which is less than or equal to the entropy H of the amplitude A, as follows:

[0056] R s = 0.95 ≤ H(A) …………… (Equation 2)

[0057] In some embodiments, an adaptable encoder may include an LDPC encoder and / or parity puncture. Assuming an LDPC coded modulation system uses M - QAM (or M - Quadrature Amplitude Modulation), M - QAM can be considered as the Cartesian product of two sqrt(M) - PAM, such that each sqrt(M) - PAM has m bits. In other words, the QAM after the Cartesian product may have 2m bits. Therefore, the number of bits m in the real dimension of M - QAM (or equivalently, the number of bits m in sqrt(M) - PAM) can be defined as follows:

[0058]

[0059] For example, 4096 - QAM (M = 4096) is the Cartesian product of 64 - PAM x 64 - PAM, where each PAM has 6 bits (m = 6). In other words, the QAM may have 6 bits in the real dimension, 6 bits in the imaginary dimension, and a total of 12 bits.

[0060] In some embodiments, an adaptable encoder (or an LDPC coded modulation system) may identify / determine / obtain the target code rate R target of the LDPC coded modulation system (e.g., the code rate is 5 / 6). The adaptable encoder (or the LDPC coded modulation system) may determine (e.g., identify, adjust, calculate, compute) one or more parameters based on the target code rate R target , which includes at least one of (1) the code rate R c of the LDPC code (or the code rate of the LDPC encoder) or (2) the number of the first set of bits (L u ) that will be input to the LDPC encoder without being output from the shaping encoder. In some embodiments, the adaptable encoder (or the LDPC coded modulation system) may determine one or more parameters using the following equation:

[0061]

[0062] Where N is the number of input information bits of the LDPC encoder.

[0063] In some embodiments, the LDPC encoder may (1) receive (N·R c -L u ) bits from the output of the shaping encoder, and (2) receive L u bits from the input data (e.g., input binary values). The LDPC encoder may use the code rate R c to encode the N·R c bits to generate encoded data. Parity puncturing may puncture some parity bits from the encoded data. In some embodiments, the code rate of the LDPC encoder (or the code rate of the LDPC code used in the LDPC encoder) may be set / adjusted to a code rate R target higher than the code rate of R c . For example, R c is 7 / 8, which is higher than the code rate R target of 5 / 6. In some embodiments, the parity check of the encoded data may be evenly distributed.

[0064] In some embodiments, the encoder may be adjusted to encode data at an overall code rate R (e.g., the actual code rate or the actually implemented code rate) as follows:

[0065]

[0066] Where K is the number of output information bits of the LDPC encoder . In some embodiments, the overall rate R may be a function of at least one of a shaping codebook (e.g., one or more shaping codes), one or more shaping factors (e.g., shaping scheme, shaping rate, shaping gain), FEC code rate (e.g., the code rate R c of the LDPC encoder), or puncturing length.

[0067] In some embodiments, the PAM symbol mapper may be sqrt(M)-PAM, which serves as a stream parser for QAM. The PAM symbol mapper may receive (1) the output of the Amp2Bits converter (e.g., output binary values) and (2) the output of the parity puncturing (or if there is no parity puncturing in the system, then the output of the LDPC encoder), and convert the received data (e.g., binary data) into an analog waveform for transmission.

[0068] In some embodiments, the combination of a shaping encoder and an LDPC encoder (or the combination of a shaping encoder and an adaptable encoder) can act as / serve as a coded modulation system with different rates by selecting one or more parameters (e.g., R c or L u ) to achieve a target code rate (e.g., R target ).

[0069] In some embodiments, even when using probabilistic QAM, parameters can be selected to achieve an overall code rate R of 5 / 6. For example, if the target code rate R target is 5 / 6, then parameters can be selected such that m and s for each M-QAM are fixed (e.g., according to Equation 3); R c = 7 / 8; L u = 81; and / or N = 1944. Using these parameters, the LDPC coded modulation system can not only achieve an overall code rate R of 5 / 6, but also achieve the same spectral efficiency (10 bits) as MCS13 (Modulation and Coding Scheme (MCS) index 13) and a shaping gain of 1.53 dB.

[0070] In some embodiments, the shaping encoder can use a shaping codebook that includes one or more shaping codes. For example, the shaping codebook can include a shaping code for 4096-QAM with an LDPC code rate of 7 / 8 to achieve a shaping rate (R s ) of 0.952, an overall code rate (R) of 5 / 6, and the same spectral efficiency as MCS13. The shaping code can include multiple mappings (e.g., 32 mappings) from input binary data (e.g., 4-bit string, 5-bit string, 6-bit string, 7-bit string, 8-bit string) to output binary data (e.g., 5-bit string) with different probabilities. For example, one or more mappings from a 4-bit string to a 5-bit string can have a probability of 1 / 16; one or more mappings from a 5-bit string to a 5-bit string can have a probability of 1 / 32; one or more mappings from a 6-bit string to a 5-bit string can have a probability of 1 / 64; one or more mappings from a 7-bit string to a 5-bit string can have a probability of 1 / 128; and / or one or more mappings from an 8-bit string to a 5-bit string can have a probability of 1 / 256. For example, using the shaping code, the shaping encoder can shape / map / convert / assign the input string [1111110] to the output string

[11100] with a probability of 1 / 128.

[0071] In some embodiments, a shaping encoder may use a prefix-free code to shape / map / transform / assign an input string of variable length (e.g., a string having 4, 5, 6, 7, 8 bits) into an output string of fixed length (e.g., a string having 5 bits). A prefix-free code is a code such that no (code-generated) codeword is a prefix of another codeword. In some embodiments, the mapping defined by the prefix-free code may be an invertible operation such that each mapping is a one-to-one mapping. In some embodiments, the shaping encoder may apply the Huffman coding method using a prefix-free code. For example, the shaping encoder may use a prefix-free code to shape / map / transform / assign a variable length input string into a fixed length output string based on the frequency of the input string. In some embodiments, the shaping encoder may use the tree structure of the prefix-free code such that the Huffman decoding can be performed using the tree structure. In some embodiments, the shaping encoder may use other structures (e.g., a lookup table or a dictionary) representing the prefix-free code such that the Huffman decoding can be performed using the same structure. In some embodiments, the shaping encoder may receive uniformly distributed input data and induce / assign non-uniform probabilities to the output data. This probability constellation shaping may have an inherent rate loss such that the shaping encoder acts as / functions as an FEC. In some embodiments, given an input string or symbol X, a prefix-free code may be used to map / assign / shape / transform N different numbers of input strings or N different symbols (e.g., N = 32); the maximum entropy may be 5 bits / symbol (e.g., H0(X) = 5 bits / symbol); the average entropy may be 4.71 bits / symbol (e.g., H(X) = 4.71 bits / symbol); the average codeword (CW) length may be 4.71 bits / CW; p(X = 0) = 0.5; p(X = 1) = 0.5.

[0072] In some embodiments, an LDPC coding demodulation system may include a parser, a decoder (e.g., a sphere decoder), an inverse parser, an LDPC decoder, and / or a shaping decoder. In some embodiments, the demodulation system may be implemented in the baseband circuitry of a communication system configured to receive encoded data from another communication system. In some embodiments, the demodulation system may use decoding methods (e.g., soft input maximum likelihood (SiML) and / or sphere maximum a posteriori (sphere MAP)) to implement a non-linear receiver that is superior to a linear receiver. The demodulation system may (1) receive encoded data Y (e.g., Y (1) , Y (2) ), (2) decode the data Y by the sphere decoder based on the probability of symbol s (e.g., P s ) and / or the log-likelihood ratio (LLR) value (e.g., ) to produce decoded data X (e.g., X (1) , X (2)), (3) the inverse parser obtains inverse parsed data from the decoded data X, (4) the LDCP decoder decodes the inverse parsed data to produce LDPC decoded data, (5) the parser parses the LDPC decoded data to produce likelihood values (e.g., ) and / or (6) the shaping decoder uses a shaping code to perform shaping decoding on the LDPC decoded data to produce the original data

[0073] In some embodiments, the sphere decoder may determine whether x i,b is 0 or 1 using the following equation:

[0074]

[0075] where is the LLR value indicating whether x i,b is 0 or 1; R is the code rate; s is the symbol with the corresponding probability P(s). In some embodiments, P(s) may be the product of two probabilities defined in the shaping code (e.g., the probabilities corresponding to two indices of the shaping code).

[0076] In some embodiments, the LDPC encoding and demodulation system may include a multiple-input multiple-output (MIMO) demapper, an LLR (or LLR calculator), an LDPC decoder, and / or a shaping decoder. In some embodiments, the demodulation system may be implemented in the baseband circuitry of a communication system configured to receive encoded data from another communication system. In some embodiments, the demodulation system may use minimum mean square error (MMSE) decoding to implement a linear receiver that is easier to implement than a non-linear receiver. The demodulation system may (1) receive the encoded data Y in an analog waveform, (2) demap the analog waveform to log2M values (M-ary signal constellation (e.g., 1024QAM)), (3) calculate / determine the LLR value by the LLR calculator based on the probability of the symbol s (e.g., P s ), (4) the LDCP decoder decodes the LLR value to produce LDPC decoded data, and / or (5) the shaping decoder uses a shaping code to perform shaping decoding on the LDPC decoded data to produce the original data (e.g., binary data). In some embodiments, the LLR calculator may calculate the LLR value by absorbing P(s) and the MMSE variance σ 2 as follows:

[0077]

[0078] where L i,b is the LLR value indicating whether x i,b is 0 or 1; H is the entropy; s iis a symbol with a corresponding probability P(s i ). In some embodiments, an LDPC-coded demodulation system can be implemented by reusing its components other than the LLR calculator. For example, an LDPC-coded demodulation system can be implemented by reusing the MIMO demapper, the LDPC decoder, and the shaping decoder and adding (or newly implementing) an LLR calculator. In some embodiments, a lookup table can be used to implement the LLR calculator.

[0079] In some embodiments, a device can include a transmitter and one or more processors. The one or more processors can be configured to identify a target code rate for which to encode data by a low-density parity-check (LDPC) encoder. The one or more processors can be configured to receive a first set of information bits by the LDPC encoder. The one or more processors can be configured to receive a second set of information bits from the output of a shaping encoder by the LDPC encoder. The one or more processors can be configured to adjust the code rate of the LDPC code to a second code rate higher than the target code rate such that the LDPC encoder encodes the data at the target code rate. The one or more processors can be configured to encode the data using the LDPC code. The transmitter can be configured to transmit the encoded data.

[0080] In some embodiments, a device can include a transmitter and one or more processors. The one or more processors can identify a target code rate for which to encode data by a low-density parity-check (LDPC) encoder. The one or more processors can receive a first set of information bits by the LDPC encoder. The one or more processors can receive a second set of information bits from the output of a shaping encoder by the LDPC encoder. The one or more processors can adjust the code rate of the LDPC code to a second code rate higher than the target code rate such that the LDPC encoder encodes the data at the target code rate. The one or more processors can use the LDPC code to encode the data. The transmitter can transmit the encoded data.

[0081] In some embodiments, the one or more processors can be further configured to adjust the number of bits in the first set and the number of bits in the second set to encode the data at the target code rate. The target rate can be 5 / 6, the second code rate can be 7 / 8, and the number of bits in the first set can be 81. In some embodiments, the first set of information bits may not be output from the shaping encoder.

[0082] In some embodiments, the one or more processors can be configured to puncture one or more bits from the output of the LDPC encoder to generate a punctured output of the LDPC encoder. The one or more processors can be configured to provide the output of the shaping encoder and the punctured output of the LDPC encoder to a symbol mapper.

[0083] In some embodiments, one or more processors may be configured to apply shaping codes to data using a shaping encoder. The shaping codes may represent codes for probability constellation shaping. The shaping codes may include one or more first mappings from 4-bit strings to 5-bit strings with a probability of 1 / 16, one or more second mappings from 5-bit strings to 5-bit strings with a probability of 1 / 32, one or more third mappings from 6-bit strings to 5-bit strings with a probability of 1 / 64, one or more fourth mappings from 7-bit strings to 5-bit strings with a probability of 1 / 128, and one or more fifth mappings from 8-bit strings to 5-bit strings with a probability of 1 / 256.

[0084] In some embodiments, one or more of the first mappings may include (

[0000] ,

[01111] ), (

[0001] ,

[01110] ), (

[0010] ,

[01100] ), (

[0011] ,

[01101] ), (

[0100] ,

[01001] ), (

[0101] ,

[01000] ), (

[0110] ,

[01010] ), and (

[0111] ,

[01011] ). One or more of the second mappings may include (

[10000] ,

[00011] ), (

[10001] ,

[00010] ), (

[10010] ,

[00000] ), (

[10011] ,

[00001] ), (

[10100] ,

[00101] ), (

[10101] ,

[00100] ), (

[10110] ,

[00110] ), (

[10111] ,

[00111] ), (

[11000] ,

[10111] ), and (

[11001] ,

[10110] ). One or more of the third mappings may include ([110100],

[10100] ), ([110101],

[10101] ), ([110110],

[10001] ), ([110111],

[10000] ), ([111000],

[10010] ), ([111001],

[10011] ), ([111010],

[11011] ), ([111011],

[11010] ), ([111100],

[11000] ), ([111101],

[11001] ), and ([111110],

[11101] ). One or more of the fourth mappings may include ([1111110],

[11100] ). One or more of the fifth mappings may include ([11111110],

[11110] ) and ([11111111],

[11111] ).

[0085] In some embodiments, a device may include a receiver and one or more processors. The receiver may be configured to receive encoded data. The one or more processors may be configured to receive log-likelihood ratio (LLR) values corresponding to the encoded data from the encoded data by a low-density parity-check (LDPC) decoder based on a shaping code. The one or more processors may be configured to decode the LLR values using an LDPC code by the LDPC decoder. The one or more processors may be configured to apply the shaping code to the decoded LLR values by a shaping decoder to obtain decoded data corresponding to the encoded data.

[0086] In some embodiments, the shaping code may include one or more first mappings from 4-bit strings to 5-bit strings with a probability of 1 / 16, one or more second mappings from 5-bit strings to 5-bit strings with a probability of 1 / 32, one or more third mappings from 6-bit strings to 5-bit strings with a probability of 1 / 64, one or more fourth mappings from 7-bit strings to 5-bit strings with a probability of 1 / 128, and one or more fifth mappings from 8-bit strings to 5-bit strings with a probability of 1 / 256.

[0087] In some embodiments, one or more first mappings may include (

[0000] ,

[01111] ), (

[0001] ,

[01110] ), (

[0010] ,

[01100] ), (

[0011] ,

[01101] ), (

[0100] ,

[01001] ), (

[0101] ,

[01000] ), (

[0110] ,

[01010] ), and (

[0111] ,

[01011] ). One or more second mappings may include (

[10000] ,

[00011] ), (

[10001] ,

[00010] ), (

[10010] ,

[00000] ), (

[10011] ,

[00001] ), (

[10100] ,

[00101] ), (

[10101] ,

[00100] ), (

[10110] ,

[00110] ), (

[10111] ,

[00111] ), (

[11000] ,

[10111] ), and (

[11001] ,

[10110] ). One or more third mappings may include ([110100],

[10100] ), ([110101],

[10101] ), ([110110],

[10001] ), ([110111],

[10000] ), ([111000],

[10010] ), ([111001],

[10011] ), ([111010],

[11011] ), ([111011],

[11010] ), ([111100],

[11000] ), ([111101],

[11001] ), and ([111110],

[11101] ). One or more fourth mappings may include ([1111110],

[11100] ). One or more fifth mappings may include ([11111110],

[11110] ) and ([11111111],

[11111] ).

[0088] The embodiments in the present disclosure have at least the following advantages and benefits: First, the embodiments in the present disclosure can provide useful techniques for (1) designing appropriate shaping codes (e.g., shaping codebooks, prefix-free codes) and / or (2) adjusting modulation / demodulation processing based on a target code rate (R target ) to achieve fine control of the overall rate (R).

[0089] Second, the embodiments in the present disclosure can provide useful techniques for selecting parameters such as LDPC code rates (e.g., R c = 7 / 8) and / or information bit numbers (e.g., L u = 81) and a 95% shaping (or compression) rate (e.g., R s = 0.95), resulting in an overall code rate of 5 / 6.

[0090] Third, embodiments in the present disclosure may provide useful techniques for achieving a shaping gain of 1.53 dB, thereby achieving a shaping gain of 1.53 dB (or higher in a system with limited impairment) when using high spectral efficiency QAM modulation.

[0091] Figure 6 FIG. is a diagram depicting an example LDPC coded modulation system 600 according to one or more embodiments. The LDPC coded modulation system 600 may include a shaping encoder 610, an adjustable encoder 620, and / or a symbol mapper 630. The symbol mapper 630 may be a PAM symbol mapper. The modulation system 600 may be implemented in the baseband circuitry (e.g., baseband circuitry 110) or the transmitter circuitry (e.g., transmitter circuitry 120) of a communication system (e.g., communication system 105).

[0092] The shaping encoder 610 may include an amplitude shaper 611 and an Amp2Bits converter 612. The amplitude shaper 611 may receive input data (e.g., input binary values) and apply probability constellation shaping to QAM symbols to produce amplitudes corresponding to the QAM symbols (e.g., the amplitudes in the n s dimensions, represented by ). The Amp2Bits converter 612 may convert the shaped amplitudes to binary values. For example, the shaping rate R s of the amplitude shaper may be 0.95, which is less than or equal to H(A) (see Equation 2).

[0093] The adjustable encoder 620 may include an LDPC encoder 621 and / or a parity check puncturing 622. Assuming the LDPC coded modulation system uses M - ary QAM (or M - QAM), M - QAM can be considered as the Cartesian product of two sqrt(M) - PAM, such that each sqrt(M) - PAM has m bits. In other words, the QAM after the Cartesian product may have 2m bits. Thus, the number of bits m in the real dimension of M - QAM (or equivalently, the number of bits m in sqrt(M) - PAM) can be defined using Equation 3. For example, 4096 - QAM (M = 4096) is the Cartesian product of 64 - PAM x 64 - PAM, such that each PAM has 6 bits (m = 6). In other words, the QAM may have 6 bits in the real dimension, 6 bits in the imaginary dimension, and a total of 12 bits.

[0094] The adjustable encoder 620 (or the LDPC coded modulation system 600) may identify / determine / obtain the target code rate R target of the LDPC coded modulation system (e.g., the code rate is 5 / 6). The adjustable encoder 620 (or the LDPC coded modulation system 600) may be based on the target code rate R targetDetermine (e.g., identify, adjust, calculate, compute) one or more parameters that include (1) the code rate R of the LDPC code c (or the code rate of the LDPC encoder) or (2) the number of the first set of bits (Lu) to be input to the LDPC encoder 621 without being output from the shaping encoder 610. The adjustable encoder 620 (or the LDPC encoding modulation system 600) can use Equation 4 to determine one or more parameters (e.g., R c , L u ).

[0095] The LDPC encoder 621 can (1) receive (N·R c -L u ) bits from the output of the shaping encoder 610 and (2) receive L u bits from the input data (e.g., input binary values). The LDPC encoder 621 can use the code rate R c to encode the N·R c bits to generate encoded data. The parity check puncturing 622 can puncture some parity check bits from the encoded data. The code rate of the LDPC encoder 621 (or the code rate of the LDPC code used in the LDPC encoder 621) can be set / adjusted to a code rate R target higher than the code rate of R c . For example, R c can be set to 7 / 8 which is higher than the code rate of 5 / 6 of R target . The parity check of the encoded data can be evenly distributed.

[0096] The adjustable encoder 620 can encode the data at an overall code rate R (e.g., the actual code rate or the actually implemented code rate) that can be calculated using Equation 5. The overall rate R can be a function of at least one of a shaping codebook (e.g., one or more shaping codes), one or more shaping factors (e.g., shaping scheme, shaping rate, shaping gain), FEC code rate (e.g., the code rate R c of the LDPC encoder) or puncturing length.

[0097] The PAM symbol mapper 630 can be sqrt(M)-PAM, which serves as a stream parser for QAM. The PAM symbol mapper 630 can receive (1) the output of the Amp2Bits converter (e.g., output binary values) and (2) the output of the parity check puncturing (or the output of the LDPC encoder if there is no parity check puncturing in the system), and convert the received data (e.g., binary data) into an analog waveform for transmission.

[0098] Reference Figure 6, the combination of the shaping encoder 610 and the LDPC encoder 621 (or the combination of the shaping encoder 610 and the adjustable encoder 620) can act as a coded modulation system with different rates by selecting one or more parameters (e.g., R c or L u ) to achieve the target code rate (e.g., R target ). Even when using probabilistic QAM, parameters can be selected to achieve an overall code rate R of 5 / 6. For example, if the target code rate R target is 5 / 6, then parameters can be selected such that m and s of each M-QAM are fixed (e.g., according to Equation 3); R c = 7 / 8; L u = 81; and / or N = 1944. Using these parameters, the LDPC coded modulation system 600 can not only achieve an overall code rate R of 5 / 6, but also achieve the same spectral efficiency (10 bits) as MCS13 and a shaping gain of 1.53 dB.

[0099] Figure 7A And Figure 7B are FIGS. 700, 750 depicting an example shaping code according to one or more embodiments. The shaping encoder (e.g., the shaping encoder 610) can use a shaping codebook that includes one or more shaping codes. For example, the shaping codebook can include a shaping code 700 for 4096-QAM with an LDPC code rate of 7 / 8 as shown in Figure 7A to achieve a shaping rate (R s ) of 0.952, an overall code rate (R) of 5 / 6, and the same spectral efficiency as MCS13. The shaping code 700 can include multiple mappings (e.g., 32 mappings indexed 701 from 1 to 32) from input binary data 702 (e.g., 4-bit string, 5-bit string, 6-bit string, 7-bit string, 8-bit string) with different probabilities to output binary data 703 (e.g., 5-bit string). For example, one or more mappings from a 4-bit string to a 5-bit string (e.g., mappings 1 to 8) can have a probability of 1 / 16; one or more mappings from a 5-bit string to a 5-bit string (e.g., mappings 9 to 18) can have a probability of 1 / 32; one or more mappings from a 6-bit string to a 5-bit string (e.g., mappings 19 to 29) can have a probability of 1 / 64; one or more mappings from a 7-bit string to a 5-bit string (e.g., mapping 30) can have a probability of 1 / 128; and / or one or more mappings from an 8-bit string to a 5-bit string (e.g., mappings 31 to 32) can have a probability of 1 / 256. For example, using the shaping code, the shaping encoder 610 can shape / map / convert / assign the input string [1111110] to the output string

[11100] with a probability of 1 / 128 (see mapping 30). Figure 7BDisplays a histogram 750 depicting probability distributions on a mapping index 751, codewords 752, and input data 753.

[0100] Figure 8 FIG. 800 depicts probability constellation shaping using a prefix-free code 840 according to one or more embodiments. A shaping encoder (e.g., shaping encoder 610) may use the prefix-free code 840 to shape / map / transform / assign an input string 830 of variable length (e.g., a string having 4, 5, 6, 7, 8 bits) into an output string 810 of fixed length (e.g., a string having 5 bits). The mapping defined by the prefix-free code 840 may be an invertible operation such that each mapping is a one-to-one mapping. The shaping encoder may apply a Huffman coding method using the prefix-free code 840. For example, the shaping encoder may use the prefix-free code 840 to shape / map / transform / assign a variable length input string into a fixed length output string based on the frequency of the input string (e.g., P[x i 820). The shaping encoder may use the tree structure of the prefix-free code such that Huffman decoding can be performed using the tree structure. For example, the tree structure of the prefix-free code 840 may be a binary tree constructed such that a node corresponding to the input string 830 has a depth corresponding to the length of the input string 830 (e.g., depth = 4, 5, 6, 7, or 8). The shaping encoder may use other structures (e.g., a lookup table or dictionary) representing the prefix-free code such that Huffman decoding can be performed using the same structure. The shaping encoder may receive uniformly distributed input data and introduce / assign non-uniform probabilities to the output data. This probability constellation shaping may have an inherent rate loss such that the shaping encoder acts as / functions as an FEC. Given an input string or symbol X, the prefix-free code may be used to map / assign / shape / transform N different numbers of input strings or N different symbols (e.g., N = 32); the maximum entropy may be 5 bits / symbol (e.g., H0(X) = 5 bits / symbol); the average entropy may be 4.71 bits / symbol (e.g., H(X) = 4.71 bits / symbol); the average codeword (CW) length may be 4.71 bits / CW; p(X = 0) = 0.5; p(X = 1) = 0.5.

[0101] Figure 9FIG. depicts an example LDPC coded demodulation system 900 according to one or more embodiments. The LDPC coded demodulation system 900 may include a parser 910, a decoder 920 (e.g., a sphere decoder), an inverse parser 930, an LDPC decoder 940, and / or a shaping decoder 950. The demodulation system 900 may be implemented in the baseband circuitry (e.g., baseband circuitry 150) or receiver circuitry (e.g., receiver circuitry 140) of a communication system (e.g., communication system 108) configured to receive encoded data from another communication system (e.g., communication system 105). The demodulation system 900 may implement a non-linear receiver that is superior to a linear receiver using decoding methods (e.g., SiML and / or sphere MAP). The demodulation system 900 may (1) receive encoded data Y (e.g., Y (1) 、Y (2) ), (2) decode the data Y by the sphere decoder 920 based on the probability of the symbol s (e.g., P s ) and / or the log-likelihood ratio (LLR) value (e.g., )) to produce decoded data X (e.g., X (1) 、X (2) ), (3) obtain inverse parsed data from the decoded data X by the inverse parser 930, (4) decode the inverse parsed data by the LDCP decoder 940 to produce LDPC decoded data, (5) parse the LDPC decoded data by the parser 910 to produce likelihood values (e.g., ) and / or (6) perform shaping decoding on the LDPC decoded data by the shaping decoder 950 using a shaping code (e.g., the shaping codes shown in Figure 7A and Figure 8 ) to produce the original data The sphere decoder 920 may determine whether x i,b is 0 or 1 using Equation 6 based on the probability P(s). In some embodiments, P(s) may be the product of two probabilities defined in the shaping code (e.g., the probabilities corresponding to two indices of the shaping code).

[0102] Figure 10FIG. is a diagram depicting an example LDPC coded demodulation system 1000 according to one or more embodiments. The LDPC coded demodulation system 1000 may include a MIMO demapper 1010, an LLR (or LLR calculator) 1020, an LDPC decoder 1030, and / or a shaping decoder 1040. The demodulation system 1000 may be implemented in a baseband circuit system (e.g., baseband circuit system 150) or a receiver circuit system (e.g., receiver circuit system 140) of a communication system (e.g., communication system 108) configured to receive encoded data from another communication system (e.g., communication system 105). The demodulation system 1000 may implement a linear receiver that is easier to implement than a non-linear receiver using minimum mean square error (MMSE) decoding. In some embodiments, the LDPC coded demodulation system 1000 may be implemented by reusing its components other than the LLR calculator 1020. For example, the LDPC coded demodulation system 1000 may be implemented by reusing the MIMO demapper 1010, the LDPC decoder 1030, and the shaping decoder 1040 and adding (or newly implementing) the LLR calculator 1020. In some embodiments, the LLR calculator 1020 may be implemented using a look-up table. The demodulation system 1000 may (1) receive the encoded data Y in an analog waveform, (2) demap the analog waveform by the MIMO demapper 1010 to log2M values of an (M-ary signal constellation (e.g., 1024QAM)), (3) calculate / compute / determine the LLR values by the LLR calculator 1020 based on the probability of the symbol s (e.g., P s ), (4) decode the LLR values by the LDCP decoder 1030 to produce LDPC decoded data, and / or (5) perform shaping decoding on the LDPC decoded data by the shaping decoder 1040 using a shaping code (e.g., Figure 7A and Figure 8 the shaping codes shown in) to produce the original data (e.g., binary data). The LLR calculator 1020 may calculate the LLR values by absorbing P(s) and the MMSE variance σ 2 using Equation 7.

[0103] Figure 11is a flowchart showing process 1100 for encoding and / or decoding data using a shaping code and an LDPC code according to an embodiment. In some embodiments, process 1100 is performed by one or more processors of a first device (e.g., encoder 130 or processor 2010 of communication system 105, modulation system 600) or one or more processors of a second device (e.g., decoder 160 or processor 2010 of communication system 108, demodulation system 900, demodulation system 1000). In other embodiments, process 1100 is performed by other entities (e.g., a computing system other than communication system 105 or 108). In some embodiments, process 1100 includes more, fewer, or different steps than those shown in Figure 11 shown in Figure 11 and shown in

[0104] At step 1102, an LDPC encoder of the first device (e.g., modulation system 600, adjustable encoder 620, or LDPC encoder 621 of communication system 105) may identify a target code rate (e.g., a code rate of 5 / 6) for which it encodes data. At step 1104, an LDPC encoder of the first device (e.g., LDPC encoder 621) may receive a first set of information bits (e.g., L u number of information bits). At step 1106, the LDPC encoder of the first device may receive a second set of information bits (e.g., (N*R c –L u ) number of information bits) from the output of a shaping encoder (e.g., shaping encoder 610). The first set of information bits (e.g., L u number of information bits) may not be output from shaping encoder 610.

[0105] In some embodiments, the first device may apply a shaping code (e.g., shaping code 700 shown in Figure 7A or shaping code 840 shown in Figure 8 ) to the data through shaping encoder 610. The shaping code may represent a code for probabilistic constellation shaping. In some embodiments, the shaping code may include one or more first mappings from a 4-bit string to a 5-bit string with a probability of 1 / 16 (e.g., mappings 1 to 8 in Figure 7A ), one or more second mappings from a 5-bit string to a 5-bit string with a probability of 1 / 32 (e.g., mappings 9 to 18 in Figure 7A ), one or more third mappings from a 6-bit string to a 5-bit string with a probability of 1 / 64 (e.g., mappings 19 to 29 in Figure 7A ), one or more fourth mappings from a 7-bit string to a 5-bit string with a probability of 1 / 128 (e.g., mappings in Figure 7Athe mapping 30) in, and one or more fifth mappings from an 8-bit string to a 5-bit string with a probability of 1 / 256 (e.g., Figure 7A mappings 31 to 32 in).

[0106] In some embodiments, one or more first mappings (e.g., Figure 7A mappings 1 to 8 in) may include (

[0000] ,

[01111] ), (

[0001] ,

[01110] ), (

[0010] ,

[01100] ), (

[0011] ,

[01101] ), (

[0100] ,

[01001] ), (

[0101] ,

[01000] ), (

[0110] ,

[01010] ), and (

[0111] ,

[01011] ). One or more second mappings (e.g., Figure 7A mappings 9 to 18 in) may include (

[10000] ,

[00011] ), (

[10001] ,

[00010] ), (

[10010] ,

[00000] ), (

[10011] ,

[00001] ), (

[10100] ,

[00101] ), (

[10101] ,

[00100] ), (

[10110] ,

[00100] ), (

[10111] ,

[00111] ), (

[11000] ,

[10111] ), and (

[11001] ,

[10110] ). One or more third mappings (e.g., Figure 7A mappings 19 to 29 in) may include ([110100],

[10100] ), ([110101],

[10101] ), ([110110],

[10001] ), ([110111],

[10000] ), ([111000],

[10010] ), ([111001],

[10011] ), ([111010],

[11011] ), ([111011],

[11010] ), ([111100],

[11000] ), ([111101],

[11001] ), and ([111110],

[11101] ). One or more fourth mappings (e.g., Figure 7A mapping 30 in) may include ([1111110],

[11100] ). One or more fifth mappings (e.g., Figure 7A mappings 31 to 32 in) may include ([11111110],

[11110] ) and ([11111111],

[11111] ).

[0107] At step 1108, one or more processors of the first device may adjust the code rate of the LDPC code to a second code rate (e.g., R target = 5 / 6) higher than the target code rate (e.g., R c= 7 / 8), so that the LDPC encoder encodes the data at a target code rate (e.g., R target = 5 / 6).

[0108] In some embodiments, the first device may adjust the number of bits in the first group (e.g., L u ) and the number of bits in the second group (e.g., N*R c - L u ) to encode the data at the target code rate. The target rate may be 5 / 6. The second code rate may be 7 / 8. The number of bits in the first group may be 81.

[0109] At step 1110, one or more processors of the first device may encode the data using an LDPC code. In some embodiments, the first device (e.g., parity check puncturing 622) may puncture one or more bits from the output of the LDPC encoder to generate a punctured output of the LDPC encoder. The first device may provide the output of the shaping encoder (e.g., shaping encoder 610) and the punctured output of the LDPC encoder (e.g., the output from parity check puncturing 622) to a symbol mapper (e.g., PAM symbol mapper 630). At step 1112, one or more processors of the first device may transmit the encoded data.

[0110] In some embodiments, a second device (e.g., communication system 108, receiver circuitry 140) may receive the encoded data from a first device (e.g., communication system 105, transmitter circuitry 120). The LDPC decoder of the second device (e.g., LDPC decoder 940, LDPC decoder 1030) may receive log-likelihood ratio (LLR) values corresponding to the encoded data from the encoded data based on a shaping code (e.g., shaping code 700 or shaping code 840). For example, LDPC decoder 1030 may receive LLR values from LLR calculator 1020. The LDPC decoder of the second device may decode the LLR values using an LDPC code. The shaping decoder of the second device (e.g., shaping decoder 950, 1040) may apply the shaping code to the decoded LLR values to obtain decoded data corresponding to the encoded data.

[0111] Figure 12 is FIG. 1200 depicting example simulation results of using an LDPC-coded modulation system according to one or more embodiments. Referring Figure 12 , lines 1201 and 1204 respectively indicate the use of and simulation results (e.g., punctured bit percentage where L punct refers to the number of punctured bits, N is the number of information bits input to the LDPC encoder 621, R cis the code rate of the LDPC encoder 621). Lines 1202 and 1203 respectively indicate the use of and simulation results (e.g., for achieving the target code rate R target = 5 / 6 ≈ 0.83 for the overall code rate R). The simulation results show that the LDPC code results in significant puncturing loss (see line 1201), while the LDPC code can provide a better trade-off between puncturing loss and achieving the target code rate of 5 / 6 (see lines 1203 and 1204). Based on Figure 12 the simulation results shown in and L u = 81.

[0112] Figure 13 FIG. 1300 is a graph depicting example simulation results (e.g., packet error rate (PER) at different SNRs) of using an LDPC coded modulation system according to one or more embodiments. The results were obtained using the following simulation settings: (1) 4096QAM; (2) 2x2 MIMO additive white Gaussian noise (AWGN) channel; (3) no RF impairments; (4) in all SNRs, the shaping rate (referred to as R s or SE) was adjusted such that 3 dB per bit; and (5) L was 8 KB. Lines 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309 respectively refer to the corresponding simulation results for settings with (1) no shaping (SE = 10); (2) R c = 7 / 8, Lu = 81 (SE = 9.894); (3) R c = 5 / 6, Lu = 90 (SE = 9.977); (4) R c = 7 / 8, Lu = 91 (SE = 9.954); (5) R c = 5 / 6, Lu = 90 (SE = 9.712); (6) shaping using PB(1944); (7) Shannon limit; (8) BICM; and (9) BICM using PB(1944). Figure 13 shows a shaping gain of up to 1.53 dB.

[0113] Figure 14FIG. 1400 depicts example simulation results (e.g., packet error rate (PER) over different SNRs) of an LDPC coded modulation system according to one or more embodiments. The results were obtained using the following simulation settings: (1) 4096QAM; (2) 2x2 MIMO AWGN channel; (3) presence of RF impairments such that there is 43 dB noise at transmit (Tx) and 43 dB noise at receive (Rx); and (4) shaping rate (referred to as R s or SE) is adjusted at all SNRs. Lines 1401, 1402, 1403, 1404, 1405, 1406, 1407, 1408, 1409 refer respectively to the corresponding simulation results for settings with (1) no shaping (SE = 10); (2) R c = 7 / 8, Lu = 81 (SE = 9.894); (3) R c = 5 / 6, Lu = 90 (SE = 9.977); (4) R c = 7 / 8, Lu = 91 (SE = 9.954); (5) R c = 5 / 6, Lu = 90 (SE = 9.712); (6) shaping using PB(1944); (7) Shannon limit; (8) BICM; and (9) BICM using PB(1944). Figure 14 Shows a shaping gain of up to 1.53 dB is obtained.

[0114] Figure 15 FIG. 1500 depicts example simulation results (e.g., packet error rate (PER) over different SNRs) of an LDPC coded modulation system according to one or more embodiments. The results were obtained using the following simulation settings: (1) 4096QAM; (2) 4x2 MIMO transmit beamforming (TxBF) BLOS channel (“BLOS” indicates 802.11 channel model type B, which is a line-of-sight channel); and (3) shaping rate (referred to as R s or SE) is adjusted at all SNRs. Lines 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508, 1509, 1510 refer to settings with (1) no shaping (SE = 10); (2) R c = 7 / 8, Lu = 81 (SE = 9.894); (3) R c = 5 / 6, Lu = 90 (SE = 9.977); (4) R c = 7 / 8, Lu = 91 (SE = 9.954); (5) R c = 5 / 6, Lu = 90 (SE = 9.712); (6) no shaping (SE = 10) with 43 dB of RF impairment; (7) R c= 7 / 8, Lu = 81 (SE = 9.894), with 43 dB of RF impairment; (8) R c = 5 / 6, Lu = 90 (SE = 9.977), with 43 dB of RF impairment; (9) R c = 7 / 8, Lu = 91 (SE = 9.954), with 43 dB of RF impairment; (10) R c = 5 / 6, Lu = 90 (SE = 9.712), corresponding simulation results for the setting with 43 dB of RF impairment. Figure 15 Shows achieving up to 1.53 dB of shaping gain.

[0115] Figure 16 Is FIG. 1600 depicting example simulation results (e.g., packet error rate (PER) at different SNRs) of using an LDPC-coded modulation system according to one or more embodiments. The results were obtained using the following simulation settings: (1) 4096QAM; (2) 4x2 MIMO transmit beamforming (TxBF) BLOS channel (“BLOS” indicates 802.11 channel model type B, which is a line-of-sight channel); (3) at all SNRs, adjusting the shaping rate (referred to as R s or SE); and (4) there is RF impairment, with 43 dB of noise at the Tx and 43 dB of noise at the Rx. Lines 1601, 1602, 1603, 1604, 1605 respectively refer to the corresponding simulation results for the settings with (1) no shaping (SE = 10); (2) Rc = 5 / 6, Lu = 90 (SE = 9.712); (3) Rc = 7 / 8, Lu = 86 (SE = 9.924); (4) Rc = 7 / 8, Lu = 91 (SE = 9.955); (5) R c = 5 / 6, Lu = 90 (SE = 9.977). Figure 16 Shows achieving significant shaping gain.

[0116] Figure 17 Is FIG. 1700 depicting example simulation results (e.g., packet error rate (PER) at different SNRs) of using an LDPC-coded modulation system according to one or more embodiments. The results were obtained using the following simulation settings: (1) 4096QAM; (2) 4x2 MIMO BNLOS channel (“BNLOS” indicates a non-line-of-sight channel) and / or 2x2 AWGN channel; (3) at all SNRs, adjusting the shaping rate (referred to as R s or SE); and (4) there is RF impairment, with 40 dB of noise at the Tx and 40 dB of noise at the Rx. Lines 1701, 1702, 1703 and 1704 respectively refer to the settings with (1) no shaping; (2) R c = 7 / 8, Lu = 86; (3) R c = 7 / 8, L u = 91; and (4) R c = 5 / 6, L u = 90 settings for the corresponding simulation results. Figure 17 Show (1) In order to achieve optimal shaping at a target code rate of 4 / 5, R c = 5 / 6, L u = 68, L p = 4, Ps = 0.95; (2) The expected effective gain is approximately 0.4 dB.

[0117] As Figures 12 to 17 shown, the shaping gain is meaningful and consistent. For example, under fading conditions, the shaping gain in both AWGN and 4x2 TxBF is as high as 1.5 dB. It is shown that in the case of RF impairments, better and significant shaping gains are achieved. For example, 4x2 TxBF and / or 2x2 fading channels are expected to achieve more shaping gain. The LDPC code rate Rc = 7 / 8 shows the best performance in achieving the target code rate, while the LDPC code rate R c = 5 / 6 does not achieve the desired spectral efficiency of 10 bps / Hz for 4K-QAM.

[0118] References to "or" may be interpreted as inclusive, such that any term described using "or" may indicate any one of the terms described, more than one, and all. References to at least one of a list of conjunctive terms may be interpreted as inclusive "or" to indicate any one of the terms described, more than one, and all. For example, a reference to "at least one of 'A' and 'B'" may include only 'A', only 'B', and both 'A' and 'B'. Such references used in conjunction with "including" or other open terms may include additional items.

[0119] Note that, for purposes of identification or differentiation of one from another or others, certain paragraphs of this disclosure may refer to terms in connection with subsets of transmit spatial streams, probe frames, responses, and devices, such as "first" and "second". These terms are not intended to relate entities (e.g., a first device and a second device) only in terms of time or according to sequence, but in some cases, these entities may include such relationships. These terms also do not limit the number of possible entities (e.g., STAs, APs, beamformers and / or beamformeess) that may operate in a system or environment. It should be understood that the systems described above may provide multiple of any or each of those components, and these components may be disposed on separate machines or, in some embodiments, on multiple machines in a distributed system. Additionally, bit field positions may vary and multi-bit words may be used. Further, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash card, PROM, RAM, ROM, or magnetic tape). The programs may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or in any byte code language (e.g., JAVA). The software programs or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0120] While the foregoing written description of the methods and systems enables one of ordinary skill in the art to make and use its embodiments, one of ordinary skill in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Accordingly, the methods and systems should not be limited by the embodiments, methods, and examples described above, but rather should be limited by all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. A method comprising: identifying, by a low-density parity check (LDPC) encoder of the first device, a target code rate for encoding data; receiving, by the LDPC encoder of the first device, a first set of information bits; receiving, by the LDPC encoder of the first device, a second set of information bits from an output of a shaping encoder; adjusting, by one or more processors of the first device, a code rate of an LDPC code to a second code rate higher than the target code rate, so that the LDPC encoder encodes the data at the target code rate; encoding, by the one or more processors of the first device, the data using the LDPC code; and The encoded data is transmitted by the one or more processors of the first device.

2. The method according to claim 1, further comprising: The number of bits in the first group and the number of bits in the second group are adjusted to encode the data at the target bit rate. 3 . The method of claim 2 , wherein the target rate is 5 / 6, the second code rate is 7 / 8, and the number of bits in the first group is 81.

4. The method of claim 1, wherein the first set of information bits are not output from the shaping encoder.

5. The method according to claim 1, further comprising: puncturing one or more bits from an output of the LDPC encoder to generate a punctured output of the LDPC encoder; and The output of the shaping encoder and the punctured output of the LDPC encoder are provided to a symbol mapper.

6. The method according to claim 1, further comprising: A shaping code is applied to the data by the shaping encoder, wherein the shaping code represents a code for probabilistic constellation shaping.

7. The method according to claim 6, wherein the shaping code comprises: one or more first mappings from 4-bit strings to 5-bit strings with a probability of 1 / 16; one or more second mappings from 5-bit strings to 5-bit strings with a probability of 1 / 32; one or more third mappings from 6-bit strings to 5-bit strings with a probability of 1 / 64; one or more fourth mappings from 7-bit strings to 5-bit strings with a probability of 1 / 128; and One or more fifth mappings from 8-bit strings to 5-bit strings with a probability of 1 / 256.

8. The method according to claim 7, wherein The one or more first mappings include ([0000], [01111]), ([0001], [01110]), ([0010], [01100]), ([0011], [01101]), ([0100], [01001]), ([0101], [01000]), ([0110], [01010]), and ([0111], [01011]), the one or more second mappings include ([10000], [00011]), ([10001], [00010]), ([10010], [00000]), ([10011], [00001]), ([10100], [00101]), ([10101], [00100]), ([10110], [00110]), ([10111], [00111]), ([11000], [10111]), and ([11001], [10110]), the one or more third mappings include ([110100], [10100]), ([110101], [10101]), ([110110], [10001]), ([110111], [10000]), ([111000], [10010]), ([111001], [10011]), ([111010], [11011]), ([111011], [11010]), ([111100], [11000]), ([111101], [11001]), and ([111110], [11101]), The one or more fourth mappings include ([1111110], [11100]), and The one or more fifth mappings include ([11111110], [11110]) and ([11111111], [11111]).

9. The method according to claim 1, further comprising: receiving, by a second device, the encoded data from the first device; and Receiving, by a low density parity check (LDPC) decoder of the second device, a log likelihood ratio (LLR) value corresponding to the encoded data from the encoded data based on the shaping code; decoding, by the LDPC decoder of the second device, the LLR values ​​using an LDPC code; and The shaping code is applied, by a shaping decoder of the second device, to the decoded LLR values ​​to obtain decoded data corresponding to the encoded data.

10. A device comprising: A transmitter and one or more processors, wherein The one or more processors are configured to: identifying, by a low-density parity check LDPC encoder, a target code rate for which to encode data; Receiving, by the LDPC encoder, a first set of information bits; receiving, by the LDPC encoder, a second set of information bits from an output of a shaping encoder; Adjusting a code rate of an LDPC code to a second code rate higher than the target code rate, so that the LDPC encoder encodes the data at the target code rate; and The data is encoded using the LDPC code, and The transmitter is configured to transmit the encoded data.

11. The apparatus of claim 10, wherein the one or more processors are further configured to: The number of bits in the first group and the number of bits in the second group are adjusted to encode the data at the target bit rate. 12 . The apparatus of claim 11 , wherein the target rate is 5 / 6, the second code rate is 7 / 8, and the number of bits in the first group is 81.

13. The apparatus of claim 10, wherein the first set of information bits are not output from the reshaping encoder.

14. The apparatus of claim 10, wherein the one or more processors are further configured to: puncturing one or more bits from an output of the LDPC encoder to generate a punctured output of the LDPC encoder; and The output of the shaping encoder and the punctured output of the LDPC encoder are provided to a symbol mapper.

15. The apparatus of claim 10, wherein the one or more processors are further configured to: A shaping code is applied to the data by the shaping encoder, wherein the shaping code represents a code for probabilistic constellation shaping.

16. The apparatus of claim 15, wherein the shaping code comprises: one or more first mappings from 4-bit strings to 5-bit strings with a probability of 1 / 16; one or more second mappings from 5-bit strings to 5-bit strings with a probability of 1 / 32; one or more third mappings from 6-bit strings to 5-bit strings with a probability of 1 / 64; one or more fourth mappings from 7-bit strings to 5-bit strings with a probability of 1 / 128; and One or more fifth mappings from 8-bit strings to 5-bit strings with a probability of 1 / 256.

17. The apparatus of claim 16, wherein The one or more first mappings include ([0000], [01111]), ([0001], [01110]), ([0010], [01100]), ([0011], [01101]), ([0100], [01001]), ([0101], [01000]), ([0110], [01010]), and ([0111], [01011]), the one or more second mappings include ([10000], [00011]), ([10001], [00010]), ([10010], [00000]), ([10011], [00001]), ([10100], [00101]), ([10101], [00100]), ([10110], [00110]), ([10111], [00111]), ([11000], [10111]), and ([11001], [10110]), the one or more third mappings include ([110100], [10100]), ([110101], [10101]), ([110110], [10001]), ([110111], [10000]), ([111000], [10010]), ([111001], [10011]), ([111010], [11011]), ([111011], [11010]), ([111100], [11000]), ([111101], [11001]), and ([111110], [11101]), The one or more fourth mappings include ([1111110], [11100]), and The one or more fifth mappings include ([11111110], [11110]) and ([11111111], [11111]).

18. An apparatus comprising: a receiver configured to receive the encoded data; and One or more processors configured to: Receiving, by a low density parity check (LDPC) decoder, a log likelihood ratio (LLR) value corresponding to the encoded data from the encoded data based on a shaping code; Decoding the LLR values ​​by the LDPC decoder using an LDPC code; and The shaping code is applied by a shaping decoder to the decoded LLR values ​​to obtain the decoded data corresponding to the encoded data.

19. The apparatus of claim 18, wherein the shaping code comprises: one or more first mappings from 4-bit strings to 5-bit strings with a probability of 1 / 16; one or more second mappings from 5-bit strings to 5-bit strings with a probability of 1 / 32; one or more third mappings from 6-bit strings to 5-bit strings with a probability of 1 / 64; one or more fourth mappings from 7-bit strings to 5-bit strings with a probability of 1 / 128; and One or more fifth mappings from 8-bit strings to 5-bit strings with a probability of 1 / 256.

20. The apparatus of claim 19, wherein The one or more first mappings include ([0000], [01111]), ([0001], [01110]), ([0010], [01100]), ([0011], [01101]), ([0100], [01001]), ([0101], [01000]), ([0110], [01010]), and ([0111], [01011]), the one or more second mappings include ([10000], [00011]), ([10001], [00010]), ([10010], [00000]), ([10011], [00001]), ([10100], [00101]), ([10101], [00100]), ([10110], [00110]), ([10111], [00111]), ([11000], [10111]), and ([11001], [10110]), the one or more third mappings include ([110100], [10100]), ([110101], [10101]), ([110110], [10001]), ([110111], [10000]), ([111000], [10010]), ([111001], [10011]), ([111010], [11011]), ([111011], [11010]), ([111100], [11000]), ([111101], [11001]), and ([111110], [11101]), The one or more fourth mappings include ([1111110], [11100]), and The one or more fifth mappings include ([11111110], [11110]) and ([11111111], [11111]).

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