Method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure, including: providing a substrate, the substrate including an array region; forming a plurality of active pillars, the active pillars being located on the array region, the active pillars being arranged along a first direction and a second direction, and the active pillars extending along a third direction; forming a word line, the word line extending along the first direction, and the word line covering sidewalls of the plurality of active pillars along the first direction; forming a bit line, the bit line extending along the second direction, and the bit line connecting the plurality of active pillars at one end along the third direction; forming a word line plug, the word line plug being located on a side of the word line close to the bit line along the third direction and electrically contacting the word line, and a normal projection of the word line plug on the substrate being located in the array region; and forming a bit line plug, the bit line plug being located on a side of the bit line away from the active pillars along the third direction and electrically contacting the bit line, and a normal projection of the bit line plug on the substrate being located in the array region, at least facilitating to improve the integration density of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a manufacturing method of a semiconductor structure. BACKGROUND

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used by a general computer system can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, which is composed of many repeated memory cells.

[0003] A memory cell generally includes a capacitor and a transistor, one of the source-drain or drain of the transistor is connected to a bit line structure, and the other is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, and then read the data information stored in the capacitor through the bit line structure, or write the data information into the capacitor through the bit line structure for storage.

[0004] At present, the integration density of the semiconductor structure needs to be improved. SUMMARY

[0005] Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which is at least beneficial to improve the integration density of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, the present disclosure provides a manufacturing method of a semiconductor structure, which includes: providing a substrate, the substrate including an array region; forming a plurality of active pillars, the active pillars being located on the array region, the active pillars being arranged along a first direction and a second direction, the active pillars extending along a third direction; forming a word line, the word line extending along the first direction, in the first direction, the word line covering sidewalls of the plurality of active pillars; forming a bit line, the bit line extending along the second direction, in the second direction, the bit line connecting the plurality of active pillars at one end along the third direction; forming a word line plug, the word line plug being located on a side of the word line along the third direction close to the bit line and electrically contacting the word line, a normal projection of the word line plug on the substrate being located in the array region; and forming a bit line plug, the bit line plug being located on a side of the bit line along the third direction away from the active pillars and electrically contacting the bit line, a normal projection of the bit line plug on the substrate being located in the array region.

[0007] In some embodiments, the active pillar has a first end closer to the substrate along the third direction, and a second end farther from the substrate along the third direction; after forming the active pillar and the word line, before forming the bit line, a planarization process is performed to expose an end surface of the first end of the active pillar; forming the bit line includes forming the bit line at the first end of the active pillar.

[0008] In some embodiments, before performing the planarization process, further comprising: forming a contact structure at an end surface of the second end of the active pillar; providing a first wafer having a plurality of capacitors therein, one end of the capacitors being exposed to a surface of the first wafer; placing the first wafer opposite to the substrate so that the capacitors are in contact with the contact structure; and performing a bonding process to electrically contact the capacitors with the contact structure.

[0009] In some embodiments, the active pillar has a first end closer to the substrate along the third direction, and a second end farther from the substrate along the third direction; forming the bit line includes forming the bit line at the second end of the active pillar; after forming the word line plug and the bit line plug, further comprising: a planarization process to expose an end surface of the first end of the active pillar.

[0010] In some embodiments, after forming the word line plug and the bit line plug, before performing the planarization process, further comprising: providing a second wafer having a plurality of drive transistors therein, a surface of the second wafer having a pad electrically connected to one of a gate, a source or a drain of the drive transistors; placing the substrate opposite to the second wafer so that the word line plug or the bit line plug is in contact with the pad; and performing a bonding process to electrically contact the word line plug with the pad and to electrically contact the bit line plug with the pad.

[0011] In some embodiments, forming the bit line includes: forming a metal layer at an end surface of one end of the active pillar along the third direction; and performing a thermal treatment process to react a portion of the active pillar with the metal layer to form a metal compound layer as the bit line.

[0012] In some embodiments, the thermal treatment process includes a rapid thermal annealing process.

[0013] In some embodiments, a material of the metal layer includes cobalt, titanium, tungsten or tantalum.

[0014] In some embodiments, a dimension of a spacing between the word line plug and an adjacent active pillar in the first direction is 5-15 nm.

[0015] In some embodiments, after forming the bit line, before forming the word line plug, forming a first protection layer covering two opposite sides of the bit line in the first direction and covering two opposite sides of the active pillar in the first direction; forming a second protection layer covering surfaces of the first protection layer away from the bit line and covering surfaces of the first protection layer away from the active pillar, a material of the second protection layer being different from a material of the first protection layer; forming the word line plug includes forming the word line plug between the second protection layers of adjacent sides of the active pillar.

[0016] In some embodiments, forming the word line plug and the bit line plug includes forming a fill layer filling gaps between the active pillars and covering surfaces of the bit line away from the active pillars; patterning the fill layer to form a word line plug hole and a bit line plug hole, a footprint of the word line plug hole overlapping a footprint of the word line in a plane where the first direction and the second direction lie, a footprint of the bit line plug hole overlapping the bit line; filling the word line plug hole to form the word line plug and filling the bit line plug hole to form the bit line plug.

[0017] In some embodiments, forming the word line plug hole includes forming a first word line plug hole and a second word line plug hole, the first word line plug hole being located on a side of the bit line away from the active pillar in the third direction, a dimension of the first word line plug hole in the first direction being greater than or equal to a spacing between adjacent active pillars; forming a second word line plug hole, the second word line plug hole being in communication with the first word line plug hole, the second word line plug hole being located between adjacent active pillars, a dimension of the second word line plug hole in the first direction being less than the dimension of the first word line plug hole; filling the first word line plug hole and the second word line plug hole to form the word line plug.

[0018] In some embodiments, providing the substrate and forming the active pillars and the word lines comprises: providing an initial substrate; forming a plurality of first trenches extending along the first direction and a plurality of second trenches extending along the second direction in the initial substrate, the initial substrate remaining between the first trenches and the second trenches as the active pillars, the initial substrate remaining at the bottom of the first trenches and the second trenches as the substrate; forming an insulating layer filling the first trenches and the second trenches; patterning the insulating layer to form a plurality of word line trenches extending along the first direction, the word line trenches exposing sidewalls of a plurality of the active pillars; and filling the word line trenches to form the word lines.

[0019] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages.

[0020] The semiconductor structure manufacturing method provided by the embodiments of the present disclosure forms the active pillars extending along the third direction and arranged along the first direction and the second direction, so that the transistor structures formed thereby are arranged along the first direction and the second direction and extend along the third direction, and the transistor structures can not occupy too much area in the plane where the first direction and the second direction are located, so as to improve the arrangement density of the transistor structures and improve the space utilization of the semiconductor structure. The word lines formed thereby cover the sidewalls of a plurality of the active pillars along the first direction, and the bit lines formed thereby connect one end of a plurality of the active pillars along the second direction, so that the word lines and the bit lines can control a plurality of the transistor structures in the first direction and the second direction, respectively. The active pillars are located in the array region of the semiconductor structure, and the transistor structures formed correspondingly are located in the array region, and in the plane where the first direction and the second direction are located, the orthographic projection of the word line plug and the orthographic projection of the bit line plug are both located in the array region, that is, without changing the division of the array region and the peripheral region in the conventional semiconductor structure, the word line plug and the bit line plug are both arranged in the array region, so that the word line plug and the bit line plug can avoid occupying the space of the peripheral region, and the integration density of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which illustrate one or more embodiments. These examples do not limit the embodiments, unless otherwise explicitly indicated, and the figures are not necessarily to scale. In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the figures needed in the embodiments will be briefly introduced below. Obviously, the figures in the following description only represent some of the embodiments of the present disclosure, and those skilled in the art can obtain other figures from these figures without creative effort.

[0022] Figure 1This is a partial structural diagram of an array region of a semiconductor structure provided in an embodiment of this application;

[0023] Figure 2 This is a partial cross-sectional view of a first semiconductor structure provided in an embodiment of the present disclosure, along a direction parallel to the bit line.

[0024] Figure 3 This is a partial cross-sectional view of a first semiconductor structure provided in an embodiment of the present disclosure, along a direction parallel to the word line.

[0025] Figure 4 This is a partial cross-sectional view of a second semiconductor structure provided in an embodiment of the present disclosure, along a direction parallel to the bit line.

[0026] Figures 5 to 9 This is a partial cross-sectional view of various semiconductor structures provided in an embodiment of the present disclosure along a direction parallel to the word line.

[0027] Figure 10 This is a partial cross-sectional view of a seventh semiconductor structure provided in an embodiment of the present disclosure, along a direction parallel to the word line.

[0028] Figure 11 for Figure 10 A partial top view of the corresponding semiconductor structure along a third direction;

[0029] Figures 12 to 18 A partial top view along a third direction of various semiconductor structures provided in an embodiment of this disclosure;

[0030] Figures 19 to 27 This is a schematic diagram of the various steps of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0031] This disclosure provides a semiconductor structure that at least helps to improve the integration density of the semiconductor structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The semiconductor structure provided in this embodiment will now be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a partial structural diagram of an array region of a semiconductor structure provided in an embodiment of this application.

[0034] refer to Figure 1The semiconductor structure comprises: a plurality of active pillars 100, word lines 200, bit lines 300, a word line plug 201 and a bit line plug 301. The active pillars 100 are arranged along a first direction X and a second direction Y, and extend along a third direction Z; the word lines 200 extend along the first direction X, and cover sidewalls of the plurality of active pillars 100 along the first direction X; the bit lines 300 extend along the second direction Y, and connect one end of the plurality of active pillars 100 along the third direction Z; the word line plug 201 is located on a side of the word line 200 along the third direction Z close to the bit line 300, and is in electrical contact with the word line 200; and the bit line plug 301 is located on a side of the bit line 300 along the third direction Z away from the active pillars 100, and is in electrical contact with the bit line 300.

[0035] The active pillars 100 extend along the third direction Z and are arranged along the first direction X and the second direction Y, so that a transistor structure arranged along the first direction X and the second direction Y is formed, and the transistor structure extends along the third direction Z. In the plane of the first direction X and the second direction Y, the transistor structure can not occupy too much area, so as to improve the arrangement density of the transistor structure and improve the space utilization of the semiconductor structure. The word lines 200 cover the sidewalls of the plurality of active pillars 100 along the first direction X, and the bit lines 300 connect one end of the plurality of active pillars 100 along the second direction Y, so that the word lines 200 and the bit lines 300 can control a plurality of transistor structures along the first direction X and the second direction Y, respectively.

[0036] In some embodiments, the semiconductor structure can have an array region and a peripheral region. The array region is used to form an array of transistor structures, and the peripheral region is used to form a circuit structure for controlling the transistor structures. The active pillars 100 are located in the array region of the semiconductor structure, and the corresponding transistor structures are located in the array region. In the plane of the first direction X and the second direction Y, the orthographic projection of the word line plug 201 and the orthographic projection of the bit line plug 301 are both located in the array region. That is, the word line plug 201 and the bit line plug 301 are both arranged in the array region without changing the division of the array region and the peripheral region in a conventional semiconductor structure. In this way, the word line plug 201 and the bit line plug 301 can avoid occupying the space of the peripheral region, and the integration density of the semiconductor structure can be improved.

[0037] It should be noted that, Figure 1The shapes of the active post 100, word line 200, bit line 300, word line plug 201, and bit line plug 301 shown do not constitute a limitation on the active post 100, word line 200, bit line 300, word line plug 201, and bit line plug 301. The shapes of the active post, word line, bit line, word line plug, and bit line plug can be designed according to actual conditions. For example, the shape of the active post can be a cylinder, elliptical cylinder, square prism, or polygonal prism; the shape of the word line can be a cylinder, elliptical cylinder, square prism, or polygonal prism; the shape of the bit line can be a cylinder, elliptical cylinder, square prism, or polygonal prism; the shape of the word line plug can be a cylinder, elliptical cylinder, square prism, or polygonal prism; and the shape of the bit line plug can be a cylinder, elliptical cylinder, square prism, or polygonal prism.

[0038] Figure 2 This is a partial cross-sectional view of a first semiconductor structure provided in an embodiment of the present disclosure, along a direction parallel to the bit line. Figure 3 This is a partial cross-sectional view of a first semiconductor structure provided in an embodiment of the present disclosure, along a direction parallel to the word line.

[0039] refer to Figure 2 and Figure 3 In some embodiments, the active pillar 100 may include a first doped region 101, a channel region 103, and a second doped region 102 arranged sequentially along a third direction Z. The word line 200 may cover the channel region 103 of the active pillar 100, and the bit line 300 may be electrically contacted with the first doped region 101 of the active pillar 100. In some embodiments, the bit line may also be electrically contacted with the second doped region of the active pillar, with a corresponding bit line plug located on the side of the bit line away from the second doped region along a third direction, and a word line plug located on the side of the word line closer to the second doped region along a third direction.

[0040] The first doped region 101 and the second doped region 102 may contain P-type or N-type doped ions. For example, N-type ions may specifically be phosphorus ions, arsenic ions, or antimony ions; and P-type ions may specifically be boron ions, indium ions, or gallium ions.

[0041] The material of the active pillar 100 may include semiconductor materials such as silicon, gallium arsenide, silicon carbide, or gallium nitride.

[0042] The material of the active pillar 100 may also include at least one of IGZO (indium gallium zinc oxide), IWO (indium tungsten oxide), or ITO (indium tin oxide).

[0043] The material of the word line 200 can include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0044] In some embodiments, a gate dielectric layer can also be included between the word line and the sidewall of the active pillar. The material of the gate dielectric layer can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material, or a combination thereof.

[0045] In some embodiments, the word line can also only cover a portion of the sidewall of the active pillar along one side in the second direction. Figure 1 In some embodiments, the word line can also only cover a portion of the sidewall of the active pillar along one side in the second direction.

[0046] The material of the bit line 300 can include a single metal, a metal compound, or an alloy. The single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc. The metal compound can be tungsten nitride, tantalum nitride, or titanium nitride. The alloy can be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0047] The material of the word line plug 201 can include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

[0048] In some embodiments, the material of the word line plug 201 can be the same as or different from the material of the word line 200.

[0049] The material of the bit line plug 301 can include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

[0050] In some embodiments, the material of the bit line plug 301 can be the same as or different from the material of the bit line 300.

[0051] Figure 4 A local cross-sectional structure schematic view of a second semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the bit line direction; Figure 5 A local cross-sectional structure schematic view of a second semiconductor structure provided by an embodiment of the present disclosure along a direction parallel to the word line direction.

[0052] Reference is made to Figure 4 and Figure 5In some embodiments, the semiconductor structure can further include a capacitor 400 extending along the third direction Z, the capacitor 400 being located at a side of the active pillar 100 away from the bit line 300 along the third direction Z and electrically connected with the active pillar 100. In this way, the transistor structure and the corresponding capacitor 400 can constitute a memory cell, and the word line 200 and the bit line 300 can be used for storing or reading the memory cell. In addition, the capacitor 400 and the word line plug 201 are respectively located at two ends of the active pillar, and the capacitor 400 and the bit line plug 302 are respectively located at two ends of the active pillar, which improves the space utilization of the semiconductor structure and can also avoid the problem of parasitic capacitance or leakage caused by the too close distance between the word line plug 201 or the bit line plug 301 and the capacitor 400, thereby improving the stability of the semiconductor structure.

[0053] In some embodiments, the capacitor can include an upper plate, a dielectric layer and a lower plate stacked in sequence, wherein the lower plate extends along the third direction and is electrically connected with one end of the active pillar away from the bit line; the dielectric layer covers the side surface of the lower plate and the surface of the lower plate away from the active pillar along the third direction; and the upper plate covers the surface of the dielectric layer away from the upper plate.

[0054] In some embodiments, the lower plate can be directly in electrical contact with the active pillar to electrically connect the capacitor with the active pillar. In some embodiments, the capacitor can further include a contact structure located between the lower plate and the active pillar, and the capacitor is electrically connected with the active pillar through the contact structure, which is conducive to reducing the contact resistance between the lower plate and the active pillar and improving the signal transmission efficiency.

[0055] The material of the upper plate and the lower plate can include at least one of nickel-platinum, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride or ruthenium.

[0056] The material of the dielectric layer can include silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide or barium strontium titanate and other high dielectric constant materials.

[0057] The material of the contact structure can include copper, silver, gold, tungsten, tin or lead.

[0058] In some embodiments, the semiconductor structure can further include a drive transistor located at a side of the word line plug away from the word line along the third direction and at a side of the bit line plug away from the bit line along the third direction, and one of the gate, the source or the drain of the drive transistor is electrically connected with the word line plug or the bit line plug. In this way, the drive transistor and the capacitor can be respectively located at two ends of the active pillar, the memory cell and the drive transistor are arranged along the third direction, and the drive transistor can not occupy an area in the plane formed by the first direction and the second direction, which is conducive to improving the space utilization of the semiconductor structure.

[0059] It should be noted that in the provided drawings of the embodiments, the angle between the first direction X and the second direction Y is 90°, and the angle between the plane on which the first direction X and the second direction Y are located and the third direction Z is 90°. In some embodiments, the angle between the first direction and the second direction can be 30°, 45°, or 60°, and the angle between the plane on which the first direction and the second direction are located and the third direction can be 30°, 45°, or 60°. The embodiments do not constitute a limitation on the angle between the first direction, the second direction, and the third direction.

[0060] Figure 6 A schematic diagram of a partial cross-sectional structure of a third semiconductor structure along a direction parallel to the word line direction is provided for an embodiment of the present disclosure.

[0061] Reference Figure 6 In some embodiments, the word line plug 201 can include a first portion 221 and a second portion 211 connected in sequence, the first portion 221 is located between adjacent active pillars 100 and in electrical contact with the word line 200, and the second portion 211 is located on the side of the first portion 221 away from the word line 200 along the third direction Z. In the first direction X, the size of the first portion 221 is smaller than the size of the second portion 211. In this way, the end surface area of the word line plug 201 away from the word line 200 along the third direction Z is larger than the end surface area of the word line plug 201 close to the word line 200 along the third direction Z, which is conducive to improving the contact window of the word line plug 201 for electrical connection with other devices, avoiding the problem of disconnection of the word line plug, and improving the stability of the semiconductor structure.

[0062] In some embodiments, in the first direction X, the size of the spacing between the first portion 221 and the adjacent active pillars 100 is 5nm-15nm, for example, it can be 5nm, 5.4nm, 6nm, 6.6nm, 7nm, 7.5nm, 8nm, 9.3nm, 10.2nm, 11.6nm, 12.8nm, 13.7nm, 14.5nm, or 15nm, etc. Since the first portion 221 is located between the first doped regions 101 of adjacent active pillars 100, in order to avoid the problem of leakage between the first portion 221 and the first doped regions 101 of the active pillars 100, the width of the first portion 221 needs to be within an appropriate range.

[0063] For example, in the first direction X, the width of the first portion 221 can be 20nm-30nm, for example, 20nm, 22nm, 25nm, 27nm, 29nm, or 30nm.

[0064] The material of the first portion 221 and the material of the second portion 211 can each include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

[0065] In some embodiments, the material of the first part 221 can be different from the material of the second part 211, so that the material with lower contact resistance to the word line 200 can be selected to make the first part 221, and the material with higher conductivity can be selected to make the second part 211, so as to reduce the contact resistance between the word line plug 201 and the word line 200 and improve the signal transmission efficiency of the word line plug 201.

[0066] In some embodiments, the material of the first part 221 can also be the same as the material of the second part 211.

[0067] Figure 7 A schematic diagram of a partial cross-sectional structure of a fourth semiconductor structure along a direction parallel to the word line is provided for an embodiment of the present disclosure.

[0068] Reference Figure 7 In some embodiments, the semiconductor structure can further include a protective layer 500, the protective layer 500 covers two opposite sides of the plurality of active pillars 100 along the first direction X and covers two opposite sides of the bit line 300 along the first direction X, and the word line plug 201 is located between the protective layers 500 of the two adjacent active pillars 100. In this way, the short circuit problem between the word line plug 201 and the bit line 300 can be avoided, and the stability of the semiconductor structure can be improved.

[0069] Figure 8 A schematic diagram of a partial cross-sectional structure of a fifth semiconductor structure along a direction parallel to the word line is provided for an embodiment of the present disclosure.

[0070] Reference Figure 8 In some embodiments, the protective layer 500 can further include a first protective layer 501 covering two opposite sides of the bit line 300 along the first direction X and covering two opposite sides of the end of the active pillar 100 close to the bit line 300 along the first direction X, and a second protective layer 502 covering the surface of the first protective layer 501 away from the bit line 300 and covering the surface of the first protective layer 501 away from the active pillar 100, and the word line plug 201 is located between the second protective layers 502 of the two adjacent active pillars 100, wherein the material of the first protective layer 501 is different from the material of the second protective layer 502. In this way, when the word line plug 201 is formed between the adjacent bit line 300 and the active pillar 100, the second protective layer 502 can be used as an etching stop layer to avoid the side surface of the bit line 300 or the side surface of the end of the active pillar 100 close to the bit line being damaged by etching during the etching process, and the subsequently formed word line plug 201 will not contact the active pillar 100 or the bit line 300, avoiding the problems of leakage or short circuit, and improving the stability of the semiconductor structure.

[0071] The material of the first protective layer 501 and the second protective layer 502 can include silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0072] Figure 9 A sixth semiconductor structure provided by an embodiment of the present disclosure is shown in a schematic view of a partial cross-sectional structure along a direction parallel to the word line.

[0073] In some embodiments, the size of the bit line plug 301 along a direction perpendicular to the second direction Y can be greater than the size of the bit line 300. The bit line plug 301, the bit line 300, and the active pillar 100 are arranged along a third direction Z, so that the size of the bit line plug 301 can not be affected by the size of the active pillar 100 or the bit line 300. The size of the bit line plug 301 being greater than the size of the bit line 300 without affecting the word line plug 201 can facilitate the electrical connection of the bit line plug 301 with other devices, improve the contact window of the bit line plug 301 with other structures, and thus improve the efficiency of signal transmission.

[0074] For example, the size of the bit line plug 301 along a direction perpendicular to the second direction Y can be 20 nm to 30 nm, such as 20 nm, 22 nm, 25 nm, 27 nm, 29 nm, or 30 nm.

[0075] The size of the bit line plug 301 along the second direction Y can not be affected by the size of the bit line 300, but the size of the bit line plug 301 still needs to be within an appropriate range to avoid the size of the bit line plug 301 being too large to affect other device structures. For example, the size of the bit line plug 301 along the second direction Y can be 60 nm to 65 nm, specifically 60 nm, 61 nm, 62 nm, 62.5 nm, 63 nm, 64 nm, or 65 nm.

[0076] In some embodiments, the size of the bit line plug along a direction perpendicular to the second direction can also be less than or equal to the size of the bit line.

[0077] In some embodiments, the bit line plug 301 and the word line plug 201 can be arranged in a staggered manner along the first direction X and the second direction Y. Figure 1 For example, the bit line plug 301 is arranged in alignment along the first direction X, and the word line plug 201 is arranged in a staggered manner along the second direction Y in the plane along the first direction X and the second direction Y.

[0078] In some embodiments, adjacent bit line plugs 301 can also be arranged in a staggered manner along the first direction X.

[0079] In some embodiments, adjacent word line plugs 201 can also be arranged in alignment along the second direction Y.

[0080] Figure 10A seventh semiconductor structure provided by an embodiment of the present disclosure is shown in a schematic view of a partial cross-sectional structure along a direction parallel to the word lines; Figure 11 For Figure 10 A corresponding semiconductor structure is shown in a partial top view along a third direction. Figures 12 to 18 A plurality of semiconductor structures provided by an embodiment of the present disclosure are shown in partial top views along a third direction.

[0081] With reference to Figure 10 And Figure 11 In some embodiments, the semiconductor structure can further include a dummy bit line 202 extending along the second direction Y, the dummy bit line 202 being located at the outermost side of the plurality of bit lines 300 arranged along the first direction X, and a footprint of the word line plug 201 overlaps a footprint of the dummy bit line 202 in a plane along the first direction X and the second direction Y. In this way, the size of the word line plug 201 can not be affected by the distance between adjacent active pillars 100, which is conducive to increasing the size of the word line plug 201 to reduce the contact resistance of the word line plug 201, and the bit line plug 301 can be far away from the word line plug 201 to avoid the problem of parasitic capacitance or short circuit between the word line plug 201 and the bit line plug 301.

[0082] It should be noted that the dummy bit line 202 and the bit line 300 are prepared by the same process, but in the present embodiment, the dummy bit line 202 is not electrically connected to other device structures, but only provides a formation area for the word line plug 201.

[0083] In some embodiments, along the first direction X, the width of the dummy bit line 202 is a first width W1, and the width of the bit line 300 is a second width W2, the first width W1 being greater than the second width W2 and less than twice the second width W2. In this way, in the plane along the first direction X and the second direction Y, the word line plug 201 still remains within the array region and can not occupy a large area, avoiding causing a space burden of the semiconductor structure, so as to be conducive to improving the integration density of the semiconductor structure.

[0084] In some embodiments, along the first direction X, the width W1 of the dummy bit line 202 can be 50-100 nm, for example, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0085] With reference to Figure 11 And Figure 12 In some embodiments, when the semiconductor structure includes the dummy bit line 202, the word line plug 201 is located at the end of the word line 200, and the word line plugs 201 of the plurality of word lines 200 can be arranged in alignment along the second direction Y, wherein the bit line plug 301 can be as Figure 12In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, such that the bit line plugs 301 can be arranged at the end of the bit lines 300; or the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. Figure 11 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 12 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 11 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 12 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A.

[0086] In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 13 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A.

[0087] In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 14 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A.

[0088] In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 15 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 16 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 17 In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A.

[0089] In some embodiments, the bit line plugs 301 can be arranged in misalignment along the first direction X, as shown in FIG. 2B. In some embodiments, the bit line plugs 301 can be arranged in alignment along the first direction X, as shown in FIG. 2A. Figure 18 and Figure 6When the word line plug 201 includes the first portion 221 and the second portion 211, the size of the second portion 211 can also be greater than the size of the bit line 300 in the first direction X, so as to further increase the top surface area of the word line plug 201 and improve the electrical connection stability of the word line plug 201 with other device structures. In the actual design process of the semiconductor structure, in order to meet the design requirements of the miniaturized semiconductor structure, the word line plug 201 can also be designed to be smaller as shown in Figures 12 to 17 Thus, the distance between the word line plugs 201 is increased, the parasitic capacitance is reduced, and the risk of leakage between the word line plug 201 and the bit line plug 301 is reduced, and the delay is reduced.

[0090] In some embodiments, the word line plugs can also be staggered in the second direction, that is, every 2, 4 or 5 aligned word line plugs form a word line plug group, and the adjacent word line plug groups are staggered. Similarly, the bit line plugs can also be staggered in the first direction, that is, every 2, 3 or 6 aligned bit line plugs form a bit line plug group, and the adjacent bit line plug groups are staggered.

[0091] It can be understood that the arrangement of the word line plugs or the bit line plugs provided in the above embodiments can be combined arbitrarily without conflict to obtain new embodiments. In the actual design process of the semiconductor structure, the arrangement and size of the word line plug 201 and the bit line plug 301 can be adjusted comprehensively in combination with the above embodiments, so that the distance between the word line plug and the bit line plug is as large as possible to avoid the problem of leakage or parasitic capacitance between the word line plug and the bit line plug.

[0092] In the semiconductor structure provided in this embodiment, the active pillars 100 extend along a third direction Z and are arranged along a first direction X and a second direction Y. This facilitates the formation of transistor structures arranged along the first direction X and the second direction Y. Furthermore, the transistor structures extend along the third direction Z, and on the plane containing the first direction X and the second direction Y, the transistor structures do not occupy excessive area, thus improving the arrangement density of the transistor structures and increasing the space utilization of the semiconductor structure. Word lines 200 cover the sidewalls of the multiple active pillars 100 along the first direction X, and bit lines 300 connect one end of the multiple active pillars 100 along the second direction Y. Thus, word lines 200 and bit lines 300 can control multiple transistor structures respectively in the first direction X and the second direction Y. A semiconductor structure can have an array region and a peripheral region. The array region is used to form an array of transistor structures, and the peripheral region is used to form a circuit structure that controls the transistor structure. The active pillar 100 is located in the array region of the semiconductor structure, and the corresponding transistor structure is located in the array region. On the plane containing the first direction X and the second direction Y, the orthographic projections of the word line plug 201 and the bit line plug 301 are both located in the array region. That is to say, without changing the division between the array region and the peripheral region in a conventional semiconductor structure, the word line plug 201 and the bit line plug 301 are both set in the array region. This can avoid the word line plug 201 and the bit line plug 301 occupying the space of the peripheral region, which is beneficial to improving the integration density of the semiconductor structure.

[0093] Another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, which can be used to form the above-described semiconductor structure to improve the integration density of the semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated in detail below. The semiconductor structure manufacturing method provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0094] Figures 19 to 27 This is a schematic diagram showing the structural steps corresponding to each step of a method for manufacturing a semiconductor structure, as provided in another embodiment of this disclosure. Figures 20 to 27 for Figure 19 Schematic diagram of cross-sectional structure along the AA1 and BB1 directions.

[0095] refer to Figures 19 to 27 The manufacturing methods of semiconductor structures include:

[0096] refer to Figure 19The base 110 is provided, and the base 110 includes an array region and a peripheral region. The array region is used to form the array-arranged transistor structures. The peripheral region is used to form the circuit structure for controlling the transistor structures. A plurality of active pillars 100 are formed on the array region of the base 110. The active pillars 100 are arranged along a first direction X and a second direction Y. The active pillars 100 extend along a third direction Z. The active pillars 100 include a first doped region 101, a channel region 103, and a second doped region 102 arranged in sequence along the third direction Z.

[0097] It should be noted that only the array region of the base 110 is shown in the Figure 19 The peripheral region of the base 110 can also have other structures. The embodiments are not limited to the structure of the peripheral region.

[0098] In some embodiments, the base 110 can be a silicon base, a silicon-germanium base, a gallium arsenide base, a silicon carbide base, or a gallium nitride base, etc.

[0099] The material of the active pillar 100 can include a semiconductor material such as silicon, gallium arsenide, silicon carbide, or gallium nitride, etc.

[0100] The material of the active pillar 100 can also be at least one of IGZO, IWO, or ITO.

[0101] In some embodiments, providing the base 110 and forming the active pillar 100 can include: providing an initial base 120; forming a plurality of first grooves 111 extending along the first direction X and a plurality of second grooves 112 extending along the second direction Y in the initial base 120. The remaining initial base 120 between the first grooves 111 and the second grooves 112 serves as the active pillar 100. The remaining initial base 120 at the bottom of the first grooves 111 and the second grooves 112 serves as the base 110. In this way, the material of the base 110 can be the same as the material of the active pillar 100.

[0102] In some embodiments, providing the base and the active pillar can also include: forming a semiconductor layer on the base, and patterning the semiconductor layer to form the active pillar. In this way, the material of the active pillar can be different from the material of the base.

[0103] In some embodiments, chamfering processing can be performed on the corners of the active pillar after the active pillar is formed, so as to avoid the problem of sharp discharges at the corners of the active pillar.

[0104] After the active pillar 100 is formed, the first doped region 101 and the second doped region 102 can be doped to have P-type or N-type doping ions, for example, the N-type ions can be phosphorus ions, arsenic ions, or antimony ions; and the P-type ions can be boron ions, indium ions, or gallium ions.

[0105] In some embodiments, the first trench 111 can have a depth in the initial substrate 120 that is less than a depth of the second trench 112 in the initial substrate 120. In some embodiments, the first trench can also have a depth in the initial substrate that is greater than or equal to a depth of the second trench in the initial substrate.

[0106] Referring to Figure 20 The word lines 200 are formed, the word lines 200 extend along the first direction X, in the first direction X, the word lines 200 cover the channel region 103 sidewalls of the plurality of active pillars 100, and the insulating layer 130 is filled between adjacent word lines 200 and between adjacent active pillars 100.

[0107] In some embodiments, forming the word lines can include forming an insulating layer, the insulating layer filling the first trench and the second trench; patterning the insulating layer to form a plurality of word line trenches extending along the first direction, the word line trenches exposing the channel region sidewalls of the plurality of active pillars; forming a gate dielectric layer, the gate dielectric layer covering the channel region surfaces of the active pillars; filling the word line trenches to form the word lines; and reforming the insulating layer on top surfaces of the word lines.

[0108] The material forming the insulating layer can include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0109] The material forming the gate dielectric layer can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material, or a combination thereof.

[0110] The material forming the word lines 200 can include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0111] Referring to Figure 21 The bit lines 300 are formed, the bit lines 300 extend along the second direction Y, in the second direction Y, the bit lines Y connect the plurality of active pillars 100 at one end along the third direction Z.

[0112] Referring to Figure 20 With the end of the active pillar 100 along the third direction Z close to the substrate 110 as the first end (i.e., the end of the second doped region 102 away from the channel region 103), and the end of the active pillar 100 along the third direction Z away from the substrate 110 as the second end (i.e., the end of the first doped region 101 away from the channel region 103).

[0113] In some embodiments, after forming the active pillar 100 and the word line 200, before forming the bit line 300, a planarization process is performed to remove the substrate 110 to expose the end surface of the first end of the active pillar 100, and then the bit line 300 is formed at the first end of the active pillar 100, i.e., the bit line 300 is located at the end surface of the second doped region 102. The planarization process can remove the substrate 110 at the first end of the active pillar 100, and also remove the insulating layer (shallow trench isolation structure) between the bottoms of the active pillars 100, so that the height of the bit line 300 can be reduced in subsequent formation, to avoid the formation of air gaps in the bit line 300.

[0114] In some embodiments, the planarization process can adopt a chemical mechanical polishing process.

[0115] In some embodiments, forming the bit line 300 can include: removing part of the thickness of the active pillar 100 (i.e., part of the second doped region); forming a metal layer at the end surface of the first end of the active pillar 100; and performing a heat treatment process to react the part of the active pillar 100 with the metal layer to form a metal compound layer as the bit line 300. The heat treatment process can reduce the contact resistance between the bit line 300 and the active pillar 100.

[0116] In some embodiments, the heat treatment process includes a rapid thermal annealing process.

[0117] In some embodiments, the material of the metal layer can be a single metal, a metal compound, or an alloy. The single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc. The metal compound can be tungsten nitride, tantalum nitride, or titanium nitride. The alloy can be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0118] In some embodiments, the metal layer can also be directly used as the bit line.

[0119] Reference Figure 22 The word line plug 201 is located at the side of the word line 200 close to the bit line 300 along the third direction Z, and the bit line plug 301 is located at the side of the bit line 300 away from the active pillar 100 along the third direction Z, i.e., the word line plug 201 and the bit line plug 301 are both close to the first end of the active pillar 100.

[0120] In some embodiments, forming the word line plug 201 and the bit line plug 301 includes: forming the fill layer 140 on surfaces of the bit line 300 distal to the active pillar 100 and on surfaces of the insulating layer 130; patterning the fill layer 140 and the insulating layer 130 to form a word line plug hole 203 and a bit line plug hole 303, a footprint of the word line plug hole 203 overlaps a footprint of the word line 200 in a plane in which the first direction X and the second direction Y lie, a footprint of the bit line plug hole 303 overlaps the bit line 300, the word line plug hole 203 exposes a surface of the word line 200 proximate to the first end of the active pillar 100 along the third direction Z, and the bit line plug hole 303 exposes a surface of the bit line 300 proximate to the first end of the active pillar 100 along the third direction Z; filling the word line plug hole 203 to form the word line plug 201, and filling the bit line plug hole 303 to form the bit line plug 301.

[0121] The material forming the fill layer 140 can include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0122] The material forming the word line plug 201 can include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

[0123] The material forming the bit line plug 301 can include one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.

[0124] In some embodiments, in the first direction X, a dimension of a spacing between the word line plug 201 and an adjacent active pillar 100 can be 5 nm to 15 nm, such as 5 nm, 5.4 nm, 6 nm, 6.6 nm, 7 nm, 7.5 nm, 8 nm, 9.3 nm, 10.2 nm, 11.6 nm, 12.8 nm, 13.7 nm, 14.5 nm, or 15 nm, etc.

[0125] In some embodiments, with reference to Figure 23After the bit line 300 is formed, before the word line plug 201 is formed, it can further include: removing the partial insulating layer 130 on the two sides of the bit line 300 along the first direction X and the partial insulating layer 130 on the two sides of the active pillar 100 along the first direction X; forming a first protective layer 501, the first protective layer 501 covering the two sides of the bit line 300 along the first direction X and covering the two sides of the active pillar 100 along the first direction X; forming a second protective layer 502, the second protective layer 502 covering the surface of the first protective layer 501 away from the bit line 300 and covering the surface of the first protective layer 501 away from the active pillar 100, the material of the second protective layer 502 being different from the material of the first protective layer 501. Forming the word line plug 201 includes: forming the word line plug 201 between the second protective layers 502 on the sides of the adjacent active pillars 100. In this way, when forming the word line plug hole, the second protective layer 502 can be used as an etching stop layer to avoid the sides of the bit line 300 or the sides of the active pillar 100 close to the bit line being damaged by etching during the etching process, and the formed word line plug 201 will not be in contact with the active pillar 100 or the bit line 300, avoiding the problems of leakage or short circuit, and improving the stability of the semiconductor structure.

[0126] The material of the first protective layer 501 and the material of the second protective layer 502 can both include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0127] In some embodiments, with reference to Figure 24In some embodiments, forming the word line plug hole 203 can include: forming a first word line plug hole 213, the first word line plug hole 213 is located at a side of the bit line 300 away from the active pillar 100 along the third direction Z, and in the first direction X, a size of the first word line plug hole 213 can be greater than or equal to a spacing between adjacent active pillars 100; forming a second word line plug hole 223, the second word line plug hole 223 is in communication with the first word line plug hole 213, and the second word line plug hole 223 is located between adjacent active pillars 100, and in the first direction X, a size of the second word line plug hole 223 is smaller than the size of the first word line plug hole 213; and filling the first word line plug hole 213 and the second word line plug hole 223 to form the word line plug 201. In this way, the word line plug 201 can include a first part 221 and a second part 211 connected in sequence, the first part 221 is located between adjacent active pillars 100 and electrically contacts the word line 200, and the second part 211 is located at a side of the first part 221 away from the word line 200 along the third direction Z, and in the first direction X, a size of the first part 221 is smaller than a size of the second part 211. The end surface area of the word line plug 201 away from the word line 200 along the third direction Z is greater than the end surface area of the word line plug 201 close to the word line 200 along the third direction Z, which can facilitate to improve the contact window of the word line plug 201 electrically connected with other devices, avoid the problem of disconnection of the word line plug 201, and improve the stability of the semiconductor structure.

[0128] In some embodiments, in the first direction X, a size of the spacing between the first part 221 and the adjacent active pillar 100 can be 5 nm to 15 nm, for example, can be 5 nm, 5.4 nm, 6 nm, 6.6 nm, 7 nm, 7.5 nm, 8 nm, 9.3 nm, 10.2 nm, 11.6 nm, 12.8 nm, 13.7 nm, 14.5 nm, or 15 nm, etc.

[0129] Reference Figure 25 In some embodiments, after forming the word line plug 201 and the bit line plug 301, the method can further include: providing a second wafer 150, the second wafer 150 has a plurality of driving transistors (not shown in the figure) therein, and a surface of the second wafer 150 has a pad 151 electrically connected with one of a gate, a source or a drain of the driving transistors; placing the second wafer 150 opposite to the word line plug 201 and the bit line plug 301, so that the word line plug 201 or the bit line plug 301 contacts the pad 151; and performing a bonding process, so that the word line plug 201 electrically contacts the pad 151, and the bit line plug 301 electrically contacts the pad 151.

[0130] The material of the pad 151 can include copper, silver, gold, tungsten, tin, lead, or the like. In some embodiments, the material of the pad 151 can be the same as the material of the word line plug 201 and / or the bit line plug 301, to facilitate the bonding process, to facilitate the electrical contact between the word line plug 201 and the pad 151, and / or to facilitate the electrical contact between the bit line plug 301 and the pad 151.

[0131] In some embodiments, the contact structure 170 can also be formed on the side end surface of the active pillar 100 away from the bit line 300 in the third direction Z, the contact structure 170 is located on the end surface of the second end of the active pillar 100 (i.e., the end surface of the first doped region 101), the first wafer 160 is provided, the first wafer 160 has a plurality of capacitors 400 therein, one end of the capacitor 400 is exposed to the surface of the first wafer 160, the first wafer 160 is placed opposite to the contact structure 170, so that the capacitor 400 is in contact with the contact structure 170, and the bonding process is performed to make the capacitor 400 in electrical contact with the contact structure 170.

[0132] In this way, the active pillar 100 and the corresponding capacitor 400 constitute a storage unit, and the drive transistor can control the conduction of the word line 200 and the bit line 300 through the word line plug 201 and the bit line plug 301 to read or store the storage unit. The storage unit and the drive transistor are arranged in the third direction Z, so that the storage unit and the corresponding drive transistor do not occupy too much area in the plane of the first direction X and the second direction Y, which is beneficial to improve the space utilization of the semiconductor structure.

[0133] The material of the contact structure 170 can include copper, silver, gold, tungsten, tin, lead, or the like.

[0134] Reference Figure 26 In some embodiments, the bit line 300 can also be formed on the second end of the active pillar 100 first, i.e., the bit line 300 is located on the end surface of the first doped region 101.

[0135] In some embodiments, forming the bit line 300 can include: removing part of the thickness of the active pillar 101 (i.e., part of the first doped region 101); forming a metal layer on the end surface of the second end of the active pillar 100; and performing a heat treatment process to react the part of the active pillar 100 with the metal layer to form a metal compound layer as the bit line 300.

[0136] The material of the metal layer can be a single metal, a metal compound, or an alloy. The single metal can be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, or the like; the metal compound can be tungsten nitride, tantalum nitride, or titanium nitride; and the alloy can be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0137] In some embodiments, the bit line can also be directly formed as a metal layer.

[0138] In some embodiments, forming the word line plug 201 and the bit line plug 301 can include: forming a fill layer 140 on the surface of the bit line 300 away from the active pillar 100 and on the surface of the insulating layer 130; patterning the fill layer 140 and the insulating layer 130 to form a word line plug hole 203 and a bit line plug hole 303, the word line plug hole 203 exposes the surface of the word line 200 along the third direction Z close to the first end of the active pillar 100, the bit line plug hole 303 exposes the surface of the bit line 300 along the third direction Z close to the first end of the active pillar 100, the projection of the word line plug hole 203 on the plane of the first direction X and the second direction Y overlaps with the projection of the word line 200 on the plane of the first direction X and the second direction Y, the projection of the bit line plug hole 303 on the plane of the first direction X and the second direction Y overlaps with the bit line 300; filling the word line plug hole to form the word line plug 201, and filling the bit line plug hole to form the bit line plug 301.

[0139] Reference Figure 27 In some embodiments, after forming the word line plug 201 and the bit line plug 301, a planarization process can also be performed to remove the substrate 110 to expose the end surface of the first end of the active pillar 100; a contact structure 170 can be formed on the end surface of the first end of the active pillar 100; a first wafer 160 can be provided, the first wafer 160 has a plurality of capacitors 400 therein, one end of the capacitor 400 is exposed to the surface of the first wafer 160; the first wafer 160 is placed opposite to the contact structure 170 so that the capacitor 400 is in contact with the contact structure 170; a bonding process is performed to make the capacitor 400 in electrical contact with the contact structure 170.

[0140] In some embodiments, a second wafer 150 can also be provided, the second wafer 150 has a plurality of drive transistors therein, the surface of the second wafer 150 has a pad 151 electrically connected to one of the gate, source or drain of the drive transistor; the second wafer 150 is placed opposite to the word line plug 201 and the bit line plug 301 so that the word line plug 201 or the bit line plug 301 is in contact with the pad 151; a bonding process is performed to make the word line plug 201 in electrical contact with the pad 151 and make the bit line plug 301 in electrical contact with the pad 151. In this way, the active pillar 100 and the corresponding capacitor 400 constitute a memory cell, and the drive transistor can control the conduction of the word line 200 and the bit line 300 through the word line plug 201 and the bit line plug 301 to read or store the memory cell. The memory cell and the drive transistor are arranged along the third direction Z, so that in the plane of the first direction X and the second direction Y, the memory cell and the corresponding drive transistor can not occupy too much area, which is conducive to improving the space utilization of the semiconductor structure.

[0141] The semiconductor structure manufacturing method provided by the embodiments of the present disclosure is used to form the active pillars 100 extending along the third direction Z and arranged along the first direction X and the second direction Y, so that the transistor structures formed thereby are arranged along the first direction X and the second direction Y and extend along the third direction Z, and the transistor structures can not occupy too much area in the plane formed by the first direction X and the second direction Y, so as to improve the arrangement density of the transistor structures and improve the space utilization of the semiconductor structure. The word lines 200 formed thereby cover the sidewalls of the plurality of active pillars 100 along the first direction X, and the bit lines 300 formed thereby connect one end of the plurality of active pillars 100 along the second direction Y, so that the word lines 200 and the bit lines 300 can control the plurality of transistor structures along the first direction X and the second direction Y, respectively. The active pillars 100 are located in the array region of the semiconductor structure, and the transistor structures formed thereby are located in the array region, and the orthographic projection of the word line plug 201 and the orthographic projection of the bit line plug 301 are both located in the array region in the plane formed by the first direction X and the second direction Y, that is, the word line plug 201 and the bit line plug 301 are both arranged in the array region without changing the division of the array region and the peripheral region in the conventional semiconductor structure, so that the word line plug 201 and the bit line plug 301 can avoid occupying the space of the peripheral region, and the integration density of the semiconductor structure can be improved.

[0142] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and various changes can be made in form and details in actual applications without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, Comprising: providing a substrate, the substrate comprising an array region; forming a plurality of active pillars on the array region, the active pillars arranged along a first direction and a second direction, the active pillars extending along a third direction; forming word lines extending along the first direction, the word lines covering sidewalls of a plurality of the active pillars along the first direction; forming bit lines extending along the second direction, the bit lines connecting a plurality of the active pillars at one end along the third direction along the second direction; forming a word line plug on a side of the word line proximate to the bit line along the third direction, the word line plug in electrical contact with the word line, a footprint of the word line plug on the substrate located in the array region; forming a bit line plug on a side of the bit line distal from the active pillars along the third direction, the bit line plug in electrical contact with the bit line, a footprint of the bit line plug on the substrate located in the array region.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein the active pillars have a first end proximate to the substrate along the third direction, the active pillars have a second end distal from the substrate along the third direction; after forming the active pillars and the word lines, before forming the bit lines, comprising: a planarization process to expose end surfaces of the first ends of the active pillars; forming the bit lines comprises forming the bit lines at the first ends of the active pillars.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein forming the bit lines comprises: forming a metal layer on end surfaces of the active pillars at one end along the third direction; performing a thermal treatment process to cause a portion of the active pillars to react with the metal layer to form a metal compound layer, the metal compound layer as the bit lines.

4. The method of manufacturing a semiconductor structure according to claim 3, wherein the thermal treatment process comprises a rapid thermal anneal process.

5. The method of manufacturing a semiconductor structure according to claim 3, wherein a material forming the metal layer comprises cobalt, titanium, tungsten, or tantalum.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein in the first direction, a dimension of a spacing between the word line plug and an adjacent active pillar is 5 nm to 15 nm.

7. The method of manufacturing a semiconductor structure according to claim 1, wherein after forming the bit lines, before forming the word line plug, comprising: forming a first protective layer covering two opposite sides of the bit line along the first direction, and covering two opposite sides of the active pillar along the first direction; forming a second protective layer covering a surface of the first protective layer distal from the bit line, and covering a surface of the first protective layer distal from the active pillar, a material of the second protective layer different from a material of the first protective layer; forming the word line plug comprises forming the word line plug between the second protective layers of the adjacent active pillar sides.

8. The method of manufacturing a semiconductor structure according to claim 1, wherein forming the word line plug and the bit line plug comprises: forming a fill layer filling gaps between the active pillars, and covering a surface of the bit line distal from the active pillars; patterning the fill layer to form a word line plug hole and a bit line plug hole, a footprint of the word line plug hole overlaps a footprint of the word line in a plane where the first direction and the second direction lie, a footprint of the bit line plug hole overlaps the bit line. filling the word line plug holes to form the word line plugs, and filling the bit line plug holes to form the bit line plugs.

9. The method of manufacturing a semiconductor structure according to claim 6, wherein The word line plug holes comprise: a first word line plug hole and a second word line plug hole, the first word line plug hole is located on a side of the bit line away from the active pillars along the third direction; the second word line plug hole is in communication with the first word line plug hole, and the second word line plug hole is located between adjacent active pillars, and the size of the second word line plug hole is smaller than the size of the first word line plug hole along the first direction.

10. The method of manufacturing a semiconductor structure according to claim 1, wherein providing the substrate and forming the active pillars and the word lines comprise: providing an initial substrate; forming a plurality of first grooves extending along the first direction and a plurality of second grooves extending along the second direction in the initial substrate, the initial substrate remaining between the first grooves and the second grooves as the active pillars, and the initial substrate remaining at the bottom of the first grooves and the second grooves as the substrate; forming an insulating layer, the insulating layer filling the first grooves and the second grooves; patterning the insulating layer to form a plurality of word line grooves extending along the first direction, the word line grooves exposing sidewalls of a plurality of the active pillars; filling the word line grooves to form the word lines.

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