Semiconductor structure and method for manufacturing the same

Abstract

An embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure includes: a substrate, and a plurality of active pillars located on the substrate, the plurality of active pillars being arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; wherein the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each active pillar group includes two active pillar columns arranged adjacent to each other along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate; a plurality of buried bit lines are located between two adjacent active pillar columns in the active pillar group and are electrically connected to each active pillar in the two adjacent active pillar columns, and two adjacent buried bit lines are separated by two adjacent active pillar columns in the two adjacent active pillar groups that belong to different active pillar groups.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] DRAM devices with vertical channel transistors typically include active pillars arranged in an array and multiple bit lines buried beneath the active pillars. As semiconductor structures continue to evolve toward miniaturization and high integration, the density of bit lines increases and their size shrinks, leading to a series of problems. Summary of the Invention

[0003] An embodiment of the present disclosure provides a semiconductor structure, comprising:

[0004] A substrate, and a plurality of active pillars located on the substrate, wherein the plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; wherein the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each active pillar group includes two active pillar columns arranged adjacent to each other along the first direction; and the first direction and the second direction intersect and are both parallel to a surface of the substrate;

[0005] A plurality of buried bit lines are located between two adjacent active pillar columns in the active pillar group and are electrically connected to each active pillar in the two adjacent active pillar columns. Two adjacent buried bit lines are separated by two adjacent active pillar columns belonging to different active pillar groups in the two adjacent active pillar groups.

[0006] In some embodiments, the semiconductor structure further includes: a plurality of bit line contacts, respectively arranged on both sides of the buried bit line along the first direction and electrically connected to the buried bit line, the bit line contacts being at least partially laterally embedded in active pillars located on both sides of the buried bit line along the first direction.

[0007] In some embodiments, the multiple active pillars of each active pillar column are arranged at intervals along the second direction, and the multiple bit line contacts are arranged at intervals along the second direction and correspondingly disposed within the multiple active pillars of the active pillar column.

[0008] In some embodiments, the orthographic projections of the active pillars on the surface of the substrate are symmetrically arranged along the first direction and the second direction; or,

[0009] A dimension of an end of the active pillar in the first direction close to the buried bit line in the second direction is greater than a dimension of an end of the active pillar in the first direction far from the buried bit line in the second direction.

[0010] In some embodiments, the semiconductor structure further comprises: a plurality of connecting portions located between lower portions of two active pillars arranged adjacent to each other along the second direction, and the lower portions of the plurality of active pillars arranged along the second direction are sequentially connected through the connecting portions;

[0011] The bit line contact portion is located within the plurality of active pillars and the plurality of connection portions and continuously extends along the second direction.

[0012] In some embodiments, the semiconductor structure further includes: a doped layer, at least partially located in the active pillar and at least surrounding a contact surface between the bit line contact portion and the active pillar.

[0013] In some embodiments, the semiconductor structure further comprises:

[0014] a first isolation structure located below the buried bit line and extending along the second direction, wherein the buried bit line covers the first isolation structure;

[0015] The second isolation structure is located between two adjacent active pillar groups and extends along the second direction, and the upper surface of the second isolation structure is higher than the upper surface of the buried bit line.

[0016] In some embodiments, a plurality of active pillar rows are arranged along the second direction; and the semiconductor structure further comprises:

[0017] A plurality of word lines are located above the buried bit lines. The plurality of word lines are arranged along the second direction, and each word line extends along the first direction. Each word line covers a portion of a sidewall of each active pillar in an active pillar row.

[0018] The present disclosure also provides a method for manufacturing a semiconductor structure, including:

[0019] providing a substrate;

[0020] forming a plurality of active pillars on a substrate;

[0021] forming a plurality of buried bit lines; wherein,

[0022] The plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each active pillar group includes two active pillar columns arranged adjacent to each other along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate;

[0023] The buried bit line is located between two adjacent active pillar columns in the active pillar group and is electrically connected to each active pillar in the two adjacent active pillar columns. The two adjacent buried bit lines are separated by two adjacent active pillar columns belonging to different active pillar groups in the two adjacent active pillar groups.

[0024] In some embodiments, a plurality of active pillars are formed on a substrate, comprising:

[0025] Etching the substrate to form a plurality of first trenches extending along the second direction on the substrate, wherein the first trenches define the substrate into a plurality of wall-like structures extending along the second direction; the plurality of first trenches include first sub-trenches and second sub-trenches alternately arranged in sequence along the first direction;

[0026] etching at least the wall-shaped structure to form a plurality of second trenches extending along a first direction in the substrate, wherein the first trenches and the second trenches intersect with each other to define a plurality of discrete active pillars in the substrate;

[0027] A plurality of buried bit lines are formed, including:

[0028] After forming the first trench and before or after forming the second trench, a buried bit line is formed in the first sub-trench, and the second sub-trench is located between two adjacent buried bit lines.

[0029] In some embodiments, before forming the buried bit line in the first sub-trench, the method further includes:

[0030] Bit line contacts are formed on both sides of the first sub-trench along a first direction, and the bit line contacts are at least partially laterally embedded in the active pillars or wall-shaped structures located on both sides of the first sub-trench.

[0031] In some embodiments, forming a bit line contact includes:

[0032] forming a first dielectric layer covering inner walls of the first sub-trench and the second sub-trench, and a first filling layer covering the first dielectric layer and filling the first sub-trench and the second sub-trench;

[0033] removing a portion of the first filling layer in the first sub-trench to a first position to expose the first dielectric layer above the first position;

[0034] forming a second dielectric layer, wherein the second dielectric layer covers the exposed sidewalls of the first dielectric layer and the upper surface of the remaining first filling layer;

[0035] removing the second dielectric layer covering the upper surface of the first filling layer and retaining the second dielectric layer covering the sidewalls of the first dielectric layer;

[0036] removing a portion of the first filling layer in the first sub-trench to a second position to expose the first dielectric layer between the first position and the second position;

[0037] removing the first dielectric layer between the first position and the second position to expose a portion of the active pillar or a portion of the wall-like structure, and retaining at least a portion of the first dielectric layer, wherein the retained first dielectric layer covers a sidewall of the first sub-trench above the first position;

[0038] Performing a lateral etching process on the first sub-trench located between the first position and the second position to form a first groove on both sides of the first sub-trench, wherein the first groove is located in the wall-shaped structure or at least partially in the active pillar, and the opening of the first groove faces the first sub-trench;

[0039] removing the remaining first dielectric layer above the first position in the first sub-trench;

[0040] A first conductive material is filled in the space between the first position and the second position of the first sub-trench and in the first groove, and an etching process is performed on the first conductive material to form a bit line contact portion, which is at least partially located in the first groove.

[0041] In some embodiments, after forming the first groove and before forming the buried bit line, the method further includes:

[0042] A doping layer is formed in the active pillar or the wall-shaped structure, and the doping layer surrounds the inner wall of the first groove.

[0043] In some embodiments, forming a doped layer in an active pillar or a wall-like structure includes:

[0044] doping a dopant into the first conductive material;

[0045] Before performing an etching process on the first conductive material to form a bit line contact portion, an annealing process is performed on the first conductive material doped with dopants, so that part of the dopants diffuse into the active pillar or the wall-shaped structure to form a doped layer.

[0046] In some embodiments, after forming the buried bit line, the method further includes:

[0047] A plurality of word lines are formed above the buried bit lines. The plurality of word lines are arranged along the second direction. Each word line extends along the first direction and covers a portion of the sidewall of each active pillar in an active pillar row.

[0048] In the embodiment of the present disclosure, a buried bit line is formed only between two adjacent active column columns in an active column group. Two active column columns arranged adjacent to each other along a first direction in an active column group share one buried bit line, and no buried bit line is formed between adjacent active column groups. In this way, the distance between adjacent buried bit lines is increased, thereby effectively reducing the coupling effect between the buried bit lines, while reducing the contact resistance of the buried bit lines and improving the performance of the semiconductor structure.

[0049] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0051] Figure 1 A schematic top view of a semiconductor structure provided for some embodiments of the present disclosure;

[0052] Figure 2 Some embodiments of the present disclosure follow Figure 1 Schematic diagram of the cross-sectional structure taken along lines A1A2 and B1B2;

[0053] Figure 3 Some embodiments of the present disclosure follow Figure 1 Schematic diagram of the cross-sectional structure taken along lines C1C2 and D1D2;

[0054] Figure 4 For other embodiments of the present disclosure, Figure 1 Schematic diagram of the cross-sectional structure taken along lines A1A2 and B1B2;

[0055] Figure 5 For other embodiments of the present disclosure, Figure 1 Schematic diagram of the cross-sectional structure taken along lines C1C2 and D1D2;

[0056] Figure 6 Some other embodiments of the present disclosure are as follows Figure 1 Schematic diagram of the cross-sectional structure taken along lines A1A2 and B1B2;

[0057] Figure 7 Some other embodiments of the present disclosure are as follows Figure 1 Schematic diagram of the cross-sectional structure taken along lines C1C2 and D1D2;

[0058] Figure 8 Schematic top views of semiconductor structures provided for other embodiments of the present disclosure;

[0059] Figure 9 A schematic top view of a semiconductor structure provided in accordance with some other embodiments of the present disclosure;

[0060] Figure 10 A schematic top view of a semiconductor structure provided in some further embodiments of the present disclosure;

[0061] Figure 11 A schematic top view of a semiconductor structure provided for some other embodiments of the present disclosure;

[0062] Figure 12Schematic top views of semiconductor structures provided for still other embodiments of the present disclosure;

[0063] Figure 13 A flowchart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0064] Figure 14 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 1 ;

[0065] Figure 15 A schematic top view of a semiconductor structure during the manufacturing process provided in some embodiments of the present disclosure Figure 2 ;

[0066] Figure 16 The semiconductor structure provided by some embodiments of the present disclosure is provided along the manufacturing process Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 3 ;

[0067] Figure 17 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 4 ;

[0068] Figure 18 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 5 ;

[0069] Figure 19 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 6 ;

[0070] Figure 20 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 7 ;

[0071] Figure 21 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-section taken along line C1C2 Figure 8 ;

[0072] Figure 22 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1The cross-sectional structure of the line C1C2 in FIG. Figure 9 ;

[0073] Figure 23 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 10 ;

[0074] Figure 24 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 10 one;

[0075] Figure 25 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 10 two;

[0076] Figure 26 The semiconductor structure provided by some embodiments of the present disclosure is provided along the manufacturing process Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 10 three;

[0077] Figure 27 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 The cross-sectional structure of the line C1C2 in FIG. Figure 10 Four;

[0078] Figure 28 A schematic top view of a semiconductor structure during the manufacturing process provided in some embodiments of the present disclosure Figure 10 five;

[0079] Figure 29 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2 Figure 10 six;

[0080] Figure 30 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines C1C2 and D1D2 Figure 10 seven;

[0081] Figure 31 A schematic top view of a semiconductor structure during the manufacturing process provided in other embodiments of the present disclosure Figure 10 eight;

[0082] Figure 32The semiconductor structure provided in some other embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2 Figure 10 Nine;

[0083] Figure 33 The semiconductor structure provided in some other embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines C1C2 and D1D2 Figure 2 ten;

[0084] Figure 34 The semiconductor structure provided in some other embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2 Figure 2 eleven;

[0085] Figure 35 The semiconductor structure provided in some other embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines C1C2 and D1D2 Figure 2 twelve;

[0086] Figure 36 The semiconductor structure provided in some other embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2 Figure 2 Thirteen;

[0087] Figure 37 The semiconductor structure provided in some other embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines C1C2 and D1D2 Figure 2 fourteen;

[0088] Figure 38 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2 Figure 2 fifteen;

[0089] Figure 39 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines C1C2 and D1D2 Figure 2 sixteen;

[0090] Figure 40 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2 Figure 2Seventeen;

[0091] Figure 41 The semiconductor structure provided in some embodiments of the present disclosure is manufactured along the Figure 1 Schematic diagram of the cross-sectional structure taken by lines C1C2 and D1D2 Figure 2 eighteen. DETAILED DESCRIPTION

[0092] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0093] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0094] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0095] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0096] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0097] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0098] As semiconductor structures continue to develop toward miniaturization and high integration, the density of bit lines increases and their size decreases, leading to a series of problems. For example, the coupling effect between bit lines increases due to the shortened distance between adjacent bit lines, resulting in increased signal crosstalk between adjacent bit lines. Furthermore, the miniaturization of the bit lines and active pillars leads to a decrease in the contact area between the bit lines and active pillars, increasing the contact resistance.

[0099] Based on this, the technical solution of the disclosed embodiment is proposed. In the disclosed embodiment, a buried bit line is formed only between two adjacent active pillar columns in an active pillar group. Two active pillar columns arranged adjacent to each other along a first direction in an active pillar group share a buried bit line, and no buried bit line is formed between adjacent active pillar groups. This increases the distance between adjacent buried bit lines, effectively reducing the coupling effect between the buried bit lines, while also reducing the contact resistance of the buried bit lines and improving the performance of the semiconductor structure.

[0100] To make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale than the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present disclosure.

[0101] The semiconductor structure provided by the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0102] like Figures 1 to 12 As shown, the semiconductor structure provided by the embodiment of the present disclosure includes: a substrate 10, and a plurality of active pillars 11 located on the substrate 10, wherein the plurality of active pillars 11 are arranged into a plurality of active pillar rows 111 extending along a first direction and a plurality of active pillar columns 112 extending along a second direction; wherein the plurality of active pillar columns 112 include a plurality of active pillar groups 20 arranged at intervals along the first direction, and each active pillar group 20 includes two active pillar columns 112 arranged adjacent to each other along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate 10;

[0103] A plurality of buried bit lines 17 are located between two adjacent active pillar columns 112 in the active pillar group 20 and are electrically connected to each active pillar 11 in the two adjacent active pillar columns 112. Two adjacent buried bit lines 17 are separated by two adjacent active pillar columns 112 in two adjacent active pillar groups 20 that belong to different active pillar groups 20.

[0104] In actual operation, the semiconductor structure provided by the embodiments of the present disclosure may be a dynamic random access memory (DRAM), such as a DRAM having vertical transistors. However, the present invention is not limited thereto and the semiconductor structure may also be any structure having vertical transistors.

[0105] In practice, substrate 10 may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, substrate 10 is a silicon substrate, which may be doped or undoped.

[0106] like Figure 1 as well as Figure 2As shown, in some embodiments, the semiconductor structure further includes a plurality of first trenches T1 and a plurality of second trenches T2, the plurality of first trenches T1 extending along the second direction in the substrate 10 and arranged at intervals along the first direction, the plurality of second trenches T2 extending along the first direction in the substrate 10 and arranged at intervals along the second direction, the first direction and the second direction are oblique or perpendicular, the plurality of first trenches T1 and the plurality of second trenches T2 intersect each other to define a plurality of active pillar rows 111 and a plurality of active pillar columns 112 in the substrate 10; wherein, the plurality of active pillar rows 111 are arranged along the second direction, and each active pillar row 111 includes a plurality of active pillars 11 arranged at intervals along the first direction; the plurality of active pillar columns 112 are arranged at intervals along the first direction, and each active pillar column 112 includes a plurality of active pillars 11 arranged along the second direction.

[0107] In some embodiments, the plurality of first trenches T1 include first sub-trenches T11 and second sub-trenches T12 alternately arranged along the first direction, the first sub-trench T11 being located between two adjacent active pillar columns 112 in each active pillar group 20 , and the second sub-trench T12 being located between two adjacent active pillar groups 20 .

[0108] like Figures 1 to 3 As shown, in some embodiments, the buried bit line 17 is located in the lower portion of the first sub-trench T11 and extends along the second direction within the first sub-trench T11, and adjacent buried bit lines are separated by two active pillar columns 112 belonging to different active pillar groups 20 and a second sub-trench T12 located between the two active pillar columns 112.

[0109] In the embodiment of the present disclosure, a buried bit line 17 is provided only between two adjacent active column columns 112 in an active column group 20. Two active column columns 112 arranged adjacent to each other along the first direction in one active column group 20 share one buried bit line 17, and no buried bit line 17 is formed between adjacent active column groups 20. In this way, the distance between adjacent buried bit lines 17 is increased, which can effectively reduce the coupling effect between the buried bit lines 17, thereby reducing the signal crosstalk between multiple buried bit lines 17, and at the same time reducing the contact resistance of the buried bit lines 17, thereby improving the performance of the semiconductor structure.

[0110] The buried bit line 17 can be a single-layer structure or a multi-layer structure. In some embodiments, the buried bit line 17 includes a main body 172 and a barrier layer 171 covering the outer sidewalls and bottom surface of the main body 172 . The main body 172 is located in a space defined by the barrier layer 171 .

[0111] In actual operation, the material of the blocking layer 171 can be a material that is conductive and can block metal diffusion, including but not limited to one or a combination of titanium nitride and tantalum nitride, which is used to block the material of the main body 172 from diffusing into the substrate 10 and the active column 11; the material of the main body 172 includes one or more of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum, such as tungsten.

[0112] like Figures 2 to 3 As shown, in some embodiments, the semiconductor structure further includes: a first isolation structure 191, located below the buried bit line 17 and extending along the second direction, and the buried bit line 17 covers the first isolation structure 191; a second isolation structure 192, located between two adjacent active column groups 20 and extending along the second direction, and the upper surface of the second isolation structure 192 is higher than the upper surface of the buried bit line 17.

[0113] Specifically, the first isolation structure 191 is located at the bottom of the first sub-trench T11, and is used to electrically isolate the buried bit line 17 and the substrate 10 to avoid leakage or short circuit; the second isolation structure 192 is located in the second sub-trench T12, and its upper surface is higher than the upper surface of the buried bit line 17, and is used to separate adjacent active column groups 20 and adjacent buried bit lines 17, further reducing the coupling effect between the buried bit lines 17.

[0114] In actual operation, the first isolation structure 191 and the second isolation structure 192 both include a first dielectric layer 12 and a first filling layer 13. The first dielectric layer 12 of the first isolation structure 191 covers part of the side walls and bottom surface of the first sub-trench T11, and the first dielectric layer 12 of the second isolation structure 192 covers part of the side walls and bottom surface of the second sub-trench T12. The first filling layer 13 is located in the space defined by the first dielectric layer 12.

[0115] In actual operation, the material of the first dielectric layer 12 includes but is not limited to nitride, such as silicon nitride; the material of the first filling layer 13 includes but is not limited to oxide, such as silicon oxide.

[0116] In some embodiments, the semiconductor structure further includes a second filling layer 18 located in the first sub-trench T11 . The second filling layer 18 extends along the second direction and covers the buried bit line 17 .

[0117] In actual operation, the second filling layer 18 can be a single-layer structure or a multi-layer structure. The material of the second filling layer 18 includes one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), etc., such as silicon oxide.

[0118] In some embodiments, the semiconductor structure further includes: a plurality of bit line contact portions 15, which are respectively arranged on both sides of the buried bit line 17 along the first direction and electrically connected to the buried bit line 17, and the bit line contact portions 15 are at least partially laterally embedded in the active pillars 11 located on both sides of the buried bit line 17 along the first direction. In this way, the buried bit line 17 is electrically connected to the active pillars 11 through the bit line contact portions 15, and there is a smaller contact resistance between the buried bit line 17 and the bit line contact portions 15 than between the buried bit line 17 and the active pillars 11, thereby further reducing the contact resistance of the buried bit line 17.

[0119] In practice, the material of the bit line contact portion 15 includes but is not limited to polysilicon, and the bit line contact portion 15 may be doped or undoped. In some specific embodiments, the bit line contact portion 15 is doped with a dopant, which may be one or more elements such as boron, phosphorus, and arsenic.

[0120] like Figures 2 to 5 As shown, in some embodiments, the semiconductor structure further includes: a plurality of connecting portions 21, located between the lower portions of two active pillars 11 arranged adjacent to each other along the second direction, and the lower portions of the plurality of active pillars 11 arranged along the second direction are sequentially connected through the connecting portions 21.

[0121] Among them, the bit line contact portion 15 can be completely embedded in the active pillar 11 and the connecting portion 21. For example, the side walls of the bit line contact portion 15 can be basically flush with the side walls of the active pillar 11 and the connecting portion 21, or slightly indented inward relative to the side walls of the active pillar 11 and the connecting portion 21; but not limited to this, the side walls of the bit line contact portion 15 can slightly protrude outward relative to the side walls of the active pillar 11 and the connecting portion 21; the upper surface of the buried bit line 17 is flush with the upper surface of the bit line contact portion 15 or higher than the upper surface of the bit line contact portion 15 to increase scenario applicability.

[0122] In actual operation, the depth of the second trench T2 can be less than the depth of the first trench T1, and the bottom surface of the second trench T2 can be higher than the upper surface of the buried bit line 17. The portion of the substrate 10 located below the second trench T2 is not etched to form a connecting portion 21. The lower portions of the multiple active pillars 11 arranged along the second direction and the connecting portion 21 located between the lower portions of two adjacent active pillars 11 constitute a structure extending continuously along the second direction.

[0123] In some embodiments, the bitline contact 15 is located within the plurality of active pillars 11 and the plurality of connecting portions 21 and extends continuously along the second direction. The bitline contact 15 is a continuous structure extending along the second direction, and a large contact area is provided between the buried bitline 17 and the bitline contact 15, as well as between the bitline contact 15 and the active pillars 11 and the connecting portions 21. This further reduces the contact resistance between the bitline contact 15 and the active pillars 11, and between the buried bitline 17 and the bitline contact 15.

[0124] In some embodiments, the semiconductor structure further includes a doped layer 16, at least a portion of which is located within the active pillar 11 and surrounds at least the contact surface between the bit line contact 15 and the active pillar 11. The presence of the doped layer 16 reduces the contact resistance between the bit line contact 15 and the active pillar 11, further improving the performance of the semiconductor structure.

[0125] In some embodiments, when the lower portions of multiple active pillars 11 arranged along the second direction are connected in sequence through connecting portions 21, the doping layer 16 is located within the multiple active pillars 11 and the multiple connecting portions 21 and extends continuously along the second direction, and the doping layer 16 surrounds the contact surface between the bit line contact portion 15 and the active pillars 11 and the connecting portions 21.

[0126] In actual operation, the dopant in the doping layer 16 can be one or more elements such as boron, phosphorus, and arsenic, and the dopant in the doping layer 16 can be the same as the dopant in the bit line contact portion 15. In some specific embodiments, the dopant in the doping layer 16 is phosphorus, and the doping concentration of phosphorus is greater than 1*E 20 atom / cm 3 , for example 2*E 20 atom / cm 3 、3*E 20 atom / cm 3 、5*E 20 atom / cm 3 、1*E 21 atom / cm 3 wait.

[0127] like Figures 1 to 3 As shown, in some embodiments, the semiconductor structure further includes: a plurality of word lines 23 located above the buried bit lines 17. The plurality of word lines 23 are arranged along the second direction, and each word line 23 extends along the first direction. Each word line 23 covers a portion of the sidewall of each active pillar 11 in an active pillar row 111. Furthermore, each word line 23 extends along the first direction and surrounds each active pillar 11 in an active pillar row 111. This helps to increase the driving capability of the word line 23 on the active pillar row 111.

[0128] In some embodiments, the semiconductor structure also includes: a third isolation structure 193, filling the lower portion of the second trench T2 and extending along the first direction, the third isolation structure 193 covers the connection portion 21, part of the second filling layer 18 and part of the second isolation structure 192 along the first direction, the word line 23 is located above the third isolation structure 193 and covers the third isolation structure 193, and the third isolation structure 193 is used to electrically isolate the word line 23 from the connection portion 21 and the word line 23 from the buried bit line 17.

[0129] But not limited to this, such as Figures 4 and 5 As shown, the third isolation structure 193 fills a portion of the lower portion of the second trench T2. The third isolation structure 193 is located between two adjacent first trenches T1 along the first direction and covers the connecting portion 21. The word line 23 covers the third isolation structure 193, a portion of the second filling layer 18, and a portion of the second isolation structure 192.

[0130] In actual operation, the third isolation structure 193 can be a single-layer structure or a multi-layer structure, and the material of the third isolation structure 193 includes one or more of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), etc., such as silicon nitride.

[0131] like Figure 1 As shown, in some embodiments, a second groove S2 is provided between two adjacent active pillars 11 of the active pillar row 111. In actual operation, the second groove S2 is formed by etching a portion of the second filling layer 18 and a portion of the second isolation structure 192. The second groove S2 is connected to the second trench T2. The word line 23 extends along the first direction in the second groove S2 and the second trench T2 and surrounds the multiple active pillars 11.

[0132] In some embodiments, the semiconductor structure further includes a gate dielectric layer 22, which is located at least between the word line 23 and the active pillar 11. In actual operation, the material of the gate dielectric layer 22 includes but is not limited to oxide, such as silicon oxide, and the gate dielectric layer 22 can be formed by performing an oxidation process on the sidewalls of the active pillar 11.

[0133] In some embodiments, the semiconductor structure further includes a fourth isolation structure 194 . The fourth isolation structure 194 covers the word lines 23 and fills the gaps between adjacent word lines 23 . The upper surface of the fourth isolation structure 194 is flush with the upper surface of the active pillar 11 .

[0134] In actual operation, the fourth isolation structure 194 may include a third filling layer 24 and a fourth filling layer 25. The third filling layer 24 extends along the first direction in the second groove S2 and the second trench T2 and covers the upper surface of the word line 23, and the upper surface of the third filling layer 24 is flush with the upper surface of the active pillar 11; the fourth filling layer 25 extends along the first direction in the second trench T2 and extends downward from the upper surface of the third filling layer 24 to pass through the word line 23, for spacing adjacent word lines 23 and adjacent third filling layers 24.

[0135] In actual operation, the materials of the third filling layer 24 and the fourth filling layer 25 may be the same or different. The materials of the third filling layer 24 and the fourth filling layer 25 include but are not limited to silicon nitride.

[0136] like Figures 2 to 3As shown, the semiconductor structure further includes: an insulating structure 26 located above the active pillar 11 and the fourth isolation structure 194. The insulating structure 26 has a plurality of discrete second openings K2 therein, and the second openings K2 expose the upper surface of the active pillar 11; and a contact plug 27 located within the second opening K2 and electrically connected to the upper surface of the active pillar 11. In subsequent processes, a capacitor structure electrically connected to the contact plug 27 may be formed on the contact plug 27, and the capacitor structure is used to store data.

[0137] In actual operation, the insulating structure 26 may include multiple first sublayers (not labeled) extending along the first direction, and multiple second sublayers (not labeled) extending along the second direction. The multiple first sublayers and the multiple second sublayers intersect with each other to form multiple second openings K2.

[0138] In actual operation, the material of the insulating structure 26 includes but is not limited to nitrides, such as silicon nitride; the contact plug 27 can be a single-layer or multi-layer structure, and the materials of the word line 23 and the contact plug 27 include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

[0139] Figures 2 to 5 The depth of the second trench T2 shown is less than the depth of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17. The lower parts of the multiple active pillars 11 arranged along the second direction are connected in sequence through the connecting parts 21. The bit line contact parts 15 and the doping layer 16 are located in the multiple active pillars 11 and the multiple connecting parts 21 and extend continuously along the second direction.

[0140] But not limited to this, such as Figures 6 and 7 As shown, in other embodiments of the present disclosure, the multiple active pillars 11 of each active pillar column 112 are arranged at intervals along the second direction, the multiple bit line contacts 15 are arranged at intervals along the second direction and are correspondingly arranged in the multiple active pillars 11 of the active pillar column 112, and the doping layer 16 is located in the active pillar 11 and surrounds the contact surface between the active pillar 11 and the bit line contact portion 15.

[0141] Specifically, the bottom surface of the second trench T2 is lower than the bottom surface of the buried bit line 17 , the third isolation structure 193 fills part of the lower portion of the second trench T2 , and in the second direction, the lower portions of adjacent active pillars 11 are separated by the third isolation structure 193 .

[0142] Among them, the bit line contact portion 15 can be completely embedded in the active pillar 11. For example, the side wall of the bit line contact portion 15 can be basically flush with the side wall of the active pillar 11, or slightly indented inward relative to the side wall of the active pillar 11; but not limited to this, the side wall of the bit line contact portion 15 can slightly protrude outward relative to the side wall of the active pillar 11 to increase scenario applicability.

[0143] like Figures 6 and 7 As shown, in some embodiments, the third isolation structure 193 fills a portion of the lower portion of the second trench T2, the third isolation structure 193 is located between two adjacent first trenches T1 in the first direction and covers a portion of the substrate 10, and the word line 23 covers the third isolation structure 193, a portion of the second filling layer 18, and a portion of the second isolation structure 192.

[0144] like Figure 8 As shown, in some embodiments, the projection of the buried bit line 17 in the second direction can partially overlap with the projection of the active pillar 11 in the second direction. In this way, when the multiple active pillars 11 of each active pillar column 112 are arranged at intervals along the second direction, the contact area between the buried bit line 17 and the active pillar 11 or the bit line contact portion 15 can be increased, thereby further reducing the contact resistance of the buried bit line 17.

[0145] In actual operation, this can be achieved by increasing the width of the first trench T1 when forming the first trench T1, so that the first trench T1 exposes the end portions of the active pillars 11 located on both sides thereof. In this way, the area of ​​the side walls of the active pillars 11 exposed by the first trench T1 is larger. For example, in addition to exposing the side walls of the active pillars 11 in the first direction, the first trench T1 can also expose part of the side walls of the active pillars 11 in the second direction, so that the finally formed buried bit lines 17 can not only contact the side walls of the active pillars 11 or the bit line contact portions 15 in the first direction, but also contact part of the side walls of the active pillars 11 or the bit line contact portions 15 in the second direction.

[0146] like Figures 8 to 11 As shown, in some embodiments, the orthographic projection of the active pillar 11 on the surface of the substrate 10 is symmetrically arranged along the first direction and the second direction. For example, the shape of the orthographic projection of the active pillar 11 on the surface of the substrate 10 can be a circle, an ellipse, or other shapes with arc edges, or a polygon with straight edges such as a quadrilateral, a pentagon, or a hexagon, or a polygon composed of straight edges and arc edges.

[0147] But not limited to this, such as Figure 12As shown, in some embodiments, the dimension of the active pillar 11 at one end in the first direction, which is closer to the buried bit line 17, in the second direction, is greater than the dimension of the active pillar 11 at one end in the first direction, which is farther from the buried bit line 17. For example, the orthographic projection of the active pillar 11 on the surface of the substrate 10 may be a regular or irregular shape, such as a triangle or a T-shape. By increasing the dimension of the active pillar 11 at one end in the second direction, which is closer to the buried bit line 17, the contact area between the bit line contact 15 and the active pillar 11 is increased. This also increases the size of the bit line contact 15 and the contact area between the buried bit line 17 and the bit line contact 15. This further reduces the contact resistance between the bit line contact 15 and the active pillar 11, as well as the contact resistance between the buried bit line 17 and the bit line contact 15.

[0148] like Figures 9 to 12 As shown, in some embodiments, the projection of the buried bit line 17 in the second direction may partially overlap with the projection of the active pillar 11 in the second direction, achieving the same technical effect as above, which will not be repeated here.

[0149] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 13 As shown, the manufacturing method includes:

[0150] Step S101: providing a substrate;

[0151] Step S102: forming a plurality of active pillars on the substrate; forming a plurality of buried bit lines; wherein,

[0152] The plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each active pillar group includes two active pillar columns arranged adjacent to each other along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate;

[0153] The buried bit line is located between two adjacent active pillar columns in the active pillar group and is electrically connected to each active pillar in the two adjacent active pillar columns. The two adjacent buried bit lines are separated by two adjacent active pillar columns belonging to different active pillar groups in the two adjacent active pillar groups.

[0154] The following further describes in detail the method for manufacturing the semiconductor structure provided by the embodiment of the present application in conjunction with the accompanying drawings. Figure 15 for Figure 16 A schematic top view of the semiconductor structure shown, Figure 28 for Figures 29 to 30 A schematic top view of the semiconductor structure shown; Figure 31 for Figures 32 to 33 as well as Figures 38 to 39 Schematic top view of the semiconductor structure shown.

[0155] First, execute step S101, as Figure 14 As shown, a substrate 10 is provided.

[0156] The material of the substrate 10 is as described above and will not be described again here.

[0157] Then, execute step S102, as shown in FIG. Figures 15 and 16 、 Figure 26 as well as Figures 28 to 30 As shown, a plurality of active pillars 11 are formed on a substrate 10, and a plurality of buried bit lines 17 are formed; wherein,

[0158] A plurality of active pillars 11 are arranged into a plurality of active pillar rows 111 extending along a first direction and a plurality of active pillar columns 112 extending along a second direction; the plurality of active pillar columns 112 include a plurality of active pillar groups 20 arranged at intervals along the first direction, and each active pillar group 20 includes two active pillar columns 112 arranged adjacent to each other along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate 10; a buried bit line 17 is located between two adjacent active pillar columns 112 in the active pillar group 20, and is electrically connected to each active pillar 11 in the two adjacent active pillar columns 112, and two adjacent buried bit lines 17 are separated by two adjacent active pillar columns 112 in the two adjacent active pillar groups 20 that belong to different active pillar groups 20.

[0159] See again Figures 15 and 16 as well as Figures 28 to 30 In some embodiments, a plurality of active pillars 11 are formed on a substrate 10, including:

[0160] The substrate 10 is etched to form a plurality of first trenches T1 extending along the second direction on the substrate 10. The first trenches T1 define the substrate 10 as a plurality of wall-like structures 11' extending along the second direction. The plurality of first trenches T1 include first sub-trenches T11 and second sub-trenches T12 alternately arranged in sequence along the first direction (e.g., Figures 15 and 16 );

[0161] At least the wall-like structure 11' is etched to form a plurality of second trenches T2 extending along the first direction in the substrate 10. The first trenches T1 and the second trenches T2 intersect with each other to define a plurality of discrete active pillars 11 (such as Figures 28 to 30 ).

[0162] See again Figure 26 In some embodiments, forming a plurality of buried bit lines 17 includes:

[0163] After forming the first trench T1 and before forming the second trench T2 , a buried bit line 17 is formed in the first sub-trench T11 , and the second sub-trench T12 is located between two adjacent buried bit lines 17 .

[0164] Specifically, such as Figure 15 and Figure 16 As shown, a plurality of first trenches T1 are arranged along a first direction and extend along a second direction. The first trenches T1 are located between two adjacent wall-like structures 11 ′. The first direction and the second direction may be perpendicular or oblique.

[0165] like Figure 26 As shown, in some embodiments, the buried bit line 17 is located in the lower portion of the first sub-trench T11 and extends along the second direction within the first sub-trench T11, adjacent buried bit lines 17 are separated by two wall-like structures 11' and a second sub-trench T12 located between the two wall-like structures 11', and the buried bit line 17 is electrically connected to the two adjacent wall-like structures 11'.

[0166] In practice, the buried bit line 17 can be a single-layer structure or a multi-layer structure. In some embodiments, the buried bit line 17 includes a main body 172 and a barrier layer 171 covering the outer sidewalls and bottom surface of the main body 172. The main body 172 is located in the space defined by the barrier layer 171.

[0167] The main body 172 and the barrier layer 171 and their materials are as described above and will not be repeated here.

[0168] like Figures 17 to 25 As shown, in some embodiments, before forming the buried bit line 17 in the first sub-trench T11, the method further includes forming bit line contacts 15 on both sides of the first sub-trench T11 along a first direction, with the bit line contacts 15 at least partially laterally embedded in the wall-like structures 11' located on both sides of the first sub-trench T11. In this way, the buried bit line 17 can be electrically connected to the subsequently formed active pillar 11 through the bit line contacts 15. The contact resistance between the buried bit line 17 and the bit line contacts 15 is lower than that between the buried bit line 17 and the active pillar 11, thereby reducing the contact resistance of the buried bit line 17.

[0169] Specifically, forming the bit line contact portion 15 includes:

[0170] A first dielectric layer 12 covering the inner walls of the first sub-trench T11 and the second sub-trench T12, and a first filling layer 13 (such as a dielectric layer 13) covering the first dielectric layer 12 and filling the first sub-trench T11 and the second sub-trench T12 are formed. Figure 17 );

[0171] The first filling layer 13 located in the first sub-trench T11 is partially removed to the first position P1 to expose the first dielectric layer 12 located above the first position P1 (eg, Figure 18 );

[0172] A second dielectric layer 14 is formed, and the second dielectric layer 14 covers the exposed sidewalls of the first dielectric layer 12 and the upper surface of the remaining first filling layer 13 (eg, Figure 19 );

[0173] The second dielectric layer 14 covering the upper surface of the first filling layer 13 is removed, and the second dielectric layer 14 covering the sidewall of the first dielectric layer 12 is retained (eg, Figure 20 );

[0174] The first filling layer 13 located in the first sub-trench T11 is partially removed to the second position P2 to expose the first dielectric layer 12 located between the first position P1 and the second position P2 (eg, Figure 21 );

[0175] The first dielectric layer 12 between the first position P1 and the second position P2 is removed to expose a portion of the wall-like structure 11', and at least a portion of the first dielectric layer 12 is retained. The retained first dielectric layer 12 covers the sidewall of the first sub-trench T11 above the first position P1 (e.g., Figure 22 );

[0176] A lateral etching process is performed on the first sub-trench T11 located between the first position P1 and the second position P2 to form a first groove S1 on both sides of the first sub-trench T11. The first groove S1 is located in the wall-like structure 11', and the opening of the first groove S1 faces the first sub-trench T11 (such as Figure 23 );

[0177] Remove the remaining first dielectric layer 12 above the first position P1 in the first sub-trench T11; fill the first conductive material 15' (such as Figure 24 );

[0178] An etching process is performed on the first conductive material 15' to form a bit line contact portion 15, and the bit line contact portion 15 is at least partially located in the first groove S1 (eg, Figure 25 ).

[0179] In actual operation, the material of the first dielectric layer 12 includes but is not limited to nitride, such as silicon nitride; the material of the first filling layer 13 includes but is not limited to oxide, such as silicon oxide.

[0180] In actual operation, the material of the second dielectric layer 14 can be the same as that of the first dielectric layer 12. It can be understood that since the sidewall of the first sub-trench T11 above the first position P1 is covered by both the first dielectric layer 12 and the second dielectric layer 14, after the first dielectric layer 12 between the first position P1 and the second position P2 is removed, at least a portion of the first dielectric layer 12 above the first position P1 will remain.

[0181] In some embodiments, the thickness of the second dielectric layer 14 can be set to be greater than the thickness of the first dielectric layer 12. In this way, after removing the first dielectric layer 12 between the first position P1 and the second position P2, a portion of the second dielectric layer 14 may still be retained to improve the protection of the sidewall of the first sub-trench T11 above the first position P1.

[0182] In other embodiments of the present disclosure, the materials of the first dielectric layer 12 and the second dielectric layer 14 may be different. For example, the material of the first dielectric layer 12 may include nitride (e.g., silicon nitride), and the material of the second dielectric layer 14 may include oxide (e.g., silicon oxide). In addition, during the process of removing the first dielectric layer 12 between the first position P1 and the second position P2, the first dielectric layer 12 and the second dielectric layer 14 may have a larger etching selectivity to reduce consumption of the second dielectric layer 14 and further improve the protection of the sidewall of the first sub-trench T11 above the first position P1.

[0183] In some embodiments, the first groove S1 extends continuously along the second direction within the wall-like structure 11 ′.

[0184] See again Figure 24 In actual operation, the remaining first dielectric layer 12 located above the first position P1 in the first sub-trench T11 can be removed before or after forming the first conductive material 15'. If the second dielectric layer 14 remains after removing the first dielectric layer 12 located between the first position P1 and the second position P2, the method further includes removing the remaining second dielectric layer 14 located above the first position P1 in the first sub-trench T11.

[0185] In actual operation, a first initial conductive material (not shown) may be filled in the space of the first sub-trench T11 above the second position P2 and in the first groove S1, and then an etch-back process may be performed on the first initial conductive material (not shown) to form a first conductive material 15' between the first position P1 and the second position P2.

[0186] Continue to see Figure 24In some embodiments, after forming the first recess S1 and before forming the buried bit line 17, the method further includes forming a doped layer 16 within the wall-like structure 11'. The doped layer 16 continuously extends along the second direction within the wall-like structure 11' and surrounds the inner wall of the first recess S1. The presence of the doped layer 16 reduces the contact resistance between the bit line contact 15 and the active pillar 11, further improving the performance of the semiconductor structure.

[0187] In some embodiments, the dopant in the doping layer 16 may be one or more elements such as boron, phosphorus, and arsenic, and the dopant in the doping layer 16 may be the same as the dopant in the bit line contact 15. In some specific embodiments, the dopant in the doping layer 16 is phosphorus, and the doping concentration of phosphorus is greater than 1*E 20 atom / cm 3 , for example 2*E 20 atom / cm 3 、3*E 20 atom / cm 3 、5*E 20 atom / cm 3 、1*E 21 atom / cm 3 wait.

[0188] In some embodiments, forming the doping layer 16 in the wall-like structure 11 ′ includes:

[0189] doping the first conductive material 15' with a dopant;

[0190] Before performing an etching process on the first conductive material 15 ′ to form the bit line contact 15 , an annealing process is performed on the first conductive material 15 ′ doped with dopants, and a portion of the dopants diffuses into the wall-shaped structure 11 ′ to form a doped layer 16 .

[0191] In some embodiments, the first conductive material 15' includes but is not limited to polysilicon. The dopant added to the first conductive material 15' can be one or more elements such as boron, phosphorus, and arsenic. The first conductive material 15' can be doped using processes such as in-situ doping, diffusion, and ion implantation.

[0192] However, the present invention is not limited thereto. Before removing the first dielectric layer 12 or the first dielectric layer 12 and the second dielectric layer 14 above the first position P1 and before forming the first conductive material 15 ′, a doping process may be performed on the inner wall of the first groove S1 to form the doping layer 16 .

[0193] In some embodiments, the bit line contact portion 15 may completely fill the first groove S1 or partially fill the first groove S1, that is, the bit line contact portion 15 may be entirely located within the first groove S1. For example, the sidewalls of the bit line contact portion 15 may be substantially flush with the sidewalls of the wall-like structure 11' (or the active pillar 11 in other embodiments), or may be slightly retracted inward relative to the sidewalls of the wall-like structure 11' (or the active pillar 11 in other embodiments); but not limited to this, the sidewalls of the bit line contact portion 15 may also slightly protrude outward relative to the wall-like structure 11' (or the active pillar 11 in other embodiments) to increase scenario applicability.

[0194] In some embodiments, the upper surface of the buried bit line 17 is flush with or higher than the upper surface of the bit line contact portion 15 to increase scenario applicability.

[0195] See again Figure 26 In some embodiments, the remaining first dielectric layer 12 and the first filling layer 13 in the first sub-trench T11 constitute a first isolation structure 191. The buried bit line 17 covers the first isolation structure 191. The first isolation structure 191 is used to electrically isolate the buried bit line 17 from the substrate 10 to prevent leakage or short circuit. The first dielectric layer 12 and the first filling layer 13 located in the second sub-trench T12 constitute a second isolation structure 192. The second isolation structure 192 is used to separate adjacent buried bit lines 17, which helps to reduce the coupling effect between the buried bit lines 17.

[0196] Next, if Figure 27 As shown, the method further includes: forming a second filling layer 18 , the second filling layer 18 filling the remaining space of the first sub-trench T11 .

[0197] In actual operation, the second filling layer 18 can be a single-layer structure or a multi-layer structure. The material of the second filling layer 18 includes one or more of oxides (such as silicon oxide), nitrides (such as silicon nitride), oxynitrides (such as silicon oxynitride), etc., such as silicon oxide.

[0198] Next, see again Figures 28 to 30 In some embodiments, forming the second trench T2 includes etching the wall-shaped structure 11 ′, the second filling layer 18 , and the second isolation structure 192 along the first direction to form the second trench T2 .

[0199] In some embodiments, a plurality of second trenches T2 extend along the first direction and are arranged at intervals along the second direction; a plurality of first trenches T1 and a plurality of second trenches T2 intersect each other to define a plurality of active pillar rows 111 and a plurality of active pillar columns 112 in the substrate 10; wherein, the plurality of active pillar rows 111 are arranged along the second direction, and each active pillar row 111 includes a plurality of active pillars 11 arranged at intervals along the first direction; a plurality of active pillar columns 112 are arranged at intervals along the first direction, and each active pillar column 112 includes a plurality of active pillars 11 arranged along the second direction.

[0200] In some embodiments, the depth of the second trench T2 is less than the depth of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17. A portion of the wall-like structure 11' located below the second trench T2 is not etched to form a connecting portion 21. The connecting portion 21 is located between the lower portions of two active pillars 11 arranged adjacent to each other along the second direction, and the lower portions of multiple active pillars 11 arranged along the second direction are connected in sequence through the connecting portion 21.

[0201] In some embodiments, the bit line contact portion 15 extends continuously along the second direction within the multiple active pillars 11 and the multiple connecting portions 21. In this way, there is a larger contact area between the buried bit line 17 and the bit line contact portion 15, and between the bit line contact portion 15 and the active pillars 11 and the connecting portions 21, further reducing the contact resistance between the bit line contact portion 15 and the active pillars 11, and the contact resistance between the buried bit line 17 and the bit line contact portion 15.

[0202] In some embodiments, the bit line contact portion 15 can be completely embedded in the active pillar 11 and the connecting portion 21. For example, the side walls of the bit line contact portion 15 can be basically flush with the side walls of the active pillar 11 and the connecting portion 21, or slightly indented inward relative to the side walls of the active pillar 11 and the connecting portion 21; but not limited to this, the side walls of the bit line contact portion 15 can slightly protrude outward relative to the side walls of the active pillar 11 and the connecting portion 21 to increase scenario applicability.

[0203] In some embodiments, when the lower portions of multiple active pillars 11 arranged along the second direction are connected in sequence through connecting portions 21, the doping layer 16 is located within the multiple active pillars 11 and the multiple connecting portions 21 and extends continuously along the second direction, and the doping layer 16 surrounds the contact surface between the bit line contact portion 15 and the active pillars 11 and the connecting portions 21.

[0204] Continue to see Figures 28 to 30In some embodiments, after forming the second trench T2, the method further includes: forming a third isolation structure 193 in the second trench T2, the third isolation structure 193 extending along the first direction at the lower portion of the second trench T2, and covering the connecting portion 21, a portion of the second filling layer 18, and a portion of the second isolation structure 192 along the first direction; removing a portion of the second filling layer 18 and a portion of the second isolation structure 192 between two adjacent active pillars 11 of the active pillar row 111 to form a second groove S2 between two adjacent active pillars 11 of the active pillar row 111, and the second groove S2 is connected to the second trench T2.

[0205] Next, if Figure 1 as well as Figures 2 to 3 As shown, after forming the buried bit line 17, the method further includes: forming a plurality of word lines 23 above the buried bit line 17, the plurality of word lines 23 being arranged along the second direction, each word line 23 extending along the first direction, and each word line 23 covering a portion of the side wall of each active pillar 11 in an active pillar row 111.

[0206] In some embodiments, each word line 23 extends along the first direction and surrounds each active pillar 11 in an active pillar row 111 , thereby increasing the driving capability of the word line 23 on the active pillar row 111 .

[0207] Specifically, the word line 23 can be formed in the following manner: first, the second trench T2 and the second groove S2 are filled with a second conductive material (not shown), and the second conductive material (not shown) covers the third isolation structure 193 and the portion of the second filling layer 18 and the portion of the second isolation structure 192 exposed by the second groove S2; then, an etch-back process is performed to make the upper surface of the second conductive material (not shown) lower than the upper surface of the active pillar 11; then, a third filling layer 24 is formed, and the third filling layer 24 covers the second conductive material (not shown) and fills the second trench T2. 2 and the second groove S2; then, the second conductive material (not shown) is etched to form a first opening K1 in the second trench T2, and the first opening K1 extends downward from the upper surface of the third filling layer 24 to penetrate the second conductive material (not shown) to divide the second conductive material (not shown) into a plurality of word lines 23 arranged at intervals along the second direction, and each word line 23 surrounds each active pillar 11 in an active pillar row 111; then, the fourth filling layer 25 is filled in the first opening K1, and the third filling layer 24 and the fourth filling layer 25 constitute a fourth isolation structure 194.

[0208] In some embodiments, before forming the word lines 23, the process further includes forming a gate dielectric layer 22, which is located at least between the word lines 23 and the active pillars 11. In practice, the material of the gate dielectric layer 22 includes, but is not limited to, oxides, such as silicon oxide. The gate dielectric layer 22 can be formed by performing an oxidation process on the sidewalls of the active pillars 11. However, the present invention is not limited thereto, and a thin film deposition process can also be used to form the gate dielectric layer 22.

[0209] Continue to see Figures 2 to 3 In some embodiments, after forming the fourth isolation structure 194, the method further includes: forming an insulating structure 26 above the active pillar 11 and the fourth isolation structure 194, wherein the insulating structure 26 has a plurality of discrete second openings K2 therein, and the second openings K2 expose the upper surface of the active pillar 11; and forming contact plugs 27 within the second openings K2, wherein the contact plugs 27 are electrically connected to the upper surface of the active pillar 11. In subsequent processes, a capacitor structure electrically connected to the contact plugs 27 may be formed on the contact plugs 27, and the capacitor structure is used to store data.

[0210] In actual operation, the insulating structure 26 may include multiple first sublayers (not labeled) extending along the first direction, and multiple second sublayers (not labeled) extending along the second direction. The multiple first sublayers and the multiple second sublayers intersect with each other to form multiple second openings K2.

[0211] The materials of the word line 23 , the third isolation structure 193 , the fourth isolation structure 194 , the insulation structure 26 , and the contact plug 27 are as described above and are not repeated here.

[0212] Figures 17 to 30 as well as Figures 2 to 3 In the illustrated structure, the buried bit line 17 is formed after the first trench T1 is formed and before the second trench T2 is formed. However, the present invention is not limited thereto. In other embodiments of the present disclosure, the first trench T1 and the second trench T2 may be formed before the buried bit line 17 is formed, thereby forming a plurality of active pillars 11. The buried bit line 17 may be formed after the first trench T1 and the second trench T2 are formed.

[0213] Specifically, such as Figure 31 、 Figures 32 to 33 or Figures 38 to 39 As shown, a plurality of second trenches T2 can be first formed in the substrate 10, and a third isolation structure 193 can be filled in the second trenches T2; then, a plurality of first trenches T1 can be formed in the substrate 10 and the third isolation structure 193, and the plurality of first trenches T1 and the plurality of second trenches T2 define a plurality of active pillars 11 in the substrate 10.

[0214] However, the present invention is not limited thereto. A mask process may also be used to form a plurality of active pillars 11 by etching the substrate 10 in one step.

[0215] like Figures 32 to 33 As shown, in some embodiments, the depth of the second trench T2 is less than the depth of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17, and a portion of the substrate 10 located below the second trench T2 is not etched to form the connecting portion 21, and the remaining third isolation structure 193 is located between adjacent first trenches T1 and covers the connecting portion 21.

[0216] Then, Figures 32 to 33 The structure shown is executed as Figures 17 to 27 The steps shown are as follows: Figures 34 to 35 The structure shown.

[0217] In some embodiments, in the step of removing the first dielectric layer 12 between the first position P1 and the second position P2, a portion of the active pillar 11 and a portion of the connecting portion 21 are exposed; in the step of forming the first groove S1, at least a portion of the first groove S1 is located in the active pillar 11. For example, the first groove S1 can be located in a plurality of active pillars 11 and a plurality of connecting portions 21 arranged along the second direction, and extend continuously along the second direction.

[0218] In some embodiments, the bit line contact portion 15 is at least partially laterally embedded in the active pillars 11 located on both sides of the first sub-trench T11. For example, the bit line contact portion 15 can be laterally embedded in the active pillars 11 and the connecting portion 21 located on both sides of the first sub-trench T11, and extend continuously along the second direction. The bit line contact portion 15 can be completely embedded in the active pillars 11 and the connecting portion 21, and can also protrude outward relative to the sidewall portions of the active pillars 11 and the connecting portion 21; in the step of forming the doping layer 16, the dopant diffuses into the multiple active pillars 11 and the multiple connecting portions 21 arranged along the second direction to form a doping layer 16 that extends continuously along the second direction.

[0219] Then, if Figures 36 to 37 As shown, part of the second filling layer 18 and part of the second isolation structure 192 between two adjacent active pillars 11 of the active pillar row 111 are removed to form a second groove S2 between two adjacent active pillars 11 of the active pillar row 111, and part of the third isolation structure 193, part of the second filling layer 18 and part of the second isolation structure 192 are removed along the first direction to reopen part of the second trench T2, and the second groove S2 is connected to the second trench T2.

[0220] Then, Figures 36 to 37 The structure shown is executed as Figures 2 to 3 The steps shown are as follows: Figures 4 and 5 The structure shown.

[0221] Figures 2 to 3 as well as Figures 4 and 5The depth of the second trench T2 shown is less than the depth of the first trench T1, and the bottom surface of the second trench T2 is higher than the upper surface of the buried bit line 17. The lower parts of the multiple active pillars 11 arranged along the second direction are connected in sequence through the connecting parts 21. The bit line contact parts 15 and the doping layer 16 are located in the multiple active pillars 11 and the multiple connecting parts 21 and extend continuously along the second direction.

[0222] But not limited to this, such as Figures 38 to 39 As shown, in other embodiments of the present disclosure, the second trench T2 may have a greater depth, and the bottom surface of the second trench T2 may be lower than the bottom surface of the subsequently formed buried bit line 17, and the multiple active pillars 11 of each active pillar column 112 are arranged at intervals along the second direction, and the remaining third isolation structure 193 is located between adjacent first trenches T1 and covers part of the substrate 10, and two adjacent active pillars 11 in the second direction are separated by the third isolation structure 193.

[0223] Then, Figures 38 to 39 The structure shown is executed as Figures 17 to 27 The steps shown are as follows: Figures 40 to 41 The structure shown.

[0224] In some embodiments, in the step of removing the first dielectric layer 12 between the first position P1 and the second position P2, a portion of the active pillar 11 and a portion of the third isolation structure 193 are exposed; in the step of forming the first groove S1, the first groove S1 is located within a plurality of active pillars 11 arranged along the second direction.

[0225] In some embodiments, the bit line contact portion 15 is at least partially laterally embedded in the active pillars 11 located on both sides of the first sub-trench T11. For example, a plurality of bit line contact portions 15 are arranged at intervals along the second direction and correspondingly laterally embedded in a plurality of active pillars 11 of the active pillar column 112 located on both sides of the first sub-trench T11. The bit line contact portion 15 can be completely embedded in the active pillar 11 and can also protrude outward relative to the sidewall portion of the active pillar 11. In the step of forming the doping layer 16, the dopant is diffused into the plurality of active pillars 11 arranged at intervals along the second direction to form a doping layer 16 in the plurality of active pillars 11, and the doping layer 16 surrounds the contact surface between the active pillar 11 and the bit line contact portion 15.

[0226] Then, Figures 38 to 39 The structure shown is executed as Figures 36 to 37 as well as Figures 4 and 5 The steps shown are as follows: Figures 6 and 7 The structure shown.

[0227] like Figure 8As shown, in some embodiments, when the multiple active pillars 11 of each active pillar column 112 are arranged at intervals along the second direction, the projection of the buried bit line 17 in the second direction can partially overlap with the projection of the active pillar 11 in the second direction, thereby increasing the contact area between the buried bit line 17 and the active pillar 11 or the bit line contact portion 15 located in the active pillar 11, and further reducing the contact resistance of the buried bit line 17.

[0228] In actual operation, this can be achieved by increasing the width of the first trench T1 when forming the first trench T1, so that the first trench T1 exposes the end portions of the active pillars 11 located on both sides thereof. In this way, the area of ​​the side walls of the active pillars 11 exposed by the first trench T1 is larger. For example, in addition to exposing the side walls of the active pillars 11 in the first direction, the first trench T1 can also expose part of the side walls of the active pillars 11 in the second direction, so that the finally formed buried bit lines 17 can not only contact the side walls of the active pillars 11 or the bit line contact portions 15 in the first direction, but also contact part of the side walls of the active pillars 11 or the bit line contact portions 15 in the second direction.

[0229] like Figures 8 to 11 As shown, in some embodiments, the orthographic projection of the active pillar 11 on the surface of the substrate 10 is symmetrically arranged along the first direction and the second direction. For example, the shape of the orthographic projection of the active pillar 11 on the surface of the substrate 10 can be a circle, an ellipse, or other shapes with arc edges, or a polygon with straight edges such as a quadrilateral, a pentagon, or a hexagon, or a polygon composed of straight edges and arc edges.

[0230] But not limited to this, such as Figure 12 As shown, in some embodiments, the dimension of the active pillar 11 at one end in the first direction, which is closer to the buried bit line 17, in the second direction, is greater than the dimension of the active pillar 11 at one end in the first direction, which is farther from the buried bit line 17. For example, the orthographic projection of the active pillar 11 on the surface of the substrate 10 may be a regular or irregular shape, such as a triangle or a T-shape. By increasing the dimension of the active pillar 11 at one end in the second direction, which is closer to the buried bit line 17, the contact area between the bit line contact 15 and the active pillar 11 is increased. This also increases the size of the bit line contact 15 and the contact area between the buried bit line 17 and the bit line contact 15. This further reduces the contact resistance between the bit line contact 15 and the active pillar 11, as well as the contact resistance between the buried bit line 17 and the bit line contact 15.

[0231] like Figures 8 to 11As shown, in some embodiments, the orthographic projection of the active pillar 11 on the surface of the substrate 10 is symmetrically arranged along the first direction and the second direction. For example, the shape of the orthographic projection of the active pillar 11 on the surface of the substrate 10 can be a circle, an ellipse, or other shapes with arc edges, or a polygon with straight edges such as a quadrilateral, a pentagon, or a hexagon, or a polygon composed of straight edges and arc edges.

[0232] But not limited to this, such as Figure 12 As shown, in some embodiments, the dimension of the active pillar 11 at one end in the first direction, which is closer to the buried bit line 17, in the second direction, is greater than the dimension of the active pillar 11 at one end in the first direction, which is farther from the buried bit line 17. For example, the orthographic projection of the active pillar 11 on the surface of the substrate 10 may be a regular or irregular shape, such as a triangle or a T-shape. By increasing the dimension of the active pillar 11 at one end in the second direction, which is closer to the buried bit line 17, the contact area between the bit line contact 15 and the active pillar 11 is increased. This also increases the size of the bit line contact 15 and the contact area between the buried bit line 17 and the bit line contact 15. This further reduces the contact resistance between the bit line contact 15 and the active pillar 11, as well as the contact resistance between the buried bit line 17 and the bit line contact 15.

[0233] like Figures 9 to 12 As shown, in some embodiments, when the multiple active pillars 11 of each active pillar column 112 are arranged at intervals along the second direction, the projection of the buried bit line 17 in the second direction can partially overlap with the projection of the active pillar 11 in the second direction, thereby achieving the same technical effect as described above, which will not be repeated here.

[0234] It can be seen that in the embodiment of the present disclosure, the buried bit line 17 is formed only in the first sub-trench T11, and the buried bit line 17 is not formed in the second sub-trench T12, that is, two active column columns 112 arranged adjacent to each other along the first direction in an active column group 20 share a buried bit line 17, and no buried bit line 17 is formed between adjacent active column groups 20. In this way, the distance between adjacent buried bit lines 17 is increased, which can effectively reduce the coupling effect between the buried bit lines 17, thereby reducing the signal crosstalk between multiple buried bit lines 17, and at the same time reducing the contact resistance of the buried bit lines 17, thereby improving the performance of the semiconductor structure.

[0235] The various technical features in the technical solutions described in the above embodiments can be arbitrarily combined without conflict. Those skilled in the art can change the order of the steps in the above-mentioned formation method without departing from the scope of protection of this disclosure. In the embodiments of this disclosure, some steps can be performed simultaneously or in a sequential order without conflict.

[0236] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor structure, characterized in that include: A substrate, and a plurality of active pillars located on the substrate, wherein the plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; wherein the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each active pillar group includes two active pillar columns arranged adjacent to each other along the first direction; and the first direction and the second direction intersect and are both parallel to the surface of the substrate; a plurality of buried bit lines located between two adjacent active pillar columns in the active pillar group and electrically connected to each active pillar in the two adjacent active pillar columns, wherein two adjacent buried bit lines are separated by two adjacent active pillar columns belonging to different active pillar groups in the two adjacent active pillar groups; a plurality of bit line contacts, the bit line contacts being at least partially laterally embedded in the active pillars located on both sides of the buried bit line along the first direction; The doped layer is at least partially located in the active pillar and at least surrounds a contact surface between the bit line contact portion and the active pillar.

2. The semiconductor structure according to claim 1, wherein: The plurality of bit line contact portions are respectively disposed on both sides of the buried bit line along the first direction and are electrically connected to the buried bit line.

3. The semiconductor structure according to claim 2, wherein: The multiple active pillars of each active pillar column are arranged at intervals along the second direction, and the multiple bit line contacts are arranged at intervals along the second direction and are correspondingly disposed in the multiple active pillars of the active pillar column.

4. The semiconductor structure according to claim 1, wherein: The orthographic projections of the active pillars on the surface of the substrate are symmetrically arranged along the first direction and the second direction; or, A dimension of an end of the active pillar in the first direction close to the buried bit line in the second direction is greater than a dimension of an end of the active pillar in the first direction far from the buried bit line in the second direction.

5. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes: a plurality of connecting portions located between lower portions of two adjacent active pillars arranged along the second direction, and the lower portions of the plurality of active pillars arranged along the second direction are sequentially connected through the connecting portions; The bit line contact portion is located within the plurality of active pillars and the plurality of connection portions and continuously extends along the second direction.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that The semiconductor structure further comprises: a first isolation structure, located below the buried bit line and extending along the second direction, wherein the buried bit line covers the first isolation structure; The second isolation structure is located between two adjacent active pillar groups and extends along the second direction, and an upper surface of the second isolation structure is higher than an upper surface of the buried bit line.

7. The semiconductor structure according to any one of claims 1 to 5, characterized in that The plurality of active pillar rows are arranged along the second direction; the semiconductor structure further comprises: A plurality of word lines are located above the buried bit lines, the plurality of word lines are arranged along the second direction, each of the word lines extends along the first direction, and each of the word lines covers a portion of a sidewall of each of the active pillars in one active pillar row.

8. A method for manufacturing a semiconductor structure, characterized in that: include; providing a substrate; forming a plurality of active pillars on the substrate; forming a plurality of buried bit lines; wherein, The plurality of active pillars are arranged into a plurality of active pillar rows extending along a first direction and a plurality of active pillar columns extending along a second direction; the plurality of active pillar columns include a plurality of active pillar groups arranged at intervals along the first direction, and each active pillar group includes two active pillar columns arranged adjacent to each other along the first direction; the first direction and the second direction intersect and are both parallel to the surface of the substrate; The buried bit line is located between two adjacent active pillar columns in the active pillar group and is electrically connected to each active pillar in the two adjacent active pillar columns, and the two adjacent buried bit lines are separated by two adjacent active pillar columns belonging to different active pillar groups in the two adjacent active pillar groups; Before forming the buried bit line, the method further includes: forming a plurality of bit line contacts, wherein the bit line contacts are at least partially laterally embedded in the active pillars located on both sides of the buried bit line along the first direction; A doping layer is formed, at least a portion of which is located in the active pillar and at least surrounds a contact surface between the bit line contact portion and the active pillar.

9. The manufacturing method according to claim 8, characterized in that The forming of a plurality of active pillars on the substrate comprises: Etching the substrate to form a plurality of first trenches extending along the second direction on the substrate, wherein the first trenches define the substrate into a plurality of wall-like structures extending along the second direction; the plurality of first trenches include first sub-trenches and second sub-trenches alternately arranged in sequence along the first direction; etching at least the wall-shaped structure to form a plurality of second trenches extending along the first direction in the substrate, wherein the first trenches and the second trenches intersect with each other to define a plurality of discrete active pillars in the substrate; The forming of a plurality of buried bit lines comprises: After forming the first trench and before or after forming the second trench, the buried bit line is formed in the first sub-trench, and the second sub-trench is located between two adjacent buried bit lines.

10. The manufacturing method according to claim 9, characterized in that: forming a plurality of bit line contacts, including: Before forming the buried bit line in the first sub-trench, bit line contacts are formed on both sides of the first sub-trench along the first direction, and the bit line contacts are at least partially laterally embedded in the active pillars or the wall-like structures located on both sides of the first sub-trench.

11. The manufacturing method according to claim 10, characterized in that: The forming of the bit line contact portion includes: forming a first dielectric layer covering inner walls of the first sub-trench and the second sub-trench, and a first filling layer covering the first dielectric layer and filling the first sub-trench and the second sub-trench; removing a portion of the first filling layer located in the first sub-trench to a first position to expose the first dielectric layer located above the first position; forming a second dielectric layer, wherein the second dielectric layer covers the exposed sidewalls of the first dielectric layer and the remaining upper surface of the first filling layer; removing the second dielectric layer covering the upper surface of the first filling layer, and retaining the second dielectric layer covering the sidewalls of the first dielectric layer; removing a portion of the first filling layer located in the first sub-trench to a second position, so as to expose the first dielectric layer located between the first position and the second position; removing the first dielectric layer between the first position and the second position to expose a portion of the active pillar or a portion of the wall-like structure, and retaining at least a portion of the first dielectric layer, wherein the retained first dielectric layer covers a sidewall of the first sub-trench above the first position; performing a lateral etching process on the first sub-trench located between the first position and the second position to form a first groove on both sides of the first sub-trench, wherein the first groove is located within the wall-like structure or at least partially within the active pillar, and an opening of the first groove faces the first sub-trench; removing the remaining first dielectric layer above the first position in the first sub-trench; A first conductive material is filled in the space between the first position and the second position of the first sub-trench and in the first groove, and an etching process is performed on the first conductive material to form the bit line contact portion, which is at least partially located in the first groove.

12. The manufacturing method according to claim 11, characterized in that: The forming of the doping layer includes: forming a doping layer in the active pillar or the wall-shaped structure after forming the first groove and before forming the buried bit line, wherein the doping layer surrounds an inner wall of the first groove.

13. The manufacturing method according to claim 12, characterized in that: Forming a doping layer in the active pillar or the wall-shaped structure includes: doping the first conductive material with a dopant; Before performing an etching process on the first conductive material to form the bit line contact portion, an annealing process is performed on the first conductive material doped with dopants, so that part of the dopants diffuses into the active pillar or the wall-shaped structure to form the doped layer.

14. The manufacturing method according to any one of claims 8 to 13, characterized in that: After forming the buried bit line, the method further includes: A plurality of word lines are formed above the buried bit lines. The plurality of word lines are arranged along the second direction. Each word line extends along the first direction and covers a portion of a sidewall of each active pillar in one active pillar row.

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