Semiconductor memory device with magnetron layer

Abstract

The invention relates to a semiconductor memory device having a magnetron layer. A semiconductor device includes: a lower interconnect line; the lower electrode is arranged on the lower interconnection line; the first magnetic control layer is arranged on the lower electrode; a selection element layer disposed on the first magnetic control layer; a second magnetic control layer disposed on the selection element layer; the storage element layer is arranged on the second magnetic control layer; an upper electrode disposed over the memory element layer; and an upper interconnection line disposed over the upper electrode. Each of the first and second magnetron layers includes at least one of cobalt, iron, nickel, molybdenum, aluminum, chromium, a permalloy, a superpermeable alloy, an oxide thereof, and a nitride thereof.

Description

[0001] Priority and Cross - Reference to Related Applications

[0002] This patent document claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0181801, filed on December 14, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed in this patent document relates to a semiconductor memory device. Background Art

[0004] Recently, there has been a demand for semiconductor devices capable of storing data in electronic devices such as miniaturization, low power consumption, high - performance computers, and portable communication devices. To meet this demand, research is being conducted on semiconductor memory devices that store data using the switching characteristics based on the voltage or current applied thereto. Summary of the Invention

[0005] In an embodiment of the disclosed technology, a semiconductor device includes: a lower interconnect; a lower electrode over the lower interconnect; a first magneto - control layer over the lower electrode; a select - element layer over the first magneto - control layer; a second magneto - control layer over the select - element layer; a storage - element layer over the second magneto - control layer; an upper electrode over the storage - element layer; and an upper interconnect over the upper electrode. In some implementations, data is read from or written to the storage - element layer through a select - element layer configured to exhibit different conductance characteristics in response to an applied voltage relative to a threshold voltage. In some implementations, the lower interconnect and the upper interconnect are configured to transmit voltage or current signals in the semiconductor device, and the first magneto - control layer and the second magneto - control layer are configured to control a magnetic field formed in the select - element layer. Each of the first magneto - control layer and the second magneto - control layer includes at least one of cobalt, iron, nickel, molybdenum, aluminum, chromium, permalloy, hyper - magnetostrictive alloy, its oxide, and its nitride.

[0006] In an embodiment of the disclosed technology, a semiconductor device includes: a lower electrode; a first magneto - control layer above the lower electrode; a selection element layer above the first magneto - control layer; a second magneto - control layer above the selection element layer; a magnetic shielding layer above the second magneto - control layer; a storage element layer above the magnetic shielding layer; and an upper electrode above the storage element layer. In some implementations, data is read from or written to the storage element layer through a selection element layer configured to exhibit different conductance characteristics in response to an applied voltage relative to a threshold voltage. In some implementations, the first magneto - control layer and the second magneto - control layer are configured to control the magnetic field formed in the selection element layer, and the magnetic shielding layer is configured to reduce the magnetic field to the storage element layer. Each of the first magneto - control layer and the second magneto - control layer includes a metal without magnetic anisotropy. The magnetic shielding layer includes at least one of a metal alloy layer, an oxide layer, and a nitride layer. Each of the metal alloy layer, the oxide layer, and the nitride layer includes at least two of nickel, iron, copper, aluminum, chromium, and molybdenum. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. is a perspective view schematically showing a cross - point cell array of a semiconductor memory device based on an embodiment of the disclosed technology.

[0008] Figures 2A to 2C is a longitudinal cross - sectional view taken along line Figure 1 I - I' of.

[0009] Figures 3A to 3C FIG. is a diagram showing a first magneto - control element based on some embodiments of the disclosed technology.

[0010] Figures 4A to 4C FIG. is a diagram showing a second magneto - control element based on some embodiments of the disclosed technology.

[0011] Figures 5A to 5C FIG. is a diagram showing adjusting the distance between the first magneto - control element and the second magneto - control element.

[0012] Figures 6A to 6C FIG. is a diagram showing a first magnetic shielding element based on some embodiments of the disclosed technology.

[0013] Figures 7A to 7C FIG. is a diagram showing a second magnetic shielding element based on some embodiments of the disclosed technology.

[0014] Figure 8 FIG. is a diagram showing a storage element layer based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0015] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0016] The accompanying drawings are not necessarily drawn to scale. In some cases, to clearly show certain features of the described embodiments, the proportions of at least some structures in the drawings may have been exaggerated. When presenting specific examples in a drawing or description having two or more layers in a multi-layer structure, the relative positional relationship of these layers as shown or the order of arranging the layers reflects a specific implementation of the described or shown example, and there may be different relative positional relationships or orders of arranging the layers. In addition, the examples of the multi-layer structures described or shown may not reflect all the layers present in that specific multi-layer structure (for example, there may be one or more additional layers between two shown layers). As a specific example, when the first layer in a described or shown multi-layer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0017] The disclosed technology can be implemented in some embodiments to provide a cross-point semiconductor memory device having a magneto-control layer.

[0018] The disclosed technology can be implemented in some embodiments to cancel eddy currents that may be generated due to electromagnetic induction and reduce leakage current in the select element layer.

[0019] The disclosed technology can be implemented in some embodiments to provide a cross-point semiconductor memory device having a magnetic shielding layer.

[0020] Figure 1 is a perspective view schematically showing a cross-point cell array 100 of a semiconductor memory device based on an embodiment of the disclosed technology.

[0021] Referring to Figure 1 , the cross-point cell array 100 of a semiconductor memory device based on an embodiment of the disclosed technology may include lower interconnections 10, upper interconnections 90, and a memory cell structure MC. In some implementations, the term "interconnection" can be used to denote a transmission line capable of transmitting electrical signals between different regions in a semiconductor memory device. The lower interconnections 10 may extend parallel to each other in a first horizontal direction X. The upper interconnections 90 may extend parallel to each other in a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. The memory cell structure MC may be disposed at the intersection between the lower interconnections 10 and the upper interconnections 90. Each memory cell structure MC may have a cylindrical columnar shape.

[0022] Figures 2A to 2C is a longitudinal cross-sectional view taken along the line I-I' of Figure 1 Referring to Figures 2A to 2C, the cross-point cell array 100 of a semiconductor memory device according to some embodiments of the present disclosure technology may include memory cell structures MC1 to MC3 respectively disposed between the lower interconnect 10 and the upper interconnect 90. The lower interconnect 10 may be disposed on a substrate or a lower insulating layer. The lower interconnect 10 may have a linear shape extending in the first horizontal direction X. The lower interconnect 10 may include a conductor, for example, a metal, a metal silicide, a metal compound, or a metal alloy. For example, the lower interconnect 10 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum (TiAl), or a combination thereof. The upper interconnect 90 may be respectively disposed on the memory cell structures MC1 to MC3. Refer to Figure 1 , the upper interconnect 90 may have a linear shape extending in the second horizontal direction Y. The upper interconnect 90 may include a conductor, for example, a metal, a metal silicide, a metal compound, or a metal alloy.

[0023] Refer to Figure 2A , the memory cell structure MC1 of a semiconductor memory device according to an embodiment of the present disclosure technology may include a lower electrode 15, a first magneto-controlled element 20, a selection element layer 30, a second magneto-controlled element 40, an intermediate electrode 60, a memory element layer 80, and an upper electrode 95 stacked in the vertical direction Z between the lower interconnect 10 and the upper interconnect 90. The lower electrode 15, the first magneto-controlled element 20, the selection element layer 30, the second magneto-controlled element 40, the intermediate electrode 60, the memory element layer 80, and the upper electrode 95 may respectively have a column shape or a pad shape.

[0024] The lower electrode 15 may be directly disposed on the lower interconnect 10. The lower electrode 15 may receive a voltage or a current from the lower interconnect 10 and transmit or supply the voltage or the current to the selection element layer 30. The lower electrode 15 may include a conductor, for example, a metal, a metal silicide, a metal compound, or a metal alloy. For example, the lower electrode 15 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum (TiAl), or a combination thereof.

[0025] The first magneto - control element 20 and the second magneto - control element 40 can control the magnetic field formed in the selection element layer 30 to keep the magnetic field at a uniform level by attenuating the electromagnetic field through channel formation. Thus, after a channel is formed in the selection element layer 30, the generated hysteresis loss can be canceled out and the leakage current can be reduced.

[0026] The selection element layer 30 can be disposed on the lower electrode 15. In some implementations, the selection element layer 30 can exhibit different conductance characteristics or states in response to an applied voltage or current relative to a threshold voltage or current. For example, the selection element layer 30 can exhibit different states of its conductivity when affected by the electric field generated between the lower electrode 15 and the intermediate electrode 60. That is, under the control of the electric field generated between the lower electrode 15 and the intermediate electrode 60, a conductive channel can be formed in the selection element layer 30. When the voltage associated with the electric field is less than the threshold voltage or the current associated with the electric field is less than the threshold current, the selection element layer 30 can exhibit non - conductive properties to cut off the current path passing through the selection element layer 30 to the storage element layer 80. When the voltage associated with the electric field is greater than or equal to the threshold voltage or the current associated with the electric field is greater than or equal to the threshold current, the selection element layer 30 can exhibit conductive properties by forming a conductive channel or current path to the storage element layer 80. In one embodiment, the selection element layer 30 can include an ion - doped insulating layer. For example, the selection element layer 30 can include ion - doped silicon oxide, ion - doped titanium oxide, ion - doped aluminum oxide, ion - doped tungsten oxide, ion - doped hafnium oxide, ion - doped tantalum oxide, ion - doped niobium oxide, ion - doped silicon nitride, ion - doped titanium nitride, ion - doped aluminum nitride, ion - doped tungsten nitride, ion - doped hafnium nitride, ion - doped tantalum nitride, ion - doped niobium nitride, ion - doped silicon oxynitride, ion - doped titanium oxynitride, ion - doped aluminum oxynitride, ion - doped tungsten oxynitride, ion - doped hafnium oxynitride, ion - doped tantalum oxynitride, ion - doped niobium oxynitride, or a combination thereof. The ions can include at least one of arsenic (As) or germanium (Ge). For example, the selection element layer 30 can include a silicon oxide layer doped with at least one of arsenic (As) or germanium (Ge) (e.g., As - SiO2, Ge - SiO2, and AsGe - SiO2).

[0027] The intermediate electrode 60 can be disposed on the selection element layer 30 or the second magneto - control element 40. The intermediate electrode 60 can include a carbon layer. In one embodiment, the intermediate electrode 60 can include at least one conductor, for example, a carbon - containing metal, a carbon - containing metal compound, a carbon - containing metal alloy, or a carbon - containing metal silicide. In another embodiment, the intermediate electrode 60 can include a carbon - structured layer, for example, a graphene layer.

[0028] The storage element layer 80 may be disposed on the intermediate electrode 60. The storage element layer 80 may include a variable resistance layer. For example, the storage element layer 80 may include a magnetoresistive layer or a phase change resistive layer. In one embodiment, the storage element layer 80 may include a magnetic tunnel junction (MTJ).

[0029] The upper electrode 95 may be disposed on the storage element layer 80. The upper electrode 95 may conduct the current flowing through the storage element layer 80 and supply it to the upper interconnect line 90. The upper electrode 95 may include a conductor, for example, a metal, a metal silicide, a metal compound, or a metal alloy. For example, the upper electrode 95 may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), chromium (Cr), tungsten nitride (WN), tungsten silicide (WSi), titanium silicide (TiSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum (TiAl), or a combination thereof.

[0030] Referring to Figure 2B , the memory cell structure MC2 of a semiconductor memory device according to an embodiment of the present disclosure may include a lower electrode 15, a first magneto - control element 20, a selection element layer 30, a second magneto - control element 40, a first magnetic shielding element 50, an intermediate electrode 60, a storage element layer 80, and an upper electrode 95 stacked in the vertical direction Z between the lower interconnect line 10 and the upper interconnect line 90. Compared with Figure 2A the memory cell structure MC1, the memory cell structure MC2 may further include a first magnetic shielding element 50 disposed between the second magneto - control element 40 and the intermediate electrode 60.

[0031] Referring to Figure 2C , the memory cell structure MC3 of a semiconductor memory device according to an embodiment of the present disclosure may include a lower electrode 15, a first magneto - control element 20, a selection element layer 30, a second magneto - control element 40, an intermediate electrode 60, a second magnetic shielding element 70, a storage element layer 80, and an upper electrode 95 stacked in the vertical direction Z between the lower interconnect line 10 and the upper interconnect line 90. Different from Figure 2A the memory cell structure MC1, the memory cell structure MC3 may further include a second magnetic shielding element 70 disposed between the intermediate electrode 60 and the storage element layer 80.

[0032] The first and second magnetic shielding elements 50 and 70 may be selectively disposed below or above the intermediate electrode 60, respectively. The first and second magnetic shielding elements 50 and 70 may shield or reduce the influence of the magnetic field on the storage element layer 80.

[0033] In some embodiments, the memory cell structures MC1 to MC3 can be implemented without the lower electrode 15 and the upper electrode 95. For example, the elements below the lower electrode 15 (e.g., the lower interconnect 10) and the elements above the lower electrode 15 (e.g., the first magneto - control element 20) can be connected to each other or in direct contact, and the elements below the upper electrode 95 (e.g., the memory element layer 80) and the elements above the upper electrode 95 (e.g., the upper interconnect) can be in direct contact with each other.

[0034] In some embodiments, the memory cell structures MC1 to MC3 can be implemented without at least one of the first magneto - control element 20, the second magneto - control element 40, or the first and second magnetic shielding elements 50 and 70.

[0035] Figures 3A to 3C FIG. is a diagram showing the first magneto - control element 20 according to some embodiments of the technology of the present disclosure.

[0036] Referring to Figure 3A , the first magneto - control element 20 according to an embodiment of the technology of the present disclosure can include a first magneto - control layer 22. For example, the first magneto - control element 20 can represent the same layer as the first magneto - control layer 22. The first magneto - control layer 22 can be in direct contact with the lower electrode 15 and the select element layer 30.

[0037] Referring to Figure 3B , the first magneto - control element 20 according to an embodiment of the technology of the present disclosure can include a first magneto - control layer 22 and a first upper magneto - control barrier layer 23. For example, the first upper magneto - control barrier layer 23 can be disposed between the first magneto - control layer 22 and the select element layer 30. The first upper magneto - control barrier layer 23 can prevent the diffusion and movement of atoms between the first magneto - control layer 22 and the select element layer 30. The first upper magneto - control barrier layer 23 can enhance the adhesion between the first magneto - control layer 22 and the select element layer 30.

[0038] Referring to Figure 3C , the first magneto - control element 20 according to an embodiment of the technology of the present disclosure can include a first lower magneto - control barrier layer 21, a first magneto - control layer 22, and a first upper magneto - control barrier layer 23. The first lower magneto - control barrier layer 21 can be disposed between the lower electrode 15 and the first magneto - control layer 22. The first lower magneto - control barrier layer 21 can prevent the diffusion and movement of atoms between the lower electrode 15 and the first magneto - control layer 22. The first lower magneto - control barrier layer 21 can enhance the adhesion between the lower electrode 15 and the first magneto - control layer 22.

[0039] The first lower magneto - control barrier layer 21 and the first upper magneto - control barrier layer 23 can include a conductor, for example, a metal, a metal silicide, a metal compound, or a metal alloy. In one embodiment, the first lower magneto - control barrier layer 21 and the first upper magneto - control barrier layer 23 can include at least one of titanium nitride (TiN), titanium tungsten (TiW), or titanium aluminum nitride (TiAlN).

[0040] Figures 4A to 4C FIG. is a diagram showing a second magneto - control element 40 according to some embodiments of the present disclosure technology.

[0041] Referring to Figure 4A , the second magneto - control element 40 according to an embodiment of the present disclosure technology may include a second magneto - control layer 42. For example, the second magneto - control element 40 may be the second magneto - control layer 42. The second magneto - control layer 42 may be in direct contact with the selection element layer 30 and the intermediate electrode 60.

[0042] Referring to Figure 4B , the second magneto - control element 40 according to an embodiment of the present disclosure technology may include a second lower magneto - control barrier layer 41 and a second magneto - control layer 42. For example, the second lower magneto - control barrier layer 41 may be disposed between the selection element layer 30 and the second magneto - control layer 42. The second lower magneto - control barrier layer 41 may prevent the diffusion and movement of atoms between the selection element layer 30 and the second magneto - control layer 42. The second lower magneto - control barrier layer 41 may enhance the adhesion between the selection element layer 30 and the second magneto - control layer 42.

[0043] Referring to Figure 4C , the second magneto - control element 40 according to an embodiment of the present disclosure technology may include a second lower magneto - control barrier layer 41, a second magneto - control layer 42, and a second upper magneto - control barrier layer 43. The second upper magneto - control barrier layer 43 may be disposed between the second magneto - control layer 42 and the intermediate electrode 60. The second upper magneto - control barrier layer 43 may prevent the diffusion and movement of atoms between the second magneto - control layer 42 and the intermediate electrode 60. The second upper magneto - control barrier layer 43 may enhance the adhesion between the second magneto - control layer 42 and the intermediate electrode 60.

[0044] The second lower magneto - control barrier layer 41 and the second upper magneto - control barrier layer 43 may include a conductor, for example, a metal, a metal silicide, a metal compound, or a metal alloy. In one embodiment, the second lower magneto - control barrier layer 41 and the second upper magneto - control barrier layer 43 may include at least one of titanium nitride (TiN) or titanium aluminum nitride (TiAlN).

[0045] The first magneto - control layer 22 and the second magneto - control layer 42 may include materials without magnetic anisotropy. For example, each of the first magneto - control layer 22 and the second magneto - control layer 42 may include at least one of cobalt (Co), iron (Fe), nickel (Ni), molybdenum (Mo), aluminum (Al), chromium (Cr), permalloy, or super - permalloy. In one embodiment, each of the first magneto - control layer 22 and the second magneto - control layer 42 may include one of the oxides containing at least one of cobalt (Co), iron (Fe), nickel (Ni), molybdenum (Mo), aluminum (Al), chromium (Cr), permalloy, or super - permalloy. In one embodiment, each of the first magneto - control layer 22 and the second magneto - control layer 42 may include one of the nitrides containing at least one of cobalt (Co), iron (Fe), nickel (Ni), molybdenum (Mo), aluminum (Al), chromium (Cr), permalloy, or super - permalloy. Permalloy may include nickel (Ni) and iron (Fe). For example, permalloy may contain approximately 80% nickel (Ni) and approximately 20% iron (Fe). Super - permalloy may include nickel (Ni), iron (Fe), and molybdenum (Mo). For example, super - permalloy may contain approximately 75% nickel (Ni), approximately 20% iron (Fe), and approximately 5% molybdenum (Mo).

[0046] Figures 5A to 5C is a diagram showing the adjustment of the distance between the first magneto - control element 20 and the second magneto - control element 40. Referring to Figure 5A , the distance (gap) between the first magneto - control layer 22 of the first magneto - control element 20 and the second magneto - control layer 42 of the second magneto - control element 40 may be a first distance d1. As Figure 3A and Figure 4A shown, the first magneto - control layer 22 of the first magneto - control element 20 and the second magneto - control layer 42 of the second magneto - control element 40 may be in direct contact with the selection element layer 30.

[0047] Referring to Figure 5B , the distance (gap) between the first magneto - control layer 22 of the first magneto - control element 20 and the second magneto - control layer 42 of the second magneto - control element 40 may be a second distance d2. As Figure 3B and Figure 4B shown, a first upper magneto - control barrier layer 23 may be disposed between the selection element layer 30 and the first magneto - control layer 22, and a second lower magneto - control barrier layer 41 may be disposed between the selection element layer 30 and the second magneto - control layer 42. The distance (gap) between the first magneto - control layer 22 and the second magneto - control layer 42 can be adjusted by the first upper magneto - control barrier layer 23 and the second lower magneto - control barrier layer 41. That is, compared with Figure 5A , the distance (gap) between the first magneto - control layer 22 and the second magneto - control layer 42 can be increased. As shown in the figure, the second distance d2 may be greater than the first distance d1.

[0048] Referring to Figure 5C , compared withFigure 5B In contrast, the thickness of the first upper magnetron blocking layer 23 and the thickness of the second lower magnetron blocking layer 41 can be increased. Accordingly, the distance (gap) between the first magnetron layer 22 of the first magnetron element 20 and the second magnetron layer 42 of the second magnetron element 40 can be a third distance d3. The third distance d3 can be greater than the second distance d2.

[0049] Referring to Figures 5A to 5C , the distance between the first magnetron layer 22 and the second magnetron layer 42 can be adjusted by the thickness of the first upper magnetron blocking layer 23 and the thickness of the second lower magnetron blocking layer 41. The first upper magnetron blocking layer 23 and the second lower magnetron blocking layer 41 can be independently provided or omitted. For example, only one of the first upper magnetron blocking layer 23 and the second lower magnetron blocking layer 41 can be selectively provided.

[0050] Figures 6A to 6C FIG. is a diagram showing a first magnetic shielding element 50 according to some embodiments of the technology of the present disclosure. Referring to Figure 6A , the first magnetic shielding element 50 according to an embodiment of the technology of the present disclosure can be provided between the second magnetron element 40 and the intermediate electrode 60. The first magnetic shielding element 50 can include a first magnetic shielding layer 52. For example, the first magnetic shielding element 50 can be the same as the first magnetic shielding layer 52. The first magnetic shielding layer 52 can be in direct contact with the second magnetron element 40 and the intermediate electrode 60.

[0051] Referring to Figure 6B , the first magnetic shielding element 50 according to an embodiment of the technology of the present disclosure can include a first magnetic shielding layer 52 and a first upper magnetic shielding blocking layer 53. The first upper magnetic shielding blocking layer 53 can be provided between the first magnetic shielding layer 52 and the intermediate electrode 60. The first upper magnetic shielding blocking layer 53 can prevent the diffusion and movement of atoms between the first magnetic shielding layer 52 and the intermediate electrode 60. The first upper magnetic shielding blocking layer 53 can enhance the adhesion between the first magnetic shielding layer 52 and the intermediate electrode 60.

[0052] Referring to Figure 6C , the first magnetic shielding element 50 according to an embodiment of the technology of the present disclosure can include a first lower magnetic shielding blocking layer 51, a first magnetic shielding layer 52, and a first upper magnetic shielding blocking layer 53. The first lower magnetic shielding blocking layer 51 can be provided between the second magnetron element 40 and the magnetic shielding layer 52. The first lower magnetic shielding blocking layer 51 can prevent the diffusion and movement of atoms between the second magnetron element 40 and the first magnetic shielding layer 52. The first lower magnetic shielding blocking layer 51 can enhance the adhesion between the second magnetron element 40 and the first magnetic shielding layer 52. In Figure 6C , the first upper magnetic shielding blocking layer 53 can be omitted.

[0053] Figures 7A to 7CFIG. is a diagram showing a second magnetic shielding element 70 according to some embodiments of the present disclosure technology. Referring to Figure 7A , a second magnetic shielding element 70 according to an embodiment of the present disclosure technology may be disposed between the intermediate electrode 60 and the storage element layer 80. The second magnetic shielding element 70 may include a second magnetic shielding layer 72. For example, the second magnetic shielding element 70 may be the same as the second magnetic shielding layer 72. The second magnetic shielding layer 72 may be in direct contact with the intermediate electrode 60 and the storage element layer 80.

[0054] Referring to Figure 7B , a second magnetic shielding element 70 according to an embodiment of the present disclosure technology may include a second lower magnetic shielding barrier layer 71 and a second magnetic shielding layer 72. The second lower magnetic shielding barrier layer 71 may be disposed between the intermediate electrode 60 and the second magnetic shielding layer 72. The second lower magnetic shielding barrier layer 71 may prevent the diffusion and movement of atoms between the intermediate electrode 60 and the second magnetic shielding layer 72. The second lower magnetic shielding barrier layer 71 may enhance the secondary adhesion between the intermediate electrode 60 and the second magnetic shielding layer 72.

[0055] Referring to Figure 7C , a second magnetic shielding element 70 according to an embodiment of the present disclosure technology may include a second lower magnetic shielding barrier layer 71, a second magnetic shielding layer 72, and a second upper magnetic shielding barrier layer 73. The second upper magnetic shielding barrier layer 73 may be disposed between the second magnetic shielding layer 72 and the storage element layer 80. The second upper magnetic shielding barrier layer 73 may prevent the diffusion and movement of atoms between the second magnetic shielding layer 72 and the storage element layer 80. The second upper magnetic shielding barrier layer 73 may enhance the adhesion between the second magnetic shielding layer 72 and the storage element layer 80. In Figure 6C , the second lower magnetic shielding barrier layer 71 may be omitted.

[0056] In one embodiment, each of the first and second magnetic shielding layers 52 and 72 may include a metal alloy that contains at least two of nickel (Ni), iron (Fe), copper (Cu), aluminum (Al), chromium (Cr), and molybdenum (Mo). In one embodiment, each of the first and second magnetic shielding layers 52 and 72 may include at least one of ferrite, permalloy, supermalloy, carbon steel, stainless steel, Ni-Co-based materials, Fe-Ni-based materials, Fe-Cr-based materials, Fe-Al-based materials, Fe-Si-B-based materials, Fe-Si-B-Cu-Nb-based materials, Mn-Zn-based materials, Ni-Zn-based materials, Ni-Co-based materials, Mg-Zn-based materials, or Cu-Zn-based materials. In one embodiment, each of the first and second magnetic shielding elements 50 and 70 may contain approximately 70% to 80% nickel (Ni), approximately 15% to 25% iron (Fe), and approximately 5% of at least one of copper (Cu), aluminum (Al), chromium (Cr), or molybdenum (Mo).

[0057] The first and second lower magnetic shielding barrier layers 51 and 71 and the first and second upper magnetic shielding barrier layers 53 and 73 may each include a conductor, e.g., a metal, metal silicide, metal compound, or metal alloy. In one embodiment, the first and second lower magnetic shielding barrier layers 51 and 71 and the first and second upper magnetic shielding barrier layers 53 and 73 may each include at least one of titanium nitride (TiN), titanium tungsten (TiW), or titanium aluminum nitride (TiAlN).

[0058] The first and second magnetic shielding elements 50 and 70 may be provided exclusively. That is, either of the first and second magnetic shielding elements 50 and 70 may be selectively provided or omitted.

[0059] Figure 8 is a diagram showing a storage element layer 80 according to an embodiment of the disclosed technology. Refer to Figure 8, the storage element layer 80 based on an embodiment of the present disclosure technology may include a magnetic tunnel junction (MTJ). For example, the storage element layer 80 may include a lower magnetic layer 81, a tunneling barrier layer 82, and an upper magnetic layer 83. In one embodiment, the lower magnetic layer 81 may be a free magnetization layer, and the upper magnetic layer 83 may be a fixed (pinned) magnetization layer. In another embodiment, the lower magnetic layer 81 may be a fixed (pinned) magnetization layer, and the upper magnetic layer 83 may be a free magnetization layer. The lower magnetic layer 81 and the upper magnetic layer 83 may include an alloy or a compound that contains at least two of iron (Fe), nickel (Ni), cobalt (Co), boron (B), platinum (Pt), and palladium (Pd). For example, the first magnetic layer 81 may include at least one of an Fe-Pt alloy, an Fe-Pd alloy, a Co-Pd alloy, a Co-Pt alloy, an Fe-Ni-Pt alloy, a Co-Fe-Pt alloy, a Co-Fe-B alloy, a Co / Pt stack, or a Co / Pd stack. The tunneling barrier layer 82 may be disposed between the lower magnetic layer 81 and the upper magnetic layer 83. Electrons may tunnel through the tunneling barrier layer 82 by an electric field between the lower electrode 15 and the upper electrode 95. The tunneling barrier layer 82 may include an insulating metal oxide. For example, the tunneling barrier layer 82 may include at least one of a magnesium oxide (MgO) layer, a calcium oxide (CaO) layer, a strontium oxide (SrO) layer, a titanium oxide (TiO) layer, a vanadium oxide (Vo) layer, a niobium oxide (NbO) layer, an aluminum oxide (AlO) layer, a tantalum oxide (TaO) layer, a ruthenium oxide (RuO) layer, a beryllium oxide (BeO) layer, a barium oxide (BaO) layer, or a bismuth oxide (BiO) layer.

[0060] In some embodiments of the present disclosure technology, the leakage current generated after the channel is formed may be reduced.

[0061] In some embodiments of the present disclosure technology, the leakage current in the off state may be reduced.

[0062] In some embodiments of the present disclosure technology, a uniform electromagnetic field may be formed in the selection element layer.

[0063] Only a few embodiments and examples are described. The disclosed embodiments and other embodiments may be enhanced and modified based on the content described and illustrated in this patent document.

Claims

1. A semiconductor device, comprising: Lower interconnection line; a lower electrode, the lower electrode being disposed on the lower interconnection line; a first magnetron layer, wherein the first magnetron layer is disposed on the lower electrode; A selection element layer, the selection element layer is arranged on the first magnetron layer; a second magnetron layer, the second magnetron layer being disposed on the selection element layer, wherein the first magnetron layer and the second magnetron layer control a magnetic field in the selection element layer; a storage element layer, the storage element layer being disposed on the second magnetron layer and storing data; an upper electrode disposed on the storage element layer; and an upper interconnection line, the upper interconnection line being arranged on the upper electrode, Wherein, each of the first magnetron layer and the second magnetron layer includes at least one of the following: cobalt, iron, nickel, molybdenum, aluminum, chromium, permalloy, superpermeable alloy, oxides thereof, and nitrides thereof.

2. The semiconductor device according to claim 1, further comprising: A first upper magnetron barrier layer is provided between the first magnetron layer and the selection element layer.

3. The semiconductor device according to claim 2, in, The first upper magnetron barrier layer includes titanium nitride.

4. The semiconductor device according to claim 1, further comprising: A first lower magnetron barrier layer is disposed between the lower electrode and the first magnetron layer.

5. The semiconductor device according to claim 1, further comprising: A lower magnetron barrier layer is provided between the selection element layer and the second magnetron layer.

6. The semiconductor device according to claim 5, in, The lower magnetron barrier layer includes titanium nitride.

7. The semiconductor device according to claim 5, further comprising: An upper magnetron barrier layer is disposed between the second magnetron layer and the storage element layer.

8. The semiconductor device according to claim 1, further comprising: An intermediate electrode is disposed between the second magnetron layer and the storage element layer.

9. The semiconductor device according to claim 8, in, The intermediate electrode includes at least one of the following: a carbon layer, a carbon-containing metal, a carbon-containing metal compound, a carbon-containing metal alloy, a carbon-containing metal silicide, and a graphene layer.

10. The semiconductor device according to claim 8, further comprising: A magnetic shielding layer is provided between the second magnetron layer and the intermediate electrode or between the intermediate electrode and the storage element layer.

11. The semiconductor device according to claim 10, in, The magnetic shielding layer includes a metal alloy containing at least two of nickel, iron, copper, aluminum, chromium, and molybdenum.

12. The semiconductor device according to claim 10, further comprising: A magnetic shielding barrier layer is disposed between the magnetic shielding layer and the intermediate electrode.

13. The semiconductor device according to claim 12, in, The magnetic shielding barrier layer includes titanium nitride.

14. The semiconductor device according to claim 10, further comprising: A magnetic shielding barrier layer is provided between the magnetic shielding layer and the storage element layer.

15. A semiconductor device comprising: Lower electrode; a first magnetron layer, wherein the first magnetron layer is disposed on the lower electrode; A selection element layer, the selection element layer is arranged on the first magnetron layer; a second magnetron layer, the second magnetron layer being disposed on the selection element layer; a magnetic shielding layer, the magnetic shielding layer being disposed on the second magnetron layer, wherein the magnetic shielding layer reduces the magnetic field to the storage element layer; the storage element layer, which is provided on the magnetic shielding layer and stores data; and an upper electrode, the upper electrode being arranged on the storage element layer, The first magnetron layer and the second magnetron layer control the magnetic field formed in the selection element layer. Wherein, each of the first magnetron layer and the second magnetron layer comprises a metal without magnetic anisotropy, Wherein, the magnetic shielding layer includes at least one of a metal alloy layer, an oxide layer and a nitride layer, Wherein, each of the metal alloy layer, the oxide layer and the nitride layer includes at least two of nickel, iron, copper, aluminum, chromium and molybdenum.

16. The semiconductor device according to claim 15, in, Each of the first magnetron layer and the second magnetron layer includes at least one of the following: cobalt, iron, nickel, molybdenum, aluminum, chromium, permalloy, supermalloy, oxides thereof, and nitrides thereof.

17. The semiconductor device according to claim 15, further comprising: An intermediate electrode is arranged between the second magnetron layer and the magnetic shielding layer or between the magnetic shielding layer and the storage element layer.

18. The semiconductor device according to claim 15, in, The storage element layer includes a magnetic tunnel junction including a free magnetization layer, a tunnel barrier layer, and a fixed magnetization layer.

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