Method for etching SiC PiN groove terminal structure

Abstract

The invention provides an etching method for a terminal structure of a semiconductor device, which comprises the following steps of: depositing two layers of silicon oxide masks with different thicknesses and densities on the surface of a SiC wafer, and then etching the SiC wafer by adjusting etching process parameters, mainly introducing SF6 and O2 into a reaction chamber as etching gases and simultaneously turning on a power supply of an upper electrode and a power supply of a lower electrode. And etching a small-angle groove structure on the SiC surface. The terminal structure is small in angle, smooth in table top bottom, free of micro-grooves and less than 0.5 nm in roughness. According to the method, the process of preparing the SiC PiN small-angle groove terminal structure is simplified, meanwhile, the roughness of the side wall and the bottom of the groove is effectively reduced, breakdown of an electric field at the corner of the groove can be effectively prevented, the reverse breakdown voltage of a SiC PiN device is improved, and more requirements for a semiconductor device etching mesa structure can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device manufacturing, and relates to an etching method for semiconductor devices, specifically to a method for etching a SiC PiN trench terminal structure. Background Art

[0002] Having a stable high breakdown voltage is one of the important characteristics of 4H-SiC PiN power diodes. The Mesa-JTE type terminal structure can effectively control the peak electric field and surface electric field, and is currently the most effective and reliable terminal technology for realizing high-voltage and ultra-high-voltage characteristics. In the design and optimization of Mesa-JTE, in addition to considering the JTE structure parameters, the Mesa trench etching morphology also plays an important role in alleviating the electric field concentration effect. Currently, the etching of 4H-SiC is generally realized by plasma technology. However, in the dry etching process of 4H-SiC Mesa structure, problems such as micro-trenches and increased roughness of the sidewalls and bottoms of the etched backplane often occur, seriously affecting the breakdown voltage and reliability of the device. Therefore, while obtaining an etched surface with a low defect density, how to eliminate the micro-trench effect is also a hot spot and difficulty in the research of Mesa-based 4H-SiC power devices.

[0003] The traditional dry etching process of SiC will obtain relatively steep sidewalls and a bottom morphology with sharp corners, while obtaining a gentle mesa morphology with a mesa angle below 30° and a rounded bottom will make the dry etching process more complex. At the same time, serious micro-trench structures will appear, and it is difficult to control the roughness of the trench mesa and bottom below 0.5 nm, generally at 3 - 4 nm or even more than ten nanometers. In high-voltage SiC PiN devices, this will greatly affect the electrical performance of the device, such as causing a decrease in breakdown voltage and an increase in reverse current. In addition, the traditional process methods for improving etching roughness and micro-trenches are high-temperature Ar annealing, sacrificial oxidation, and H2 hydrogen etching, but these methods require additional steps, increasing the process complexity. Summary of the Invention

[0004] Aiming at the problems existing in the prior art, the present invention provides an etching method for semiconductor devices. The method simplifies the process of preparing a SiC PiN small-angle trench terminal structure, and at the same time effectively reduces the roughness of the trench sidewalls and bottoms, greatly improving the preparation efficiency of the etched small-angle SiC trench terminal structure.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A method for etching a SiC PiN trench terminal structure, comprising the following steps:

[0007] (1) Pre - cleaning of SiC wafers: After cleaning with Cleaning Solution No. 1 (NH4OH:H2O2:H2O), Cleaning Solution No. 2 (HCl:H2O2:H2O), and BOE cleaning solution, they are ready for use.

[0008] (2) Depositing a dense SiO2 thin film on the surface of SiC wafers by PECVD method.

[0009] (3) Depositing a loose SiO2 thin film on top of the dense SiO2 thin film by PECVD method.

[0010] (4) Coating a layer of photoresist on the loose SiO2 thin film.

[0011] (5) Exposure by a lithography machine.

[0012] (6) Developing after exposure.

[0013] (7) Hard - baking after developing.

[0014] (8) Etching two SiO2 thin films with different densities using BOE solution, requiring over - etching by 50%, and controlling the SiO2 inclination angle within 10° - 15°.

[0015] (9) Etching the bottom of the dense SiO2 thin film using BOE solution.

[0016] (10) Dry etching process: Using the SiO2 thin film with an inclination angle of 10° - 15° as a mask to etch SiC wafers, and introducing SF6 and O2 as etching gases.

[0017] (11) Removing the surface photoresist and SiO2 mask layer.

[0018] (12) Pickling and soaking the etched SiC wafers using BOE solution.

[0019] (13) Testing the SiC mesa inclination angle, bottom morphology, and side - wall roughness using AFM and SEM.

[0020] Further, the cleaning time in step (1) is as follows: Cleaning SiC wafers with Cleaning Solution No. 1 (NH4OH:H2O2:H2O) for 5 - 10 minutes; cleaning SiC wafers with Cleaning Solution No. 2 (HCl:H2O2:H2O) for 5 - 10 minutes; cleaning SiC wafers with BOE cleaning solution for 30 - 60 seconds.

[0021] Further, the thickness of the dense SiO2 thin film in step (2) is 1 - 2μm.

[0022] Further, the thickness of the loose SiO2 thin film in step (3) is 40 - 200nm.

[0023] Further, the thickness of the photoresist in step (4) is 1.8 - 2.2 μm.

[0024] Further, the focal length of the exposure by the lithography machine in step (5) is 0.3 ± 0.1, the light intensity is adjusted to 680 - 750 mW / cm 2 , the uniformity requirement is within 2%, and the exposure time is 7 - 9 s.

[0025] Further, the development time in step (6) is 60 - 90 s.

[0026] Further, the temperature of the hard baking in step (7) is 100 - 120 °C; the time of the hard baking is 60 - 120 s.

[0027] Further, the parameters of the dry etching process in step (10) are as follows: the value range of the SF6 flow rate is 40 - 60 sccm, the value range of the O2 flow rate is 5 - 20 sccm, the value range of the pressure in the chamber is 5 - 20 mT, the power range of the upper electrode power supply is 1600 - 1800 W, and the value range of the lower electrode power is 100 - 200 W.

[0028] Further, in step (11), a mixed solution of H2SO4 and H2O2 is used to remove the surface photoresist, and a DHF solution is used to remove the SiO2 mask layer.

[0029] An etching method for a semiconductor device provided by the present invention has key characteristics as follows: first, two silicon dioxide thin films with different thicknesses and different densities deposited on the SiC surface are etched to realize the patterning of the silicon oxide mask; then, the etching process parameters are adjusted to etch the SiC wafer, mainly by introducing SF6 and O2 into the reaction chamber as etching gases, and at the same time turning on the upper and lower electrode power supplies to etch a small-angle trench structure on the SiC wafer surface. Among them, the lower electrode power supply is a low-frequency power supply. By reducing the power of the lower electrode power supply and increasing the flow rate of SF6, the purpose is to weaken the etching of the reaction ions on the corner of the trench mesa, prevent the formation of micro-trenches at the corner, make the trench sidewalls straight and smooth, and finally obtain a trench terminal structure with a small angle, a smooth bottom, no micro-trenches, and a roughness less than 0.5 nm.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The traditional process methods for improving etching roughness and micro-trenches are mainly high-temperature Ar annealing, sacrificial oxidation, and H2 etching, but additional steps are required, which complicate the process. The present invention simplifies the process flow for preparing the SiC PiN small-angle trench terminal structure, and at the same time effectively reduces the roughness of the trench sidewalls and the bottom, can effectively prevent the electric field from breaking down at the trench corners, improve the reverse breakdown voltage of the SiC PiN device, and will meet more requirements for the etching mesa structure of semiconductor devices. Description of the Drawings

[0032] Figure 1 This is the full process flow chart of the method for etching the SiC PiN trench terminal structure in Embodiment 1 of the present invention;

[0033] Figure 2 This is the AFM test result of the bottom of the SiC trench after dry etching in Embodiment 1 of the present invention;

[0034] Figure 3 This is the AFM test result of the sidewall of the SiC trench after dry etching in Embodiment 1 of the present invention;

[0035] Figure 4 This is the SEM test result of the SiC trench mesa after dry etching in Embodiment 1 of the present invention. Detailed Embodiments

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. In addition, it is worth noting that the raw materials involved in the present invention are all ordinary commercially available products unless otherwise specified.

[0037] Embodiment 1

[0038] As Figure 1 shown, a method for etching the SiC PiN trench terminal structure specifically includes the following steps:

[0039] (1) Pre-cleaning of the SiC wafer: 1# cleaning solution (NH4OH:H2O2:H2O), for 5 - 10 minutes; 2# cleaning solution (HCl:H2O2:H2O), for 5 - 10 minutes; BOE cleaning solution, for 30 - 60 seconds, for standby;

[0040] (2) Depositing a dense SiO2 film on the SiC wafer by PECVD method, with a thickness of 1.5 μm;

[0041] (3) Depositing a loose SiO2 film on the dense SiO2 film by PECVD method, with a thickness of 200 nm;

[0042] (4) Spin-coating photoresist on the loose SiO2 film, with a thickness of 1.8 μm, pre-baking at 95 °C for 90 seconds;

[0043] (5) Contact exposure with a lithography machine for 7 seconds;

[0044] (6) Developing for 45 seconds after exposure;

[0045] (7) The hardening process lasts for 60 seconds;

[0046] (8) Use BOE solution for wet etching of the double-layer SiO2 mask, with a required over-etching of 50%, and control the SiO2 inclination angle within 10° - 15°;

[0047] (9) BOE etches the bottom of the SiO2 mask for 10 s;

[0048] (10) The etching machine dry-etchs the SiC material, introducing SF6 and O2 as etching gases, with an SF6 flow rate of 50 sccm, an O2 flow rate of 15 sccm, a chamber pressure of 5 mT, an upper electrode power of 1700 W, and a lower electrode power of 150 W;

[0049] (11) Use a mixed solution of H2SO4 and H2O2 to remove the surface photoresist, and use DHF solution to remove the SiO2 mask layer;

[0050] (12) Use BOE solution to pickle and soak the etched SiC wafer;

[0051] (13) Use AFM and SEM to test the SiC mesa inclination angle, bottom morphology, and sidewall roughness.

[0052] As Figures 2-4 shown, they are respectively the AFM test results of the bottom of the SiC trench after dry etching in this embodiment, the AFM test results of the sidewall of the SiC trench, and the SEM test results of the SiC trench mesa. It can be seen from the figure that a SiC mesa with a small angle, a flat bottom, and a smooth sidewall is finally obtained, thereby improving the preparation efficiency of the etched small-angle SiC flat mesa.

[0053] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, rather than limiting the protection scope of the present invention. Any simple modification or equivalent replacement of the technical solution of the present invention by those of ordinary skill in the art shall not depart from the essence and scope of the technical solution of the present invention.

Claims

1. A method for etching a SiC PiN trench terminal structure, comprising the following steps: (1) Pre-cleaning of the SiC wafer: After cleaning with a No. 1 cleaning solution, a No. 2 cleaning solution, and a BOE cleaning solution, it is ready for use. The No. 1 cleaning solution contains NH4OH, H2O2, and H2O, and the No. 2 cleaning solution contains HCl, H2O2, and H2O; (2) Depositing a dense SiO2 thin film on the surface of the SiC wafer by PECVD method; (3) Depositing another layer of porous SiO2 thin film on top of the dense SiO2 thin film by PECVD method; (4) Coating a layer of photoresist on the porous SiO2 thin film; (5) Exposure by a lithography machine; (6) Developing after exposure; (7) Hardening the film after developing; (8) Etching two SiO2 thin films with different degrees of density using a BOE solution, requiring over-etching by 50%, and controlling the SiO2 inclination angle within 10° - 15°; (9) Etching the bottom of the dense SiO2 thin film using a BOE solution; (10) Dry etching process: Using the SiO2 thin film with an inclination angle of 10° - 15° as a mask to etch the SiC wafer, and introducing SF6 and O2 as etching gases; (11) Removing the surface photoresist and SiO2 mask layer; (12) The etched SiC wafer is pickled and soaked with BOE solution; (13) AFM and SEM are used to measure the SiC mesa inclination angle, bottom morphology and sidewall roughness.

2. The method according to claim 1, wherein The cleaning time in step (1) is as follows: The SiC wafer is cleaned with the 1# cleaning solution for 5 - 10 minutes; the SiC wafer is cleaned with the 2# cleaning solution for 5 - 10 minutes; the SiC wafer is cleaned with the BOE cleaning solution for 30 - 60 seconds.

3. The method according to claim 1, wherein The thickness of the dense SiO2 film in step (2) is 1 - 2 μm.

4. The method according to claim 1, wherein The thickness of the porous SiO2 film in step (3) is 40 - 200 nm.

5. The method according to claim 1, wherein The thickness of the photoresist in step (4) is 1.8 - 2.2 μm.

6. The method according to claim 1, wherein The focal length of the exposure by the lithography machine described in step (5) is 0.3 ± 0.1, the light intensity is adjusted to 680 - 750 mW / cm 2 , the uniformity requirement is within 2%, and the exposure time is 7 - 9 s.

7. The method according to claim 1, wherein The development time in step (6) is 60 - 90 s.

8. The method according to claim 1, wherein The temperature of the hard baking in step (7) is 100 - 120 °C; the time of the hard baking is 60 - 120 s.

9. The method according to claim 1, wherein The parameters of the dry etching process in step (10) are as follows: the SF6 flow rate ranges from 40 to 60 sccm, the O2 flow rate ranges from 5 to 20 sccm, the chamber pressure ranges from 5 to 20 mT, the upper electrode power ranges from 1600 to 1800 W, and the lower electrode power ranges from 100 to 200 W.

10. The method according to claim 1, wherein In step (11), a mixed solution of H2SO4 and H2O2 is used to remove the surface photoresist, and DHF solution is used to remove the SiO2 mask layer.

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