Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a plurality of gate trenches in a semiconductor layer; forming a body region and a source region in the semiconductor layer between the adjacent gate trenches, wherein the body region between the adjacent gate trenches comprises a first body region and a second body region; forming a first groove in the semiconductor layer; forming a body contact area at the bottom of the first groove; etching the first groove, and removing a contact region at the bottom of the first groove to form a second groove; depositing a conductive material in the second groove to form a first conductive layer; wherein the width of the second groove is greater than the width of the interval between the first body region and the second body region. According to the semiconductor device and the manufacturing method thereof, the Schottky diode is integrated in the MOS region, so that the area and the cost of the device can be reduced while low reverse recovery charges are maintained.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and particularly to a semiconductor device integrated with a diode and a manufacturing method thereof. Background Art

[0002] In the current technical field of power devices, with the continuous improvement of the performance requirements of electronic products, reducing Qrr (Reverse Recovery Charge) has become one of the key technical indicators. Generally, an integrated chip including an SBD (Schottky Barrier Diode) and a main MOS has specific functional performances during circuit operation. The SBD has fast switching characteristics, and its forward conduction voltage is relatively low, which can quickly respond during processes such as circuit current commutation, reducing energy loss; while the main MOS (Metal - Oxide - Semiconductor Field - Effect Transistor) can effectively control and amplify current. The two work together to theoretically optimize the circuit performance.

[0003] Regarding existing power devices, a common practice is to perform specific structure integration in areas other than the MOS, that is, to connect the SBD in parallel with the main MOS, in order to achieve the purpose of reducing Qrr. Although this integration method is helpful to a certain extent in reducing Qrr, it has caused new problems. On the one hand, in order to accommodate the SBD, it is necessary to reserve a certain amount of chip area additionally, which directly leads to an additional increase in chip cost, making the entire power device at a disadvantage in cost control. On the other hand, in order to further reduce Qrr, the prior art also uses the method of purchasing expensive platinum diffusion equipment. The platinum diffusion equipment is expensive, which not only greatly increases the upfront equipment investment cost, but also the subsequent maintenance and operation costs cannot be underestimated, bringing a heavy economic burden to related enterprises and R & D work. Summary of the Invention

[0004] In view of the above problems, the purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, by integrating a diode in the MOS region, so as to reduce the device area and cost while maintaining a low reverse recovery charge.

[0005] According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a plurality of gate trenches in a semiconductor layer, the semiconductor layer including opposite first and second surfaces, the gate trenches extending from the first surface of the semiconductor layer towards the second surface; forming a body region and a source region in the semiconductor layer between adjacent gate trenches, the body region between adjacent gate trenches including a first body region and a second body region, the first body region and the second body region respectively adjacent to the sidewalls of adjacent gate trenches, and a platform region of the semiconductor layer being spaced between the first body region and the second body region; forming a first groove in the semiconductor layer between the first body region and the second body region between adjacent gate trenches, a bottom of the first groove being lower than a bottom of the source region and higher than a bottom of the body region; forming body contact regions in the semiconductor layer at the bottom of the first groove and in the body regions near the bottom regions of both sidewalls of the first groove; etching the first groove to remove the body contact regions at the bottom of the first groove to form a second groove, a bottom of the second groove being lower than a bottom of the body contact regions; and depositing a conductive material in the second groove to form a first conductive layer; wherein a width of the second groove is greater than a spacing width between the first body region and the second body region.

[0006] Optionally, the material of the first conductive layer includes Ti, TiN.

[0007] Optionally, the bottom of the second groove is higher than the bottoms of the first body region and the second body region.

[0008] Optionally, the step of forming a body region and a source region in the semiconductor layer between adjacent gate trenches includes: forming a patterned second mask layer on the semiconductor layer; performing ion implantation and diffusion in the semiconductor layer via the second mask layer to form a body region; removing the second mask layer; performing ion implantation in the semiconductor layer to form a source region; wherein an upper surface of the body region is adjacent to a lower surface of the source region, and at least one sidewall of the body region and the source region is adjacent to the gate trench.

[0009] Optionally, between the step of forming a plurality of gate trenches in the semiconductor layer and the step of forming a body region and a source region in the semiconductor layer between adjacent gate trenches, further included is: forming a trench gate in the gate trench and forming an interlayer dielectric layer on the first surface of the semiconductor layer.

[0010] Optionally, the steps of forming a trench gate in the gate trench and forming an interlayer dielectric layer on the first surface of the semiconductor layer include: forming a first oxide layer and a first polysilicon layer in the gate trench, the first oxide layer covering the sidewalls of the gate trench and the first surface of the semiconductor layer, the first oxide layer separating the first polysilicon layer and the semiconductor layer; performing a re-etching on the first oxide layer and the first polysilicon layer to remove the first oxide layer and the first polysilicon layer on the first surface of the semiconductor layer and in the upper portion of the gate trench; forming a second oxide layer on the first oxide layer and the first polysilicon layer in the gate trench; forming a third oxide layer and a second polysilicon layer in the gate trench above the second oxide layer, the third oxide layer covering the sidewalls of the upper portion of the gate trench and separating the second polysilicon layer and the semiconductor layer; performing a re-etching on the second polysilicon layer to make the upper surface of the second polysilicon layer in the gate trench lower than the first surface of the semiconductor layer; forming a fourth oxide layer on the first surface of the semiconductor layer and in the gate trench, wherein the third oxide layer covers the first surface of the semiconductor layer, and the third oxide layer and the fourth oxide layer located on the first surface of the semiconductor layer serve as the interlayer dielectric layer.

[0011] Optionally, the thickness of the first oxide layer is greater than the thickness of the third oxide layer.

[0012] Optionally, after the step of depositing a conductive material in the second groove to form a first conductive layer, the method further includes: forming a second conductive layer on the interlayer dielectric layer, the second conductive layer being adjacent to the first conductive layer; forming a third conductive layer on the second surface of the semiconductor layer.

[0013] According to another aspect of the present invention, there is provided a semiconductor device, including: a semiconductor layer including a plurality of gate trenches extending from a first surface of the semiconductor layer to a second surface; a body region, a source region, and a contact region located in the semiconductor layer between adjacent gate trenches, the body region between adjacent gate trenches including a first body region and a second body region, the first body region and the second body region respectively adjacent to the sidewalls of adjacent gate trenches, and a platform region of the semiconductor layer being spaced between the first body region and the second body region; a first conductive layer located in the semiconductor layer between adjacent gate trenches, wherein the first conductive layer penetrates through the source region and the contact region and extends below the source region, at least a part of the bottom surface of the first conductive layer is adjacent to the semiconductor layer separating the first body region and the second body region, and the lateral dimension of the first conductive layer is greater than the interval width between the first body region and the second body region.

[0014] Optionally, the material of the first conductive layer includes Ti, TiN.

[0015] Optionally, the bottom of the first conductive layer is higher than the bottoms of the first body region and the second body region.

[0016] Optionally, further comprising: a trench gate located in the gate trench, the trench gate including a gate dielectric layer, a shielding gate, and a control gate, the shielding gate being located in the lower part of the gate trench, the control gate being located in the upper part of the gate trench, the gate dielectric layer surrounding the shielding gate and the control gate respectively, and separating the shielding gate from the control gate, the shielding gate from the semiconductor layer, and the control gate from the semiconductor layer.

[0017] Optionally, further comprising: an interlayer dielectric layer located on the first surface of the semiconductor layer; a second conductive layer located on the interlayer dielectric layer, the second conductive layer being adjacent to the first conductive layer; and a third conductive layer located on the second surface of the semiconductor layer.

[0018] The semiconductor device and its manufacturing method provided by the present invention integrate a Schottky diode in the cell region of the semiconductor device. Specifically, in the first conductive layer in the cell region, it penetrates the source region and extends to the lower half of the body region, and is adjacent to the semiconductor layer below the body region, so that the first conductive layer forms a Schottky contact with the semiconductor layer. Further, the upper sidewall of the first conductive layer is adjacent to the source region, so as to form a Schottky diode with the anode shorted to the source region and the cathode shorted to the drain region, saving the extra area for forming the Schottky diode, thereby reducing the device area and cost while maintaining a low reverse recovery charge.

[0019] In the process of forming the first conductive layer in the cell region of the semiconductor device and its manufacturing method provided by the present invention, first, a first etching is performed in the corresponding region, and ion doping is performed at the bottom of the first groove after the first etching to form a contact region; then, a second etching is performed on the first groove to remove the doped region at the bottom of the first groove and form a second groove, and the bottom of the second groove exposes the semiconductor layer, so as to ensure that the first conductive layer formed in the second groove subsequently can form a good Schottky contact with the semiconductor layer, thereby reducing the reverse recovery charge. In addition, the manufacturing method of the present application can be compatible with the existing process and does not require purchasing expensive equipment, so the cost can be reduced. Description of the Drawings

[0020] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0021] Figure 1 A schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown;

[0022] Figure 2The flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0023] Figures 3a to 3l The cross-sectional schematic diagrams of the stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention are shown. Detailed implementation manners

[0024] In the following figures, the same elements are denoted by like reference numerals. For clarity, the various parts in the figures are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps may be described in one figure.

[0025] When describing the structure of a device, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or the other region, or there may be other layers or regions between it and the other layer or the other region. And if the device is flipped, this layer or this region will be "below" or "under" the other layer or the other region.

[0026] If for the purpose of describing the case of being directly above another layer or another region, the expressions "directly on... above" or "above and adjacent to..." will be used herein.

[0027] Unless otherwise specifically indicated hereinafter, the various parts of the semiconductor device may be made of materials well-known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors such as silicon carbide (SiC), etc., II-VI compound semiconductors such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV semiconductors such as silicon (Si), germanium (Ge), etc. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric may be made of SiO2 or a material having a dielectric constant greater than that of SiO2, such as including oxides, nitrides, oxynitrides, silicates, aluminates, titanates. And the gate dielectric can not only be formed of materials well-known to those skilled in the art, but also materials developed in the future for gate dielectrics can be used.

[0028] The following will further describe in detail the specific implementation manners of the present invention in conjunction with the drawings and embodiments.

[0029] Figure 1 A schematic structural diagram of a semiconductor device according to an embodiment of the present invention is shown. Among them, Figure 1 For example, a cross-sectional schematic diagram of a semiconductor device including two cell structures is shown.

[0030] Reference Figure 1 , the semiconductor device of the present application includes: a semiconductor layer 100, a plurality of trench gates 130, an interlayer dielectric layer 150, a plurality of first conductive layers 181, a second conductive layer 182, and a third conductive layer 183.

[0031] The semiconductor layer 100 has opposite first and second surfaces. The interlayer dielectric layer 150 and the second conductive layer 182 are located on the first surface of the semiconductor layer 100. The upper surface of the first conductive layer 181 is adjacent to the lower surface of the second conductive layer 182, and the lower surface extends into the semiconductor layer 100. The third conductive layer 183 is located on the second surface of the semiconductor layer 100. The semiconductor layer 100 includes a plurality of gate trenches 101, and the gate trenches 101 extend from the first surface of the semiconductor layer 100 into the semiconductor layer 100 towards the second surface.

[0032] Among them, the semiconductor layer is, for example, a SiC, GaN, Ga2O3, Al2O3 substrate or a stacked structure composed of a substrate and an epitaxial layer. However, the embodiments of the present application are not limited thereto, and those skilled in the art can make other settings on the material and number of layers of the semiconductor layer according to needs, such as other wide-bandgap semiconductor materials, etc.

[0033] In the present application, the semiconductor layer 100 includes, for example, a substrate 110, an epitaxial layer 120, a body region 141, a source region 142, and a body contact region 143.

[0034] Specifically, the epitaxial layer 120 is located above the substrate 110. The gate trench 101 extends from the first surface of the semiconductor layer 100 to the second surface into the epitaxial layer 120. A plurality of trench gates 130 are located in the corresponding gate trenches 101 in the semiconductor layer 100. The source regions 142 are located on both sides of the trench gate 130 and extend from the first surface of the semiconductor layer 100 to the second surface. The source regions 142 are adjacent to the sidewalls of the trench gate 130. The body region 141 includes a first body region 141a and a second body region 141b, and is located between two adjacent gate trenches 101. The first body region 141a is adjacent to the sidewall of one of the two adjacent gate trenches 101, and the second body region 141b is adjacent to the sidewall of the other one of the two adjacent gate trenches 101. There is a platform region 121 of the semiconductor layer 100 between the first body region 141a and the second body region 141b. The upper surface of the body region 141 is adjacent to the lower surface of the source region 142. The body contact region 143 is located below the source region 142. The upper surface of the body contact region 143 is adjacent to the lower surface of the source region 142, and the side surface is adjacent to the body region 141. The body region 141 separates the body contact region 143 from the trench gate 130. The sidewalls between at least a part of the body regions 141 located between two adjacent trench gates 130 in two adjacent cells are separated by the epitaxial layer 120.

[0035] Wherein, the depth of the lower surface of the body region 141 extending from the first surface of the semiconductor layer 100 to the second surface is less than the depth of the bottom of the trench gate 130 extending from the first surface of the semiconductor layer 100 to the second surface.

[0036] The trench gate 130 located in the gate trench 101 includes a gate dielectric layer 131 and an electrode conductor. Specifically, the electrode conductor includes a shielding gate 132 located below in the gate trench 101 and a control gate 133 located above in the gate trench 101. The gate dielectric layer 131 includes a first oxide layer 1311 located between the shielding gate 132 and the semiconductor layer 100, a second oxide layer 1312 located between the shielding gate 132 and the control gate 133, a third oxide layer 1313 located between the control gate 133 and the semiconductor layer 100, and a fourth oxide layer 1314 located above the control gate 133. Therefore, the first oxide layer 1311 and the second oxide layer 1312 surround the shielding gate 132 and separate the shielding gate 132 from the semiconductor layer 100. The second oxide layer 1312, the third oxide layer 1313, and the fourth oxide layer 1314 surround the control gate 133 and separate the control gate 133 from the semiconductor layer. In addition, the thickness of the first oxide layer 1311 is greater than the thickness of the third oxide layer 1313.

[0037] The interlayer dielectric layer 150 is located on the first surface of the semiconductor layer 100 and covers the upper surface of the trench gate 130 and the upper surface of the source region 142. The first conductive layer 181 serves as a source electrode lead layer, penetrates the interlayer dielectric layer 150 and extends into the semiconductor layer 100. At the same time, the portion of the first conductive layer 181 located in the semiconductor layer 100 has its sidewalls adjacent to the source region 142, the body contact region 143, and the body region 141 in sequence, and the lower surface of the first conductive layer 181 is adjacent to the epitaxial layer 120. The second conductive layer 182 covers the upper surface of the interlayer dielectric layer 150 on the upper layer of the semiconductor layer 100 and is adjacent to the first conductive layer 181 for electrical connection. In this embodiment, the bottom of the body region 141 is lower than the bottom of the first conductive layer 181. The first body region 141a and the second body region 141b in the body region 141 that are lower than the bottom of the first conductive layer 181 are separated by the epitaxial layer 120, and the lateral dimension of the first conductive layer 181 is greater than the spacing width between the first body region 141a and the second body region 141b.

[0038] The substrate 110 serves as a drain region, and the third conductive layer 183 serves as a drain electrode. The third conductive layer 183 covers the lower surface of the substrate 110.

[0039] In this embodiment, the source region 142, the epitaxial layer 120, and the substrate 110 are of the first conductive type, the body region 111 and the body contact region 143 are of the second conductive type, and the doping concentration of the body contact region 143 is greater than that of the body region 141. The first conductive type is opposite to the second conductive type. The first conductive type is one of P-type and N-type, and the second conductive type is the other of P-type and N-type.

[0040] In the present application, the first conductive layer 181 in the cell region penetrates the source region 142 and extends to the lower half of the body region 141, and is adjacent to the semiconductor layer 100 below the body region 141. Thus, the first conductive layer 181 forms a Schottky contact with the semiconductor layer 100. Further, the upper sidewall of the first conductive layer 181 is adjacent to the source region 142, thereby forming a Schottky diode with the anode shorted to the source region 142 and the cathode shorted to the drain region, saving the extra area for forming the Schottky diode, and thus reducing the device area and cost while maintaining a low reverse recovery charge.

[0041] Figure 2 The flowchart shows the manufacturing method of the semiconductor device according to the embodiment of the present invention; Figures 3a to 3l The cross-sectional schematic diagrams of the various stages of the manufacturing method of the semiconductor device according to the embodiment of the present invention are shown. The following will be combined with Figure 2 and Figures 3a to 3l to illustrate the manufacturing method of the semiconductor device provided by the embodiment of the present application.

[0042] The method starts with a semiconductor layer 100, which in this embodiment includes a substrate 110 and an epitaxial layer 120.

[0043] Step S210: Form a gate trench in the semiconductor layer, and sequentially deposit a first oxide layer and a first polysilicon layer in the gate trench.

[0044] In this step, a patterned first mask layer is formed on the first surface of the semiconductor layer 100, and then an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or gas-phase etching and other processes, is used to form a gate trench 101 in the semiconductor layer 100 via the first mask layer, as Figure 3a shown.

[0045] The gate trench 101 is a deep trench that extends from the upper surface of the epitaxial layer 120 to a portion close to the substrate 110.

[0046] Furthermore, a deposition process, such as physical vapor deposition, chemical vapor deposition and other processes, is used to sequentially deposit a first oxide layer 1311 and a first polysilicon layer 132 in the gate trench 101. The first oxide layer 1311 covers the sidewalls and bottom of the gate trench 101 to form a cavity, and the first polysilicon layer 132 is located in the cavity formed by the first oxide layer 1311. Thus, the first oxide layer 1311 acts as an insulating layer to separate the first polysilicon layer 132 and the semiconductor layer.

[0047] In the step of depositing the first oxide layer 1311 and the first polysilicon layer 132, the first oxide layer 1311 and the first polysilicon layer 132 are also deposited on the first surface of the semiconductor layer 100. Therefore, the first oxide layer 1311 and the first polysilicon layer 132 on the first surface of the semiconductor layer 100 can be removed by a chemical mechanical polishing process CMP, as Figure 3b shown.

[0048] Step S220: Perform a re-etch on the first oxide layer and the first polysilicon layer in the gate trench to form a second oxide layer on the first oxide layer and the first polysilicon layer.

[0049] In this step, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or gas-phase etching and other processes, is used to perform a re-etch on the first oxide layer 1311 and the first polysilicon layer 132 in the gate trench 101 to remove the first oxide layer 1311 and the first polysilicon layer 132 located in the upper part of the gate trench 101, so that the upper surfaces of the first oxide layer 1311 and the first polysilicon layer 132 terminate at the middle of the gate trench 101, thereby forming the first oxide layer 1311 and the shield gate 132, as Figure 3c shown.

[0050] Further, a deposition process, such as physical vapor deposition, chemical vapor deposition, or the like, is used to deposit a second oxide layer on the upper surfaces of the first oxide layer 1311 and the shielding gate 132 in the gate trench 101. The second oxide layer serves as the second oxide layer 1312, so that the first oxide layer 1311 and the second oxide layer 1312 surround the shielding gate 132, as Figure 3c shown.

[0051] Step S230: Form a third oxide layer, a second polysilicon layer, and a fourth oxide layer in the gate trench on the second oxide layer.

[0052] In this step, a deposition process, such as physical vapor deposition, chemical vapor deposition, or the like, is used to sequentially deposit a third oxide layer 1313 and a second polysilicon layer 133 above the second oxide layer 1312 in the gate trench 101 and in the upper half of the gate trench 101, as Figure 3d shown.

[0053] Among them, the third oxide layer 1313 is located on the first surface of the semiconductor layer 100, on the surface of the second oxide layer 1312 in the gate trench 101, and on the sidewalls of the upper half of the gate trench 101. The second polysilicon layer 133 is located in the gate trench 101 and on the third oxide layer 1313 on the first surface of the semiconductor layer 100. The third oxide layer 1313 separates the second polysilicon layer 133 from the semiconductor layer 100, and the thickness of the third oxide layer 1313 on the sidewalls in the gate trench 101 is less than the thickness of the first oxide layer 1311 on the sidewalls in the gate trench 101.

[0054] Further, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or gas-phase etching, is used to perform a back-etching on the second polysilicon layer 133 to remove the second polysilicon layer 133 on the third oxide layer 1313 on the first surface of the semiconductor layer 100, and to perform a back-etching on the second polysilicon layer 133 in the gate trench 101 so that the upper surface of the second polysilicon layer 133 in the gate trench 101 is lower than the first surface of the semiconductor layer 100, thereby forming a control gate 133, as Figure 3d shown.

[0055] Further, a deposition process, such as physical vapor deposition, chemical vapor deposition, or the like, is used to deposit and form a fourth oxide layer 1314 on the surface of the second polysilicon layer 133 and on the third oxide layer 1313 on the first surface of the semiconductor layer 100, as Figure 3e shown.

[0056] In this embodiment, for the purpose of more conveniently describing the oxide layers formed in different steps, the third oxide layer 1313 and the fourth oxide layer 1314 located on the first surface of the semiconductor layer 100 are collectively referred to as the interlayer dielectric layer 150, and the first oxide layer 1311, the second oxide layer 1312, the third oxide layer 1313, and the fourth oxide layer 1314 located in the gate trench 101 are collectively referred to as the gate dielectric layer 131. The gate dielectric layer 131 surrounds and shields the gate 132 and the control gate 133, separates the shield gate 132 and the control gate 133, separates the shield gate 132 from the semiconductor layer 100, and separates the control gate 133 from the semiconductor layer 100, as Figure 3f shown.

[0057] Step S240: Form a body region and a source region in the semiconductor layer on both sides of the gate trench.

[0058] In this step, a patterned second mask layer 104 is formed on the surface of the interlayer dielectric layer 150, and impurity ions of a second conductivity type are implanted into the semiconductor layer 100 on both sides of the gate trench 101 through the second mask layer 104 to form a body region 141, and a diffusion process is used to diffuse the implanted impurity ions of the second conductivity type, as Figure 3g shown. In the semiconductor layer 100 between adjacent gate trenches 101, the body region 141 includes a first body region 141a and a second body region 141b.

[0059] Wherein, there is a certain distance between the body regions 141 between adjacent two cells, that is, the first body region 141a and the second body region 141b between adjacent two gate trenches 101 are separated by the epitaxial layer 120. One side wall of the first body region 141a is adjacent to the side wall of one of the adjacent gate trenches 101, and one side wall of the second body region 141b is adjacent to the side wall of the other adjacent gate trench 101. The body region 141 extends from the first surface of the semiconductor layer 100 to the second surface. Specifically, the bottom surface of the body region 141 extends from the first surface of the semiconductor layer 100 to the second surface to a depth approximately equal to the depth to which the bottom surface of the control gate 133 extends from the first surface of the semiconductor layer 100 to the second surface. In this embodiment, the impurity ions of the second conductivity type are, for example, P-type impurity ions.

[0060] Furthermore, the mask layer 104 is removed, and impurity ions of a first conductivity type are implanted into the semiconductor layer 100 by an ion implantation process to form a source region 142, as Figure 3h shown.

[0061] In this embodiment, the impurity ions of the first conductivity type are, for example, N-type impurity ions. The sidewall of the source region 142 is adjacent to the sidewall of the gate trench 101. The depth of the bottom surface of the source region 142 extending from the first surface of the semiconductor layer 100 to the second surface is less than the depth of the bottom surface of the body region 141 extending from the first surface of the semiconductor layer 100 to the second surface, so that the upper surface of the body region 141 is adjacent to the bottom surface of the source region 142.

[0062] During the process of forming the body region 141 and the source region 142 in the semiconductor layer 100 by using an ion implantation process, the interlayer dielectric layer 150 protects the first surface of the semiconductor layer 100 from being damaged.

[0063] Step S250: Form a first groove in the semiconductor layer between two adjacent body regions.

[0064] In this step, a patterned third mask layer is formed on the surface of the interlayer dielectric layer 150. An etching process is used, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or gas-phase etching, etc. A first groove 102 is formed in the semiconductor layer 100 via the third mask layer, as Figure 3i shown.

[0065] Among them, the first groove 102 penetrates through the interlayer dielectric layer 150 and the source region 142 and extends into the body region 141 below the source region 142. In addition, the first groove 102 is located between the body regions 141 between two adjacent gate trenches 101. The sidewall of the first groove 102 extending into the body region 141 below the source region 142 is adjacent to both adjacent body regions 141, and at least the bottom of the first groove 102 is adjacent to the epitaxial layer 120.

[0066] Step S260: Perform ion doping on the bottom of the first groove to form a contact region.

[0067] In this step, the semiconductor layer 100 at the bottom of the first groove 102 is implanted with impurity ions of the second conductivity type via the first groove 102 to form a contact region 143 in the semiconductor layer 100 at the bottom of the first groove 102, as Figure 3i shown.

[0068] Among them, the doping concentration of the contact region 143 is greater than the doping concentration of the body region 141.

[0069] Step S270: Etch the first groove to form a second groove.

[0070] In this step, an etching process is adopted, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching processes, etc. The first groove 102 is etched again through the third mask layer to form a second groove 103, as Figure 3j shown.

[0071] Wherein, during the process of etching the first groove 102 to form the second groove 103, the contact region 143 at the bottom of the first groove 102 is etched away, so that at least part of the bottom of the formed second groove 103 is adjacent to the epitaxial layer 120. The side wall of the second groove 103 is sequentially adjacent to the interlayer dielectric layer 150, the source region 142, and the contact region 143. The depth of the bottom surface of the second groove 103 extending from the first surface of the semiconductor layer 100 to the second surface is less than the depth of the bottom surface of the body region 141 extending from the first surface of the semiconductor layer 100 to the second surface, that is, the bottom of the second groove 103 is higher than the bottom of the body region 141.

[0072] In other embodiments, the depth of the bottom surface of the second groove 103 extending from the first surface of the semiconductor layer 100 to the second surface may also be greater than or equal to the depth of the bottom surface of the body region 141 extending from the first surface of the semiconductor layer 100 to the second surface, that is, the bottom of the second groove 103 is lower than the bottom of the body region 141.

[0073] Furthermore, it also includes: removing the third mask layer.

[0074] Step S280: Deposit a first conductive layer in the second groove.

[0075] In this step, a deposition process is adopted, such as physical vapor deposition, chemical vapor deposition and other processes, to deposit a conductive material in the second groove 103 to form a first conductive layer 181, as Figure 3k shown.

[0076] Wherein, after the first conductive layer 181 fills the second groove 103, it is sequentially adjacent to the interlayer dielectric layer 150, the source region 142, and the contact region 143, and at least part of the bottom of the first conductive layer 181 is adjacent to the epitaxial layer 120, so that a Schottky contact is formed between the first conductive layer 181 and the epitaxial layer 120.

[0077] The material of the first conductive layer 181 is Ti or TiN.

[0078] Step S290: Form a second conductive layer on the upper surface of the interlayer dielectric layer and form a third conductive layer on the second surface of the semiconductor layer.

[0079] In this step, a deposition process, such as physical vapor deposition, chemical vapor deposition or other processes, is adopted to form a second conductive layer 182 on the upper surface of the interlayer dielectric layer 150 and form a third conductive layer 183 on the second surface of the semiconductor layer 100, as Figure 3l shown.

[0080] In addition, before forming the third conductive layer 183, for example, it further includes thinning the substrate 110 through the second surface of the semiconductor layer 100.

[0081] The second conductive layer 182 is adjacent to the first conductive layer 181 to achieve electrical connection, so that the first conductive layer 181 and the second conductive layer 182 serve as the source electrode of the semiconductor device; the third conductive layer 183 serves as the drain electrode of the semiconductor device.

[0082] In the semiconductor device and its manufacturing method provided by the present invention, during the process of forming the first conductive layer in the cell region, first, a first etching is performed in the corresponding region, and ion doping is performed at the bottom of the first groove after the first etching to form a contact region; then, a second etching is performed on the first groove to remove the doped region at the bottom of the first groove and form a second groove, and the bottom of the second groove exposes the semiconductor layer, so as to ensure that the first conductive layer formed in the second groove subsequently can form a good Schottky contact with the semiconductor layer, thereby reducing the reverse recovery charge.

[0083] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, according to the above description, many modifications and variations can be made. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and its modified use based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: Forming a plurality of gate trenches in a semiconductor layer, the semiconductor layer comprising a first surface and a second surface opposite to each other, the gate trenches extending from the first surface to the second surface of the semiconductor layer; forming a body region and a source region in the semiconductor layer between adjacent gate trenches, wherein the body region between adjacent gate trenches comprises a first body region and a second body region, wherein the first body region and the second body region are respectively adjacent to sidewalls of adjacent gate trenches, and a platform region of the semiconductor layer is spaced between the first body region and the second body region; forming a first groove in the semiconductor layer, the first groove being located between the first body region and the second body region between adjacent gate trenches, the bottom of the first groove being lower than the bottom of the source region and higher than the bottom of the body region; forming a body contact region in the semiconductor layer at the bottom of the first groove and in the body region of the two side walls of the first groove close to the bottom region; Etching the first groove to remove the body contact region at the bottom of the first groove to form a second groove, wherein the bottom of the second groove is lower than the bottom of the body contact region; as well as depositing a conductive material in the second groove to form a first conductive layer; Wherein, the width of the second groove is greater than the interval width between the first body region and the second body region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first conductive layer includes Ti and TiN.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The bottom of the second groove is higher than the bottoms of the first body region and the second body region.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a body region and a source region in the semiconductor layer between adjacent gate trenches comprises: forming a patterned second mask layer on the semiconductor layer; Performing ion implantation and diffusion in the semiconductor layer through the second mask layer to form a body region; removing the second mask layer; Performing ion implantation in the semiconductor layer to form a source region; The upper surface of the body region is adjacent to the lower surface of the source region, and at least one side wall of the body region and the source region is adjacent to the gate trench.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: Between the steps of forming a plurality of gate trenches in the semiconductor layer and forming a body region and a source region in the semiconductor layer between adjacent gate trenches, the method further includes: A trench gate is formed in the gate trench and an interlayer dielectric layer is formed on the first surface of the semiconductor layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The steps of forming a trench gate in the gate trench and forming an interlayer dielectric layer on the first surface of the semiconductor layer include: forming a first oxide layer and a first polysilicon layer in the gate trench, wherein the first oxide layer covers the sidewall of the gate trench and the first surface of the semiconductor layer, and the first oxide layer separates the first polysilicon layer and the semiconductor layer; Etching back the first oxide layer and the first polysilicon layer to remove the first oxide layer and the first polysilicon layer on the first surface of the semiconductor layer and in the upper portion of the gate trench; forming a second oxide layer on the first oxide layer and the first polysilicon layer in the gate trench; forming a third oxide layer and a second polysilicon layer in the gate trench above the second oxide layer, wherein the third oxide layer covers the sidewall of the upper portion of the gate trench and separates the second polysilicon layer from the semiconductor layer; Etching back the second polysilicon layer so that an upper surface of the second polysilicon layer in the gate trench is lower than the first surface of the semiconductor layer; forming a fourth oxide layer on the first surface of the semiconductor layer and in the gate trench, The third oxide layer covers the first surface of the semiconductor layer, and the third oxide layer and the fourth oxide layer located on the first surface of the semiconductor layer serve as interlayer dielectric layers.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The thickness of the first oxide layer is greater than the thickness of the third oxide layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: After the step of depositing a conductive material in the second groove to form a first conductive layer, the method further comprises: forming a second conductive layer on the interlayer dielectric layer, wherein the second conductive layer is adjacent to the first conductive layer; A third conductive layer is formed on the second surface of the semiconductor layer.

9. A semiconductor device comprising: A semiconductor layer, wherein the semiconductor layer includes a plurality of gate trenches, and the gate trenches extend from a first surface to a second surface of the semiconductor layer; A body region, a source region and a contact region are located in the semiconductor layer between adjacent gate trenches, wherein the body region between adjacent gate trenches includes a first body region and a second body region, wherein the first body region and the second body region are respectively adjacent to sidewalls of adjacent gate trenches, and a platform region of the semiconductor layer is spaced between the first body region and the second body region; A first conductive layer is located in the semiconductor layer between adjacent gate trenches. The first conductive layer penetrates the source region and the contact region and extends to below the source region, at least a portion of the bottom surface of the first conductive layer is adjacent to the semiconductor layer separating the first body region and the second body region, and a lateral dimension of the first conductive layer is greater than a spacing width between the first body region and the second body region.

10. The semiconductor device according to claim 9, wherein The material of the first conductive layer includes Ti and TiN.

11. The semiconductor device according to claim 9, wherein: The bottom of the first conductive layer is higher than the bottoms of the first body region and the second body region.

12. The semiconductor device according to claim 9, wherein Also includes: A trench gate is located in the gate trench, and the trench gate includes a gate dielectric layer, a shielding gate and a control gate. The shielding gate is located at the lower part of the gate trench, and the control gate is located at the upper part of the gate trench. The gate dielectric layer surrounds the shielding gate and the control gate respectively, and separates the shielding gate and the control gate, the shielding gate and the semiconductor layer, and the control gate and the semiconductor layer.

13. The semiconductor device according to claim 12, wherein: Also includes: An interlayer dielectric layer, located on the first surface of the semiconductor layer; A second conductive layer, located on the interlayer dielectric layer, the second conductive layer being adjacent to the first conductive layer; The third conductive layer is located on the second surface of the semiconductor layer.

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