A semiconductor structure and a method of fabricating the same

Abstract

The application discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a channel structure on the substrate, the channel structure comprising a channel layer and a barrier layer formed on the substrate in sequence, the channel structure comprising a gate region, and a source region and a drain region on both sides of the gate region, a first recess in the source region and the drain region, the first recess penetrating through at least the barrier layer, an insertion layer arranged in the barrier layer, a side wall of the insertion layer at the end of the source region and the drain region, the side wall being recessed by a preset distance relative to the side wall of the barrier layer to form a recessed groove, the recessed groove being communicated with the first recess, and a heavily doped material layer, the heavily doped material layer filling the first recess and the recessed groove. The technical scheme provided by the application reduces the contact resistance between the heavily doped material layer and the side wall of the channel structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In the fabrication process of GaN-based HEMT devices, the source-drain ohmic contact process is one of the key technologies, directly affecting the frequency and power performance of the device. Secondary epitaxial growth of heavily doped N-type GaN in the ohmic contact region to reduce ohmic contact resistivity and improve surface morphology has become a novel international process in recent years.

[0003] Currently, most secondary epitaxial growth of heavily doped N-type GaN is achieved using molecular beam epitaxy (MBE), but some researchers use metal-organic chemical vapor deposition (MOCVD). The ohmic contact resistance achieved by this method mainly includes the contact resistance between the metal and the heavily doped N-type GaN, the bulk resistance of the heavily doped N-type GaN, and the contact resistance between the heavily doped N-type GaN and the channel sidewalls. Among these, the quality of the contact between the heavily doped N-type GaN and the channel sidewalls directly affects the contact resistance between the N-type heavily doped GaN and the channel sidewalls, and this contact resistance has the greatest impact on the overall ohmic contact. Figure 1 This is a cross-sectional view of the structure of heavily doped GaN material after secondary epitaxial growth in the prior art. Figure 1 As shown, a buffer layer 2, a GaN channel layer 3, and a barrier layer 4 are stacked on substrate 1; the GaN channel layer 3 and the barrier layer 4 constitute the channel structure. Using a patterned SiO2 layer 5 as a mask, the exposed barrier layer 4 and GaN channel layer 3 are sequentially etched to a depth below the GaN heterojunction interface. In actual operation, due to etching precision issues, over-etching of the channel structure is prone to occur, resulting in the side portion of the channel structure being recessed relative to the SiO2 mask layer 5 above it. During the secondary epitaxial growth of heavily doped GaN material 6, due to over-etching, poor contact occurs between the side of the heavily doped GaN material 6 and the channel structure, causing a significant increase in the contact resistance between the N-type heavily doped GaN material 6 and the sidewall of the channel structure. Therefore, effectively reducing the contact resistance between the N-type heavily doped GaN material 6 and the sidewall of the channel structure is crucial for reducing overall ohmic contact. Summary of the Invention

[0004] This invention provides a semiconductor structure and its fabrication method to reduce the contact resistance between the heavily doped material layer and the sidewall of the channel structure.

[0005] According to one aspect of the present invention, a semiconductor structure is provided, comprising:

[0006] Substrate;

[0007] A channel structure located on the substrate, the channel structure including a channel layer and a barrier layer sequentially formed on the substrate, the channel structure including a gate region, and a source region and a drain region located on both sides of the gate region;

[0008] A first groove located in the source region and the drain region, the first groove at least penetrating the barrier layer;

[0009] An insertion layer is disposed within the barrier layer; the sidewall of the insertion layer located at the source region and the drain region ends is recessed inward by a predetermined distance relative to the sidewall of the barrier layer to form an indented trench, the indented trench communicating with the first groove;

[0010] A heavily doped material layer that fills the first groove and the recessed trench.

[0011] Optionally, the semiconductor structure further includes:

[0012] A gate located within the gate region, the gate being located on the side of the barrier layer away from the substrate;

[0013] The source and drain are respectively located in the source region and the drain region, and the source and drain are formed on the side of the heavily doped material layer away from the substrate.

[0014] Optionally, the heavily doped material layer is a single-layer material layer or a stacked material layer, wherein the stacked material layer includes a superlattice structure.

[0015] Optionally, the barrier layer and the insertion layer are made of group III nitride materials, the barrier layer is made of AlGaN, and the insertion layer is made of AlN or GaN.

[0016] Optionally, the sidewall of the heavily doped material layer near the insertion layer includes at least one protrusion; the recessed trench includes at least one finger-shaped trench, and the at least one finger-shaped trench is spaced apart along the direction of the trench width; the protrusion is embedded in the finger-shaped trench one-to-one.

[0017] Optionally, the sidewall of the heavily doped material layer near the insertion layer has a serrated or comb-like vertical projection on the substrate.

[0018] Optionally, the distance between the at least one finger-shaped groove and the side of the recessed groove near the first groove is ≥0.

[0019] Optionally, a plurality of insertion layers are disposed within the barrier layer; the plurality of insertion layers are disposed sequentially at intervals in a direction perpendicular to the substrate.

[0020] Optionally, the semiconductor structure includes a plurality of the channel structures, which are sequentially stacked on one side of the substrate, and each of the plurality of insertion layers corresponding to the plurality of channel structures includes the recessed trench.

[0021] Optionally, the first groove extends at least through the barrier layer of the channel structure on the side adjacent to the substrate.

[0022] Optionally, the lengths of the plurality of channel structures gradually decrease along the direction from the substrate to the channel layer.

[0023] Optionally, along the direction from the substrate to the channel layer, the lengths of the plurality of inserted layers remain constant, gradually decrease, or gradually increase.

[0024] According to another aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising:

[0025] Provide substrate;

[0026] A channel structure is formed on one side of the substrate. Forming the channel structure includes sequentially forming a channel layer and a barrier layer on the substrate. The channel structure includes a gate region and source and drain regions located on either side of the gate region. Forming the barrier layer includes...

[0027] The channel structure is etched to form a first groove, the first groove penetrating at least the barrier layer;

[0028] The sidewalls of the insertion layer are etched laterally to reduce the sidewalls of the insertion layer at the source region and the drain region by a predetermined distance relative to the sidewalls of the barrier layer to form an indented trench, which communicates with the first groove.

[0029] A heavily doped material layer is formed within the first groove; the heavily doped material layer fills the first groove and the recessed trench.

[0030] Optionally, after forming a heavily doped material layer in the first groove, the method further includes:

[0031] A gate is formed on the barrier layer;

[0032] A source and a drain are formed on the heavily doped material layer; the source and the drain are located on opposite sides of the gate.

[0033] Optionally, forming a barrier layer on the surface of the channel layer away from the substrate, and forming an insertion layer within the barrier layer includes:

[0034] A first barrier sublayer is formed on the surface of the channel layer on the side away from the substrate;

[0035] An insertion layer is formed on the surface of the first barrier sublayer on the side away from the substrate;

[0036] A second barrier sublayer is formed on the surface of the insertion layer away from the substrate; the barrier layer includes the first barrier sublayer and the second barrier sublayer.

[0037] Optionally, the lateral etching of the sidewalls of the insertion layer to form the recessed trench includes:

[0038] The sidewalls of the insertion layer are selectively etched laterally along the direction of the channel width to form at least one finger-shaped trench, and the at least one finger-shaped trench is spaced apart along the direction of the channel width;

[0039] The process of forming a heavily doped material layer within the first groove also includes:

[0040] The heavily doped material layer is grown laterally so that it fills the at least one first sub-trench to form a protrusion.

[0041] Optionally, forming a heavily doped material layer within the first groove includes:

[0042] A heavily doped material layer or a stacked material layer is formed within the first groove.

[0043] Optionally, an insertion layer is formed within the barrier layer, comprising:

[0044] A plurality of insertion layers are formed within the barrier layer; the plurality of insertion layers are arranged sequentially at intervals in a direction perpendicular to the substrate.

[0045] Optionally, forming a trench structure on one side of the substrate includes:

[0046] A plurality of channel structures are formed on one side of the substrate; the plurality of channel structures are stacked sequentially on one side of the substrate.

[0047] Optionally, etching the channel structure to form a first groove includes:

[0048] The plurality of said channel structures are etched such that the length of the plurality of said channel structures gradually decreases along the direction from the substrate toward the channel layer.

[0049] The technical solution provided by this invention involves setting an insertion layer within a barrier layer, and after etching a channel structure to form a first groove that at least penetrates the barrier layer, laterally etching the sidewalls of the insertion layer. This causes the sidewalls of the insertion layer located at the source and drain regions to be recessed by a predetermined distance relative to the sidewalls of the barrier layer to form an indented trench. The indented trench is connected to the first groove. When a heavily doped material layer is formed within the first groove, the heavily doped material layer can fill both the first groove and the indented trench, thereby increasing the contact area between the heavily doped material layer and the channel structure and reducing the contact resistance between the heavily doped material layer and the heterojunction sidewall.

[0050] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a cross-sectional view of the structure of heavily doped GaN material after secondary epitaxial growth in the prior art;

[0053] Figure 2 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present invention;

[0054] Figure 3 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0055] Figure 4 This is a top view of an insertion layer, a barrier layer, and a channel layer provided in an embodiment of the present invention;

[0056] Figure 5 yes Figure 2 A schematic diagram of the cross-sectional structure along section line AA1 in the structure shown.

[0057] Figure 6 This is a top view of an insertion layer, a barrier layer, and a channel layer provided in an embodiment of the present invention;

[0058] Figure 7 yes Figure 2 A schematic diagram of another cross-sectional structure along section line AA1 in the structure shown.

[0059] Figure 8This is a top view of another insertion layer, barrier layer, and channel layer provided in an embodiment of the present invention;

[0060] Figure 9 yes Figure 2 A schematic diagram of another cross-sectional structure along section line AA1 in the structure shown.

[0061] Figure 10 This is a top view of another insertion layer, barrier layer, and channel layer provided in an embodiment of the present invention;

[0062] Figure 11 This is a top view of another insertion layer, barrier layer, and channel layer provided in an embodiment of the present invention;

[0063] Figure 12a This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0064] Figure 12b This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0065] Figure 12c This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0066] Figure 13 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0067] Figure 14 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention;

[0068] Figures 15-18 This is a cross-sectional structural diagram of steps S110 to S150 in a semiconductor structure fabrication method provided in an embodiment of the present invention;

[0069] Figures 19-22 This is a cross-sectional structural diagram of steps S210 to S250 in a semiconductor structure fabrication method provided in an embodiment of the present invention;

[0070] Figures 23-24 The preparation method provided in the embodiments of the present invention Figure 14 A cross-sectional schematic diagram of some steps in the fabrication method of the semiconductor structure shown. Detailed Implementation

[0071] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0072] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0073] This invention provides a semiconductor structure. Figure 2 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present invention, with reference to... Figure 2 ,include:

[0074] Substrate 10;

[0075] The channel structure 302 located on the substrate 10 includes a channel layer 20 and a barrier layer 30 sequentially formed on the substrate 10. The channel structure 302 includes a gate region Q1 and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1.

[0076] A first groove 70 is located within the source region Q2 and the drain region Q3, and the first groove 70 at least penetrates the barrier layer 30;

[0077] An insertion layer 40 is disposed within a barrier layer 30; the sidewalls of the insertion layer 40 located at the source region Q2 and the drain region Q3 are recessed by a predetermined distance relative to the sidewalls of the barrier layer 30 to form a recessed trench 60, which communicates with the first groove 70.

[0078] A heavily doped material layer 50 is formed, which fills the first groove 70 and the recessed trench 60.

[0079] Specifically, substrate 10 may be a semiconductor substrate 10. The material of substrate 10 may include, but is not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (such as silicon-on-insulator (SOI)), or other suitable substrate 10 materials. In some embodiments, substrate 10 may include, for example, but not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the material of substrate 10 may include materials having… <111> An oriented silicon substrate 10. In some embodiments, the substrate 10 may include a buffer layer that may contact the channel structure 302. The buffer layer is used to reduce lattice and thermal mismatch between the substrate 10 and the channel structure 302, thereby addressing defects attributed to mismatch / difference. The buffer layer may contain a III-V compound. The III-V compound may contain, but is not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, exemplary materials of the buffer layer may further contain, for example, but not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

[0080] The channel structure 302 includes a channel layer 20 and a barrier layer 30 sequentially formed on the substrate 10. The material of the channel layer 20 may include, but is not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, InxAlyGa(1-xy)N (where x+y≤1), AlyGa(1-y)N (where y≤1). The material of the barrier layer 30 may include, but is not limited to, III-V nitride semiconductor materials, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or combinations thereof. The band gap (i.e., bandgap width) of the material of the channel layer 20 differs from that of the material of the barrier layer 30, resulting in different electron affinities and the formation of a heterojunction between them. A triangular well potential is generated at the junction interface between the channel layer 20 and the barrier layer 30, causing electrons to accumulate in the triangular well, thereby creating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

[0081] Etching is performed within the source region Q2 and drain region Q3 of the channel structure 302 to form a first groove 70 within the source region Q2 and drain region Q3. The first groove 70 penetrates at least the barrier layer 30, such that the bottom height of the first groove 70 is less than or equal to the interface height of the heterojunction, i.e., the first groove 70 can partially penetrate the trench layer 20 or completely penetrate the channel layer 20; the bottom height of the first groove 70 can be the height of the bottom surface (etching mesa 01) of the first groove 70 relative to the substrate 10, and the interface height of the heterojunction can be the height of the interface of the heterojunction relative to the substrate 10. This ensures that the heavily doped material layer 50 located in the first groove 70 can contact the heterojunction. The heavily doped material layer 50 includes, but is not limited to, an N-type heavily doped nitride semiconductor material layer. The N-type doping concentration of the heavily doped material layer 50 is greater than 1E18 / cm³. 3 This ensures that the heavily doped material layer 50 has a low resistance and improves the conductivity of the heavily doped material layer 50.

[0082] To reduce the contact resistance between the heavily doped material layer 50 and the channel structure 302, an insertion layer 40 is provided within the barrier layer 30 in this embodiment of the invention. The barrier layer 30 may include a first barrier sub-layer 31 and a second barrier sub-layer 32, with the insertion layer 40 located between the first barrier sub-layer 31 and the second barrier sub-layer 32. The material of the insertion layer 40 is different from that of the barrier layer 30. There is an etching selectivity between the barrier layer 30 and the insertion layer 40. Therefore, by laterally etching the insertion layer 40, the sidewalls of the insertion layer 40 are recessed inward by a predetermined distance relative to the sidewalls of the barrier layer 30, forming an indented trench 60. The recessed trench 60 is connected to the first groove 70. When a heavily doped N-type nitride semiconductor material is epitaxially prepared in the first groove 70 to form a heavily doped material layer 50, the nitride semiconductor material can be prepared in the recessed trench 60 by lateral epitaxy. This increases the contact area between the heavily doped material layer 50 and the channel structure 302, and the laterally epitaxial heavily doped material layer 50 has better crystal quality, effectively reducing the contact resistance between the heavily doped material layer 50 and the heterojunction sidewall. The material of the insertion layer 40 is a group III nitride material. The materials of the barrier layer 30 and the insertion layer 40 are group III nitride materials. The material of the barrier layer 30 is AlGaN, and the material of the insertion layer 40 is AlN or GaN. Optionally, if the material of the barrier layer 30 is, for example, AlGaN, the material of the insertion layer 40 can be GaN or AlN. The barrier layer 30 and the insertion layer 40 form a sandwich barrier layer structure. The insertion layer 40 uses a material composed of some of the chemical elements found in the barrier layer 30. This satisfies the requirements for selective etching while also ensuring that the lattice constant of the insertion layer 40 material is similar to that of the barrier layer 30 material, thereby improving the growth quality of the semiconductor structure. Optionally, the projection of the recessed groove 60 onto the substrate 10 is located within the source region Q2 and the drain region Q3. The sidewalls of the insertion layer 40 are recessed inward relative to the sidewalls of the barrier layer 30 by a predetermined distance to form the recessed groove 60. This predetermined distance is less than one-third of the length of the channel structure 302.

[0083] The semiconductor structure provided in this embodiment of the invention includes: a substrate; a channel structure 302 located on the substrate 10, the channel structure 302 including a channel layer 20 and a barrier layer 30 sequentially formed on the substrate 10, the channel structure 302 including a gate region Q1, and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1; a first groove 70 located in the source region Q2 and the drain region Q3, the first groove 70 at least penetrating the barrier layer 30; an insertion layer 40 disposed in the barrier layer 30; the sidewalls of the insertion layer 40 located at the ends of the source region Q2 and the drain region Q3 are recessed inward by a predetermined distance relative to the sidewalls of the barrier layer 30 to form a recessed trench 60, the recessed trench 60 communicating with the first groove 70; and a heavily doped material layer 50 filling the first groove 70 and the recessed trench 60. This can increase the contact area between the heavily doped material layer 50 and the channel structure 302, and reduce the contact resistance between the heavily doped material layer 50 and the heterojunction sidewalls.

[0084] Based on the above embodiments, in one embodiment of the present invention, please continue to refer to... Figure 2 The semiconductor structure also includes: a gate G located in the gate region Q1, the gate G being located on the side of the barrier layer 30 away from the substrate 10; a source S and a drain D located in the source region Q2 and the drain region Q3, respectively, the source S and the drain D being formed on the side of the heavily doped material layer 50 away from the substrate 10.

[0085] Specifically, the gate G can be a metal or metal compound, including but not limited to tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds, nitrides, oxides, silicides, doped semiconductors, metal alloys, or combinations thereof. A layer of p-doped III-V group nitride semiconductor material, such as p-type GaN, can be present between the gate G and the barrier layer 30. The p-doped material can be obtained by using p-type impurities such as Be, Zn, Cd, and Mg. The source S and drain D can be, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The source S and drain D can be a single layer or multiple layers having the same or different compositions. In some embodiments, the source S and drain D form an ohmic contact with the heavily doped material layer 50. Ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the source (S) and drain (D).

[0086] Based on the above embodiments, in one embodiment of the present invention, please continue to refer to... Figure 2The heavily doped material layer 50 is a single-layer material layer. The heavily doped material layer 50 is an N-type heavily doped nitride semiconductor material layer, and the N-type doping concentration of the heavily doped material layer 50 is greater than 1E18 / cm³. 3 .

[0087] Based on the above embodiments, in one embodiment of the present invention, Figure 3 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present invention, for reference. Figure 3 The heavily doped material layer 50 is a stacked material layer. The stacked material layer includes a superlattice structure. Adjacent material layers (e.g., film layer 51 and film layer 52) are made of different N-type heavily doped nitride semiconductor materials, with an N-type doping concentration greater than 1E18 / cm³. 3 For example, the heavily doped material layer 50 is a superlattice structure in which InGaN layers and GaN layers are stacked alternately. Alternatively, the heavily doped material layer 50 is a superlattice structure in which AlGaN layers and GaN layers are stacked alternately. The superlattice structure has high crystal quality, thereby further improving the growth quality of the semiconductor structure.

[0088] Based on the above embodiments, in one embodiment of the present invention, Figure 4 This is a top view of an insertion layer, a barrier layer, and a channel layer provided in an embodiment of the present invention. Figure 5 yes Figure 2 The schematic diagram of the cross-sectional structure along section line AA1 shown is for reference. Figure 4 , Figure 5 and Figure 2 The recessed trench 60 is a trench that extends through the channel width direction X. This can be understood as forming the recessed trench 60 by etching the entire sidewall of the insertion layer 40 along the channel width direction X. The sidewall of the heavily doped material layer 50 near the insertion layer 40 is planar, making the bottom surface of the recessed trench 60 a flat surface. The vertical projection of the sidewall of the heavily doped material layer 50 near the insertion layer 40 onto the substrate 10 is a straight line.

[0089] Based on the above embodiments, in one embodiment of the present invention, Figure 6 This is a top view of another insertion layer, barrier layer, and channel layer provided in an embodiment of the present invention. Figure 7 yes Figure 2 Another cross-sectional view of the structure shown along section line AA1 is illustrated in the diagram. (Refer to...) Figure 6 and Figure 7 and combined Figure 2The recessed trench 60 includes at least one finger-shaped trench 601, which is arranged at intervals along the channel width direction X. The sidewall of the heavily doped material layer 50 near the insertion layer 40 includes at least one protrusion 501. The protrusions 501 are embedded in the finger-shaped trenches 601 one by one. It can be understood that when etching the sidewall of the insertion layer 40, the sidewall at a certain location is selectively etched to form the first sub-trench 601. Setting the recessed trench 60 as multiple finger-shaped trenches 601 can further increase the contact area between the heavily doped material layer 50 and the channel structure 302 and reduce the contact resistance between the heavily doped material layer 50 and the heterojunction sidewall. The recessed trench 60 may include multiple rectangular finger-shaped trenches 601, and the vertical projection of the sidewall of the heavily doped material layer 50 near the insertion layer 40 on the substrate 10 is comb-shaped. In this embodiment, the distance between the finger-shaped trenches 601 and the sidewall of the recessed trench 60 near the first groove 70 is equal to 0.

[0090] Based on the above embodiments, Figure 8 This is a top view of another insertion layer, barrier layer, and channel layer provided in an embodiment of the present invention. Figure 9 yes Figure 2 Another cross-sectional view of the structure shown along section line AA1 is illustrated in the diagram. (Refer to...) Figure 8 and Figure 9 The recessed groove 60 provided in this embodiment of the invention and Figure 6 and Figure 7 The difference of the recessed trench 60 shown is that the recessed trench 60 provided in the embodiment of the present invention includes a plurality of triangular finger trenches 601, and the vertical projection of the sidewall of the heavily doped material layer 50 near the insertion layer 40 on the substrate 10 is sawtooth-shaped.

[0091] Based on the above embodiments, in one embodiment of the present invention, Figure 10 This is a top view of another insertion layer, barrier layer, and channel layer provided in an embodiment of the present invention. Figure 11 This is a top view of another insertion layer, barrier layer, and channel layer provided in an embodiment of the present invention, with reference to... Figure 10 and Figure 11 The distance between the finger-shaped groove 601 and the side of the recessed groove 60 near the first groove 70 is greater than 0; at least one finger-shaped groove 401 is arranged at intervals along the channel width direction X; the sidewall of the heavily doped material layer 50 near the insertion layer 40 includes at least one protrusion 501, and the protrusion 501 is embedded in the finger-shaped groove 401 one by one.

[0092] This can be understood as follows: after etching the entire sidewall of the insertion layer 40 to form the recessed trench 60, the bottom of the recessed trench 60 is selectively etched in the channel width direction X to form the finger trench 401; or, when etching the sidewall of the insertion layer 40 to form the recessed trench 60, the etching rate and / or etching time at different locations can be adjusted to simultaneously form the recessed trench 60 and the finger trench 401. For example, when etching the sidewall of the insertion layer 40, the etching time at locations with finger trenches 401 can be extended, and the etching time at locations without finger trenches 401 can be shortened. Forming at least one finger trench 401 communicating with the recessed trench 60 on the sidewall of the insertion layer 40 near the heavily doped material layer 50 can further increase the contact area between the heavily doped material layer 50 and the channel structure 302, reducing the contact resistance between the heavily doped material layer 50 and the heterojunction sidewall. Optionally, when the finger grooves 401 are shaped as follows Figure 10 When the rectangle shown is shown, the vertical projection of the sidewall of the heavily doped material layer 50 near the insertion layer 40 onto the substrate 10 is comb-shaped (see reference). Figure 7 When the finger-shaped groove 401 is as follows Figure 11 When the triangle shown is formed, the vertical projection of the sidewall of the heavily doped material layer 50 near the insertion layer 40 onto the substrate 10 is serrated (see reference). Figure 9 ).

[0093] In summary, the distance between at least one finger-shaped groove 601 and the side of the recessed groove 60 near the first groove 70 is ≥0.

[0094] Based on the above embodiments, in one embodiment of the present invention, Figure 12a This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present invention, for reference. Figure 12a Multiple insertion layers 40 are disposed within the barrier layer 30; the multiple insertion layers 40 are disposed sequentially at intervals in a direction perpendicular to the substrate 10.

[0095] Specifically, the sidewalls of each insertion layer 40 near the source region and near the drain region are recessed by a predetermined distance relative to the sidewalls of the barrier layer 30, thereby forming multiple recessed trenches 60, each of which communicates with the first groove 70. The figure exemplarily shows two insertion layers 40 within the barrier layer 30, each forming a recessed trench 60 near both the source and drain regions, thus forming four recessed trenches 60. By providing multiple insertion layers 40 within the barrier layer 30, the contact area between the heavily doped material layer 50 and the channel structure 302 can be further increased, reducing the contact resistance between the heavily doped material layer 50 and the heterojunction sidewalls. In an optional embodiment, along the direction from the substrate 10 to the channel layer 20, the lengths of the multiple insertion layers 40 remain constant, gradually decrease, or gradually increase, wherein the length direction of the insertion layers 40 is parallel to the channel length direction of the channel structure 302. Specifically, refer to... Figure 12b , Figure 12b This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present invention. Along the direction from the substrate 10 to the channel layer 20, the lengths of the plurality of insertion layers 40 gradually decrease; Reference Figure 12c , Figure 12c This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present invention. Along the direction from the substrate 10 to the channel layer 20, the lengths of the multiple insertion layers 40 gradually increase.

[0096] Based on the above embodiments, in one embodiment of the present invention, Figure 13 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present invention, for reference. Figure 13 The channel structure 302 includes multiple channel structures 302, which are sequentially stacked on one side of the substrate 10. Each of the multiple insertion layers 40 corresponding to the multiple channel structures 302 includes an indented trench 60. The first groove 70 extends at least to the barrier layer 30 adjacent to the substrate 10. Specifically, the present invention employs a multi-channel AlGaN / GaN heterojunction stacked structure, which enables the formation of multiple parallel two-dimensional electron gas paths between the source and drain, increasing the total density of the two-dimensional electron gas and significantly increasing the saturation current of the device.

[0097] Optional, see reference Figure 14 Along the direction from the substrate 10 to the channel layer 20, the length of the multiple channel structures 302 gradually decreases.

[0098] Specifically, if according to Figure 13In the structure shown, the lengths of the multiple channel structures 302 are roughly equal, and the bottom surface of the first groove 70 formed by etching the multiple channel structures 302 includes an etched mesa 01. In this embodiment of the invention, the lengths of the multiple channel structures 302 gradually decrease along the direction from the substrate 10 to the channel layer 20, and can have multiple mesas. When the multi-channel stacked heterojunction has k layers, each barrier layer 30 except the top barrier layer 30 can have a corresponding etched mesa on its upper surface, plus the 01 set inside the first channel layer 20, which is k etched mesas; or the corresponding mesas can be set on the upper surface of m-1 barrier layers 30 (excluding the top barrier layer 30) in the k-layer barrier layers 30, that is, the total number of etched mesas is m, where 2≤m≤k; in this way, there are multiple steps on the sidewalls of the multi-layer heterojunction stacked structure, and N-type heavily doped GaN material is formed on the m mesas and wraps the sidewalls of the k-layer GaN layer and the barrier layer 30 heterojunction. Due to the presence of multiple stepped mesa on the sidewalls, the n-type heavily doped GaN material makes closer contact with the sidewalls of the heterojunction, thus reducing the contact resistance between the n-type heavily doped GaN material and the sidewalls of the multilayer GaN heterojunction. Figure 14 The example shows two channel structures, namely a multi-channel stacked heterostructure with two layers, and two etching mesa, etching mesa 01 and etching mesa 02.

[0099] This invention also provides a method for preparing a semiconductor structure. Figures 15-18 This is a cross-sectional structural diagram of steps S110 to S150 in a semiconductor structure fabrication method provided in an embodiment of the present invention, with reference to... Figures 15-18 Methods for fabricating semiconductor structures include:

[0100] S110, providing substrate 10.

[0101] S120. A channel structure 302 is formed on one side of the substrate 10. Forming the channel structure 302 includes sequentially forming a channel layer 20 and a barrier layer 30 on the substrate 10. The channel structure 302 includes a gate region Q1, and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1. Forming the barrier layer 30 includes forming an insertion layer 40 in the barrier layer 30. See details for further information. Figure 15 .

[0102] Optionally, forming a barrier layer 30 on the surface of the channel layer 20 away from the substrate 10 and forming an insertion layer 40 within the barrier layer 30 includes: forming a first barrier sublayer 31 on the surface of the channel layer 20 away from the substrate 10; forming an insertion layer 40 on the surface of the first barrier sublayer 31 away from the substrate 10; and forming a second barrier sublayer 32 on the surface of the insertion layer 40 away from the substrate 10; the barrier layer 30 includes the first barrier sublayer 31 and the second barrier sublayer 32.

[0103] S130, etching the channel structure 302 to form a first groove 70, the first groove 70 at least penetrating the barrier layer 30.

[0104] For details, please refer to Figure 16 A first groove 70 is formed by etching the channel structure 302 down to the barrier layer 30 or to a portion of the barrier layer 30, such that the bottom height of the first groove 70 is less than or equal to the interface height of the heterojunction. That is, the first groove 70 can partially penetrate the trench layer 20 or completely penetrate the channel layer 20. The bottom height of the first groove 70 can be the height of the bottom surface of the first groove 70 relative to the substrate 10, and the interface height of the heterojunction can be the height of the interface of the heterojunction relative to the substrate 10. This ensures that the heavily doped material layer 50 located in the first groove 70 can contact the heterojunction.

[0105] S140, laterally etch the sidewalls of the insertion layer 40 so that the sidewalls of the insertion layer 40 located at the source region Q2 and the drain region Q3 are recessed by a predetermined distance relative to the sidewalls of the barrier layer 30 to form a recessed trench 60, the recessed trench 60 being connected to the first groove 70.

[0106] For details, please refer to Figure 17 In order to reduce the contact resistance between the heavily doped material layer 50 and the channel structure 302, an insertion layer 40 is provided in the barrier layer 30 in this embodiment of the invention. The material of the insertion layer 40 is different from that of the barrier layer 30. Therefore, by laterally etching the insertion layer 40, the sidewall of the insertion layer 40 is recessed by a predetermined distance relative to the sidewall of the barrier layer 30, forming an indented trench 60 at the insertion layer 40 of the channel structure 302. The indented trench 60 communicates with the first groove 70.

[0107] S150, a heavily doped material layer 50 is formed in the first groove 70; the heavily doped material layer 50 fills the first groove 70 and the recessed trench 60.

[0108] For details, please refer to Figure 18 When depositing N-type heavily doped nitride semiconductor material in the first groove 70 to form a heavily doped material layer 50, the nitride semiconductor material can be filled in the recessed trench 60, thereby increasing the contact area between the heavily doped material layer 50 and the channel structure 302 and reducing the contact resistance between the heavily doped material layer 50 and the heterojunction sidewall.

[0109] Optionally, after forming the heavily doped material layer 50 within the first groove 70, the method further includes:

[0110] S160: A gate G is formed on the barrier layer 30, and a source S and a drain D are formed on the heavily doped material layer 50; the source S and drain D are located on opposite sides of the gate G. See details in [reference needed]. Figure 2 .

[0111] The technical solution provided by this embodiment of the invention involves setting an insertion layer 40 within a barrier layer 30. After etching a channel structure 302 to form a first groove 70 that at least penetrates the barrier layer 30, the sidewalls of the insertion layer 40 are laterally etched. This causes the sidewalls of the insertion layer 40 located at the source region Q2 and drain region Q3 to be recessed by a predetermined distance relative to the sidewalls of the barrier layer 30 to form a recessed trench 60. The recessed trench 60 is connected to the first groove 70. When a heavily doped material layer 50 is formed within the first groove 70, the heavily doped material layer 50 can fill both the first groove 70 and the recessed trench 60, thereby increasing the contact area between the heavily doped material layer 50 and the channel structure 302 and reducing the contact resistance between the heavily doped material layer 50 and the heterojunction sidewalls.

[0112] Optionally, lateral etching of the sidewalls of the insertion layer 40 to form a recessed trench 60 includes: selectively laterally etching the sidewalls of the insertion layer 40 to form at least one finger-shaped trench 601 at the ends of the insertion layer 40 located in the source region Q2 and the drain region Q3, wherein the at least one finger-shaped trench 601 is spaced apart along the width of the trench; the recessed trench 60 includes at least one finger-shaped trench 601. Through the above-described method of fabricating the recessed trench 60, the recessed trench 60 can be formed to include, for example,... Figure 6 Or, as shown in Figure 8, multiple finger-shaped grooves 601. (Reference) Figure 7 or Figure 9 When forming a heavily doped material layer 50 in the first groove 70, the process further includes: laterally growing the heavily doped material layer 50 so that the heavily doped material layer 50 fills at least one finger-shaped trench 601 to form a protrusion 501.

[0113] Optionally, the sidewalls of the insertion layer 40 can be selectively etched laterally to form, as shown in the image. Figure 4 Following the recessed trench 60, the process further includes: continuing to laterally etch the sidewalls of the insertion layer 40 to form at least one finger-shaped trench 401. (See reference) Figure 10 and Figure 11 At least one finger-shaped trench 401 is spaced apart along the width of the trench. When forming a heavily doped material layer 50 in the first groove 70, the process further includes: laterally growing the heavily doped material layer 50 so that the heavily doped material layer 50 fills the recessed trench 60 and the at least one finger-shaped trench 401 to form a protrusion 501 in the at least one finger-shaped trench 401.

[0114] Optionally, forming a heavily doped material layer 50 within the first groove 70 includes:

[0115] A heavily doped material layer 50, either a single-layer material layer or a multilayer material layer, is formed within the first groove 70, and the heavily doped material layer 50 is N-type doped during its formation; wherein the doping concentration is greater than 1E18 / cm. 3 .

[0116] Optionally, forming an insertion layer 40 within the barrier layer 30 includes: forming a plurality of insertion layers 40 within the barrier layer 30; and the plurality of insertion layers 40 being sequentially spaced apart in a direction perpendicular to the substrate 10. This allows for the formation of, for example... Figure 12a The semiconductor structure shown.

[0117] This invention also provides another method for fabricating a semiconductor structure. Figures 19-22 This is a cross-sectional structural diagram of steps S210 to S250 in a semiconductor structure fabrication method provided in an embodiment of the present invention. (Refer to...) Figures 19-22 Methods for fabricating semiconductor structures include:

[0118] S210, providing substrate 10.

[0119] S220: A plurality of channel structures 302 are formed on one side of the substrate 10, and the plurality of channel structures 302 are stacked sequentially on one side of the substrate 10. For details, refer to... Figure 19 Multiple channel structures 302 are formed on one side of the substrate 10. Forming the channel structure 302 includes forming a channel layer 20 and a barrier layer 30 sequentially on the substrate 10. The channel structure 302 includes a gate region Q1 and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1. Forming the barrier layer 30 includes forming an insertion layer 40 in the barrier layer 30.

[0120] S230: Etch multiple channel structures 302 to form a first groove 70 that extends at least through one side of the barrier layer 30 adjacent to the substrate 10. See details for further information. Figure 20 .

[0121] S240, selectively etch the sidewalls of the insertion layer 40 laterally, so that the sidewalls of the insertion layer 40 located at the source region Q2 and drain region Q3 are recessed by a predetermined distance relative to the sidewalls of the barrier layer 30 to form a recessed trench 60, which communicates with the first groove 70. Specifically, refer to... Figure 21 It can simultaneously etch the sidewalls of the insertion layers 40 located in different layers, or it can stagger the etching of the sidewalls of the insertion layers 40 located in different layers.

[0122] S250, a heavily doped material layer 50 is formed within the first groove 70; the heavily doped material layer 50 fills the first groove 70 and the recessed trench 60. See details for further information. Figure 22 .

[0123] S260: A gate G is formed on the barrier layer 30 furthest from the substrate 10, and a source S and a drain D are formed on the heavily doped material layer 50; the source S and drain D are located on opposite sides of the gate G. See details in [reference needed]. Figure 13 .

[0124] The present invention also provides a method for fabricating a semiconductor structure, wherein multiple channel structures 302 are formed on one side of a substrate 10, and the multiple channel structures 302 are sequentially stacked on one side of the substrate 10. The multiple channel structures 302 are etched to form a first groove 70 that at least penetrates the barrier layer 30 adjacent to one side of the substrate 10. The present invention employs a multi-channel AlGaN / GaN heterojunction stacked structure, which enables the formation of multiple parallel two-dimensional electron gas pathways between the source and drain, increasing the total two-dimensional electron gas density and significantly increasing the saturation current of the device.

[0125] Optional, see reference Figure 14 Along the direction from the substrate 10 to the channel layer 20, the length of the multiple channel structures 302 gradually decreases. Figures 23-24 The preparation method provided in the embodiments of the present invention Figure 14 The schematic cross-sectional structure of some steps in the fabrication method of the semiconductor structure shown is for reference. Figure 23 and Figure 24 During the etching of multiple channel structures 302, the barrier layer 30, the insertion layer 40 and the channel layer 20 are etched multiple times from deep to shallow along the direction from the gate to the substrate 10 to form multiple etching mesas at different heights (e.g., etching mesa 01 and etching mesa 02); wherein, the different etching mesas are located below the interface of the heterojunction formed by the channel layer 20 and the barrier layer 30 of different layers.

[0126] In this way, multiple steps exist on the sidewalls of the multilayer heterojunction stacked structure, and N-type heavily doped GaN material is formed on these multiple mesas and wraps around the sidewalls of the multilayer channel layer 20 and barrier layer 30 heterojunction. Due to the presence of multiple stepped mesas on the sidewalls, the N-type heavily doped GaN material has a closer contact with the sidewalls of the heterojunction, thus reducing the contact resistance between the N-type heavily doped GaN material and the sidewalls of the multilayer GaN heterojunction.

[0127] refer to Figure 14 Optionally, along the direction from the substrate 10 to the trench layer 20, the lengths of the plurality of recessed trenches 60 corresponding to the plurality of insertion layers 40 of the plurality of channel structures 302 gradually decrease. Optionally, along the direction from the substrate 10 to the trench layer 20, the projections of the plurality of recessed trenches 60 corresponding to the plurality of insertion layers 40 of the plurality of channel structures 302 onto the substrate 10 do not overlap.

[0128] In this embodiment, reference Figure 13The sidewall of the first groove 70 near the multiple channel structures 302 is a vertical surface; Reference Figure 14 The first groove 70 is stepped near the sidewall of the plurality of channel structures 302; in other embodiments, the length of the plurality of channel structures 302 gradually decreases, and the first groove 70 is inclined near the sidewall of the plurality of channel structures 302.

[0129] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate (10); A channel structure (302) is located on the substrate (10). The channel structure (302) includes a channel layer (20) and a barrier layer (30) formed sequentially on the substrate (10). The channel structure (302) includes a gate region (Q1) and a source region (Q2) and a drain region (Q3) located on both sides of the gate region (Q1). A first groove (70) is located within the source region (Q2) and the drain region (Q3), and the first groove (70) penetrates at least the barrier layer (30). An insertion layer (40) is disposed within the barrier layer (30); the sidewall of the insertion layer (40) located at the source region (Q2) and the drain region (Q3) is recessed by a predetermined distance relative to the sidewall of the barrier layer (30) to form an indented trench (60), the indented trench (60) communicating with the first groove (70); A heavily doped material layer (50) fills the first groove (70) and the recessed trench (60).

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A gate (G) located within the gate region (Q1), the gate (G) being located on the side of the barrier layer (30) away from the substrate (10); The source (S) and drain (D) are located in the source region (Q2) and drain region (Q3), respectively, and the source (S) and drain (D) are formed on the side of the heavily doped material layer (50) away from the substrate (10).

3. The semiconductor structure according to claim 1, characterized in that, The heavily doped material layer (50) is a single-layer material layer or a stacked material layer, and the stacked material layer includes a superlattice structure.

4. The semiconductor structure according to claim 1, characterized in that, The barrier layer (30) and the insertion layer (40) are made of group III nitride materials, the barrier layer (30) is made of AlGaN, and the insertion layer (40) is made of AlN or GaN.

5. The semiconductor structure according to claim 1, characterized in that, The heavily doped material layer (50) near the sidewall of the insertion layer (40) includes at least one protrusion (501); the recessed trench (60) includes at least one finger trench (601), the at least one finger trench (601) being spaced apart along the width of the trench; the protrusion is embedded in the finger trench (601) one by one.

6. The semiconductor structure according to claim 5, characterized in that, The sidewall of the heavily doped material layer (50) near the insertion layer (40) has a serrated or comb-like vertical projection on the substrate (10).

7. The semiconductor structure according to claim 5, characterized in that, The distance between the at least one finger groove (601) and the side of the recessed groove (60) near the first groove (70) is ≥0.

8. The semiconductor structure according to claim 1, characterized in that, The barrier layer (30) is provided with a plurality of insertion layers (40); the plurality of insertion layers (40) are arranged at intervals in sequence in a direction perpendicular to the substrate (10).

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The semiconductor structure includes a plurality of channel structures (302), which are stacked sequentially on one side of the substrate (10). Each of the plurality of insertion layers (40) corresponding to the plurality of channel structures (302) includes the recessed trench (60).

10. The semiconductor structure according to claim 9, characterized in that, The first groove (70) extends at least through the barrier layer (30) of the channel structure (302) on the side adjacent to the substrate (10).

11. The semiconductor structure according to claim 9, characterized in that, Along the direction from the substrate (10) to the channel layer (20), the length of the plurality of channel structures (302) gradually decreases.

12. The semiconductor structure according to claim 9, characterized in that, Along the direction from the substrate (10) to the channel layer (20), the lengths of the plurality of insertion layers (40) remain constant, gradually decrease, or gradually increase.

13. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate (10); A channel structure (302) is formed on one side of the substrate (10). The formation of the channel structure (302) includes the sequential formation of a channel layer (20) and a barrier layer (30) on the substrate (10). The channel structure (302) includes a gate region (Q1) and a source region (Q2) and a drain region (Q3) located on both sides of the gate region (Q1). The formation of the barrier layer (30) includes the formation of an insertion layer (40) within the barrier layer (30). The channel structure (302) is etched to form a first groove (70), the first groove (70) penetrating at least through the barrier layer (30). The sidewalls of the insertion layer (40) are etched laterally so that the sidewalls of the insertion layer (40) located at the source region (Q2) and the drain region (Q3) are recessed by a predetermined distance relative to the sidewalls of the barrier layer (30) to form an indented trench (60), which communicates with the first groove (70). A heavily doped material layer (50) is formed in the first groove (70); the heavily doped material layer (50) fills the first groove (70) and the recessed trench (60).

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, After forming a heavily doped material layer (50) within the first groove (70), the method further includes: A gate (G) is formed on the barrier layer (30); A source (S) and a drain (D) are formed on the heavily doped material layer (50); the source (S) and the drain (D) are located on opposite sides of the gate (G).

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming a barrier layer (30) on the surface of the channel layer (20) away from the substrate (10), and forming an insertion layer (40) within the barrier layer (30) includes: A first barrier sublayer (31) is formed on the surface of the channel layer (20) on the side away from the substrate (10). An insertion layer (40) is formed on the surface of the first barrier sublayer (31) on the side away from the substrate (10). A second barrier sublayer (32) is formed on the surface of the insertion layer (40) away from the substrate (10); the barrier layer (30) includes the first barrier sublayer (31) and the second barrier sublayer (32).

16. The method for preparing a semiconductor structure according to claim 13, characterized in that, The lateral etching of the sidewalls of the insertion layer (40) to form the recessed trench (60) includes: selectively laterally etching the sidewalls of the insertion layer (40) along the direction of the trench width to form at least one finger trench (601), the at least one finger trench (601) being spaced apart along the direction of the trench width. The process of forming a heavily doped material layer (50) within the first groove (70) further includes: The heavily doped material layer (50) is grown laterally so that the heavily doped material layer (50) fills the at least one finger trench (601) to form a protrusion (501).

17. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming a heavily doped material layer (50) within the first groove (70) includes: A heavily doped material layer (50) of a single material layer or a heavily doped material layer of a stacked material layer is formed in the first groove (70).

18. The method for preparing a semiconductor structure according to claim 13, characterized in that, An insertion layer (40) is formed within the barrier layer (30), comprising: A plurality of insertion layers (40) are formed within the barrier layer (30); the plurality of insertion layers (40) are arranged sequentially at intervals in a direction perpendicular to the substrate (10).

19. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming a channel structure (302) on one side of the substrate (10) includes: A plurality of channel structures (302) are formed on one side of the substrate (10); the plurality of channel structures (302) are stacked sequentially on one side of the substrate (10).

20. The method for preparing a semiconductor structure according to claim 19, characterized in that, Etching the channel structure (302) to form a first groove (70) includes: The multiple channel structures (302) are etched such that the length of the multiple channel structures (302) gradually decreases along the direction from the substrate (10) to the channel layer (20).

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