P-type LDMOS, P-type LDMOS operation method and integrated circuit chip

Abstract

The invention relates to a P-type LDMOS, a P-type LDMOS operation method and an integrated circuit chip, the P-type LDMOS comprises a substrate, a first buried layer arranged on the substrate, and a source region, a gate region and a drain region arranged above the first buried layer, a drift region is arranged between the source region and the drain region, the P-type LDMOS further comprises an N body region arranged in the drift region, the N body region is connected with the drain region; the side wall of the trench gate is in contact with the N body region, the drift region and the first buried layer, and the trench gate is filled with second polycrystalline silicon; and the first polycrystalline silicon is arranged on the upper surface of the drift region, and the first polycrystalline silicon is connected with the second polycrystalline silicon. The LDMOS provided by the invention has the characteristics of high reliability and low area cost.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and particularly to a P-type LDMOS, a method for operating a P-type LDMOS, and an integrated circuit chip. Background Art

[0002] Power semiconductors are a type of electronics that can perform energy conversion, high-voltage protection, and switching control. Briefly referred to as power, they have an important impact on the efficiency and speed of chips and are widely used in fields such as motor drives, automotive electronics, and communication devices. It is estimated that more than 75% of the electrical energy globally is utilized under the control of power.

[0003] For LDMOS, the current density of P-type LDMOS is limited by the low mobility of holes. To increase the current density, the manufacturing area of P-type LDMOS is relatively large, increasing the manufacturing cost. Especially in complementary logic integrated circuits, it is usually required that the current magnitudes of N-type LDMOS and P-type LDMOS are close to each other. However, due to the low mobility of holes, the current density of P-type LDMOS is much lower than that of N-type LDMOS. Therefore, the area of P-type LDMOS in the chip is significantly larger than that of N-type LDMOS, increasing the area cost during manufacturing. At the same time, when the LDMOS is in the on-state of high voltage and large current, the base-width modulation effect (Kirk effect) will occur. The Kirk effect will cause an increase in the carriers generated by impact ionization in the drift region of the LDMOS, and the output characteristic curve of the LDMOS shows an unsaturated trend; the Kirk effect also leads to premature breakdown at the drain, affecting the reliability.

[0004] Regarding the problem of low reliability and high area cost of existing LDMOS in related technologies, no effective solution has been proposed yet. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a P-type LDMOS, a method for operating a P-type LDMOS, and an integrated circuit chip that can solve the problems of low reliability and high area cost of LDMOS.

[0006] In a first aspect, in the present embodiment, a P-type LDMOS is provided, including a substrate, a first buried layer disposed on the substrate, a source region, a gate region, and a drain region disposed above the first buried layer. A drift region is provided between the source region and the drain region. The P-type LDMOS further includes:

[0007] An N-body region disposed in the drift region and connected to the drain region;

[0008] A trench gate, the sidewalls of the trench gate are respectively in contact with the N-body region, the drift region, and the first buried layer, and the trench gate is filled with second polysilicon;

[0009] The first polysilicon is disposed on the upper surface of the drift region, and the first polysilicon is connected to the second polysilicon.

[0010] In some embodiments, the ratio of the first distance to the second distance is greater than the ratio of the second voltage to the first voltage; wherein, the first distance is the distance between the first polysilicon and the N-body region, the second distance is the distance between the source region and the N-body region, the first voltage is the voltage difference between the first polysilicon and the N-body region when the P-type LDMOS operates, and the second voltage is the threshold voltage of the N-type UMOS formed by the N-body region, the drift region, the first buried layer, and the trench gate.

[0011] In some embodiments, the N-body region includes a heavily doped region, and the heavily doped region is connected to the drain region.

[0012] In some embodiments, the P-type LDMOS further includes a second buried layer; wherein,

[0013] The second buried layer is disposed in the drift region and the upper surface of the second buried layer is in contact with the upper surface of the drift region, and the majority carriers in the second buried layer and the majority carriers in the drift region have opposite polarities.

[0014] In some embodiments, the P-type LDMOS further includes a third buried layer; wherein,

[0015] The third buried layer is disposed in the drift region and the upper surface of the third buried layer is not in contact with the upper surface of the second buried layer, and the majority carriers in the third buried layer and the majority carriers in the drift region have opposite polarities.

[0016] In some embodiments, the P-type LDMOS further includes: a first oxide, one side of the first oxide is in contact with the upper surface of the drift region, and the other side of the first oxide is in contact with the lower surface of the first polysilicon and the lower surface of the gate region.

[0017] In some embodiments, the trench gate includes a second oxide, one side of the second oxide is in contact with the N-body region, the drift region, and the first buried layer, and the other side of the second oxide is in contact with the second polysilicon.

[0018] In some embodiments, the trench gate is filled with a third polysilicon; wherein,

[0019] The third polysilicon is disposed below the second polysilicon at intervals, and an insulating layer is provided between the second polysilicon and the third polysilicon.

[0020] In a second aspect, a method for operating a P-type LDMOS is provided in this embodiment, which is applied to the P-type LDMOS described in the first aspect above. The method includes:

[0021] Input a drain signal to the connection terminal between the N-body region and the drain region of the P-type LDMOS;

[0022] Input a gate signal to the gate region of the P-type LDMOS;

[0023] Input a source signal to the source region of the P-type LDMOS.

[0024] In a third aspect, an integrated circuit chip is provided in this embodiment. The integrated circuit chip includes the LDMOS described in the first aspect above.

[0025] Based on the traditional P-type LDMOS, the above-mentioned P-type LDMOS, the method for operating the P-type LDMOS, and the integrated circuit chip are provided with a first polysilicon, an N-body region, and a trench gate, so as to realize the integration of UMOS on the basis of the P-type LDMOS. By using the high current density of the N-type UMOS to increase the overall current density, the problem of increased area cost is solved; the LDMOS has two types of carriers injected into the drift region, reducing the net charge amount in the injected drift region, avoiding premature breakdown of the LDMOS at the drain, and solving the problem of low reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of power in a related technology;

[0027] Figure 2 It is a schematic diagram of the surface electric field distribution when the P-type LDMOS in an embodiment undergoes off-state and on-state breakdown;

[0028] Figure 3 It is a schematic diagram of the P-type LDMOS in an embodiment;

[0029] Figure 4 It is a schematic structural diagram of the LDMOS in another embodiment;

[0030] Figure 5 It is a schematic diagram of the working principle and current path of the LSMOS when it is conducting in an embodiment;

[0031] Figure 6 It is a schematic diagram of the current path of the LDMOS when it is conducting in an embodiment;

[0032] Figure 7 It is a schematic structural diagram of the LDMOS when a second buried layer is provided in an embodiment;

[0033] Figure 8Schematic diagram of the structure when the third buried layer is set for LDMOS in an embodiment;

[0034] Figure 9 Schematic diagram of the structure when the third polysilicon is set for LDMOS in an embodiment;

[0035] Figure 10 Comparison chart of the output characteristic curves of the traditional P-type LDMOS and the P-type LDMOS in this embodiment in an embodiment. Detailed implementation manners

[0036] In order to make the purpose, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] In order to make the purpose, technical solutions and advantages of the present application clearer and more understandable, the present application will be described and explained below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present application without making creative efforts belong to the scope of protection of the present application. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes made on the basis of the technical content disclosed in the present application are only conventional technical means and should not be understood as insufficient disclosure of the content of the present application.

[0038] Referring to "embodiment" in the present application means that the specific features, structures or characteristics described in combination with the embodiment may be included in at least one embodiment of the present application. The phrase appears at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those of ordinary skill in the art explicitly and implicitly understand that the embodiments described in the present application may be combined with other embodiments without conflict.

[0039] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. The words such as "a", "an", "one kind", "the" and the like involved in this application do not indicate a quantity limitation and may represent a singular or plural number. The terms "comprising", "including", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to these processes, methods, products or devices. The similar words such as "connected", "coupled" and "linked" involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application means greater than or equal to two. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, "A and / or B" may represent: A exists alone, A and B exist simultaneously, and B exists alone. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects and do not represent a specific order of the objects.

[0040] Figure 1 The schematic diagram of power in the related art is provided. Among them, classified according to the positions of the power source, drain, and gate electrodes, when all three electrodes are located on the surface, it is called lateral. Figure 1 (a) of is the schematic diagram of the structure of a kind of lateral double-diffused MOSFET (LDMOS). The lateral double-diffused MOSFET is easy to integrate with others, but the current density per unit area is relatively small. When there is an electrode located on the bottom surface, it is called vertical. Figure 1 (b) of is the schematic diagram of the structure of a kind of trench MOSFET (UMOS), as Figure 1 shown in (b), the current density per unit area of the trench MOSFET is relatively large, but it is difficult to integrate with others. Classified according to the type of majority carriers in the conductive channel, the one using electron conduction is called N-type, and the channel is turned on under a positive gate voltage; for example, Figure 1 (b) of is a kind of N-type MOS. The one using hole conduction is called P-type MOS, and the channel is turned on under a negative gate voltage; for example, Figure 1 (a) of is a kind of P-type. Since the mobility of carriers will affect the current density, and the mobility of electrons is much greater than that of holes, the current density of N-type LDMOS is much higher than that of P-type LDMOS. In complementary logic integrated circuits, it is usually required that the currents of N-type and P-type are close to each other. Therefore, the area of P-type will be significantly larger than that of N-type, increasing the area cost of chip manufacturing.

[0041] The main optimization goal of power is to increase the breakdown voltage and current density. For LDMOS, under certain conditions of drift region length and thickness, as the doping concentration of the drift region increases, the current density will increase, and the off-state breakdown voltage will show a trend of increasing first and then decreasing. At the same time, the position of the electric field peak under high voltage will shift from the source to the drain. In order to achieve the maximum off-state breakdown voltage, it is necessary to achieve charge balance in the drift region. However, when in the on state of high voltage and high current, a large number of carriers injected into the drift region will introduce additional charges, destroy the original charge balance, and cause the base width modulation effect (Kirk effect).

[0042] The Kirk effect will significantly enhance the electric field and impact ionization rate near the drain of LDMOS compared to the off state. On the one hand, the increase in impact ionization rate will lead to an increase in carriers generated by impact ionization in the drift region, and the output characteristic curve of LDMOS will show an unsaturated trend. The curve will "upward" under high voltage, affecting the reliability; on the other hand, the Kirk effect will also cause premature breakdown at the drain, making the on-state breakdown voltage much lower than the off-state breakdown voltage, thus affecting the reliability of LDMOS.

[0043] Figure 2 This is a schematic diagram of the surface electric field distribution when the P-type LDMOS is in the off state and the on state. When the electric field strength at a certain point reaches the limit electric field strength limited by the material properties, avalanche breakdown will occur. Figure 2 (a) is a schematic diagram of the electric field distribution when the P-type LDMOS undergoes off-state breakdown. Figure 2 As shown in (a), the drift region reaches charge balance, the electric field distribution is relatively uniform, and there are several electric field peaks of similar magnitude. Since voltage is the integral of the electric field over the distance, a larger off-state breakdown voltage can be achieved at this time. Figure 2 (b) is a schematic diagram of the electric field distribution when the P-type LDMOS undergoes on-state breakdown. Figure 2 As shown in (b), in the on state, holes are injected into the drift region, destroying the charge balance and causing the Kirk effect, which makes the electric field strength near the drain significantly higher than that in other regions, causing early breakdown at the drain. Therefore, the on-state breakdown voltage is much lower than the off-state breakdown voltage. In order to take into account both the off-state and on-state breakdown voltages, it is necessary to reduce the doping concentration of the drift region, which will lead to a decrease in current density.

[0044] In view of the above problems, in one embodiment, Figure 3As shown in the figure, a schematic diagram of a P-type LDMOS (hereinafter referred to as LDMOS) is provided. The LDMOS includes a substrate, a first buried layer disposed on the substrate, a source region, a gate region, and a drain region disposed above the first buried layer. A drift region is provided between the source region and the drain region, and further includes: an N-body region disposed in the drift region, and the N-body region is connected to the drain region; a trench gate, the side walls of the trench gate are respectively in contact with the N-body region, the drift region, and the first buried layer, and the trench gate is filled with second polysilicon; a first polysilicon disposed on the upper surface of the drift region, and the first polysilicon is connected to the second polysilicon.

[0045] Among them, in the traditional P-type LDMOS, the first buried layer is an N-type buried layer, a P-type source region, a gate region, and a P-type drain region are disposed above the N-type buried layer, and a P drift region is disposed between the source region and the drain region. Optionally, reference can be made to Figure 1 (a) of, where an N well and a P drift region are disposed above the first buried layer. The source N-body region in the N well includes an N+ region and a P+ region, and the N+ region and the P+ region together serve as the source (S) of the P-type LDMOS to obtain the source region; a planar gate polysilicon is connected to the upper layer of the N well and the P drift region, and the planar gate polysilicon is the gate (G) of the P-type LDMOS to obtain the gate region; the P drift region includes a P+ region with a doping concentration higher than other regions in the P drift region, and the P+ region is used as the drain (D) of the P-type LDMOS to obtain the drain region.

[0046] The LDMOS in this embodiment is further provided with a first polysilicon, an N-body region, and a trench gate on the basis of the traditional P-type LDMOS. Among them, the first polysilicon belongs to floating polysilicon, which is connected to the second polysilicon in the trench gate but not connected to an external signal. The N-body region is connected to the drain region and serves as the drain of the LDMOS, so that the regions where the N-body region, the trench gate, and part of the drift region and part of the first buried layer are located conform to the characteristic that the electrode is located on the bottom surface. Therefore, the semiconductor structure composed of the drain N-body region, the trench gate, and part of the P drift region and the first buried layer in the LDMOS can be regarded as an N-type UMOS. In the LDMOS, except for the N-type UMOS, the remaining structure conforms to the characteristic that all three electrodes are located on the surface, and since the turn-on and turn-off of the LDMOS depend on the control of the planar gate on the hole channel, the overall semiconductor structure in this embodiment can still be regarded as a P-type LDMOS.

[0047] When the P-type LDMOS is turned on, the voltage difference between the gate and the source is less than the threshold voltage of the above-mentioned P-type LDMOS, and the voltage difference between the drain and the source is less than 0. A hole inversion layer will be formed on the upper surface of the source N-body region and the N-well, and the holes in the source N-body region enter the drain region, that is, the P+ region in the P drift region, through the hole inversion layer, to form a hole current. At the same time, the potential of the first polysilicon is higher than the potential of the drain, forming an electric field line pointing from the node where the polysilicon is located to the node where the drain is located, so that the node where the first polysilicon is located is larger than the node where the drain is located. In the case where the potential difference between the first polysilicon and the drain is greater than the threshold voltage of the N-type UMOS, an electron inversion layer will be formed on the side surface of the P drift region close to the trench gate, so that the electrons of the drain are injected into the first buried layer through the drain N-body region and the electron inversion layer, and are finally collected by the electrode connected to the source region to form an electron current.

[0048] In the above embodiment, when the LDMOS is working, there are two types of carriers inside that participate in conduction at the same time, and the mobility of electrons is much higher than that of holes. Therefore, while retaining the advantage of easy integration of the P-type LDMOS, the high current density of the N-type UMOS is used to increase the overall current density, thereby solving the problem of increased area cost during manufacturing due to the low current density of the P-type LDMOS in the related art; when the LDMOS is working, there are two types of carriers inside that participate in conduction at the same time, and there can also be a charge compensation effect between the two carriers injected into the drift region. The net charge amount injected into the drift region is greatly reduced compared with the traditional P-type LDMOS, and the Kirk effect is suppressed, so the output characteristic curve will be flatter, and no obvious upward warping will occur before the on-state breakdown, and the on-state breakdown voltage will be increased, thereby solving the problem of premature breakdown of the LDMOS at the drain and affecting the reliability; the effect of improving the reliability of the LDMOS while reducing the manufacturing area cost is achieved.

[0049] Moreover, the width of the trench gate in the N-type UMOS region can be set very narrow, so the increase in the overall area of ​​LDMOS is very small. In addition, electrons and holes appear as majority carriers in their respective flow regions, and do not appear as minority carriers like in bipolar transistors, so there is no minority carrier accumulation effect, which does not affect the turn-on and turn-off speeds.

[0050] In some of the embodiments, the ratio of the first distance to the second distance is greater than the ratio of the second voltage to the first voltage; wherein the first distance is the distance between the first polysilicon and the N body region, the second distance is the distance between the source region and the N body region, the first voltage is the voltage difference between the first polysilicon and the N body region when the LDMOS is operating, and the second voltage is the threshold voltage of the N-type UMOS composed of the N body region, the drift region, the first buried layer and the trench gate.

[0051] Among them, when the LDMOS operates, the gate potential in the gate region is higher than the drain potential corresponding to the N-body region. When the LDMOS is in a charge balance state, the potential difference between the first polysilicon and the drain is related to the first distance and the second distance. Among them, with the second distance and the potential difference between the gate and the drain remaining unchanged, the longer the first distance, the greater the first voltage; the shorter the first distance, the smaller the first voltage. Optionally, the first distance can be adjusted through experiments such that the ratio of the first distance to the second distance is greater than the ratio of the specified threshold voltage to the first voltage. When the LDMOS operates, the potential difference between the first polysilicon and the drain is greater than the threshold voltage, causing an electron inversion layer to form on the side surface of the P-drift region close to the trench gate, thereby forming an electron current, which serves to increase the overall current density of the LDMOS device.

[0052] In some of these embodiments, the LDMOS further includes: a first oxide, one side of the first oxide is in contact with the upper surface of the drift region, and the other side of the first oxide is in contact with the lower surface of the first polysilicon and the lower surface of the gate region. Optionally, a trench is etched on the upper surface of the P-drift region by means of oxide shallow trench isolation, and the first oxide is filled in the trench. By providing the first oxide, electrical isolation can be provided between the P-drift region, the first polysilicon, and the planar gate polysilicon.

[0053] In some of these embodiments, the N-body region includes a heavily doped region, and the heavily doped region is connected to the drain region. Among them, the doping concentration of the heavily doped region is higher than that of other regions in the N-body region. Connecting the heavily doped region to the drain region reduces the barrier height between the semiconductor and the metal electrode, reduces the ohmic contact resistance, achieves the effect of reducing the total resistance of the LDMOS and ensuring good ohmic contact, thereby improving the stability of the LDMOS.

[0054] In some of these embodiments, the LDMOS further includes a second buried layer; wherein, the second buried layer is disposed in the drift region and the upper surface of the second buried layer is in contact with the upper surface of the drift region, and the majority carriers in the second buried layer and the majority carriers in the drift region have opposite polarities. Optionally, when the drift region is a P-type drift region, the second buried layer is an N-type buried layer, and vice versa. By providing the second buried layer in the drift region, two regions with different doping concentrations are introduced in the drift region, making the electric field distribution more uniform, thereby significantly increasing the breakdown voltage. This enables operation at a higher voltage without breakdown, improving the reliability of the LDMOS.

[0055] In some of these embodiments, the LDMOS further includes a third buried layer; wherein, the third buried layer is disposed in the drift region and the upper surface of the third buried layer does not contact the upper surface of the second buried layer, and the majority carriers in the third buried layer and the majority carriers in the drift region have opposite polarities. Optionally, when the drift region is a P-type drift region, the third buried layer is an N-type buried layer, and vice versa. By disposing the third buried layer in the drift region and the upper surface of the third buried layer not contacting the upper surface of the second buried layer, three regions with different doping concentrations are introduced into the drift region. Through the three regions with different doping concentrations, the electric field distribution in the drift region during the operation of the LDMOS can be further optimized, making the electric field distribution more uniform, reducing the possibility of breakdown of the LDMOS operating under high voltage, and improving the reliability of the LDMOS.

[0056] In some of these embodiments, the trench gate includes a second oxide. One side of the second oxide contacts the N-body region, the drift region, and the first buried layer, and the other side of the second oxide contacts the second polysilicon. Wherein, the trench gate oxide layer can be formed through the second oxide to isolate the polysilicon from the N-body region, the drift region, and the first buried layer, avoid electrical conduction of the second polysilicon, ensure that the first polysilicon is in a floating state, and thus improve the stability of the LDMOS.

[0057] In some of these embodiments, the trench gate is filled with a third polysilicon; wherein, the third polysilicon is disposed below the second polysilicon at intervals, and an insulating layer is disposed between the second polysilicon and the third polysilicon. By disposing the third polysilicon, an additional polysilicon layer can be introduced on the basis of the N-type UMOS. The third polysilicon is used as a shielding gate polysilicon to avoid breakdown caused by too high an electric field intensity at the bottom of the trench gate. Thus, by optimizing the electric field distribution, the breakdown voltage in the LDMOS interval is increased, thereby improving the breakdown voltage resistance and conduction characteristics.

[0058] Optionally, the trench gate includes a second oxide, a second polysilicon, and a third polysilicon. One side of the second oxide contacts the N-body region, the drift region, and the first buried layer, and the other side of the second oxide contacts the second polysilicon and the third polysilicon. The second polysilicon and the third polysilicon are disposed at intervals through an insulating layer.

[0059] In one embodiment, Figure 4 Another structural schematic diagram of the LDMOS is provided. As Figure 4As shown, the LDMOS includes a substrate, and a first buried layer disposed on the substrate is an N-type buried layer. Above the N-type buried layer, there are provided: an N-well and a P-drift region. Among them, the source region provided in the N-well is a source N-body region, and the source N-body region includes an N+ region and a P+ region; the drain region provided in the P-drift region is a drain P+ region. Above the source N-body region and the P-drift region, a gate region composed of planar gate polysilicon is provided. Among them, a planar gate oxide is disposed below the planar gate polysilicon, and a shallow trench isolation oxide is disposed on the upper surfaces of the source N-body region and the drain P+ region, that is, the first oxide in the above embodiment. The planar gate oxide is in contact with the shallow trench isolation oxide.

[0060] The LDMOS further includes: a floating polysilicon, a drain N-body region, and a trench gate. Among them, the floating polysilicon is the first polysilicon in the above embodiment, and it is disposed above the P-drift region and is in contact with the shallow trench isolation oxide. The drain N-body region includes a drain N+ region, and the drain N+ region is connected to the drain P+ region. The sidewalls of the trench gate are respectively in contact with the drain N-body region, the P-drift region, and the N-type buried layer. The trench gate includes a trench gate oxide, that is, the second oxide in the above embodiment, and the trench gate further includes a trench gate polysilicon, that is, the second polysilicon in the above embodiment. The first polysilicon and the second polysilicon are connected.

[0061] Among them, the floating polysilicon and the trench gate polysilicon are connected and kept floating, not directly connected to an external signal, denoted as the Gn node; the drain N+ region and the drain P+ region are connected and connected to an external drain signal, denoted as the D node; the planar gate polysilicon is connected to an external gate signal, denoted as the G node; the source N+ region and the source P+ region are connected and connected to an external source signal, denoted as the S node; the voltage between the D node and the S node is denoted as V D-S , and the voltages between the remaining nodes are the same; the threshold voltage of the P-type LDMOS is denoted as V Tp (V Tp <0), and the threshold voltage of the N-type UMOS is denoted as V Tn (V Tn >0).

[0062] Figure 5 is a schematic diagram of the working principle and current path of the LSMOS in this embodiment when it is turned on. When V G-S <V Tp , V D-S <0, a hole inversion layer will be formed on the upper surfaces of the source N-body region and the N-well. The holes in the source P+ region are attracted by the low potential of the drain, injected into the P-drift region through the hole inversion layer, enter the drain P+ region, and are collected by the drain electrode to form a hole current.

[0063] Figure 6 provides a schematic diagram of the current path when the LDMOS is turned on, as shown in Figure 6As shown, the LDMOS includes a first oxide. Since the potential of the G node is higher than that of the D node when the LDMOS operates, there will be electric field lines pointing from G to D in the oxide layer, causing the potential of the Gn node to be induced. Also, because when the LDMOS is in a charge balance state, the electric field lines from G to D are almost uniform, so the magnitude of V Gn-D depends on Figure 5 the ratio of L1 and L2 in

[0064]

[0065] By adjusting the ratio of L1 and L2, it can be made that at a certain voltage, V Gn-D > V Tn . For reference, Figure 6 an electron inversion layer will be formed on the side surface of the P drift region close to the trench gate. The electrons of the drain will be attracted by the high voltage of the source, injected into the N-type buried layer through the drain N body region and the electron inversion layer, and flow through the N well and the source N body region, and finally be collected by the source electrode to form an electron current. Therefore, when operating under high-voltage and high-current conditions, both electron current and hole current exist in the P drift region.

[0066] Optionally, when the LDMOS is provided with a second buried layer, the second buried layer is an N-type buried layer, and its upper surface is connected to the shallow trench isolation oxide, Figure 7 is a schematic structural diagram when the LDMOS is provided with a second N-type buried layer. When the LDMOS is provided with a third N-type buried layer, the third buried layer is an N-type buried layer, and its upper surface is not connected to the shallow trench isolation oxide, Figure 8 is a schematic structural diagram when the LDMOS is provided with a third buried layer.

[0067] Optionally, when a third polysilicon is provided in the trench gate of the LDMOS, the third polysilicon is a shielding gate polysilicon, Figure 9 is a schematic structural diagram when the LDMOS is provided with a third polysilicon.

[0068] The P-type LDMOS in this embodiment has two majority carrier conductions during operation, which can increase the current density of the P-type LDMOS, relieve the Kirk effect under high voltage at the same time, make the output characteristic curve smoother, and increase the on-state breakdown voltage. Figure 10 is a comparison diagram of the output characteristic curves of the traditional P-type LDMOS and the P-type LDMOS in this embodiment. Among them, Figure 10 the abscissa VDS in is the drain voltage, and the ordinate ID is the drain current.

[0069] In the LDMOS of this embodiment, a trench gate is added to the drift region of the P-type LDMOS, so as to realize the integration of the N-type UMOS on the basis of the traditional P-type LDMOS. By detecting the potential of the drift region through the floating P+ region, the indirect control of the trench gate is realized, and an electron current is formed. Since both electrons and holes exist in the drift region, the high mobility of electrons will increase the current density. At the same time, the two injected carriers will produce a charge compensation effect, suppressing the influence of the injected carriers on the charge balance and suppressing the Kirk effect.

[0070] Based on the same inventive concept, an embodiment of the present application also provides a method for operating a P-type LDMOS for implementing the above-mentioned P-type LDMOS. The implementation solutions described in the method embodiments are similar to the implementation solutions for solving problems provided by the above P-type LDMOS. Therefore, the specific limitations in one or more of the following method embodiments for operating a P-type LDMOS can refer to the limitations on the LDMOS in the above text, and will not be repeated here. In one embodiment, a method for operating a P-type LDMOS, applied to the LDMOS in the above embodiments, the method includes: inputting a drain signal to the connection end between the N-body region and the drain region of the P-type LDMOS; inputting a gate signal to the gate region of the P-type LDMOS; inputting a source signal to the source region of the P-type LDMOS.

[0071] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0072] Based on the same inventive concept, an embodiment of the present application also provides an LDMOS integrated circuit chip for implementing the above-mentioned P-type LDMOS. In one embodiment, the integrated circuit chip includes the P-type LDMOS in any one or more of the above embodiments.

[0073] The solution for solving the problem provided in this chip embodiment is similar to the solution described in the above LDMOS embodiment. Therefore, the specific limitations in an embodiment of the integrated circuit chip provided below can refer to the limitations on LDMOS in the above text and will not be repeated here.

[0074] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0075] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several variations and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A P-type LDMOS, comprising a substrate, a first buried layer arranged on the substrate, a source region, a gate region and a drain region arranged above the first buried layer, a drift region being arranged between the source region and the drain region, characterized in that: The P-type LDMOS further comprises: An N body region is disposed in the drift region, and the N body region is connected to the drain region; A trench gate, wherein sidewalls of the trench gate are in contact with the N body region, the drift region and the first buried layer respectively, and the trench gate is filled with second polysilicon; The first polysilicon is disposed on the upper surface of the drift region, and the first polysilicon is connected to the second polysilicon.

2. The P-type LDMOS according to claim 1, characterized in that: The ratio of the first distance to the second distance is greater than the ratio of the second voltage to the first voltage; wherein the first distance is the distance between the first polysilicon and the N body region, the second distance is the distance between the source region and the N body region, the first voltage is the voltage difference between the first polysilicon and the N body region when the P-type LDMOS is running, and the second voltage is the threshold voltage of the N-type UMOS composed of the N body region, the drift region, the first buried layer and the trench gate.

3. The P-type LDMOS according to claim 1, characterized in that: The N body region includes a heavily doped region, and the heavily doped region is connected to the drain region.

4. The P-type LDMOS according to claim 1, characterized in that: The P-type LDMOS also includes a second buried layer; wherein, The second buried layer is disposed in the drift region and an upper surface of the second buried layer contacts an upper surface of the drift region. The polarities of majority carriers in the second buried layer and majority carriers in the drift region are opposite.

5. The P-type LDMOS according to claim 4, characterized in that: The P-type LDMOS further includes a third buried layer; wherein, The third buried layer is arranged in the drift region and an upper surface of the third buried layer does not contact an upper surface of the second buried layer. The polarities of majority carriers in the third buried layer and majority carriers in the drift region are opposite.

6. The P-type LDMOS according to claim 1, characterized in that: The P-type LDMOS further includes a first oxide, one side of the first oxide contacts the upper surface of the drift region, and the other side of the first oxide contacts the lower surface of the first polysilicon and the lower surface of the gate region.

7. The P-type LDMOS according to claim 1, characterized in that: The trench gate includes a second oxide, one side of the second oxide is in contact with the N body region, the drift region and the first buried layer, and the other side of the second oxide is in contact with the second polysilicon.

8. The P-type LDMOS according to claim 1 or 7, characterized in that: The trench gate is filled with third polysilicon; wherein, The third polysilicon is disposed below the second polysilicon at intervals, and an insulating layer is disposed between the second polysilicon and the third polysilicon.

9. A P-type LDMOS operation method, applied to the P-type LDMOS according to any one of claims 1 to 8, characterized in that: Methods include: Inputting a drain signal to a connection terminal between an N-body region of the P-type LDMOS and the drain region; Inputting a gate signal to the gate region of the P-type LDMOS; A source signal is input to the source region of the P-type LDMOS.

10. An integrated circuit chip, characterized in that: The integrated circuit chip comprises the P-type LDMOS according to any one of claims 1 to 8.

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