Semiconductor device

Abstract

The invention provides a semiconductor device capable of improving resistance to malfunction and damage caused by noise and the like. The present invention is provided with: a base of a first conductivity type; a first well region of a second conductivity type, which is provided in the base body, and in which a high-side circuit is formed; a second well region of the first conductivity type provided above the first well region; a first withstand voltage region of a second conductivity type provided around the first well region; a contact region of a second conductivity type provided on the first well region or the first withstand voltage region; a slit region of the first conductivity type provided between the contact region and a second well region above the first well region, the slit region being connected to the second well region via a resistor; a second withstand voltage region of the first conductivity type provided on the outer peripheral side of the first withstand voltage region; and a level shifter that transmits a signal between the low-side circuit and the high-side circuit.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Patent Document 1 discloses the following structure: In a high-voltage integrated circuit (HVIC), a p-type region of a reference potential (VS potential) of a high-side circuit and an n-type region of a power supply potential (VB potential) of the high-side circuit are formed separately, thereby preventing the formation of a parasitic pnp bipolar transistor.

[0003] Patent Document 2 discloses the following structure: In an HVIC, in order to improve the tolerance to noise that causes VB potential < ground potential (GND potential), sides of a p-type slit are provided and sides of a non-p-type slit are provided, and a hole current is absorbed by the sides of the non-p-type slit, thereby making it difficult for current to flow into the high-side circuit. - type slit and sides of a non-p - type slit, and a hole current is absorbed by the sides of the non-p - type slit, thereby making it difficult for current to flow into the high-side circuit.

[0004] Patent Document 3 discloses the following structure; in an HVIC, in a contact region of the VB potential, not only an n + type region but also a p + type region are formed, and a hole current is absorbed by the n + type region and the p + type region, thereby making it difficult for current to flow into the high-side circuit.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent No. 6008054 Gazette

[0008] Patent Document 2: Japanese Patent No. 6447139 Gazette

[0009] Patent Document 3: Japanese Patent No. 5099282 Gazette Summary of the Invention

[0010] Problems to be Solved by the Invention

[0011] When operating an HVIC, it is used while maintaining a potential relationship of VB potential > VS potential ≥ GND potential. However, when this potential relationship is disrupted due to noise or the like, parasitic operation is triggered, which becomes a cause of malfunction and damage. Regarding the technologies described in Patent Documents 1 to 3, in addition to the case where these technologies cannot be applied due to differences in the target chip size and design concept, there are also cases where the noise tolerance of a single unit is insufficient. Therefore, noise countermeasures based on different methods are always required.

[0012] In view of the above problems, an object of the present invention is to provide a semiconductor device capable of improving tolerance to malfunction and damage caused by noise and the like.

[0013] Solution to the problem

[0014] The gist of one aspect of the present invention is a semiconductor device including: a substrate of a first conductivity type; a first well region of a second conductivity type provided in the substrate, in which a high-side circuit is formed; a second well region of the first conductivity type provided above the first well region; a first breakdown voltage region of the second conductivity type provided around the first well region, the impurity concentration of the first breakdown voltage region being lower than the impurity concentration of the first well region; a contact region of the second conductivity type provided above the first well region or the first breakdown voltage region, the impurity concentration of the contact region being higher than the impurity concentration of the first well region; a slit region of the first conductivity type provided between the second well region and the contact region above the first well region, the slit region being connected to the second well region via a resistor; a second breakdown voltage region of the first conductivity type provided on the outer peripheral side of the first breakdown voltage region in a grounded manner; and a level shifter that transfers a signal between a low-side circuit and a high-side circuit formed on the outer peripheral side of the second breakdown voltage region.

[0015] Effect of the invention

[0016] According to the present invention, it is possible to provide a semiconductor device capable of improving tolerance to malfunction and damage caused by noise and the like. Description of the drawings

[0017] Figure 1 is a circuit diagram of the semiconductor device according to the first embodiment.

[0018] Figure 2 is a top view of the semiconductor device according to the first embodiment.

[0019] Figure 3 is the semiconductor device according to the first embodiment with Figure 2 a cross-sectional view taken along line A-A'.

[0020] Figure 4 is a cross-sectional view of a region including a polysilicon resistor of the semiconductor device according to the first embodiment.

[0021] Figure 5 is the semiconductor device according to the first embodiment with Figure 2 a cross-sectional view taken along line B-B'.

[0022] Figure 6 is a top view of the semiconductor device according to the comparative example.

[0023] Figure 7The cross-sectional view obtained by cutting along the A-A' line of the semiconductor device according to the comparative example when the potential relationship is VS potential > VB potential >> GND potential Figure 6

[0024] Figure 8 The cross-sectional view obtained by cutting along the A-A' line of the semiconductor device according to the first embodiment when the potential relationship is VS potential > VB potential >> GND potential Figure 2

[0025] Figure 9 The cross-sectional view obtained by cutting along the A-A' line of the semiconductor device according to the comparative example when the potential relationship is VB potential < VS potential Figure 6

[0026] Figure 10 The cross-sectional view obtained by cutting along the A-A' line of the semiconductor device according to the first embodiment when the potential relationship is VB potential < VS potential Figure 2

[0027] Figure 11 The cross-sectional view obtained by cutting along the B-B' line of the semiconductor device according to the comparative example when the potential relationship is VB potential < GND potential Figure 6

[0028] Figure 12 The cross-sectional view obtained by cutting along the B-B' line of the semiconductor device according to the first embodiment when the potential relationship is VB potential < GND potential Figure 2

[0029] Figure 13 The cross-sectional view corresponding to the position where the semiconductor device according to the second embodiment is cut along the A-A' line Figure 2

[0030] Figure 14 The cross-sectional view corresponding to the position where the semiconductor device according to the second embodiment is cut along the B-B' line Figure 2

[0031] Figure 15 The top view of the semiconductor device according to the third embodiment

[0032] Figure 16 The cross-sectional view corresponding to the position where the semiconductor device according to the fourth embodiment is cut along the A-A' line Figure 2

[0033] Figure 17 The cross-sectional view corresponding to the position where the semiconductor device according to the fourth embodiment is cut along the A-A' line Figure 2 ​​​​​​​​​The sectional view corresponding to the position cut by the B-B' line.

[0034] Figure 18 It is a top view of the semiconductor device according to the fifth embodiment. Detailed implementation manners

[0035] Hereinafter, the first to fifth embodiments of the present invention will be described with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thicknesses of the respective layers, etc. may sometimes be different from the actual ones. In addition, there may also be parts with different dimensional relationships and ratios between the drawings. In addition, the first to fifth embodiments shown below illustrate devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the material, shape, structure, configuration, etc. of the structural components as the following material, shape, structure, configuration, etc.

[0036] In this specification, the "carrier supply region" refers to a semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field effect transistor (FET) or a static induction transistor (SIT), or the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a diode, a static induction (SI) thyristor, or a gate turn-off (GTO) thyristor, the anode region is the carrier supply region. In addition, the "carrier receiving region" refers to a semiconductor region that receives majority carriers constituting the main current, such as the drain region of an FET or an SIT, or the collector region of an IGBT. In a diode, an SI thyristor, or a GTO thyristor, the cathode region functions as the carrier receiving region.

[0037] In addition, in this specification, the definitions of up and down and other directions are only for the convenience of description and are not used to limit the technical idea of the present invention. For example, it goes without saying that if the object is rotated by 90° and observed, then up and down are changed to left and right and read, and if the object is rotated by 180° and observed, then up and down are flipped and read.

[0038] In addition, in this specification, the case where the first conductivity type is p-type and the second conductivity type is n-type is illustratively described. However, the conductivity types can also be selected in the reverse relationship, with the first conductivity type being n-type and the second conductivity type being p-type. In addition, the “+” and “-” marked for “n” and “p” refer to semiconductor regions with relatively high or low impurity concentrations compared to the semiconductor regions without the “+” and “-” attached. However, even for semiconductor regions marked with the same “n” and “n”, it does not mean that the impurity concentrations of each semiconductor region are strictly the same. Also, in the following description, for components and regions with the limitations of “first conductivity type” and “second conductivity type” applied, even without specific explicit limitations, they refer to components and regions made of semiconductor materials.

[0039] (First Embodiment)

[0040] <Circuit of Semiconductor Device>

[0041] As the semiconductor device according to the first embodiment, as Figure 1 shown, a high-voltage integrated circuit (HVIC) 100 is illustrated. The HVIC 100 drives, for example, a power conversion unit 200 that is one phase of a power conversion bridge circuit as a driving object. The power conversion unit 200 forms a half-bridge circuit by connecting a high-potential side switching element T3 and a low-potential side switching element T4 in series. In Figure 1 , as the high-potential side switching element T3 and the low-potential side switching element T4, an IGBT is illustrated, but other power switching elements such as a metal-oxide semiconductor field-effect transistor (MOSFET) can also be used.

[0042] The collector of the high-potential side switching element T3 is connected to the high-potential side HV potential. The emitter of the low-potential side switching element T4 is connected to the low-potential side ground potential (GND potential). The connection point (midpoint of the half-bridge circuit) 105 between the emitter of the high-potential side switching element T3 and the collector of the low-potential side switching element T4 is connected to the VS potential on the negative side of the high-potential side power supply (high-potential side power supply) 104. And the connection point 105 is connected to a load such as a motor (not shown).

[0043] The HVIC 100 applies a drive signal for turning on and off the gate of the high-potential side switching element T3 to the gate of the high-potential side switching element T3 according to an input signal IN from an external microcomputer or the like. The HVIC 100 includes a low-potential side circuit (low side circuit) 101 and a high-potential side circuit (high side circuit) 102. The low side circuit 101 is connected to the VCC potential on the positive side of the low-potential side power supply (low-potential side power supply) 103 and the GND potential on the negative side of the low-potential side power supply 103. And the low side circuit 101 is connected to the gates of the level conversion elements (level converters) T1, T2.

[0044] The low-side circuit 101 operates with the GND potential as the reference potential and the VCC potential higher than the GND potential as the power supply potential. The low-side circuit 101 generates an on / off signal with the GND potential as the reference based on an input signal IN from an external microcomputer or the like and outputs it to the gates of the level converters T1 and T2.

[0045] The level converters T1 and T2 perform signal transfer between the low-side circuit 101 and the high-side circuit 102. The level converters T1 and T2 convert the on / off signal with the GND potential as the reference from the low-side circuit 101 into an on / off signal with the VS potential as the reference and output the converted on / off signal to the high-side circuit 102. The level converters T1 and T2 are composed of, for example, high-voltage-resistant n-channel MOSFETs.

[0046] The source of the level converter T1 is connected to the GND potential. The drain of the level converter T1 is connected to one end of the high-side circuit 102 and the level conversion resistor R1. The other end of the level conversion resistor R1 is connected to the VB potential on the positive electrode side of the high-potential-side power supply 104. The drain of the level converter T1 and one end of the level conversion resistor R1 are connected to the cathode of the diode D1. The anode of the diode D1 is connected to the VS potential on the negative electrode side of the high-side circuit 102 and the high-potential-side power supply 104. The diode D1 has the function of preventing the drain potential of the level converter T1 from dropping excessively.

[0047] The source of the level converter T2 is connected to the GND potential. The drain of the level converter T2 is connected to one end of the high-side circuit 102 and the level conversion resistor R2. The other end of the level conversion resistor R2 is connected to the VB potential on the positive electrode side of the high-potential-side power supply 104. The drain of the level converter T2 and one end of the level conversion resistor R2 are connected to the cathode of the diode D2. The anode of the diode D2 is connected to the VS potential on the negative electrode side of the high-side circuit 102 and the high-potential-side power supply 104. The diode D2 has the function of preventing the drain potential of the level converter T2 from dropping excessively.

[0048] The other ends of the level conversion resistors R1 and R2 and the VB potential on the positive electrode side of the high-potential-side power supply 104 are connected to the cathode of a high-voltage-resistant diode D0 called a high-voltage junction terminal (HVJT). The anode of the diode D0 is connected to the GND potential.

[0049] The high-side circuit 102 operates with the VS potential as the reference potential and the VB potential, which is higher than the VS potential, as the power supply potential. The high-side circuit 102 outputs a drive signal referenced to the VS potential to the gate of the high-potential side switching element T3 according to the on / off signals from the level converters T1 and T2, to drive the gate of the high-potential side switching element T3. The high-side circuit 102 includes, for example, a CMOS circuit with an n-channel MOSFET and a p-channel MOSFET in the output stage.

[0050] The VB potential is the highest potential applied to the HVIC 100 and remains approximately 15 V higher than the VS potential in the normal state without being affected by noise. Through the complementary on / off of the high-potential side switching element T3 and the low-potential side switching element T4, the VS potential repeats rising and falling between the HV potential (e.g., around 400 V to 600 V) on the high-potential side and the GND potential on the low-potential side, varying between 0 V and several hundred volts. In addition, the VS potential may sometimes become a negative potential.

[0051] <Structure of the semiconductor device>

[0052] Figure 2 Shows Figure 1 the planar layout of the semiconductor device according to the first embodiment corresponding to the HVIC 100 shown. The HVIC 100 includes a substrate (semiconductor chip) 1 of the first conductivity type (p - -type). The substrate 1 is composed of, for example, a silicon (Si) substrate. In addition, the substrate 1 may also be composed of semiconductor substrates such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenide (GaAs), diamond (C), etc. The substrate 1 may also be composed of a semiconductor substrate of the p - -type or the like and a p - -type epitaxial layer provided on the semiconductor substrate. The lower surface of the substrate 1 may be fixed at the GND potential.

[0053] A well region (first well region) 2 of the second conductivity type (n-type) is provided on the upper part of the substrate 1. The well region 2 has a substantially rectangular planar pattern. A high-side circuit (high-side circuit region) 102 is formed in the well region 2. In Figure 2 it, the illustration of various elements included in the high-side circuit 102 is omitted.

[0054] A pick-up region (contact region) 2a of the second conductivity type (n + -type) with an impurity concentration higher than that of the well region 2 is provided on the upper part of the well region 2. In Figure 2In this case, an example is shown where the contact region 2a is provided in a ring shape along the outer periphery of the well region 2. The contact region 2a does not necessarily have to be in a ring shape. For example, one or more contact regions may be provided locally. The contact region 2a may not be provided on the upper part of the well region 2, but may be provided on the upper part of the portion of the n - type breakdown voltage region (first breakdown voltage region) 8 that is connected to the well region 2 and is located on the outer peripheral side of the well region 2. The well region 2 is applied with the power supply potential, i.e., the VB potential, of the high-side circuit 102 via the contact region 2a.

[0055] A p-type well region (second well region) 7 is provided on the upper part of the well region 2. The well region 7 has a substantially rectangular planar pattern. In Figure 2 the top view, an example of being provided on the lower left side of the well region 2 is shown, but as long as it is inside the well region 2, there is no particular limitation on the arrangement position of the well region 7. There is no particular limitation on the size of the well region 7. A plurality of well regions 7 may also be provided on the upper part of the well region 2. The well region 7 is applied with the reference potential, i.e., the VS potential, of the high-side circuit 102.

[0056] A p-type slit region 6 is provided between the contact region 2a on the upper part of the well region 2 and the well region 7. In Figure 2 the top view, the slit region 6 has a substantially L-shaped planar pattern. The slit region 6 is locally provided between the two sides of the well region 7 that are closer to the contact region 2a and the contact region 2a. By locally providing the slit region 6, the area required for providing the slit region 6 can be reduced compared to the case where the slit region 6 is provided in a ring shape. The distance between the slit region 6 and the well region 7, the distance between the slit region 6 and the contact region 2a, and the width of the slit region 6 can be appropriately adjusted.

[0057] In addition, the slit region 6 may be locally provided in a substantially linear (strip-shaped) planar pattern between the side of the well region 7 that is closest to the contact region 2a and the contact region 2a. The slit region 6 may also be provided in a ring shape so as to surround the well region 7 and the high-side circuit 102. In the case where there are a plurality of well regions 7, one or more p-type slit regions 6 may be provided between the plurality of well regions 7 and the contact region 2a.

[0058] The slit region 6 is connected to the well region 7 via the resistor R11. The slit region 6 is applied with the reference potential, i.e., the VS potential, of the high-side circuit 102 via the resistor R11. The resistance value of the resistor R11 is, for example, about 10 Ω or more and 1 kΩ or less, but is not limited thereto. The resistor R11 is, for example, composed of a polysilicon resistor. The resistor R11 may also be a diffusion resistor.

[0059] An n-type impurity concentration lower than that of the well region 2 is provided in contact with the well region 2 so as to surround the periphery of the well region 2. -The high-voltage resistant region 8 of the [type]. The high-voltage resistant region 8 is annular, and the outer shape of the high-voltage resistant region 8 has a substantially rectangular planar pattern. A p-type high-voltage resistant region (second high-voltage resistant region) 3 is provided at a prescribed distance from the well region 2. The high-voltage resistant region 3 is annular, and the outer shape of the high-voltage resistant region 3 has a substantially rectangular planar pattern. The high-voltage resistant region 3 is applied with a GND potential. The outer periphery of the high-voltage resistant region 3 is surrounded by the substrate 1.

[0060] The pn junction composed of the high-voltage resistant region 8 and the high-voltage resistant region 3 forms a high-voltage resistant junction terminal (HVJT) (3, 8). The HVJT (3, 8) corresponds to Figure 1 the high-voltage resistant diode D0 shown. The HVJT (3, 8) is substantially annular, and the outer shape of the HVJT (3, 8) has a substantially rectangular planar pattern. The HVJT (3, 8) electrically separates the well region 2 on the inner peripheral side of the high-voltage resistant region 8 from the low-side circuit (low-side circuit region) 101 of the substrate 1 formed on the outer peripheral side of the high-voltage resistant region 8. Through the HVJT (3, 8), even when the potential of the high-side circuit 102 becomes several hundreds of V higher than the potential of the low-side circuit 101, normal operation will be carried out.

[0061] In a part of the HVJT (3, 8) composed of an n - type high-voltage resistant region 8 and a p-type high-voltage resistant region 3, level converters 10a, 10b are integrally formed. The level converters 10a, 10b are composed of high-voltage resistant n-channel MOSFETs. The level converters 10a, 10b correspond to Figure 1 the level converters T1, T2 shown.

[0062] Here, regarding the formation method of the MOSFETs constituting Figure 1 the level converters T1, T2 shown, roughly speaking, there are two types. One method is called the wire bonding method (WB method), and the other method is called the self-shielding method (SS method). The WB method is the following method: MOSFETs are formed separately outside the HVJT (3, 8), and the drain potential (Dr potential) of the MOSFETs is connected to the high-side circuit 102 through bonding wires. The SS method is the following method: MOSFETs are integrally formed with the HVJT (3, 8). In the semiconductor device according to the first embodiment, the case where the level converters 10a, 10b are formed by the SS method is illustrated.

[0063] The level shifters 10a and 10b are respectively disposed on the opposite sides of the rectangle formed by the planar pattern of the HVJT (3, 8). The planar patterns of the well region 2 and the contact region 2a have recessed portions recessed inwardly so as to surround a part of the level shifters 10a and 10b. In addition, the positions of the level shifters 10a and 10b are not particularly limited. For example, both the level shifters 10a and 10b may be disposed on one side of the rectangle formed by the planar pattern of the HVJT (3, 8). The level shifters 10a and 10b are electrically separated from the well region 2 by p - -type isolation regions 5a and 5b provided in the breakdown voltage region 8. The isolation regions 5a and 5b have a U-shaped planar pattern so as to surround the peripheries of the level shifters 10a and 10b.

[0064] The level shifter 10a faces the well region 7 across the isolation regions 5a, the contact region 2a, and the slit region 6. The level shifter 10a includes an n + -type carrier supply region (source region) 11a, a gate electrode 12a, and an n + -type carrier receiving region (drain region) 13a. The source region 11a, the gate electrode 12a, and the drain region 13a have linear planar patterns extending parallel to each other. A part of the breakdown voltage region 8 sandwiched between the source region 11a and the drain region 13a constitutes the drift region 14a of the level shifter 10a. The source region 11a is applied with a GND potential as the source potential (So potential). The drain region 13a is applied with a drain potential (Dr potential).

[0065] The level shifter 10b has the same structure as the level shifter 10a. That is, the level shifter 10b includes an n + -type source region 11b, a gate electrode 12b, and an n + -type drain region 13b. The source region 11b, the gate electrode 12b, and the drain region 13b have linear planar patterns extending parallel to each other. A part of the breakdown voltage region 8 sandwiched between the source region 11b and the drain region 13b constitutes the drift region 14b of the level shifter 10b. The source region 11b is applied with a GND potential as the source potential (So potential). The drain region 13b is applied with a drain potential (Dr potential).

[0066] Figure 3 Shows a cross section obtained by cutting along the A-A' line passing through the level shifter 10a, the isolation region 5a, the slit region 6, the well region 7, etc. As shown on the right side from the center in Figure 2 , an n-type well region 2 is provided on the upper part of the p Figure 3 -type substrate 1. An n - -type region having an impurity concentration higher than that of the well region 2 is provided on the upper part of the well region 2. In the well region 2, an n +The pick-up area (contact area) 2a of the type. The contact area 2a is applied with the VB potential.

[0067] On the upper part of the well region 2, a p-type well region 7 is provided separately from the contact area 2a. On the upper part of the well region 7, a p-type + pick-up area (contact area) 7a having an impurity concentration higher than that of the well region 7 is provided. The contact area 7a is applied with the VS potential. In addition, in Figure 2 the illustration of the contact area 7a shown is omitted. The planar pattern shape of the contact area 7a is not particularly limited. Figure 3 The planar pattern shape of the contact area 7a is not particularly limited.

[0068] A p-type slit region 6 is provided between the contact area 2a on the upper part of the well region 2 and the well region 7. The slit region 6 can be formed, for example, in the same process as the well region 7. By forming the slit region 6 and the well region 7 in the same process, an increase in the man-hours for forming the slit region 6 can be suppressed. The depth of the slit region 6 is substantially the same as the depth of the well region 7. The impurity concentration of the slit region 6 is substantially the same as the impurity concentration of the well region 7 and is higher than the impurity concentration of the substrate 1.

[0069] The slit region 6 can also be formed in a different process from the well region 7. In the case where the slit region 6 and the well region 7 are formed in different processes, the depth of the slit region 6 can be substantially the same as the depth of the well region 7, can be deeper than the depth of the well region 7, or can be shallower than the depth of the well region 7. In the case where the slit region 6 and the well region 7 are formed in different processes, the impurity concentration of the slit region 6 can be substantially the same as the impurity concentration of the well region 7, can be higher than the impurity concentration of the well region 7, or can be lower than the impurity concentration of the well region 7.

[0070] By deepening the depth of the slit region 6, the well region 2, which is the main noise current path, can be reduced, so that the noise tolerance can be improved. In the case where there is no buried layer 13 below the slit region 6, if the depletion layer extending from the interface between the n-type well region 7 and the p - type substrate 1 reaches the bottom surface of the slit region 6, the breakdown voltage decreases. Therefore, the depth of the slit region 6 is adjusted to such an extent that the depletion layer does not reach the bottom surface of the slit region 6. On the other hand, in the case where there is a buried layer 13 below the slit region 6, the depletion layer is not easily extended toward the buried layer 13 side. Therefore, the deeper the depth of the slit region 6, the more preferable.

[0071] As will be described later, the slit region 6 may operate as a noise current source (see Figure 8 and Figure 10 ) and as a destination for absorbing noise current (see Figure 12) The operating conditions. When the slit region 6 operates as a noise current source, the noise tolerance can be improved by reducing the impurity concentration in the slit region 6. On the other hand, when the slit region 6 operates as a destination for absorbing noise current, the noise tolerance can be improved by increasing the impurity concentration in the slit region 6.

[0072] An upper portion of the slit region 6 is provided with a p + -type pickup region (contact region) 6a having an impurity concentration higher than that of the slit region 6. The contact region 6a is connected to the contact region 7a via a resistor R11. Alternatively, the contact region 6a may be connected to the VS potential via the resistor R11 without passing through the contact region 7a. In addition, Figure 2 the illustration of Figure 3 the contact region 6a shown is omitted. The planar pattern shape of the contact region 6a is not particularly limited. The resistor R11 is formed of, for example, a polysilicon resistor. The resistor R11 may also be formed of a diffused resistor.

[0073] Figure 4 Shows a cross-section of a region including the polysilicon resistor 35 when the resistor R11 shown in Figure 3 is the polysilicon resistor 35. An insulating film 31 is provided on the upper surfaces of the well region 2, the slit region 6, and the well region 7. A polysilicon resistor 35 is provided on the upper surface of the insulating film 31. The polysilicon resistor 35 is composed of polysilicon with a high concentration of p-type or n-type impurities added. An insulating film 32 is provided so as to cover the upper surface, the upper surface, and the side surfaces of the polysilicon resistor 35 of the insulating film 31. Metal wiring layers 33 and 34 are provided on the upper surface of the insulating film 32. The metal wiring layer 33 connects the contact region 7a to one end of the polysilicon resistor 35 via openings (contact holes) provided in the insulating films 31 and 32. The metal wiring layer 34 connects the contact region 6a to the other end of the polysilicon resistor 35 via openings (contact holes) provided in the insulating films 31 and 32.

[0074] As Figure 3 shown, below the well region 2, an n + -type buried layer 13 having an impurity concentration higher than that of the well region 2 is provided in contact with the lower surface of the well region 2. The buried layer 13 is provided uniformly in the horizontal direction along between the substrate 1 and the well region 2. The buried layer 13 has the following function: reducing the magnification of the pnp bipolar transistor formed by the p-type well region 7, the n-type well region 2, and the p - -type substrate 1 to reduce the amount of generated current. In Figure 3, the following case is exemplified: the slit region 6 is provided at a position overlapping with the end of the buried layer 13 in the horizontal direction and located above the buried layer 13 when viewed in the depth direction from the upper surface side or the lower surface side of the slit region 6. The slit region 6 may be provided at a position that is inside (on the well region 7 side) the end of the buried layer 13 and located above the buried layer 13, or may be provided at a position that is outside (on the contact region 2a side) the end of the buried layer 13 and has no buried layer 13 below it.

[0075] By setting the slit region 6 at a position overlapping with the end of the buried layer 13, or at a position inner than the end of the buried layer 13, since the slit region 6 is located above the buried layer 13, the well region 2 that becomes the main noise current path can be further reduced by the slit region 6 and the buried layer 13, compared with the case where there is no buried layer 13 below the slit region 6, and the noise tolerance can be further improved.

[0076] On the outer periphery of the well region 2 on the upper part of the substrate 1, n - The pressure-resistant region 8 is shallower than the depth of the well region 2. A p-type pressure-resistant region 8 is provided on the upper part of the substrate 1 so as to penetrate the pressure-resistant region 8 in the depth direction. - The separation region 5a is deeper than the pressure-resistant region 8. The impurity concentration of the separation region 5a is higher than the impurity concentration of the substrate 1.

[0077] The level converter 10a is electrically isolated from the well region 2 by the isolation region 5a. A portion of the voltage-resistant region 8 surrounded by the isolation region 5a serves as the n of the level converter 10a. - The drift region 14a of the type functions. An n + The voltage-resistant region 3 connected to the drift region 14a functions as a p-type base region of the level converter 10a. An n-type + Type source region 11a and p + The gate electrode 12a is provided above a portion of the voltage-resistant region 3 sandwiched between the source region 11a and the drift region 14a via a gate insulating film (not shown). Figure 2 The cross-sectional structure of the level converter 10b shown in FIG. Figure 3 The cross-sectional structure of the level converter 10a shown is the same.

[0078] Figure 5 Shown with Figure 2 The cross section is obtained by cutting the BB' line perpendicular to the AA' line. - An n-type well region 2 is provided on the upper part of the substrate 1. An n-type well region 2 having an impurity concentration higher than that of the well region 2 is provided on the upper part of the well region 2. +The contact area 2a of the type. The VB potential is applied to the contact area 2a.

[0079] In the upper part of the well region 2, a p-type well region 7 is provided separately from the contact area 2a. In the upper part of the well region 7, a p + type contact area 7a with an impurity concentration higher than that of the well region 7 is provided. The VS potential is applied to the contact area 7a.

[0080] A p-type slit region 6 is provided between the contact area 2a in the upper part of the well region 2 and the well region 7. In the upper part of the slit region 6, a p + type contact area 6a with an impurity concentration higher than that of the slit region 6 is provided. The contact area 6a is connected to the contact area 7a via the resistor R11.

[0081] In the upper part of the substrate 1, an n - type breakdown voltage region 8 is selectively provided in contact with the well region 2. In the upper part of the substrate 1, a p-type breakdown voltage region 3 is provided in contact with the breakdown voltage region 8 on the side opposite to the well region 2. In the upper part of the breakdown voltage region 3, a p + type contact area 4 is provided. The GND potential is applied to the contact area 4. The depletion layer extending from the pn junction of the breakdown voltage region 8 and the breakdown voltage region 3 is mainly extended to the breakdown voltage region 8 side, thereby maintaining the breakdown voltage.

[0082] Next, the effects of the semiconductor device according to the first embodiment will be described in comparison with the semiconductor device according to the comparative example. Figure 6 The planar layout of the semiconductor device according to the comparative example is shown. As Figure 6 shown, the difference between the semiconductor device according to the comparative example and Figure 2 the semiconductor device according to the first embodiment shown is that it does not have an n + type p-type slit region 6 between the contact area 2a and the p-type well region 7, and the resistor R11 connecting the slit region 6 and the well region 7.

[0083] When the HVIC is operating, the potential relationship of VB potential > VS potential, VS potential ≥ GND potential is maintained for use. However, when this potential relationship is disrupted due to noise or the like, parasitic operation is triggered, causing malfunction and damage. Hereinafter, three modes in the cases of the potential relationships of VS potential > VB potential and VB potential >> GND potential (VS potential > VB potential >> GND potential), VB potential < VS potential (VB potential < VS potential), and VB potential < GND potential (VB potential < GND potential) will be described.

[0084] <Regarding VS potential> VB potential >> GND potential >

[0085] Figure 7 Therefore Figure 6 The cross-sectional view of the semiconductor device according to the comparative example obtained by cutting along the line A-A' of Figure 7 is shown. As shown, in the semiconductor device according to the comparative example, when, for example, due to noise or the like, the VS potential suddenly rises and thus the potential relationship becomes VS potential > VB potential >> GND potential, the parasitic pnp bipolar transistor T11 formed by the p - -type substrate 1, the n-type well region 2, and the p-type well region 7 operates in a state where a high voltage is applied, and a large parasitic current I11 flows from the well region 7 toward the contact region 4 and the source region 11a, sometimes causing damage due to heat generation.

[0086] In contrast Figure 8 Therefore Figure 2 The cross-sectional view of the semiconductor device according to the first embodiment obtained by cutting along the line A-A' of Figure 8 is shown. As shown, in the semiconductor device according to the first embodiment, when the potential relationship becomes VS potential > VB potential >> GND potential, the parasitic currents I12 and I13 flow from the slit region 6 and the well region 7 connected to the VS potential toward the contact region 4 and the source region 11a. At this time, the parasitic current I12 from the slit region 6 is current-limited by the connected resistor R11, and the parasitic current I13 from the well region 7 is current-limited by the diffusion resistor R12 made highly resistive through the slit region 6, so damage can be suppressed.

[0087] <Regarding VB potential < VS potential>

[0088] Figure 9 Therefore Figure 6 The cross-sectional view of the semiconductor device according to the comparative example obtained by cutting along the line A-A' of Figure 9 is shown. As shown, in the semiconductor device according to the comparative example, when, for example, due to noise or the like, the VS potential suddenly rises and thus the potential relationship becomes VB potential < VS potential, the parasitic current I14 flows as a forward current in the parasitic diode D11 formed by the p-type well region 7 and the n-type well region 2, and this parasitic current I14 flows toward the contact region 2a. Therefore, carriers accumulate near the p - -type separation region 5a where electrical separation is performed, thereby reducing the separation function and sometimes causing malfunction.

[0089] In contrast, Figure 10 is a cross-sectional view of a semiconductor device according to a first embodiment obtained by cutting along line A-A' of Figure 2 . Parasitic currents I15 and I16 generated when the potential relationship is VB potential < VS potential are schematically shown by arrows. As Figure 10 shown, in the semiconductor device according to the first embodiment, when the potential relationship becomes VB potential < VS potential, a parasitic current I15, which is a forward current, flows in a parasitic diode D12 formed by a p-type slit region 6 and an n-type well region 2, and a parasitic current I16, which is a forward current, flows in a parasitic diode D13 formed by a p-type well region 7 and an n-type well region 2. The parasitic currents I15 and I16 flow from the slit region 6 and the well region 7 connected to the VS potential toward the contact region 2a of the outermost peripheral VB potential. At this time, the parasitic current I15 from the slit region 6 is current-limited by the connected resistor R11, and the parasitic current I16 from the well region 7 is current-limited by the diffusion resistor R13 that is made highly resistive through the slit region 6. Therefore, the carriers accumulated around the contact region 2a of the outermost peripheral VB potential are reduced, and malfunction can be suppressed.

[0090] <Regarding VB potential < GND potential>

[0091] Figure 11 is a cross-sectional view of a semiconductor device according to a comparative example obtained by cutting along line B-B' of Figure 6 . Parasitic currents I17 and I18 generated when the potential relationship is VB potential < GND potential are schematically shown by arrows. As Figure 11 shown, in the semiconductor device according to the comparative example, when, for example, due to noise or the like, the VB potential becomes lower than during normal operation and thus the potential relationship becomes VB potential < GND potential, parasitic currents I17 and I18, which are forward currents, flow in a parasitic diode D14 formed by a p-type breakdown voltage region 3 and an n - -type breakdown voltage region 8. A part of the parasitic currents I17 and I18, i.e., the parasitic current I17, flows toward the contact region 2a, and a part of the parasitic currents I17 and I18, i.e., the parasitic current I18, reaches the high-side circuit 102, whereby the logic circuit may malfunction.

[0092] In contrast, Figure 12 is a cross-sectional view of a semiconductor device according to the first embodiment obtained by cutting along line B-B' of Figure 2 . Parasitic currents I19, I20, and I21 generated when the potential relationship is VB potential < GND potential are schematically shown by arrows. As Figure 12As shown, in the semiconductor device according to the first embodiment, when the potential relationship is such that VB potential < GND potential, the parasitic current I19 as a part of the parasitic currents I19, I20, and I21 flowing in from the contact region 4 at the GND potential flows toward the contact region 2a, and the parasitic current I20 as a part of the parasitic currents I19, I20, and I21 flows toward the slit region 6. The parasitic current I21 as a part of the parasitic currents I19, I20, and I21 also attempts to flow toward the high-side circuit 102, but most of the carriers are absorbed by the slit region 6, and thus are suppressed from flowing into the high-side circuit 102, so that malfunction can be suppressed.

[0093] As described above, according to the semiconductor device involved in the first embodiment, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, thereby being able to improve tolerance to erroneous operation and damage when a potential relationship different from normal operation such as VS potential>VB potential>>GND potential, VB potential<VS potential, VB potential<GND potential, etc. is encountered due to noise, etc.

[0094] (Second Embodiment)

[0095] Figure 13 is a cross-sectional view of a semiconductor device according to a second embodiment, and Figure 3 The positions correspond to the cross-sectional view of the semiconductor device according to the first embodiment shown. Figure 14 is a cross-sectional view of a semiconductor device according to a second embodiment, and Figure 5 The positions correspond to the cross-sectional view of the semiconductor device according to the first embodiment shown.

[0096] like Figure 13 and Figure 14 As shown, the semiconductor device according to the second embodiment is Figure 3 and Figure 5 The semiconductor device according to the first embodiment shown in the figure is different in that no n-type well region 2 is provided below the n-type well region 2. + The lower surface of the well region 2 is connected to the p - The other structures of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, duplicate descriptions are omitted.

[0097] According to the semiconductor device according to the second embodiment, similarly to the semiconductor device according to the first embodiment, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, thereby improving the tolerance to malfunction and damage when the potential relationship different from the normal operation, such as VS potential > VB potential >> GND potential, VB potential < VS potential, and VB potential < GND potential, occurs due to noise or the like.

[0098] (Third Embodiment)

[0099] Figure 15 is a top view of the semiconductor device according to the third embodiment. As Figure 15 shown, the difference between the semiconductor device according to the third embodiment and Figure 2 the semiconductor device according to the first embodiment shown is that the p-type slit region 6 between the n + -type contact region 2a and the p-type well region 7 is provided in a ring shape. The slit region 6 is provided to surround the well region 7 and the high-side circuit 102. Other structures of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, so repeated descriptions are omitted.

[0100] According to the semiconductor device according to the third embodiment, similarly to the semiconductor device according to the first embodiment, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, thereby improving the tolerance to malfunction and damage when the potential relationship different from the normal operation, such as VS potential > VB potential >> GND potential, VB potential < VS potential, and VB potential < GND potential, occurs due to noise or the like. And, according to the semiconductor device according to the third embodiment, the slit region 6 is provided in a ring shape, thereby more reliably suppressing malfunction and damage when the potential relationship different from the normal operation occurs compared to the case where the slit region 6 is provided locally.

[0101] (Fourth Embodiment)

[0102] Figure 16 is a cross-sectional view of the semiconductor device according to the fourth embodiment, corresponding to the position of the cross-sectional view of the semiconductor device according to the first embodiment shown in Figure 3 . Figure 17 is a cross-sectional view of the semiconductor device according to the fourth embodiment, corresponding to the position of the cross-sectional view of the semiconductor device according to the first embodiment shown in Figure 5 .

[0103] As Figure 16 and Figure 17As shown, the semiconductor device according to the fourth embodiment is different from the semiconductor device according to the first embodiment shown in Figure 3 and Figure 5 in that the substrate 1 is composed of a p - -type semiconductor substrate 1a and a p - -type epitaxial layer 1b provided on the semiconductor substrate 1a. Other structures of the semiconductor device according to the fourth embodiment are the same as those of the semiconductor device according to the first embodiment, so repeated descriptions are omitted.

[0104] According to the semiconductor device according to the fourth embodiment, similar to the semiconductor device according to the first embodiment, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, thereby improving the tolerance to malfunction and damage when in a potential relationship different from the normal operation, such as VS potential > VB potential >> GND potential, VB potential < VS potential, VB potential < GND potential, etc. due to noise or the like.

[0105] (Fifth Embodiment)

[0106] Figure 18 is a top view of the semiconductor device according to the fifth embodiment. As Figure 18 shown, in the semiconductor device according to the fifth embodiment, the difference from the semiconductor device according to the first embodiment shown in Figure 2 is that the level converters 20a and 20b are formed by the WB method. The level converters 20a and 20b are provided outside the p-type breakdown voltage region 3. The level converters 20a and 20b have a substantially circular planar pattern. The level converters 20a and 20b are composed of high-voltage-resistant n-channel MOSFETs.

[0107] The level converter 20a includes an n + -type carrier supply region (source region) 22a, a gate electrode 23a, an n - -type drift region 24a, and an n + -type carrier receiving region (drain region) 25a. The source region 22a has an annular planar pattern. The drift region 24a is provided on the inner peripheral side of the source region 22a and has an annular planar pattern. The gate electrode 23a is provided above an annular p-type base region (not shown) sandwiched between the source region 22a and the drift region 24a with a gate insulating film (not shown) interposed therebetween. The drain region 25a is provided on the upper part of the drift region 24a and has a circular planar pattern.

[0108] A drain electrode 26a is provided on the upper part of the drain region 25a. The drain electrode 26a is connected to the pad 18a via a bonding wire 17a. A p+ The base region 21a of the type. The base region 21a has an annular planar pattern.

[0109] The level shifter 20b has the same structure as the level shifter 20a. The level shifter 20b includes an n + -type source region 22b, a gate electrode 23b, an n - -type drift region 24b, and an n + -type drain region 25b. The source region 22b has an annular planar pattern. The drift region 24b is disposed on the inner peripheral side of the source region 22b and has an annular planar pattern. The gate electrode 23b is disposed above an annular p-type base region (not shown) sandwiched between the source region 22b and the drift region 24b with a gate insulating film (not shown) interposed therebetween. The drain region 25b is disposed on the upper portion of the drift region 24b and has a circular planar pattern.

[0110] A drain electrode 26b is disposed on the upper portion of the drain region 25b. The drain electrode 26b is connected to the pad 18b via a bonding wire 17b. A p + -type base region 21b is disposed on the outer peripheral side of the source region 22b. The base region 21b has an annular planar pattern. Other structures of the semiconductor device according to the fifth embodiment are the same as those of the semiconductor device according to the first embodiment, and thus repeated descriptions are omitted.

[0111] According to the semiconductor device according to the fifth embodiment, similarly to the semiconductor device according to the first embodiment, a p-type slit region 6 connected to the VS potential via a resistor R11 is provided between the well region 7 connected to the VS potential and the contact region 2a of the VB potential, thereby improving the tolerance to malfunction and damage when in a potential relationship different from the normal operation, such as VS potential > VB potential >> GND potential or VB potential < GND potential due to noise or the like. In addition, in the semiconductor device according to the fifth embodiment, the level shifters 20a and 20b are formed by the WB method, so the malfunction in the case of a potential relationship where VB potential < VS potential in the SS method does not become a problem.

[0112] (Other Embodiments)

[0113] As described above, the present invention has been described by the first embodiment to the fifth embodiment, but it should not be understood that the discussions and drawings forming a part of this disclosure are used to limit the present invention. According to this disclosure, those skilled in the art will clearly understand various alternative embodiments, examples, and application techniques.

[0114] For example, as the semiconductor device according to the first to fifth embodiments, a structure having a high-side circuit 102 of one phase is illustrated, but it is not limited thereto. For example, it may also be a structure having a high-side circuit of three phases. In the case of a structure having a high-side circuit of three phases, a p-type slit region connected to the VS potential via a resistor may be provided between the p-type well region connected to the VS potential and the p-type contact region of the VB potential in each of the high-side circuits of the three phases. + Moreover, the structures disclosed in the first to fifth embodiments can be appropriately combined within a range where no contradiction occurs. Needless to say, the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention features related to the claims that are appropriate based on the above description.

[0115] In addition, the structures disclosed in the first to fifth embodiments can be appropriately combined within a range where no contradiction occurs. It goes without saying that the present invention includes various embodiments not described herein. Thus, the technical scope of the present invention is defined only by the invention features related to the claims that are appropriate based on the above description.

[0116] Description of Reference Numerals

[0117] 1: Substrate (semiconductor chip); 1a: Semiconductor substrate; 1b: Epitaxial layer; 2: Well region; 2a: Contact region; 3: Breakdown voltage region; 5a: Isolation region; 6: Slit region; 6a: Contact region; 7: Well region; 7a: Contact region; 8: Breakdown voltage region; 10a, 10b: Level shifters; 11a, 11b: Source regions; 12a, 12b: Gate electrodes; 13: Buried layer; 13a, 13b: Drain regions; 14a, 14b: Drift regions; 17a, 17b: Bonding wires; 18a, 18b: Bond pads; 20a, 20b: Level shifters; 21a, 21b: Base regions; 22a, 22b: Source regions; 23a, 23b: Gate electrodes; 24a, 24b: Drift regions; 25a, 25b: Drain regions; 26a, 26b: Drain electrodes; 31, 32: Insulating films; 33, 34: Metal wiring layers; 35: Polysilicon resistor; 101: Low-side circuit; 102: High-side circuit; 103: Low-potential side power supply; 104: High-potential side power supply; 105: Connection point; 100: High-voltage integrated circuit (HVIC); 200: Power conversion unit; D0, D1, D2: Diodes; D11 to D14: Parasitic diodes; I11 to I21: Parasitic currents; R1, R2: Level conversion resistors; R11: Resistor; R12, R13: Diffusion resistors; T1, T2: Level shifters; T11: Parasitic pnp bipolar transistor; T3: High-potential side switching element; T4: Low-potential side switching element.

Claims

1. A semiconductor device comprising: A substrate of a first conductivity type; A first well region of a second conductivity type, which is disposed in the substrate, and a high-side circuit is formed in the first well region; A second well region of the first conductivity type, which is disposed on an upper portion of the first well region; A first voltage-sustaining region of a second conductivity type is arranged around the first well region, and the impurity concentration of the first voltage-sustaining region is lower than the impurity concentration of the first well region; A contact region of the second conductivity type, which is disposed on the first well region or the first voltage-resistant region, and the impurity concentration of the contact region is higher than the impurity concentration of the first well region; A slit region of the first conductivity type, which is disposed between the second well region and the contact region on the upper portion of the first well region, and the slit region is connected to the second well region via a resistor; A second voltage-resistant region of the first conductivity type, which is in contact with the first voltage-resistant region and is disposed on the outer peripheral side of the first voltage-resistant region; as well as A level converter performs signal transmission between a low-side circuit formed on the outer peripheral side of the second voltage-withstanding region and the high-side circuit.

2. The semiconductor device according to claim 1, wherein The level converter is disposed in a portion of the first voltage-resistant region and the second voltage-resistant region.

3. The semiconductor device according to claim 2, wherein: A separation region of the first conductivity type is further provided to separate the level shifter from the first well region.

4. The semiconductor device according to claim 2 or 3, wherein: The slit region is disposed between the level converter and the second well region.

5. The semiconductor device according to claim 2 or 3, wherein: A carrier receiving region of the level converter is arranged on the upper part of the first voltage-sustaining region. A carrier supply region of the level converter is provided on the upper portion of the second voltage-resistant region.

6. The semiconductor device according to claim 1, wherein The level converter is provided on an outer peripheral side of the second voltage-resistant region.

7. The semiconductor device according to claim 1 or 2, wherein: A buried layer of the second conductivity type is further provided, the buried layer being provided below the first well region, and the impurity concentration of the buried layer being higher than the impurity concentration of the first well region.

8. The semiconductor device according to claim 7, wherein: The slit region is provided at a position overlapping with an end of the buried layer in a horizontal direction and located above the buried layer when viewed in a depth direction from an upper surface side or a lower surface side of the slit region.

9. The semiconductor device according to claim 1 or 2, wherein: The slit region is selectively disposed between the second well region and the contact region.

10. The semiconductor device according to claim 1 or 2, wherein: The slit region is provided in a ring shape in such a manner as to surround the second well region and the high-side circuit.

11. The semiconductor device according to claim 1 or 2, wherein: The depth of the slit region is the same as the depth of the second well region.

12. The semiconductor device according to claim 1 or 2, wherein: The impurity concentration of the slit region is the same as the impurity concentration of the second well region.

13. The semiconductor device according to claim 1 or 2, wherein: The resistor is a polysilicon resistor.

14. The semiconductor device according to claim 1 or 2, wherein: A first potential is applied to the contact region, A second potential lower than the first potential is applied to the second well region, The second potential is applied to the slit region via the resistor.

Images