Quick-opening type high-maintaining-voltage bidirectional SCR device for electrostatic protection of high-voltage integrated circuit
By optimizing the design of the conduction path and shunt path, the problems of slow conduction speed and low maintenance voltage of the bidirectional SCR structure are solved, and efficient electrostatic protection is achieved.
Patent Information
- Application Number
- CN202510326799.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-06-17
AI Technical Summary
The existing bidirectional SCR structure has a slow conduction speed and maintains a low voltage, which cannot effectively provide electrostatic protection.
By optimizing the conduction path and shunt path, a fast-open type high-sustaining voltage bidirectional SCR device is designed, and a multi-layer doping region and parasitic transistor structure is used to form a low-resistance conduction path and a high-injection efficiency shunt path.
Faster turn-on speed and higher maintenance voltage are achieved, improving the effectiveness of electrostatic protection.
Smart Images
Figure CN120166772A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of design of electrostatic discharge protection devices for high-voltage integrated circuits, and specifically relates to the structural design of an ESD protection device, particularly a Dual-Directional Silicon Controlled Rectifier (DDSCR). Background Art
[0002] Electrostatic Discharge (ESD) refers to the process in which a conductive path is formed between two objects with different electric potentials and charge transfer occurs when the induced electric field strength between them is greater than the dielectric breakdown electric field between the two objects. ESD has the characteristics of being concealed, latent, random, and complex in damaging integrated circuits. With the development of semiconductor process technology, IC failures and damages caused by it have become an increasingly serious problem. As one of the mainstream protection devices, electrostatic protection devices play an important role in electrostatic protection of circuits and chips. Classified by protection type, electrostatic protection devices can be divided into bidirectional and unidirectional protection devices. Unidirectional protection devices only have unilateral blocking ability, while bidirectional protection devices have bidirectional blocking ability. For situations where there are positive and negative voltages at some ports, it is necessary to select bidirectional protection devices for ESD protection.
[0003] Dual-Directional Silicon Controlled Rectifier (DDSCR) is a type of commonly used bidirectional protection ESD protection device, which has advantages such as small off-state leakage current, high area utilization rate, and high robustness. Therefore, DDSCR and its improved structures are widely used in the field of integrated circuit ESD protection design.
[0004] With the continuous evolution of the integrated circuit process node, the integration degree of the chip is getting higher and higher, but the breakdown voltage of its transistors is continuously decreasing. For fast discharge events, such as LEC discharge and CDM (charge device model) discharge, the discharge pulse is usually about 1 ns. At this time, to provide reliable electrostatic protection for the protected circuit, it is required that the electrostatic protection device has a fast enough turn-on response speed. For DDSCR devices, its turn-on speed is related to the base region lengths of two parasitic bipolar transistors and the resistance on the DDSCR trigger path: the shorter the base region lengths of the two bipolar transistors, the shorter the carrier transit time, and at the same time the positive feedback establishment time is also shortened; the larger the trigger path resistance, the larger the current injected into the bipolar transistor, and at the same time the positive feedback establishment time is also shortened, making the device turn on and conduct faster.
[0005] With the application of high supply voltage, the latch-up effect inside the chip becomes more and more serious. The form of the latch-up effect is that the holding voltage of the SCR inside the chip is less than the supply voltage of the chip, making the SCR path unable to be turned off once established. Then, through the long-term large-current discharge, the chip is damaged. Therefore, to use SCR to provide electrostatic protection, it is required that the holding voltage of the SCR device is greater than the supply voltage. For the DDSCR device, its holding voltage is related to the gains of two parasitic bipolar transistors and the current intensity on the SCR path; the higher the gains of the two bipolar transistors, the stronger the conductance modulation phenomenon, and the lower the holding voltage of the SCR; similarly, the higher the current intensity injected into the two bipolar transistors, the stronger the conductance modulation phenomenon, and the lower the holding voltage of the SCR.
[0006] Figure 1 (a) and Figure 1 (b) respectively show a typical bidirectional SCR structure and circuit diagram. As Figure 1 (a) and Figure 1 (b) show, a P-well resistor R is connected in series on both the forward and reverse conduction paths. PW The ESD discharge path is relatively long, so the SCR conduction speed is usually poor; at the same time, the ESD currents of this structure all flow into the SCR path, making the current on the SCR path relatively large and the holding voltage relatively low as well.
[0007] In summary, for the existing bidirectional SCR structure, the conduction speed is usually slow and the holding voltage is low, and it cannot provide effective clamping ability for electrostatic protection. Therefore, for the bidirectional SCR structure, how to improve the holding voltage while optimizing the conduction speed is worthy of research. Summary of the Invention
[0008] To solve the problems of the existing bidirectional SCR structure, which usually has a slow conduction speed and a low holding voltage, the present invention provides a fast-turn-on type high-holding voltage bidirectional SCR device for electrostatic protection of high-voltage integrated circuits, which realizes a faster turn-on speed and holding voltage by optimizing the conduction path and the shunt path.
[0009] The technical solution adopted by the present invention is as follows: A fast-turn-on type high-holding voltage bidirectional SCR device for electrostatic protection of high-voltage integrated circuits, comprising: The device includes a P-type silicon substrate, on which a first N-type doped region is formed; a second N-type doped region, a first P-type doped region, a third N-type doped region, a second P-type doped region, and a fourth N-type doped region are formed on the first N-type doped region; the first P-type doped region is completely surrounded by the first N-type doped region, the second N-type doped region, and the third N-type doped region; the second P-type doped region is completely surrounded by the first N-type doped region, the third N-type doped region, and the fourth N-type doped region.
[0010] A first P-type heavily doped region is formed on the second N-type doped region; a first N-type heavily doped region spanning across the two regions is formed between the second N-type doped region and the first P-type doped region; in the first P-type doped region, a second P-type heavily doped region and a second N-type heavily doped region are sequentially arranged from far to near with the first P-type heavily doped region as a reference; a third N-type heavily doped region spanning across the two regions is formed between the first P-type doped region and the third N-type doped region; a fourth N-type heavily doped region spanning across the two regions is formed between the third N-type doped region and the second P-type doped region; in the second P-type doped region, a fifth N-type heavily doped region and a third P-type heavily doped region are sequentially arranged from far to near with the fourth N-type heavily doped region as a reference; a sixth N-type heavily doped region spanning across the two regions is formed between the second P-type doped region and the fourth N-type doped region; a fourth P-type heavily doped region is formed on the fourth N-type doped region. The second P-type heavily doped region, the second N-type heavily doped region are connected to port T1; the fifth N-type heavily doped region, the third P-type heavily doped region are connected to port T2; the first P-type heavily doped region, the sixth N-type heavily doped region are interconnected; the first N-type heavily doped region, the fourth P-type heavily doped region are interconnected.
[0011] Shallow trench isolations are respectively provided between the first P-type heavily doped region and the first N-type heavily doped region, between the first N-type heavily doped region and the second P-type heavily doped region, between the second P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the third N-type heavily doped region, between the third N-type heavily doped region and the fourth N-type heavily doped region, between the fourth N-type heavily doped region and the fifth N-type heavily doped region, between the fifth N-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the sixth N-type heavily doped region, and between the sixth N-type heavily doped region and the fourth P-type heavily doped region.
[0012] The first P-type doped region and the second P-type doped region are formed by longitudinally stacking one or more P-type doped regions with different doping doses; the first N-type doped region, the second N-type doped region, the third N-type doped region, and the fourth N-type doped region are formed by longitudinally stacking one or more N-type doped regions with different doping doses.
[0013] The device consists of three parasitic PNP transistors, two parasitic NPN transistors, and two parasitic well resistors: The first parasitic PNP transistor Q P1 , includes the second P-type heavily doped region, the first P-type doped region, the third N-type doped region, the third N-type heavily doped region, the fourth N-type heavily doped region, the second P-type doped region, and the third P-type heavily doped region; the second parasitic PNP transistor Q P2, including a first P-type heavily doped region, a second N-type doped region, a first N-type heavily doped region, a first P-type doped region, and a second P-type heavily doped region; the third parasitic PNP transistor Q P3 , including a fourth P-type heavily doped region, a fourth N-type doped region, a sixth N-type heavily doped region, a second P-type doped region, and a third P-type heavily doped region; the first parasitic NPN transistor Q N1 , including a second N-type heavily doped region, a first P-type doped region, a first N-type doped region, a third N-type doped region, and a third N-type heavily doped region; the second parasitic NPN transistor Q N2 , including a fifth N-type heavily doped region, a second P-type doped region, a first N-type doped region, a third N-type doped region, and a fourth N-type heavily doped region; the first parasitic well resistor R PW1 , including a first P-type doped region; the second parasitic well resistor R PW2 , including a second P-type doped region.
[0014] The present invention provides a fast-turn-on and high-holding-voltage bidirectional SCR device for electrostatic protection of high-voltage integrated circuits. The device not only inherits the characteristics of high robustness, simple structure, and high area utilization rate of traditional DDSCR devices, but also has the advantages of high holding voltage and high turn-on speed. Compared with traditional DDSCR devices, the device has an additional trigger path. When a positive voltage reaches the T1 port, the main ESD trigger path of the device is the second parasitic PNP transistor Q P1 and the third PNP parasitic transistor Q P2 to form a trigger path of a diode series PNP. The low on-resistance and fast turn-on speed of this path improve the turn-on speed of the DDSCR device; the current passing through the trigger path is discharged by the SCR path formed by the first parasitic PNP transistor Q P1 and the second NPN transistor Q N2 for the main ESD current, and at the same time, a shunt path of a diode series PNP formed by the second parasitic PNP transistor Q P1 and the third PNP parasitic transistor Q P2 increases the holding voltage of the device. Description of the Drawings
[0015] Figure 1 (a) is a structural diagram of a traditional DDSCR device.
[0016] Figure 1 (b) is an equivalent circuit diagram of a traditional DDSCR device.
[0017] Figure 2 (a) and Figure 2 (b) are structural diagrams of the device DSTTDDSCR described in Example 1.
[0018] Figure 2 (c) is the equivalent circuit diagram of the device DSTTDDSCR described in Example 1. Detailed implementation manners
[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings and specific implementation manners. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
[0020] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.
[0021] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features.
[0022] In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.
[0023] Example 1:
[0024] This embodiment provides a fast-turn-on and high-holding-voltage bidirectional SCR device for electrostatic protection of high-voltage integrated circuits. The structure and equivalent circuit diagram of the device are as Figure 2 shown.
[0025] The device described in Example 1 includes a P-type silicon substrate 110, and a first N-type doped region 120 is formed on the P-type silicon substrate 110; a second N-type doped region 121, a first P-type doped region 131, a third N-type doped region 122, a second P-type doped region 132, and a fourth N-type doped region 123 are formed on the first N-type doped region 120; the first P-type doped region 132 is completely surrounded by the first N-type doped region 120, the second N-type doped region 121, and the third N-type doped region 122; the second P-type doped region 132 is completely surrounded by the first N-type doped region 120, the third N-type doped region 122, and the fourth N-type doped region 123.
[0026] A first P-type heavily doped region 140 is formed on the second N-type doped region 121; a first N-type heavily doped region 141 spanning the two regions is formed between the second N-type doped region 121 and the first P-type doped region 131; a second P-type heavily doped region 142 and a second N-type heavily doped region 143 are sequentially arranged in the first P-type doped region 131 from far to near with the first N-type heavily doped region 141 as a reference; a third N-type heavily doped region 144 spanning the two regions is formed between the first P-type doped region 131 and the third N-type doped region 122; a fourth N-type heavily doped region 145 spanning the two regions is formed between the third N-type doped region 122 and the second P-type doped region 132; a fifth N-type heavily doped region 146 and a third P-type heavily doped region 147 are sequentially arranged in the second P-type doped region 132 from far to near with the fourth N-type heavily doped region 145 as a reference; a sixth N-type heavily doped region 148 spanning the two regions is formed between the second P-type doped region 132 and the fourth N-type doped region 123; a fourth P-type heavily doped region 149 is formed on the fourth N-type doped region 123.
[0027] The second P-type heavily doped region 142 and the second N-type heavily doped region 143 are connected to the port T1; the fifth N-type heavily doped region 146 and the third P-type heavily doped region 147 are connected to the port T2; the first P-type heavily doped region 140 and the sixth N-type heavily doped region 148 are interconnected; the first N-type heavily doped region 141 and the fourth P-type heavily doped region 147 are interconnected.
[0028] Shallow trench isolations are respectively provided between the first P-type heavily doped region 140 and the first N-type heavily doped region 141, between the first N-type heavily doped region 141 and the second P-type heavily doped region 142, between the second P-type heavily doped region 142 and the second N-type heavily doped region 143, between the second N-type heavily doped region 143 and the third N-type heavily doped region 144, between the third N-type heavily doped region 144 and the fourth N-type heavily doped region 145, between the fourth N-type heavily doped region 145 and the fifth N-type heavily doped region 146, between the fifth N-type heavily doped region 146 and the third P-type heavily doped region 147, between the third P-type heavily doped region 147 and the sixth N-type heavily doped region 148, and between the sixth N-type heavily doped region 148 and the fourth P-type heavily doped region 149.
[0029] The first P-type doped region 131 and the second P-type doped region 132 are formed by longitudinally stacking one or more P-type doped regions with different doping doses; the first N-type doped region 120, the second N-type doped region 121, the third N-type doped region 122, and the fourth N-type doped region 123 are formed by longitudinally stacking one or more N-type doped regions with different doping doses; The device consists of three parasitic PNP transistors, two parasitic NPN transistors, and two parasitic well resistors: The first parasitic PNP transistor QP1 , including a second P-type heavily doped region 142, a first P-type doped region 131, a third N-type doped region 122, a third N-type heavily doped region 144, a fourth N-type heavily doped region 145, a second P-type doped region 132, and a third P-type heavily doped region 147; the second parasitic PNP transistor Q P2 , including a first P-type heavily doped region 140, a second N-type doped region 121, a first N-type heavily doped region 141, a first P-type doped region 131, and a second P-type heavily doped region 132; the third parasitic PNP transistor Q P3 , including a fourth P-type heavily doped region 149, a fourth N-type doped region 123, a sixth N-type heavily doped region 148, a second P-type doped region 132, and a third P-type heavily doped region 147; the first parasitic NPN transistor Q N1 , including a second N-type heavily doped region 143, a first P-type doped region 131, a first N-type doped region 120, a third N-type doped region 122, and a third N-type heavily doped region 144; the second parasitic NPN transistor Q N2 , including a fifth N-type heavily doped region 146, a second P-type doped region 132, a first N-type doped region 120, a third N-type doped region 122, and a fourth N-type heavily doped region 145; the first parasitic well resistance R PW1 , including a first P-type doped region 131; the second parasitic well resistance R PW2 , including a second P-type doped region 132.
[0030] The operating principle of the device described in Embodiment 1 can be divided into two types according to the ESD positive voltage reaching different ports T1 and T2: When an ESD positive voltage reaches port T1, as Figure 2 shown in (a), the ESD current first passes through the emitter diode of Q P2 to reach the base of Q P3 . When the ESD voltage is greater than the BV P3 (collector avalanche breakdown voltage) of Q CEO , the hole current flows from the collector of Q P3 to the T2 end of the device; as the breakdown current increases, the voltage drop of the second parasitic well resistance R PW2 is greater than the emitter conduction voltage of the second NPN transistor Q N2 , and Q P1 and Q N1 operate in the amplification region, forming a positive feedback path, and the SCR is turned on. When an ESD positive voltage reaches port T2, as Figure 2 shown in (b), the ESD current first passes through the emitter diode of Q P3 to reach the base of Q P2 . When the ESD voltage is greater than the BV P2 of Q CEOWhen (the collector avalanche breakdown voltage), the hole current flows from the collector of Q to the T2 terminal of the device; as the breakdown current increases, the voltage drop across R of the second parasitic well resistance is greater than the emitter conduction voltage of the second NPN transistor Q, and Q and Q operate in the amplification region, forming a positive feedback path, and the SCR is turned on. P2 The collector of P2 flows towards the T2 end of the device; as the breakdown current increases, the voltage drop across R of the second parasitic well resistance is greater than the emitter conduction voltage of the second NPN transistor Q PW1 and the emitter conduction voltage of the second NPN transistor Q N1 is greater than the emitter conduction voltage of the second NPN transistor Q P1 and Q N1 operate in the amplification region, forming a positive feedback path, and the SCR is turned on.
[0031] The device described in Embodiment 1 improves the turn-on speed, which is proportional to the resistance on the trigger path and the turn-on speed of the PNP. Due to the presence of parasitic PNP and parasitic NPN transistors in the SCR, when the SCR conducts, the PNP transistor needs to conduct first, and then a voltage drop is established through the well resistance to make the NPN transistor conduct. Improving the conduction speed of the PNP transistor and the magnitude of the current injected into the emitter of the NPN transistor can improve the turn-on speed of the device. The device forms a low-resistance PNP conduction path through the collector diodes of Q, Q and the PNP path, and at the same time, the starting speed of the transistors with high injection efficiency Q, Q is also better than that of Q, which improves the turn-on speed of the device. P2 、Q P3 The device described in Embodiment 1 improves the turn-on speed, which is proportional to the resistance on the trigger path and the turn-on speed of the PNP. Due to the presence of parasitic PNP and parasitic NPN transistors in the SCR, when the SCR conducts, the PNP transistor needs to conduct first, and then a voltage drop is established through the well resistance to make the NPN transistor conduct. Improving the conduction speed of the PNP transistor and the magnitude of the current injected into the emitter of the NPN transistor can improve the turn-on speed of the device. The device forms a low-resistance PNP conduction path through the collector diodes of Q, Q and the PNP path, and at the same time, the starting speed of the transistors with high injection efficiency Q, Q is also better than that of Q, which improves the turn-on speed of the device. P2 、Q P3 transistors is also better than that of Q P1 crystals, which improves the turn-on speed of the device.
[0032] The holding voltage of the device described in Embodiment 1 is proportional to the ratio of the current magnitude passing through the PNP channel to the current magnitude passing through the SCR channel. Due to the presence of parasitic PNP and parasitic NPN transistors in the SCR, when the SCR conducts, a positive feedback will be formed between the parasitic PNP and parasitic NPN transistors. This positive feedback effect enables the SCR to maintain the conduction state with a relatively small applied voltage, and the holding voltage of the SCR path is relatively low; while when the triode conducts, a relatively large applied voltage is required to make the emitter junction forward-biased and the collector junction reverse-biased to maintain the conduction state, and the holding voltage of the triode path is relatively high. Therefore, the regulation of the holding voltage can be achieved by changing the current in the auxiliary trigger path and the current in the SCR path, that is, mainly by connecting a Q and Q in parallel on the SCR path formed by Q and Q to realize the shunting of the SCR path, thereby reducing the current on the SCR path to increase the holding voltage of the device. P1 and Q N2 to form a Q and Q in parallel on the SCR path formed by Q and Q P2 and Q P3 transistors to realize the shunting of the SCR path, thereby reducing the current on the SCR path to increase the holding voltage of the device.
[0033] The above examples are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described with reference to the preferred examples, those of ordinary skill in the art should understand that any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or alternative features with similar purposes. All the features disclosed, or all the steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way without departing from the gist and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.
Claims
1. A fast-on, high-maintaining-voltage bidirectional SCR device for ESD protection of high-voltage integrated circuits, characterized in that: The device comprises a P-type silicon substrate, a first N-type doping region is formed on the P-type silicon substrate; a second N-type doping region, a first P-type doping region, a third N-type doping region, a second P-type doping region, and a fourth N-type doping region are formed on the first N-type doping region; the first P-type doping region is fully surrounded by the first N-type doping region, the second N-type doping region, and the third N-type doping region; the second P-type doping region is fully surrounded by the first N-type doping region, the third N-type doping region, and the fourth N-type doping region; A first P-type heavily doped region is formed on the second N-type doped region; a first N-type heavily doped region spanning the two regions is formed between the second N-type doped region and the first P-type doped region; a second P-type heavily doped region and a second N-type heavily doped region are sequentially arranged in the first P-type doped region from far to near with reference to the first P-type heavily doped region; a third N-type heavily doped region spanning the two regions is formed between the first P-type doped region and the third N-type doped region; a fourth N-type heavily doped region spanning the two regions is formed between the third N-type doped region and the second P-type doped region; a fifth N-type heavily doped region and a third P-type heavily doped region are sequentially arranged in the second P-type doped region from far to near with reference to the fourth N-type heavily doped region; a sixth N-type heavily doped region spanning the two regions is formed between the second P-type doped region and the fourth N-type doped region; a fourth P-type heavily doped region is formed on the fourth N-type doped region; The second P-type heavily doped region and the second N-type heavily doped region are connected to port T1; the fifth N-type heavily doped region and the third P-type heavily doped region are connected to port T2; the first P-type heavily doped region and the sixth N-type heavily doped region are interconnected; the first N-type heavily doped region and the fourth P-type heavily doped region are interconnected; Shallow trench isolation is respectively provided between the first P-type heavily doped region and the first N-type heavily doped region, between the first N-type heavily doped region and the second P-type heavily doped region, between the second P-type heavily doped region and the second N-type heavily doped region, between the second N-type heavily doped region and the third N-type heavily doped region, between the third N-type heavily doped region and the fourth N-type heavily doped region, between the fourth N-type heavily doped region and the fifth N-type heavily doped region, between the fifth N-type heavily doped region and the third P-type heavily doped region, between the third P-type heavily doped region and the sixth N-type heavily doped region, and between the sixth N-type heavily doped region and the fourth P-type heavily doped region.