Uncooled infrared detector, manufacturing method and alignment mark processing method

Abstract

The invention discloses an uncooled infrared detector, a manufacturing method and an alignment mark processing method, and the method comprises the steps: 1, providing an uncooled infrared detector to be subjected to alignment mark processing, and enabling the uncooled infrared detector to comprise a substrate and a first sacrificial layer used for forming a resonant cavity, a first type of alignment mark is formed on the first sacrificial layer in a cutting channel area of the substrate; step 2, etching is carried out in the cutting channel region until the surface of the first sacrificial layer; and 3, releasing the first sacrificial layer. According to the alignment mark processing method provided by the invention, the residual alignment mark in the cutting channel region is etched before the sacrificial layer is released, so that the problem that the alignment mark floats after the sacrificial layer is released and the normal use of the detector is influenced is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a non-cooled infrared detector, a manufacturing method, and an alignment mark processing method. Background Art

[0002] The basic working principle of a resistive non-cooled infrared detector is to convert the received infrared radiation of the observed target into a change in its own resistance value, and the infrared imaging system converts the change in the electrical signal into an image that can be visually distinguished by humans through a certain algorithm. In order to improve the infrared radiation absorption rate, the most widely used structure of the non-cooled infrared detector is a microbridge type design with a resonant cavity and a metal reflective layer.

[0003] When manufacturing a non-cooled infrared detector, it is necessary to deposit, etch, and release a sacrificial layer, and finally form a cavity inside the non-cooled infrared detector to form a resonant cavity structure. If the sacrificial layer is removed halfway through the process, due to the high steps of the sacrificial layer, it will cause abnormal glue coating and affect the yield of the detector. Therefore, the sacrificial layer on the wafer dicing lane needs to be released last. Therefore, all the processes after the sacrificial layer coating are carried out on this sacrificial layer. If the manufacturing process design is unreasonable, the alignment marks will remain on the sacrificial layer, and then when the detector removes the sacrificial layer by subsequent release, the remaining alignment marks will be in a suspended state, extremely easy to fall into the cavity, float on the detector, and affect the reliability of the detector. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides a non-cooled infrared detector, a manufacturing method, and an alignment mark processing method, which solve the problems that the alignment marks remain during the production process of the non-cooled infrared detector and float after release, affecting the normal use of the detector.

[0005] The present invention provides an alignment mark processing method for a non-cooled infrared detector, including the following steps:

[0006] Step 1: Provide a non-cooled infrared detector to be processed with alignment marks. The non-cooled infrared detector includes a substrate and a first sacrificial layer for forming a resonant cavity. A first type of alignment mark is formed on the first sacrificial layer in the dicing lane area of the substrate.

[0007] Step 2: Etch in the dicing lane area until the surface of the first sacrificial layer.

[0008] Step 3: Release the first sacrificial layer.

[0009] Further, the first type of alignment mark in Step 1 is a groove or a convex structure, and includes one or more of silicon nitride, vanadium oxide, titanium, and copper-aluminum alloy.

[0010] Further, Step 2 includes dividing the film layer where the first type of alignment mark is located into a top dielectric layer, a metal layer, and a bottom dielectric layer according to the film layer structure on the surface of the first sacrificial layer, and performing step-by-step etching.

[0011] Further, the step-by-step etching process includes:

[0012] Etching the first type of alignment mark on the top dielectric layer;

[0013] Etching the first type of alignment mark on the metal layer;

[0014] Etching the first type of alignment mark on the bottom dielectric layer.

[0015] Further, the alignment mark processing method further includes, when performing Step 2 and Step 3, performing component analysis on the film layer where the alignment mark is located after each etching to confirm the etching effect.

[0016] Further, the uncooled infrared detector to be processed with alignment marks further includes a second sacrificial layer for forming an umbrella layer suspension cavity. There are second type of alignment marks on the second sacrificial layer in the dicing channel area. Before performing Step 2, it is necessary to first etch and remove the second type of alignment marks to release the second sacrificial layer.

[0017] Optionally, the first sacrificial layer and the second sacrificial layer are made of polyimide material.

[0018] The present invention also provides a manufacturing method for an uncooled infrared detector, including the following steps:

[0019] Depositing the first sacrificial layer on the surface of the substrate;

[0020] Preparing a thermosensitive unit on the surface of the first sacrificial layer in the device area of the substrate, and a film layer including the first type of alignment mark is correspondingly formed in the dicing channel area of the substrate;

[0021] Using the alignment mark processing method described in any one of the above technical solutions to process the remaining alignment marks.

[0022] Optionally, the substrate includes an integrated circuit wafer, a reflective layer, and a passivation layer, and the passivation layer covers the surfaces of part of the integrated circuit wafer and the reflective layer.

[0023] The present invention also provides an uncooled infrared detector prepared by the above manufacturing method.

[0024] Advantages of the present invention:

[0025] A method for processing alignment marks of a non-cooled infrared detector provided by the present invention etches the alignment marks remaining in the scribing lane area before the release of the sacrificial layer, avoiding the problem that the alignment marks float after the release of the sacrificial layer and affect the normal use of the detector. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0027] Figure 1 is a sectional view change diagram of the device area during the manufacturing process of an existing non-cooled infrared detector;

[0028] Figure 2 is a sectional view change diagram of the scribing lane area during the manufacturing process of an existing non-cooled infrared detector;

[0029] Figure 3 is a flowchart of a method for processing alignment marks of a non-cooled infrared detector provided in Embodiment 1 of the present invention;

[0030] Figure 4 is a flowchart of a method for processing alignment marks of a non-cooled infrared detector provided in Embodiment 2 of the present invention;

[0031] Figure 5 is a sectional view change diagram of the device area during the manufacturing process of the non-cooled infrared detector in this Embodiment 2;

[0032] Figure 6 is a sectional view change diagram of the scribing lane area during the manufacturing process of the non-cooled infrared detector in this Embodiment 2;

[0033] Figure 7 is a schematic diagram of the electron energy spectrum analysis of the PAD area after the etching of the first type of marks in this Embodiment 2;

[0034] Figure 8 is a schematic diagram of the electron energy spectrum analysis of the PAD area after the etching of the medium in the PAD area in this Embodiment 2;

[0035] Figure 9 is a flowchart of a manufacturing method of a non-cooled infrared detector provided in Embodiment 3 of the present invention.

[0036] Reference Signs:

[0037] 11. Integrated circuit wafer; 12. Passivation layer; 13. Aluminum pad; 14. Reflective layer; 21. First sacrificial layer; 22. Dielectric layer; 23. Vanadium oxide layer; 24. Dielectric layer; 25. Dielectric layer; 26. Titanium metal layer; 27. Aluminum metal layer; 28. Dielectric layer; 31. Second sacrificial layer; 32. Umbrella-shaped absorption layer; 41. Dielectric layer of PAD test area; 42. Aluminum pad of PAD test area; 43. Photoresist. Detailed implementation manners

[0038] To make the objectives, technical solutions and advantages of the present invention clearer, the following will describe in detail the specific implementation manners of the present invention with reference to the accompanying drawings. Examples of these preferred implementation manners are illustrated in the accompanying drawings. The implementation manners of the present invention shown in the drawings and described according to the drawings are merely exemplary, and the present invention is not limited to these implementation manners.

[0039] Here, it should also be noted that in order to avoid obscuring the present invention with unnecessary details, only the structures and / or processing steps closely related to the solution of the present invention are shown in the drawings, while other details less related to the present invention are omitted.

[0040] Existing uncooled infrared detectors generally include a substrate and a thermosensitive unit. As shown in combination with Figure 1 and Figure 2 , the manufacturing process of this uncooled infrared detector is as follows:

[0041] S201: Coat the first sacrificial layer 21 on the substrate and cure it at a temperature of 350 °C for 30 min to make its final thickness 2.0 ± 0.2 microns. The substrate includes an integrated circuit wafer 11, a passivation layer 12, an aluminum pad 13, and a reflective layer 14. Perform photolithography and etching on the above wafer to make a CON pattern. The etching is to etch the first sacrificial layer 21 and stop at the passivation layer 12. The scribing lanes of this layer are protected by photoresist, and no alignment marks are reserved on the scribing lanes.

[0042] S202: Sequentially deposit a dielectric layer 22, a vanadium oxide layer 23, and a dielectric layer 24 on the wafer obtained in S201. Perform photolithography and etching on the above wafer to make a VOX pattern to obtain a thermistor. The etching is to etch the dielectric layer 24 and the vanadium oxide layer 23 and stop at the dielectric layer 22. The VOX marks reserved on the scribing lanes of this layer are protected by photoresist and are not etched; the areas outside the VOX marks on the scribing lanes are all etched and stop at the dielectric layer 22.

[0043] S203: Deposit the dielectric layer 25 on the wafer described in S202. Perform photolithography and etching on the above-mentioned wafer to fabricate the VA1 pattern. The VA1 pattern in the device area is opened without photoresist protection, and the dielectric layer 25, the dielectric layer 22, and the passivation layer 12 are etched, stopping at the aluminum pad 13. The areas outside the VA1 pattern in the device area and the scribe lane area (including the alignment mark VOX) are protected by photoresist and not etched. No alignment marks are reserved for this layer.

[0044] S204: Perform photolithography and etching on the wafer described in S203 again to fabricate the VA2 pattern. The VA2 pattern in the device area is opened without photoresist protection, and the dielectric layer 25 and the dielectric layer 24 are etched, stopping at the vanadium oxide layer 23. The areas outside the VA2 pattern in the device area and the scribe lane area (including the alignment mark VOX) are protected by photoresist and not etched. No alignment marks are reserved for this layer.

[0045] S205: Deposit the titanium metal layer 26 and the aluminum metal layer 27 on the wafer described in S204 at one time. Perform photolithography and etching on the above-mentioned wafer to fabricate the ME3 pattern. The ME3 pattern in the device area and the scribe lane alignment mark ME3 are protected by photoresist and not etched. The areas in the device area (except the ME3 pattern) and the scribe lane (except the alignment mark ME3) are without photoresist protection. The aluminum metal layer 27 is etched and stopped at the titanium metal layer 26, leaving alignment marks. The alignment mark of the ME3 is placed outside the VOX mark area.

[0046] S206: Perform photolithography and etching on the wafer described in S205 again to fabricate the ME2 pattern. The ME2 pattern in the device area and the scribe lane alignment mark ME2 are protected by photoresist and not etched. The areas in the device area (except the ME2 pattern) and the scribe lane (except the alignment mark ME2) are without photoresist protection. The titanium metal layer 26 is etched and stopped at the dielectric layer 25, leaving alignment marks. The alignment mark of the ME2 is placed outside the VOX and ME3 alignment mark areas.

[0047] S207: Deposit the dielectric layer 28 on the wafer described in S206. Perform photolithography and etching on the above-mentioned wafer to fabricate the BRG pattern. The BRG pattern in the device area and the scribe lane alignment marks VOX, ME3, ME2, and BRG are protected by photoresist. The areas in the device area (except the BRG pattern) and the scribe lane (except the alignment marks VOX, ME3, ME2, and BRG) are without photoresist protection. The dielectric layer 28, the titanium metal layer 26, the dielectric layer 25, and the dielectric layer 22 are etched and stopped at the first sacrificial layer 21, leaving the alignment mark BRG. The BRG alignment mark is placed outside the VOX, ME3, and ME2 alignment marks.

[0048] The above processing process cannot completely remove alignment marks such as VOX, ME3, ME2, and BRG before the release of the sacrificial layer, which is likely to cause the problem of floating alignment marks. Therefore, this embodiment provides a method for processing alignment marks of a non-cooled infrared detector, which can remove all remaining alignment marks by etching before the release of the sacrificial layer, and solve the problem that the floating of the remaining alignment marks after the release of the sacrificial layer affects the normal use of the detector.

[0049] Embodiment 1

[0050] As Figure 3 shown, a method for processing alignment marks of a non-cooled infrared detector provided in this embodiment includes the following steps:

[0051] Step 1: Provide a non-cooled infrared detector to be processed with alignment marks. The non-cooled infrared detector includes a substrate and a first sacrificial layer for forming a resonant cavity. A first type of alignment mark is formed on the first sacrificial layer in the dicing channel area of the substrate.

[0052] Step 2: Perform etching in the dicing channel area until the surface of the first sacrificial layer is reached.

[0053] Step 3: Release the first sacrificial layer.

[0054] In Step 1, the substrate includes an integrated circuit wafer 11, a reflective layer 13, and a passivation layer 12. The passivation layer 12 covers the surfaces of part of the integrated circuit wafer 11 and the reflective layer 13. The first sacrificial layer is made of polyimide material. The formation process of the first type of alignment mark is similar to that of Figure 1 、 Figure 2 . The first type of alignment mark includes VOX, ME3, ME2, and BRG located on the first sacrificial layer 21, all of which are convex structures.

[0055] Among them, the final film layer structures on the first type of alignment marks are different, as shown in Table 1:

[0056] Layer / film layer VOX ME3 ME2 BRG Dielectric layer 28 √ √ √ √ Aluminum metal layer 27 / √ / / Titanium metal layer 26 / √ √ / Dielectric layer 25 √ √ √ √ Dielectric layer 24 √ / / / Vanadium oxide layer 23 √ / / / Dielectric layer 22 √ √ √ √

[0057] Table 1

[0058] In Step 2, the process of performing etching in the dicing channel area until the surface of the first sacrificial layer is reached includes: according to the film layer structure on the surface of the first sacrificial layer, dividing the film layer where the first type of alignment mark is located into a top dielectric layer, a metal layer, and a bottom dielectric layer, which means re-dividing each layer where the alignment mark in the first type of alignment mark is located according to the position of the metal (vanadium oxide layer 23, titanium metal layer 26, aluminum metal layer 27). The re-division of VOX, ME3, ME2, and BRG is shown in Table 2.

[0059]

[0060] Table 2

[0061] After re - dividing the first - type alignment marks, step - by - step etching is performed on the first - type alignment marks in the scribe line region:

[0062] First, etch the first - type alignment marks on the top - layer dielectric, that is, etch all the dielectric layers above the metal layer, including successively etching off dielectric layer 28 and part of dielectric layers 24 and 25; second, etch the first - type alignment marks on the metal layer, that is, etch vanadium oxide layer 23, titanium metal layer 26, and aluminum metal layer 27 until the surface of the bottom - layer dielectric; finally, etch the first - type alignment marks on the bottom - layer dielectric, that is, etch dielectric layer 22 and dielectric layer 25, where dielectric layers 22, 24, 25, and 28 are all silicon nitride materials.

[0063] In the FAB, the dielectric and the metal are generally etched by different machines. Since the film - layer structure included in the first - type alignment marks is relatively complex, including SIN, VOX, TI, and ALCU layers, where the thickness of the VOX layer is 600 - 1000 Å, the thickness of the TI layer is 100 - 200 Å, and the thickness of the ALCU layer is 2000 - 3000 Å, it is necessary to use different etching machines to remove the dielectric layer and the metal layer. It is relatively difficult to remove them only in the dielectric etching machine or the metal etching machine. Therefore, re - dividing the layer where each alignment mark in the first - type alignment marks is located and performing step - by - step etching can avoid the residue of the alignment marks.

[0064] To ensure that the uncooled infrared detector is not damaged by etching, it is necessary to provide a sufficient photoresist thickness. In this embodiment, first, the alignment mark processing step is performed on the bare silicon wafer, and it is confirmed that the actually consumed photoresist thickness is 15 ± 1.5 μm. Then, the alignment mark processing step is performed on the uncooled infrared detector where the alignment marks are actually to be removed. Since there are various patterns on the uncooled infrared detector where the alignment marks are actually to be removed, there are differences in the etching effect compared with the bare silicon wafer. Therefore, it is necessary to perform compositional analysis on the film layer where the alignment marks are located after steps two and three respectively to confirm whether the remaining alignment marks are etched clean.

[0065] Embodiment 2

[0066] This embodiment provides a method for processing alignment marks of an uncooled infrared detector. The difference from Embodiment 1 is that the uncooled infrared detector to be processed with alignment marks further includes an umbrella - shaped absorption structure and a second sacrificial layer for forming an umbrella - layer suspension cavity. There are second - type alignment marks on the second sacrificial layer in the scribe line region. The alignment mark processing method further includes etching and removing the second - type alignment marks and releasing the second sacrificial layer before removing the first - type alignment marks, and other processes are the same as those in Embodiment 1.

[0067] As Figure 4 shown, the alignment mark processing method provided in this embodiment includes the following steps:

[0068] Step 1: Provide an uncooled infrared detector to be processed with alignment marks. The uncooled infrared detector includes a substrate, a first sacrificial layer for forming a resonant cavity, and a second sacrificial layer for forming an umbrella-shaped suspended cavity. There are first-type alignment marks on the first sacrificial layer in the dicing street area of the substrate, and second-type alignment marks on the second sacrificial layer in the dicing street area;

[0069] Step 2: Etch and remove the second-type alignment marks in the dicing street area;

[0070] Step 3: Release the second sacrificial layer;

[0071] Step 4: Perform etching in the dicing street area until the surface of the first sacrificial layer;

[0072] Step 5: Release the first sacrificial layer.

[0073] Among them, in Step 1, the materials of the first sacrificial layer and the second sacrificial layer are both polyimide materials. The preparation processes of the umbrella-shaped absorption structure and the second-type alignment marks are as Figure 5 and Figure 6 shown, including the following processes:

[0074] S208: Coat a polyimide sacrificial layer 31 on the wafer described in S207 and perform high-temperature curing to make the final thickness 2.0 ± 0.2 um. Perform photolithography and etching on the wafer to make a CO2 pattern. The areas where the CO2 pattern is opened in the device area are not protected by photoresist, and the etching of the second sacrificial layer 31 stops on the dielectric 28. The areas outside the CO2 pattern and the entire dicing street (including alignment marks) are covered and protected by photoresist and not etched, and no marks are reserved for this layer.

[0075] S209: Deposit an umbrella-shaped absorption layer material 32 on the wafer described in S208. Perform photolithography and etching on the wafer to make an ABR pattern. The device area ABR pattern and the alignment mark ABR are protected by photoresist and not etched; the areas in the device area (except for the ABR pattern and the dicing street (except for the alignment mark ABR)) are not protected by photoresist, and the dielectric 32 is etched and stops on the second sacrificial layer 31, leaving an ABR alignment mark, and the ABR alignment mark is placed outside the VOX, ME3, ME2, and BRG alignment marks.

[0076] S210: Lithographically pattern and etch the wafer described in S209 to fabricate a PAD pattern test area. The PAD pattern test area is located in the scribe lane region and is used for subsequent test parameter measurement and chip package wire bonding. The device area is protected by photoresist and not etched, while the PAD pattern area, scribe lane region, and alignment marks have no photoresist protection. The etching of the PAD pattern area etches the polyimide sacrificial layer 31, polyimide sacrificial layer 21, and dielectric 41 and stops at the aluminum pad 42; the alignment mark area is successively etched with the second type of alignment mark ABR, second polyimide sacrificial layer 31, first type of alignment marks (VOX, ME3, ME2, BRG), first polyimide sacrificial layer 21, and PAD test area dielectric layer 41. After etching, the alignment marks have been removed. To clearly identify the cross-section of the scribe lane alignment marks, S210 only shows the cross-section after lithography.

[0077] In this embodiment, the second type of alignment mark can be removed separately in the etcher because the second type of alignment mark generally only contains the dielectric layer SIN and a very thin TI (TI < 100 Å), and the metal layer is very thin, so it can be etched in the dielectric etcher. In contrast, the film layer structure of the first type of mark is more complex, and it is more difficult to remove it solely in the dielectric or metal etcher.

[0078] When the technical solution provided by this patent etches the alignment marks, the opened area of the PAD is also etched. Through analysis, it is not difficult to find that the film layer etched in the PAD area is less than that in the alignment mark area. To ensure that the alignment marks are etched clean while the metal in the opened area of the PAD is not etched, the alignment mark processing method provided by the technical solution of this patent is actually carried out in five steps, including: the first step is to etch and remove the second type of alignment mark, the second step is to release the second sacrificial layer, the third step is to etch and remove the first type of alignment mark, the fourth step is to release the first sacrificial layer, and the fifth step is to etch and remove the dielectric in the PAD area. By analyzing the elemental composition of the PAD area through electron energy spectroscopy, it can be found that, as Figure 7 shown, during the process of etching and removing the first type of alignment mark in the third step, at this time, the first sacrificial layer 21 has been etched clean, that is, the fourth step of releasing the first sacrificial layer can be omitted in the actual operation process because the over-etching in the first three steps results in the thickness of the first sacrificial layer 21 being less than the theoretical value; as Figure 8 shown, the dielectric 42 in the PAD area is etched clean after the fifth step of etching.

[0079] Embodiment 3

[0080] As Figure 9 shown, this embodiment provides a manufacturing method for a non-cooled infrared detector, including the following steps:

[0081] First, deposit the first sacrificial layer on the surface of the substrate. The substrate includes an integrated circuit wafer, a reflective layer, and a passivation layer. The passivation layer covers part of the integrated circuit wafer and the surface of the reflective layer. The reflective layer is an aluminum mirror and a gasket, and the first sacrificial layer is made of polyimide material;

[0082] Then, prepare a thermal sensing unit on the surface of the first sacrificial layer in the device area. A layer including the first type of alignment marks is formed correspondingly in the scribing lane area. The first type of alignment marks includes VOX, ME3, ME2, and BRG; wherein, the thermal sensing unit and the first type of alignment marks are the same in the Figure 1 and Figure 2 preparation process.

[0083] Finally, use the alignment mark processing method provided in Embodiment 1 to process the remaining alignment marks, that is, remove all the remaining alignment marks by etching, solving the problem that the floating remaining alignment marks after the release of the sacrificial layer affect the normal use of the detector.

[0084] Embodiment 4

[0085] This embodiment provides a manufacturing method of a non-cooled infrared detector, which is carried out on the basis of Embodiment 3, and further includes the preparation of an umbrella-shaped absorption structure on the thermal sensing unit and the processing of corresponding alignment marks, specifically including the following steps:

[0086] First, deposit the first sacrificial layer on the surface of the substrate. The substrate includes an integrated circuit wafer, a reflective layer, and a passivation layer. The passivation layer covers part of the integrated circuit wafer and the surface of the reflective layer. The reflective layer is an aluminum mirror and a gasket, and the first sacrificial layer is made of polyimide material;

[0087] Then, prepare a thermal sensing unit on the surface of the first sacrificial layer in the device area. A layer including the first type of alignment marks is formed correspondingly in the scribing lane area. The first type of alignment marks includes VOX, ME3, ME2, and BRG;

[0088] Again, deposit the second sacrificial layer on the surface of the above thermal sensing unit. The second sacrificial layer is made of polyimide material; prepare an umbrella-shaped absorption structure on the surface of the second sacrificial layer in the device area. A layer including the second type of alignment marks is formed correspondingly in the scribing lane area. The second type of alignment marks is ABR;

[0089] Finally, perform alignment mark processing by using the alignment mark processing method provided in Embodiment 2 of this patent.

[0090] Embodiment 5

[0091] This embodiment provides a non-cooled infrared detector, including a substrate, a thermosensitive unit and an umbrella-shaped absorption structure, which is prepared by the preparation method provided in Embodiment 4.

[0092] In addition, it should be noted that in this specification, "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0093] It should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for processing alignment marks of an uncooled infrared detector, characterized in that: The following steps are involved: Step 1: providing an uncooled infrared detector to be processed with an alignment mark, wherein the uncooled infrared detector comprises a substrate and a first sacrificial layer for forming a resonant cavity, and a first type of alignment mark is formed on the first sacrificial layer in a cutting path area of ​​the substrate; Step 2: Etching the cutting path area until the surface of the first sacrificial layer is reached; Step three: releasing the first sacrificial layer.

2. The method for processing alignment marks of an uncooled infrared detector according to claim 1, characterized in that: The first type of alignment mark in step one is a groove or a protrusion structure, including one or more of silicon nitride, vanadium oxide, titanium, and copper-aluminum alloy.

3. The method for processing alignment marks of an uncooled infrared detector according to claim 1, characterized in that: Step 2 includes dividing the film layer where the first type of alignment mark is located into a top dielectric layer, a metal layer and a bottom dielectric layer according to the film layer structure on the surface of the first sacrificial layer, and performing step-by-step etching.

4. The method for processing alignment marks of an uncooled infrared detector according to claim 3, characterized in that: The step-by-step etching process comprises: Etching the first type of alignment mark on the top layer medium in the scribe line area; Etching the first type of alignment mark on the metal layer in the scribe line area; The first type of alignment mark on the underlying medium in the scribe line area is etched.

5. The method for processing alignment marks of an uncooled infrared detector according to claim 1, characterized in that: The method also includes performing a component analysis on the film layer where the alignment mark is located after each etching is completed during the step 2 and the step 3 to confirm the etching effect.

6. A method for processing alignment marks of an uncooled infrared detector according to claims 1-5, characterized in that: The uncooled infrared detector to be processed for alignment marks also includes a second sacrificial layer for forming an umbrella layer suspended cavity. The second sacrificial layer in the cutting path area has a second type of alignment mark. Before performing step two, the second type of alignment mark needs to be etched away to release the second sacrificial layer.

7. The method for processing alignment marks of an uncooled infrared detector according to claim 6, characterized in that: The first sacrificial layer and the second sacrificial layer are made of polyimide material.

8. A method for manufacturing an uncooled infrared detector, characterized in that: The following steps are involved: Depositing a first sacrificial layer on the surface of the substrate; A thermal sensitive unit is prepared on the surface of the first sacrificial layer in the device area of ​​the substrate, and a layer including the first type of alignment mark is correspondingly formed in the cutting road area of ​​the substrate; The residual alignment mark is processed using the alignment mark processing method described in any one of claims 1 to 5.

9. The method for manufacturing an uncooled infrared detector according to claim 8, characterized in that: The substrate comprises an integrated circuit wafer, a reflective layer and a passivation layer, wherein the passivation layer covers a portion of the integrated circuit wafer and a surface of the reflective layer.

10. An uncooled infrared detector, characterized in that: The method is used to prepare the product according to claim 8.

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