Preparation method of TBC battery electrode grid line, electrode grid line and TBC battery

Abstract

The invention discloses a preparation method of a TBC battery electrode grid line, the electrode grid line and a TBC battery, and belongs to the technical field of solar cells, and the preparation method comprises the following steps: carrying out double-sided polishing on a silicon wafer; sequentially depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface of the silicon wafer, and performing boron diffusion; digging an N region and a PN connection partition region on the back surface of the silicon wafer; sequentially depositing a tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back surface of the silicon wafer, and performing phosphorus diffusion on the basis of the tunneling oxide layer and the intrinsic polycrystalline silicon layer; digging a P region and a GAP region on the back surface of the silicon wafer, and digging a hole channel by using a second laser; removing the borosilicate glass layer and the phosphorosilicate glass layer in the pore channel area; sequentially depositing an aluminum oxide layer and a silicon nitride layer on the surface of the silicon wafer; printing non-burn-through slurry in the main grid areas of the P area and the N area through the silk screen printing plate; and carrying out laser-assisted sintering on the auxiliary grid line pore channel region. The completeness of a passivation film layer structure on the back surface of the battery piece is ensured, meanwhile, the contact area of a metal electrode and a silicon substrate is reduced, and metal contact recombination is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and particularly relates to a preparation method of an electrode grid line of a TBC battery, the electrode grid line, and a TBC battery. Background Art

[0002] In the composition and development of solar cells, from the early PERC, TOPCon to the current electrode grid lines of TBC batteries, they are all important components and an important link in the photoelectric conversion process of solar cells, having a crucial impact on the performance of the battery. The main function of the electrode grid line is to collect the current generated by the photovoltaic effect of the battery chip and conduct it to the external circuit for storage or use. The preparation of the auxiliary grid line of the solar cell chip mainly relies on the burn-through paste, and through high-temperature sintering or laser-assisted sintering processes to assist the paste in corroding the passivation film layer structure on the surface of the battery chip, contacting the underlying doped polysilicon layer, collecting the current, and converging it to the main grid of the electrode. However, the auxiliary grid line of the electrode prepared by high-temperature sintering or laser-assisted sintering processes will cause great damage to the passivation film layer structure of the battery chip, increase the recombination of the battery chip, and reduce the photoelectric conversion efficiency of the battery chip.

[0003] In the prior art, the electrode grid line of the TBC battery is mainly prepared by printing conductive paste. The traditional screen printing process of the electrode grid line includes the printing of the main / auxiliary grid lines in the P region on the back, the printing of the main / auxiliary grid lines in the N region on the back, as well as drying and sintering and other steps. The auxiliary grid line of the electrode prepared by high-temperature sintering or laser-assisted sintering processes will cause great damage to the passivation film layer structure of the battery chip, increase the recombination of the battery chip, and reduce the photoelectric conversion efficiency of the battery chip.

[0004] In view of this, the inventor of the present invention conducted in-depth research on this need, and thus this case was born. Summary of the Invention

[0005] To solve the problems in the prior art that the auxiliary grid line of the electrode prepared by high-temperature sintering or laser-assisted sintering processes causes great damage to the passivation film layer structure of the battery chip, increases the recombination of the battery chip, and reduces the photoelectric conversion efficiency of the battery chip, the present invention provides a preparation method of an electrode grid line of a TBC battery, the electrode grid line, and a TBC battery, and the specific content is as follows:

[0006] A preparation method of an electrode grid line of a TBC battery includes the following steps:

[0007] Step 1: Double-sidedly polish the silicon wafer in an alkaline solution;

[0008] Step 2: Sequentially deposit a first tunneling oxide layer and a first intrinsic polysilicon layer on the back of the silicon wafer by chemical vapor deposition; and on this basis, perform boron diffusion, and a P-type doped contact layer and a borosilicate glass layer are successively formed on the back of the silicon wafer;

[0009] Step 3: Use the first laser to cut out the N region and the PN junction isolation region on the back of the silicon wafer according to the designed pattern, and etch the laser-treated silicon wafer with an alkaline solution;

[0010] Step 4: Use chemical vapor deposition to sequentially deposit a second tunneling oxide layer and a second intrinsic polysilicon layer on the back of the etched silicon wafer, and form a phosphosilicate glass layer by phosphorus diffusion on this basis. The tunneling oxide layer, the intrinsic polysilicon, and the phosphosilicate glass are suspended above the borosilicate glass layer formed in Step 2 in the P region;

[0011] Step 5: Use the first laser to cut out the P region and the GAP region on the back of the silicon wafer according to the designed laser pattern. At the same time, use the second laser to cut out channels with a length of 2 - 5 cm at intervals of 5 - 20 cm in the electrode grid line regions of the P region and the N region;

[0012] Step 6: Use an HF solution to remove the borosilicate glass layer, the phosphosilicate glass layer, and the corresponding polysilicon layer in the P region, the N region, and the channel region, and texture the front surface of the silicon wafer to form a textured surface, obtaining a semi-finished TBC cell;

[0013] Step 7: Use PECVD or atomic layer deposition to sequentially deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer;

[0014] Step 8: Through screen printing, print non-burn-through paste in the main electrode grid line regions of the P region and the N region, print burn-through paste in the auxiliary electrode grid regions and pour it into the channels, and dry the main and auxiliary electrode pastes at low temperature and perform light injection;

[0015] Step 9: Perform laser-assisted sintering on the electrode auxiliary grid line channel region, so that the paste corrodes the underlying passivation film layer and forms contact with the polysilicon layer, obtaining the TBC cell electrode grid lines.

[0016] Further, the power of the first laser is 100 - 200 W, the laser wavelength is 300 - 1100 nm, the frequency is 500 - 1000 kHz, the scanning speed is 10 - 200 m / s, and the spot size > 200 μm.

[0017] Further, the power of the second laser is 2 - 5 W, the laser wavelength is 330 - 420 nm, the frequency is 200 - 1000 kHz, the scanning speed is 10 - 100 m / s, and the spot size is 20 - 40 μm.

[0018] Further, in Step 3, the thickness of the first tunneling oxide layer is 1 - 3 nm, the thickness of the first intrinsic polysilicon layer is 200 - 500 nm, the concentration of the alkaline solution is 5% - 15%, and the treatment time is 200 - 400 s;

[0019] The thickness of the second tunneling oxide layer described in step 4 is 1 - 3 nm, and the thickness of the second intrinsic polysilicon layer is 100 - 300 nm.

[0020] Further, the concentration of the HF solution described in step 6 is 5% - 20%.

[0021] Further, the thickness of the aluminum oxide described in step 7 is 1 - 10 nm, and the thickness of the silicon nitride is 20 - 200 nm.

[0022] Further, in step 9, the laser-assisted sintering uses a second laser to selectively sinter the pore region to form a low recombination contact.

[0023] Further, the drying temperature described in step 8 is 150 - 250 °C, and the time is 1 - 10 minutes.

[0024] This application also provides a TBC battery electrode grid line, which is obtained by using the preparation method of the TBC battery electrode grid line as described above; the electrode grid line includes a main electrode grid line and a sub-electrode grid line arranged crosswise;

[0025] On the outer surface of the back of the battery, a P region and an N region are alternately arranged in parallel. The P region is provided with a P region sub-grid line and a P region main grid line, the N region is provided with an N region sub-grid line and an N region main grid line, and a plurality of pores are correspondingly and equidistantly arranged on the N region sub-grid line and the P region sub-grid line.

[0026] This application also provides a TBC battery. The back of the battery includes, from the inside to the outside, a silicon substrate, a tunneling oxide layer, a doped polysilicon layer, a passivation layer, an antireflection layer, and the electrode grid line as described in claim 9.

[0027] The beneficial effects of adopting the technical solution of the present invention are as follows:

[0028] (1) Through the pore design, it is not necessary to perform high-temperature sintering and laser-assisted sintering on a large area for the electrode grid line, ensuring the integrity of the passivation film layer structure on the back of the battery cell while reducing the contact area between the metal electrode and the silicon substrate, and effectively reducing the metal contact recombination.

[0029] (2) By introducing pores as local contact windows, only the pore region needs to be subjected to low-energy laser-assisted sintering. Utilizing the high precision and characteristics of the second laser, the aluminum oxide or silicon nitride passivation layer below the pores is accurately etched, avoiding the collateral damage to the surrounding passivation structure caused by traditional wide-width laser or high-temperature sintering; the sub-grid paste in the non-pore region is mechanically fixed through drying and curing, and the passivation layer below it remains intact, and the chemical passivation performance is not affected.

[0030] (3) The main grids of the electrodes in the P region and the N region adopt non-burn-through conductive pastes to avoid direct damage to the passivation film layer caused by high-temperature sintering, maintain the chemical passivation effect of the passivation layer, and reduce the surface recombination of carriers in the main grid region of the electrodes; the auxiliary grids of the electrodes adopt burn-through conductive pastes and are accurately filled into the channels, and only the local area below the channels is corroded by laser-assisted sintering, so that the paste is in direct contact with the polysilicon layer to form a low-recombination ohmic contact, significantly improving the current collection efficiency. Brief Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0032] Figure 1 It is a schematic diagram of the back structure of a TBC battery of the present invention;

[0033] Figure 2 It is a distribution diagram of the channels on the auxiliary grid on the back of a TBC battery of the present invention;

[0034] Figure 3 It is a sectional view of a TBC battery of the present invention at the channel of the auxiliary grid line;

[0035] Figure 4 It is a sectional view of a TBC battery of the present invention at the main grid line;

[0036] In the figure, 1, main grid line of the electrode; 2, auxiliary grid line of the electrode; 3, P region; 4, N region; 5, auxiliary grid line of the P region; 6, main grid line of the P region; 7, auxiliary grid line of the N region; 8, main grid line of the N region; 9, channel; 10, silicon substrate; 11, tunneling oxide layer; 12, doped polysilicon layer; 13, passivation layer; 14, antireflection layer. Detailed Embodiments

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Therefore, the detailed description of the embodiments of the present invention provided in the following drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0038] In this embodiment, through channel design, the electrode grid lines do not need to be sintered at high temperature and laser-assisted sintered over a large area, ensuring the integrity of the passivation film layer structure on the back of the cell while reducing the contact area between the metal electrode and the silicon substrate, effectively reducing metal contact recombination. The specific implementation method is as follows:

[0039] A method for preparing the electrode grid lines of a TBC cell, comprising the following steps:

[0040] Step 1: Double-sided polish the silicon wafer in an alkaline solution;

[0041] Step 2: Sequentially deposit a first tunneling oxide layer 11 and a first intrinsic polysilicon layer on the back of the silicon wafer by chemical vapor deposition; and perform boron diffusion on this basis, and a P-type doped contact layer and a borosilicate glass layer are successively formed on the back of the silicon wafer;

[0042] Step 3: Use a first laser to cut out an N region 4 and a PN junction isolation region on the back of the silicon wafer according to a designed pattern, and etch the laser-treated silicon wafer with an alkaline solution;

[0043] Here, the first laser is used to locally open the film (BSG) of the overall P-type doped contact layer on the back of the silicon wafer, and the boron-doped polysilicon and the first tunneling oxide layer 11 in this region are completely cleaned by wet method, and the silicon substrate 10 is exposed, which is the reserved N region 4.

[0044] Step 4: Sequentially deposit a second tunneling oxide layer 11 and a second intrinsic polysilicon layer on the back of the etched silicon wafer by chemical vapor deposition, and form a phosphosilicate glass layer by phosphorus diffusion on this basis. The tunneling oxide layer 11, the intrinsic polysilicon and the phosphosilicate glass are suspended above the borosilicate glass layer formed in Step 2 in the P region 3;

[0045] Step 5: Use a first laser to cut out a P region 3 and a GAP region 3 on the back of the silicon wafer according to a designed laser pattern, and at the same time use a second laser to cut out holes 9 with a length of 2 - 5 cm at intervals of 5 - 20 cm in the electrode grid line regions of the P region 3 and the N region 4;

[0046] Here, the second laser is used to open the film PSG again in the region that has not been processed by the laser process in Step 3, cooperate with wet method to clean the mask on the surface of the P region 3, and prepare the GAP region 3; before wet cleaning, the second laser is used to perform regular grooving in the electrode grid line regions in the P and N regions 4 to prepare a space for the slurry to be poured in when printing the electrode sub-grid lines 2 later, and only perform laser-assisted sintering in this region, corrode the film layer below the holes 9, and the passivation film layers in other regions are all retained without damage, forming good contact and reducing surface recombination and metal contact recombination.

[0047] Step 6: Use HF solution to remove the borosilicate glass layer, phosphosilicate glass layer and the corresponding polysilicon layer in the P region 3, N region 4 and the pore region 9, and texture the front side of the silicon wafer to form a textured surface, obtaining a semi-finished TBC cell;

[0048] Step 7: Deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer in sequence by PECVD or atomic layer deposition;

[0049] Step 8: Through screen printing, print non-burn-through paste in the main grid line 1 region of the electrodes in the P region 3 and N region 4, print burn-through paste in the electrode sub-grid region and pour it into the pore 9, and dry the main and sub-grid pastes of the electrodes at low temperature and perform photo-injection;

[0050] Here, the burn-through paste printed on the electrode sub-grid in the P and N regions 4 is completely poured into the pore 9 region, and it is ensured that the passivation film layer structure in the non-pore 9 region is not damaged during the drying process.

[0051] Step 9: Perform laser-assisted sintering on the pore 9 region of the electrode sub-grid line 2, so that the paste corrodes the underlying passivation film layer and forms contact with the polysilicon layer, obtaining the TBC cell electrode grid line.

[0052] Furthermore, the power of the first laser is 100 - 200 W, the laser wavelength is 300 - 1100 nm, the frequency is 500 - 1000 kHz, the scanning speed is 10 - 200 m / s, and the spot size > 200 μm.

[0053] Furthermore, the power of the first laser is 2 - 5 W, the laser wavelength is 330 - 420 nm, the frequency is 200 - 1000 kHz, the scanning speed is 10 - 100 m / s, and the spot size is 20 - 40 μm.

[0054] Here, the large spot of the first laser is for opening the film, and the area to be opened is relatively large; the small spot of the second laser is for drilling the pore 9, and the area to be opened is relatively small.

[0055] Furthermore, in Step 3, the thickness of the first tunneling oxide layer 11 is 1 - 3 nm, the thickness of the first intrinsic polysilicon layer is 200 - 500 nm, the concentration of the alkali solution is 5% - 15%, and the treatment time is 200 - 400 s;

[0056] In Step 4, the thickness of the second tunneling oxide layer 11 is 1 - 3 nm, and the thickness of the second intrinsic polysilicon layer is 100 - 300 nm.

[0057] Furthermore, the concentration of the HF solution in Step 6 is 5% - 20%.

[0058] Further, in step 7, the thickness of the aluminum oxide is 1 - 10 nm, and the thickness of the silicon nitride is 20 - 200 nm.

[0059] Further, in step 9, the laser-assisted sintering uses a second laser to selectively sinter the channel 9 region to form a low recombination contact.

[0060] Here, low-temperature drying is to dry the main and auxiliary grid pastes so that the pastes are tightly adsorbed to the battery chip and are not easily detached.

[0061] Here, by introducing the channel 9 as a local contact window, only the channel 9 region needs to be subjected to low-energy laser-assisted sintering. Utilizing the high precision and small spot characteristics of the second laser, the aluminum oxide / silicon nitride passivation layer 13 below the channel 9 is accurately etched, avoiding collateral damage to the surrounding passivation structure caused by traditional wide-width laser sintering.

[0062] The channel 9 structure is formed by being drilled with the second laser, enabling the auxiliary grid paste to contact the polysilicon layer through the channel 9, and the passivation film layer in the non-channel 9 region remains intact. The auxiliary grid paste in the non-channel 9 region is mechanically fixed through drying and curing, and the passivation layer 13 below it remains intact, and the chemical passivation performance is not affected.

[0063] Further, in step 8, the temperature of the drying is 150 - 250 °C, and the time is 1 - 10 minutes.

[0064] Refer to Figures 1 - 4 As shown, the present application also provides a TBC battery electrode grid line, and the battery electrode grid line is obtained by using the preparation method of the TBC battery electrode grid line as described above; the electrode grid line includes a main electrode grid line 1 and an auxiliary electrode grid line 2 arranged crosswise;

[0065] On the outer surface of the back of the battery, a P region 3 and an N region 4 are arranged in parallel and alternately. The P region 3 is provided with a P region auxiliary grid line 5 and a P region main grid line 6. The N region 4 is provided with an N region auxiliary grid line 7 and an N region main grid line 8. A plurality of channels 9 are correspondingly and equidistantly opened on the N region auxiliary grid line 7 and the P region auxiliary grid line 5.

[0066] The present application also provides a TBC battery. The back of the battery sequentially includes a silicon substrate 10, a tunneling oxide layer 11, a doped polysilicon layer 12, a passivation layer 13, an antireflection layer 14, and the electrode grid line as described above from the inside to the outside.

[0067] Example 1:

[0068] A preparation method of a TBC battery electrode grid line, characterized by comprising the following steps:

[0069] Step 1: Double-sided polish the silicon wafer in an alkaline solution;

[0070] Step 2: Sequentially deposit a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 200 nm on the back side of the silicon wafer by chemical vapor deposition; and on this basis, perform boron diffusion to successively form a P-type doped contact layer and a borosilicate glass layer on the back side of the silicon wafer;

[0071] Step 3: Use a high-power first laser to cut out the N region and the PN junction isolation region on the back side of the silicon wafer according to the designed pattern, and etch the laser-treated silicon wafer with an alkaline solution. The concentration of the alkaline solution is 5%, the treatment time is 200 s, the laser wavelength is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm;

[0072] Step 4: Sequentially deposit a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 100 nm on the back side of the silicon wafer by chemical vapor deposition, and on this basis, form a phosphosilicate glass layer by phosphorus diffusion. The tunneling oxide layer, the intrinsic polysilicon, and the phosphosilicate glass are suspended above the borosilicate glass layer in the P region;

[0073] Step 5: Use the first laser to cut out the P region and the GAP region on the back side of the silicon wafer according to the designed laser pattern. At the same time, use the second laser to cut out 2-cm channels at intervals of 5 - 20 cm in the electrode grid line regions of the P region and the N region. The laser wavelength of the first laser is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm; the laser wavelength of the second laser is 330 nm, the frequency is 200 kHz, the scanning speed is 10 m / s, and the spot size is 20 μm;

[0074] Step 6: Use a 5% HF solution to remove the borosilicate glass layer, the phosphosilicate glass layer in the P region and the N region, the borosilicate glass layer and the phosphosilicate glass layer in the channel region, and the polysilicon layer at the corresponding positions, and texture the front side of the silicon wafer to form a textured surface to obtain a semi-finished TBC cell;

[0075] Step 7: Sequentially deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer by PECVD or atomic layer deposition. The thickness of the alumina is 1 nm, and the thickness of the silicon nitride is 20 nm;

[0076] Step 8: Screen-print non-burn-through type paste on the main grids of the P and N region inner electrodes, print burn-through type paste on the sub-grids of the electrodes and pour paste into the channel region, and dry the main and sub-grid pastes at a temperature of 150°C for 1 minute and perform light injection;

[0077] Step 9: Perform laser-assisted sintering on the sub-grid line channel region. The laser-assisted sintering uses the second laser with a wavelength of 330 nm and a frequency of 200 kHz to corrode the underlying passivation film layer with the paste and form contact with the polysilicon layer.

[0078] Example 2:

[0079] A method for preparing the electrode grid lines of a TBC battery, characterized by comprising the following steps:

[0080] Step 1: Double-side polish the silicon wafer in an alkaline solution;

[0081] Step 2: Sequentially deposit a tunneling oxide layer with a thickness of 3 nm and an intrinsic polysilicon layer with a thickness of 500 nm on the back of the silicon wafer by chemical vapor deposition; and on this basis, perform boron diffusion, and a P-type doped contact layer and a borosilicate glass layer are successively formed on the back of the silicon wafer;

[0082] Step 3: Use a high-power first laser to cut out the N region and the PN junction isolation region on the back of the silicon wafer according to the designed pattern, and etch the laser-treated silicon wafer with an alkaline solution. The concentration of the alkaline solution is 15%, the treatment time is 400 s, the laser wavelength is 1100 nm, the frequency is 1000 kHz, the scanning speed is 200 m / s, and the spot size > 200 μm;

[0083] Step 4: Sequentially deposit a tunneling oxide layer with a thickness of 3 nm and an intrinsic polysilicon layer with a thickness of 300 nm on the back of the silicon wafer by chemical vapor deposition, and on this basis, form a phosphosilicate glass layer by phosphorus diffusion. The tunneling oxide layer, the intrinsic polysilicon, and the phosphosilicate glass are suspended above the borosilicate glass layer in the P region;

[0084] Step 5: Use the first laser to cut out the P region and the GAP region on the back of the silicon wafer according to the designed laser pattern. At the same time, use a second laser to cut out 3-cm channels at 20-cm intervals in the inner electrode grid line regions of the P region and the N region. The laser wavelength of the first laser is 1100 nm, the frequency is 1000 kHz, the scanning speed is 200 m / s, and the spot size > 200 μm; the wavelength of the second laser is 420 nm, the frequency is 1000 kHz, the scanning speed is 100 m / s, and the spot size is 40 μm;

[0085] Step 6: Use a 20% HF solution to remove the borosilicate glass layer, the phosphosilicate glass layer in the P region and the N region, the borosilicate glass layer and the phosphosilicate glass layer in the channel region, and the polysilicon layer at the corresponding positions, and texture the front surface of the silicon wafer to form a textured surface, obtaining a semi-finished TBC battery wafer;

[0086] Step 7: Sequentially deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer by PECVD or atomic layer deposition. The thickness of the alumina is 10 nm, and the thickness of the silicon nitride is 200 nm;

[0087] Step 8: Screen printing non-burning-through paste on the main grid of the inner electrodes in the P and N regions, printing burning-through paste on the secondary grid of the electrodes, and pouring paste into the channel region. Dry the main and secondary grid pastes at a temperature of 250°C for 10 minutes and perform light injection;

[0088] Step 9: Perform laser-assisted sintering on the channel region of the secondary grid lines. The laser-assisted sintering uses a second laser with a wavelength of 420 nm and a frequency of 1000 kHz, causing the paste to corrode the underlying passivation film layer and form contact with the polysilicon layer to complete the preparation of the electrode grid lines.

[0089] Example 3:

[0090] A method for preparing electrode grid lines of a TBC cell, characterized by comprising the following steps:

[0091] Step 1: Double-side polish the silicon wafer in an alkaline solution;

[0092] Step 2: Sequentially deposit a tunneling oxide layer with a thickness of 2 nm and an intrinsic polysilicon layer with a thickness of 300 nm on the back of the silicon wafer by chemical vapor deposition; and perform boron diffusion on this basis, and a P-type doped contact layer and a borosilicate glass layer are successively formed on the back of the silicon wafer;

[0093] Step 3: Use a high-power first laser to cut out the N region and the PN junction partition region on the back of the silicon wafer according to the designed pattern, and etch the laser-treated silicon wafer with an alkaline solution. The concentration of the alkaline solution is 10%, the treatment time is 300 s, the laser wavelength is 600 nm, the frequency is 700 kHz, the scanning speed is 150 m / s, and the spot size > 200 μm;

[0094] Step 4: Sequentially deposit a tunneling oxide layer with a thickness of 2 nm and an intrinsic polysilicon layer with a thickness of 200 nm on the back of the silicon wafer by chemical vapor deposition, and form a phosphosilicate glass layer by phosphorus diffusion on this basis. The tunneling oxide layer, the intrinsic polysilicon, and the phosphosilicate glass are suspended above the borosilicate glass layer in the P region;

[0095] Step 5: Use the first laser to cut out the P region and the GAP region on the back of the silicon wafer according to the designed laser pattern. At the same time, use a second laser to cut out channels with a length of 5 cm at intervals of 10 cm in the inner electrode grid line regions of the P region and the N region. The laser wavelength of the first laser is 700 nm, the frequency is 700 kHz, the scanning speed is 100 m / s, and the spot size > 200 μm; the laser wavelength of the second laser is 400 nm, the frequency is 600 kHz, the scanning speed is 80 m / s, and the spot size is 30 μm;

[0096] Step 6: Use a 15% HF solution to remove the borosilicate glass layer, phosphosilicate glass layer in the P region and N region, the borosilicate glass layer and phosphosilicate glass layer in the pore region, and the polysilicon layer at the corresponding position, and texture the front side of the silicon wafer to form a textured surface, obtaining a semi-finished TBC cell;

[0097] Step 7: Sequentially deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer by PECVD or atomic layer deposition method, with the alumina thickness of 5 nm and the silicon nitride thickness of 80 nm;

[0098] Step 8: Print non-burn-through paste on the main grid of the inner electrodes in the P and N regions through a screen printing stencil, print burn-through paste on the secondary grid of the electrodes and pour paste into the pore region, and dry the main and secondary grid pastes at a temperature of 200 °C for 5 minutes and perform light injection;

[0099] Step 9: Perform laser-assisted sintering on the pore region of the secondary grid lines. The laser-assisted sintering uses a second laser with a wavelength of 400 nm and a frequency of 600 kHz.

[0100] Comparative Example 1

[0101] A method for preparing the electrode grid lines of a TBC cell, characterized by comprising the following steps:

[0102] Step 1: Perform double-sided polishing on the silicon wafer in an alkaline solution;

[0103] Step 2: Sequentially deposit a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 200 nm on the back side of the silicon wafer by chemical vapor deposition method; and perform boron diffusion on this basis, and a P-type doped contact layer and a borosilicate glass layer are successively formed on the back side of the silicon wafer;

[0104] Step 3: Use a high-power first laser to cut out the N region and the PN junction partition region on the back side of the silicon wafer according to the designed pattern, and etch the laser-treated silicon wafer with an alkaline solution. The concentration of the alkaline solution is 5%, the treatment time is 200 s, the laser wavelength is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm;

[0105] Step 4: Sequentially deposit a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 100 nm on the back side of the silicon wafer by chemical vapor deposition method, and form a phosphosilicate glass layer by phosphorus diffusion on this basis. The tunneling oxide layer, intrinsic polysilicon, and phosphosilicate glass are suspended above the borosilicate glass layer in the P region;

[0106] Step 5: Use the first laser to cut out the P region and the GAP region on the back side of the silicon wafer according to the designed laser pattern. The laser wavelength of the first laser is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm;

[0107] Step 6: Use a 5% HF solution to remove the borosilicate glass layer, phosphosilicate glass layer in the P region and N region, the borosilicate glass layer and phosphosilicate glass layer in the pore region, and the polysilicon layer at the corresponding position, and texture the front side of the silicon wafer to form a textured surface, obtaining a semi-finished TBC cell;

[0108] Step 7: Deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer in sequence by PECVD or atomic layer deposition method, with the thickness of the alumina being 1 nm and the thickness of the silicon nitride being 20 nm;

[0109] Step 8: Print non-burn-through paste on the main grid of the inner electrodes in the P and N regions through a screen printing stencil, and print burn-through paste on the sub-grid of the electrodes;

[0110] Step 9: Dry and sinter the paste at high temperature through a screen sintering process, so that the paste corrodes the underlying passivation layer and forms good contact with the polysilicon layer.

[0111] Comparative Example 2:

[0112] A method for preparing the electrode grid lines of a TBC cell, characterized by comprising the following steps:

[0113] Step 1: Double-side polish the silicon wafer in an alkaline solution;

[0114] Step 2: Deposit a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 200 nm on the back side of the silicon wafer in sequence by chemical vapor deposition method; and on this basis, perform boron diffusion, and a P-type doped contact layer and a borosilicate glass layer are formed on the back side of the silicon wafer successively;

[0115] Step 3: Use a high-power first laser to cut out the N region and the PN junction partition region on the back side of the silicon wafer according to the designed pattern, and etch the laser-treated silicon wafer with an alkaline solution, the concentration of the alkaline solution is 5%, the treatment time is 200 s, the laser wavelength is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm;

[0116] Step 4: Deposit a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 100 nm on the back side of the silicon wafer in sequence by chemical vapor deposition method, and on this basis, form a phosphosilicate glass layer by phosphorus diffusion. The tunneling oxide layer, intrinsic polysilicon and phosphosilicate glass are suspended above the borosilicate glass layer in the P region;

[0117] Step 5: Use the first laser to cut out the P-removal and GAP regions on the back of the silicon wafer according to the designed laser pattern. At the same time, use the second laser to cut out 1-cm channels at intervals of 5 - 20 cm in the electrode grid line regions of the P region and the N region. The laser wavelength of the first laser is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm; the laser wavelength of the second laser is 330 nm, the frequency is 200 kHz, the scanning speed is 10 m / s, and the spot size is 20 μm;

[0118] Step 6: Use a 5% HF solution to remove the borosilicate glass layer, phosphosilicate glass layer in the P region and the N region, the borosilicate glass layer in the channel region, the phosphosilicate glass layer, and the polysilicon layer at the corresponding positions, and texture the front side of the silicon wafer to form a textured surface, obtaining a semi-finished TBC cell;

[0119] Step 7: Use PECVD or atomic layer deposition method to sequentially deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer. The thickness of the alumina is 1 nm, and the thickness of the silicon nitride is 20 nm;

[0120] Step 8: Print non-burn-through paste on the main grids of the inner electrodes in the P and N regions through a screen printing plate, print burn-through paste on the sub-grids of the electrodes, and pour paste into the channel regions. Dry the main and sub-grid pastes at a temperature of 150°C for 2 minutes and perform photo-injection;

[0121] Step 9: Perform laser-assisted sintering on the sub-grid line channel regions. The laser-assisted sintering uses the second laser with a wavelength of 330 nm and a frequency of 200 kHz to corrode the underlying passivation film layer with the paste and form contact with the polysilicon layer.

[0122] Comparative Example 3:

[0123] A method for preparing the electrode grid lines of a TBC cell, characterized by comprising the following steps:

[0124] Step 1: Perform double-sided polishing on the silicon wafer in an alkaline solution;

[0125] Step 2: Use chemical vapor deposition method to sequentially deposit a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 200 nm on the back of the silicon wafer; and perform boron diffusion on this basis, and a P-type doped contact layer and a borosilicate glass layer are successively formed on the back of the silicon wafer;

[0126] Step 3: Use a high-power first laser to cut out the N region and the PN junction partition region on the back of the silicon wafer according to the designed pattern, and etch the laser-treated silicon wafer with an alkaline solution. The concentration of the alkaline solution is 5%, the treatment time is 200 s, the laser wavelength is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm;

[0127] Step 4: On the back side of the silicon wafer, a tunneling oxide layer with a thickness of 1 nm and an intrinsic polysilicon layer with a thickness of 100 nm are sequentially deposited by chemical vapor deposition, and a phosphosilicate glass layer formed by phosphorus diffusion is deposited on this basis. The tunneling oxide layer, intrinsic polysilicon, and phosphosilicate glass are suspended above the borosilicate glass layer in the P region;

[0128] Step 5: Use the first laser to cut out the P region and the GAP region on the back side of the silicon wafer according to the designed laser pattern. At the same time, use the second laser to cut out 7-cm channels at intervals of 5 - 20 cm in the electrode grid line regions of the P region and the N region. The laser wavelength of the first laser is 300 nm, the frequency is 500 kHz, the scanning speed is 10 m / s, and the spot size > 200 μm; the laser wavelength of the second laser is 330 nm, the frequency is 200 kHz, the scanning speed is 10 m / s, and the spot size is 20 μm;

[0129] Step 6: Use a 5% HF solution to remove the borosilicate glass layer, phosphosilicate glass layer in the P region and the N region, and the borosilicate glass layer, phosphosilicate glass layer in the channel region and the corresponding polysilicon layer, and texture the front side of the silicon wafer to form a textured surface, obtaining a semi-finished TBC cell;

[0130] Step 7: Use PECVD or atomic layer deposition to sequentially deposit an alumina layer and a silicon nitride layer on the surface of the silicon wafer. The thickness of the alumina is 1 nm, and the thickness of the silicon nitride is 20 nm;

[0131] Step 8: Print non-burn-through type paste on the main grids of the inner electrodes in the P and N regions through a screen printing plate, print burn-through type paste on the sub-grids of the electrodes and pour paste into the channel region, and dry the main and sub-grid pastes at a temperature of 150 °C for 2 minutes and perform light injection;

[0132] Step 9: Perform laser-assisted sintering on the sub-grid line channel region. The laser-assisted sintering uses the second laser with a wavelength of 330 nm and a frequency of 200 kHz, so that the paste corrodes the underlying passivation film layer and forms contact with the polysilicon layer.

[0133] Next, the electrode grid lines obtained in the above 1 - 7 groups of examples and comparative examples are subjected to performance tests, and the results are as follows:

[0134] Table 1 Performance test results of electrode grid lines in each group of examples

[0135] Serial number Duct Transformation efficiency <![CDATA[P-region composite (fA / cm 2 )]]> <![CDATA[N-region recombination (fA / cm 2 ) <!-- 8 -->]]> Example 1 2 cm 26.135％ 26 11 Example 2 3 cm 26.254％ 24 10 Example 3 5 cm 26.182％ 25 10 Comparative example 1 0 cm 24.083％ 28 12 Comparative example 2 1 cm 25.895％ 27 13 Comparative example 3 7 cm 25.125％ 27 12

[0136] Referring to Table 1, in Examples 1 - 3, holes with lengths of 2 cm, 3 cm, and 5 cm are opened in the sub-grid electrode regions of the P and N regions respectively. The recombination in the P and N regions is reduced, and the conversion efficiency of the cell protected by the passivation film layer is significantly improved.

[0137] As shown in Table 1 for Comparative Example 1, there are no openings in the sub-grid electrode regions within the P and N regions. The entire sub-grid line corrodes the underlying passivation layer, resulting in increased recombination and low conversion efficiency of the solar cell. In Comparative Example 2, holes with a channel length of 1 cm are opened in the sub-grid electrode regions within the P and N regions. Drying and laser-assisted sintering minimize the damage to the underlying passivation layer by the entire grid line, and the recombination within the P and N regions significantly decreases. However, the channel length is too small, resulting in a weakened ability of the sub-grid electrode to collect current and a significant decrease in the conversion efficiency of the solar cell. In Comparative Example 3, holes with a channel length of 7 cm are opened in the sub-grid electrode regions within the P and N regions. The excessive channel length leads to an increase in recombination within the P and N regions.

[0138] Opening holes in the sub-grid electrode regions within the P and N regions with a channel length within 2 - 5 cm significantly reduces the recombination of the solar cell and significantly improves the conversion efficiency of the solar cell. When the channel length is 3 cm, the overall conversion efficiency of the solar cell is the highest. The present invention uses a second laser to open holes in a regular pattern in the electrode grid line regions within the P and N regions of the TBC solar cell, and only performs laser-assisted sintering on the opened regions, effectively solving the corrosion of the underlying passivation film layer by the high-temperature sintering of the electrode sub-grid, forming good contact with the doped polysilicon layer, and reducing surface recombination and metal contact recombination.

[0139] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for preparing a TBC battery electrode grid line, characterized in that: The following steps are involved: Step 1: Double-sided polishing of the silicon wafer in an alkaline solution; Step 2: depositing a first tunneling oxide layer and a first intrinsic polysilicon layer in sequence on the back of the silicon wafer by chemical vapor deposition; and performing boron diffusion on this basis, so that a P-type doped contact layer and a borosilicate glass layer are successively formed on the back of the silicon wafer; Step 3: Use the first laser to carve out the N region and the PN junction isolation region on the back of the silicon wafer according to the design pattern, and etch the silicon wafer after the laser with alkaline solution; Step 4: depositing a second tunnel oxide layer and a second intrinsic polysilicon layer in sequence on the back side of the etched silicon wafer by chemical vapor deposition, and performing phosphorus diffusion to form a phosphosilicate glass layer on this basis, wherein the tunnel oxide layer, the intrinsic polysilicon and the phosphosilicate glass are suspended on the borosilicate glass layer formed in step 2 in the P region; Step 5: Use the first laser to carve out the P region and the GAP region on the back of the silicon wafer according to the designed laser pattern, and use the second laser to carve out 2-5 cm holes at intervals of 5-20 cm in the electrode grid line areas of the P region and the N region; Step 6: Use HF solution to remove the borosilicate glass layer, phosphorus silicon glass layer and polysilicon layer in the P area, N area and channel area, and the polysilicon layer in the corresponding area, and perform texturing on the front side of the silicon wafer to form a velvet surface to obtain a semi-finished TBC cell; Step 7: Using PECVD or atomic layer deposition method to deposit an aluminum oxide layer and a silicon nitride layer on the surface of the silicon wafer in sequence; Step 8: Print non-burn-through paste in the electrode main grid area in the P area and the N area through screen printing, print burn-through paste in the electrode sub-grid area and fill it into the channel, dry the main electrode sub-grid paste at low temperature and inject light; Step 9: Perform laser-assisted sintering on the electrode sub-gate line channel area, so that the slurry corrodes the passivation film layer below and forms contact with the polysilicon layer to obtain the TBC battery electrode gate line.

2. The method for preparing a TBC battery electrode grid line according to claim 1, characterized in that: The power of the first laser is 100-200W, the laser wavelength is 300-1100nm, the frequency is 500-1000kHz, the scanning speed is 10-200m / s, and the spot size is >200μm.

3. The method for preparing a TBC battery electrode grid line according to claim 1, characterized in that: The second laser has a power of 2-5 W, a laser wavelength of 330-420 nm, a frequency of 200-1000 kHz, a scanning speed of 10-100 m / s, and a spot size of 20-40 μm.

4. The method for preparing a TBC battery electrode grid line according to claim 1, characterized in that: In step 3, the thickness of the first tunneling oxide layer is 1-3 nm, the thickness of the first intrinsic polysilicon layer is 200-500 nm, the concentration of the alkali solution is 5%-15%, and the processing time is 200-400 s; In step 4, the thickness of the second tunneling oxide layer is 1-3 nm, and the thickness of the second intrinsic polysilicon layer is 100-300 nm.

5. The method for preparing a TBC battery electrode grid line according to claim 1, characterized in that: The concentration of the HF solution in step 6 is 5%-20%.

6. The method for preparing a TBC battery electrode grid line according to claim 1, characterized in that: In step 7, the thickness of the aluminum oxide is 1-10 nm, and the thickness of the silicon nitride is 20-200 nm.

7. The method for preparing a TBC battery electrode grid line according to claim 1, characterized in that: The laser assisted sintering described in step 9 uses a second laser to selectively sinter the channel area to form a low-composite contact.

8. The method for preparing a TBC battery electrode grid line according to claim 1, characterized in that: The drying temperature in step 8 is 150-250° C. and the drying time is 1-10 minutes.

9. A TBC battery electrode grid line, characterized in that: The battery electrode grid lines are obtained by the method for preparing the TBC battery electrode grid lines according to any one of claims 1 to 8; the electrode grid lines include cross-arranged electrode main grid lines and electrode auxiliary grid lines; The outer surface of the back side of the battery is provided with P regions and N regions arranged in parallel and alternately in sequence, the P region is provided with P region auxiliary grid lines and P region main grid lines, the N region is provided with N region auxiliary grid lines and N region main grid lines, and a number of channels are opened on the N region auxiliary grid lines and the P region auxiliary grid lines at equal intervals.

10. A TBC battery, characterized in that: The back side of the battery comprises, from inside to outside, a silicon substrate, a tunneling oxide layer, a doped polysilicon layer, a passivation layer, an anti-reflection layer and the electrode grid line as claimed in claim 9.

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