3D dynamic random access memory (DRAM) and method of fabricating 3D-DRAM

Abstract

A three-dimensional (3D) dynamic random access memory (DRAM) includes a substrate and a plurality of nanosheet transistors vertically stacked on a surface of the substrate. Each nanosheet transistor comprises a grid electrode, a source electrode and a drain electrode. The plurality of bit lines are connected to corresponding ones of the drains of the nanosheet transistors on one side of the plurality of nanosheet transistors. A plurality of capacitors are vertically stacked on the substrate, extend parallel to a surface of the substrate, and are connected with corresponding ones of the sources on opposite sides of the plurality of nanosheet transistors.

Description

Cross - Reference to Related Applications

[0001] This application claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 420,179, filed on October 28, 2022, and U.S. Provisional Patent Application No. 63 / 438,083, filed on January 10, 2023, the entire disclosures of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to memories, and more particularly, to 3D dynamic random access memories (3D - DRAMs) and methods of manufacturing 3D - DRAMs. Background Art

[0003] The background description provided here is for the purpose of generally presenting the background of the disclosure. Work of the currently named inventors within the scope of the background art described herein and aspects of the specification that were not determined to be prior art at the time of filing the application are neither expressly nor impliedly admitted to be prior art to the disclosure.

[0004] Dynamic random access memories (DRAMs) store each data bit in a memory cell. Each memory cell includes a capacitor and one or more transistors. Memories typically employ metal - oxide - semiconductor (MOS) technology. Advanced DRAMs are typically processed using two transistors per active region (e.g., based on FinFETs). The transistor gates are connected (or contacted) to word lines. The drains contact bit lines. The storage node contacts connect the source of the transistor to the vertical metal capacitor of the memory cell. Due to the high aspect ratios required for contact and capacitor processing, current 3D DRAM architectures have reached scaling saturation. Summary of the Invention

[0005] A three-dimensional (3D) dynamic random access memory (DRAM) includes: a substrate; and a plurality of nanosheet transistors vertically stacked on a surface of the substrate, wherein each of the nanosheet transistors includes a gate, a source, and a drain. The 3D-DRAM includes: a first step; a plurality of bit line contacts; a plurality of bit lines connected to corresponding drains of the drains of the nanosheet transistors at the first step through the plurality of bit line contacts; a plurality of second steps; a plurality of third steps; a plurality of capacitor contacts; and a plurality of storage node contacts including a first end connected to a corresponding source of the sources of the plurality of nanosheet transistors. A plurality of capacitors are vertically stacked on the substrate and extend parallel to the surface of the substrate. A first end of the plurality of capacitors positioned adjacent to the plurality of nanosheet transistors is connected to a corresponding capacitor contact of the plurality of capacitor contacts at a corresponding second step of the plurality of second steps. A second end of the plurality of capacitor contacts is connected to a corresponding storage node contact of the plurality of storage node contacts at a corresponding third step of the plurality of third steps.

[0006] In other features, the first step includes a two-dimensional (2D) step. The first step descends along a first orthogonal direction and a second orthogonal direction with respect to the surface of the substrate. At least a portion of the first step extends below the surface of the substrate. The first step and the plurality of bit lines are disposed on one side of the plurality of nanosheet transistors. The plurality of second steps, the plurality of third steps, and the capacitors are disposed on an opposite side of the plurality of nanosheet transistors.

[0007] In other features, the capacitor contacts are J-shaped and have a plurality of vertical lengths in a direction transverse to the surface of the substrate. The plurality of second steps are staggered between the plurality of third steps. The plurality of second steps descend in a direction toward the plurality of nanosheet transistors. The plurality of third steps ascend in a direction toward the plurality of nanosheet transistors. The gates of the plurality of nanosheet transistors include fork gates corresponding to word lines.

[0008] A three-dimensional (3D) dynamic random access memory (DRAM) includes: a substrate; and a plurality of nanosheet transistors vertically stacked on a surface of the substrate. Each of the nanosheet transistors includes a gate, a source, and a drain. A plurality of bit lines are connected to corresponding drains of the drains of the nanosheet transistors on one side of the plurality of nanosheet transistors. A plurality of capacitors are vertically stacked on the substrate, extend parallel to the surface of the substrate, and are connected to corresponding sources of the sources of the plurality of nanosheet transistors on an opposite side of the plurality of nanosheet transistors.

[0009] Among other features, the plurality of bit lines are connected to corresponding drains of the drains of the nanosheet transistors at the first step via a plurality of bit line contacts.

[0010] Among other features, the 3D-DRAM further includes: a plurality of second steps; a plurality of third steps; a plurality of capacitor contacts; and a plurality of storage node contacts including a first end connected to a corresponding source of the sources of the plurality of nanosheet transistors. A first end of the plurality of capacitors positioned adjacent to the plurality of nanosheet transistors is connected to a corresponding capacitor contact of the plurality of capacitor contacts at a corresponding second step among the plurality of second steps. A second end of the plurality of capacitor contacts is connected to a corresponding storage node contact of the plurality of storage node contacts at a corresponding third step among the plurality of third steps.

[0011] Among other features, the first step includes a two-dimensional (2D) step. The first step descends along a first orthogonal direction and a second orthogonal direction with respect to the surface of the substrate. At least a portion of the first step extends below the surface of the substrate. The capacitor contact is J-shaped and has a plurality of vertical lengths in a direction transverse to the surface of the substrate. The plurality of second steps are staggered between the plurality of third steps.

[0012] Among other features, the plurality of second steps descend in a direction toward the plurality of nanosheet transistors; and the plurality of third steps ascend in a direction toward the plurality of nanosheet transistors. The gates of the plurality of nanosheet transistors include cross-sheet gates corresponding to word lines.

[0013] A method for manufacturing a three-dimensional (3D) dynamic random access memory (DRAM) includes: depositing alternating first and second layers on a surface of a substrate; patterning active regions of a plurality of nanosheet transistors in the alternating first and second layers; patterning cross-sheet gates of the plurality of nanosheet transistors; selectively doping portions of the plurality of nanosheet transistors; and forming a first step and a plurality of second steps, the first step providing a plurality of connection positions for a plurality of bit line contacts on one side of the plurality of nanosheet transistors, and the plurality of second steps providing a plurality of connection positions for a plurality of storage node contacts on an opposite side of the plurality of nanosheet transistors.

[0014] Among other features, the first step descends along a first orthogonal direction and a second orthogonal direction with respect to the surface of the substrate. The method further includes forming a plurality of capacitors on an opposite side of the plurality of nanosheet transistors. The plurality of capacitors are vertically stacked on the substrate and extend parallel to the surface of the substrate.

[0015] Among other features, the method further includes forming a plurality of third steps between the plurality of second steps to provide connection locations for first ends of the plurality of capacitors. The plurality of second steps rise in a direction toward the plurality of nanosheet transistors, and the plurality of third steps descend in a direction toward the plurality of nanosheet transistors. The method further includes patterning a plurality of capacitor contacts that connect the first ends of the plurality of capacitors to the plurality of storage node contacts. The plurality of capacitor contacts are J-shaped and have a plurality of vertical lengths in a direction transverse to the surface of the substrate.

[0016] Among other features, the method further includes patterning and depositing a plurality of bit lines that are connected to corresponding bit line contacts among the plurality of bit line contacts. At least a portion of the first step extends below the surface of the substrate.

[0017] A three-dimensional (3D) dynamic random access memory (DRAM) includes: a substrate; and a first nanosheet transistor array disposed on the substrate in a first vertically stacked manner. The first nanosheet transistor array includes N layers of rows, each row including M nanosheet transistors. A second nanosheet transistor array is disposed on the substrate in a second vertically stacked manner, where the second nanosheet transistor array includes N layers of rows, each row including M nanosheet transistors, where M and N are integers greater than 1. N bit line layers are stacked and vertically aligned with the N layers of the first nanosheet transistor array and the second nanosheet transistor array. A first side of channels of the M nanosheet transistors in each of the N layers of the first nanosheet transistor array is connected to a first side of a corresponding bit line layer among the N bit line layers, and a first side of channels of the M nanosheet transistors in each of the N layers of the second nanosheet transistor array is connected to a second side of a corresponding bit line layer among the N bit line layers, such that each bit line layer among the N bit line layers is connected to 2×M nanosheet transistors.

[0018] Among other features, a first one of the N vertical bit lines is connected to a first one of the N bit line layers. The other of the N vertical bit lines is connected to one of the N bit line layers, extends through one or more of the N bit line layers, and is isolated from one or more of the N bit line layers. 2M vertical word lines are connected to gates of the first nanosheet transistor array and the second nanosheet transistor array.

[0019] Among other features, M of the 2M vertical word lines are respectively connected to gates of vertically aligned ones in the first nanosheet transistor array. M of the 2M vertical word lines are respectively connected to gates of vertically aligned ones in the second nanosheet transistor array.

[0020] Among other features, the 2M vertical character lines surround the gates of the corresponding nanosheet transistors in the first nanosheet transistor array and the second nanosheet transistor array. A first bridge array connects the first side of the channels of the N bitline layers to the first nanosheet transistor array. The first bridge array includes N layers of rows, each row including M bridges. A second bridge array connects the second side of the channels of the N bitline layers to the second nanosheet transistor array, wherein the second bridge array includes N layers of rows, each row including M bridges.

[0021] Among other features, a first capacitor array is connected to the second side of the channels of the first nanosheet transistor array, wherein the first capacitor array includes N layers of rows, each row including M capacitors; and

[0022] Among other features, a second capacitor array is connected to the second side of the channels of the second nanosheet transistor array, wherein the second capacitor array includes N layers of rows, each row including M capacitors. A first bridge array connects the first capacitor array to the second side of the channels of the first nanosheet transistor array. The first bridge array includes N layers of rows, each row including M bridges; and

[0023] A second bridge array connects the second capacitor array to the second side of the channels of the second nanosheet transistor array, wherein the second bridge array includes N layers of rows, each row including M bridges.

[0024] Among other features, the first capacitor array includes metal-insulator-metal capacitors. The first capacitor array includes: an inner metal layer, which is connected to the second side of the channels of the first nanosheet transistor array; an isolation layer, which surrounds the inner metal layer; and an outer layer, which surrounds the inner metal layer.

[0025] A method of manufacturing a three-dimensional (3D) dynamic random access memory (DRAM) includes: disposing a first nanosheet transistor array on the substrate in a first vertically stacked manner, wherein the first nanosheet transistor array includes N layers of rows, and each row includes M nanosheet transistors; disposing a second nanosheet transistor array on the substrate in a second vertically stacked manner, wherein the second nanosheet transistor array includes N layers of rows, and each row includes M nanosheet transistors, where M and N are integers greater than 1; stacking and vertically aligning N bitline layers with the N layers of the first nanosheet transistor array and the second nanosheet transistor array; and connecting a first side of the channels of the M nanosheet transistors in each of the N layers of the first nanosheet transistor array to a first side of the N bitline layers, and connecting a first side of the channels of the M nanosheet transistors in each of the N layers of the second nanosheet transistor array to a second side of the N bitline layers, such that each bitline layer in the N bitline layers is connected to 2×M nanosheet transistors.

[0026] In other features, the method includes: connecting a first one of the N vertical bitlines to one of the N bitline layers, and connecting other ones of the N vertical bitlines to one of the N bitline layers, and extending through one or more of the N bitline layers and being isolated from one or more of the N bitline layers.

[0027] In other features, the method includes connecting 2M vertical wordlines to the gates of the first nanosheet transistor array and the second nanosheet transistor array. In other features, the method includes: connecting M of the 2M vertical wordlines to the gates of vertically aligned ones in the first nanosheet transistor array respectively. In other features, the method includes: connecting M of the 2M vertical wordlines to the gates of vertically aligned ones in the second nanosheet transistor array respectively. The 2M vertical wordlines surround the gates of the corresponding nanosheet transistors in the first nanosheet transistor array and the second nanosheet transistor array.

[0028] In other features, the method includes: using a first bridge array to connect the first side of the channels of the N bitline layers to the first nanosheet transistor array, wherein the first bridge array includes N layers of rows, and each row includes M bridges. The method includes: using a second bridge array to connect the second side of the channels of the N bitline layers to the second nanosheet transistor array, wherein the second bridge array includes N layers of rows, and each row includes M bridges.

[0029] Among other features, the method includes: connecting a first capacitor array to a second side of the channel of the first nanosheet transistor array, wherein the first capacitor array includes N rows, each row including M capacitors. The method includes: connecting a second capacitor array to a second side of the channel of the second nanosheet transistor array, wherein the second capacitor array includes N rows, each row including M capacitors.

[0030] Among other features, the method includes: using a first bridge array to connect the first capacitor array to the second side of the channel of the first nanosheet transistor array, wherein the first bridge array includes N rows, each row including M bridges. Among other features, the method includes: using a second bridge array to connect the second capacitor array to the second side of the channel of the second nanosheet transistor array, wherein the second bridge array includes N rows, each row including M bridges.

[0031] Among other features, the first capacitor array includes metal-insulator-metal capacitors. The first capacitor array includes: an inner metal layer connected to the second side of the channel of the first nanosheet transistor array; an isolation layer surrounding the inner metal layer; and an outer layer surrounding the inner metal layer.

[0032] Further scope of applicability of the present disclosure will become apparent from the detailed description, claims and drawings. The detailed description and specific examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present disclosure will be more fully understood from the detailed description and the drawings, wherein:

[0034] Figure 1A A cross-sectional view of an example of a 2D DRAM cell;

[0035] Figure 1B For Figure 1A A cross-sectional view of an example of a 2D DRAM cell rotated on a first plane;

[0036] Figure 1C For Figure 1B A cross-sectional view of an example of a 2D DRAM cell rotated on a second plane;

[0037] Figures 2A to 2C A perspective view of an example of a 3D DRAM integrated circuit according to the present disclosure;

[0038] Figures 3A to 3C A perspective view of an example of 2D ladders, up-and-down alternating ladders and capacitor contacts in a 3D DRAM according to the present disclosure;

[0039] Figure 4 A flowchart of an example of a method for manufacturing a 3D DRAM according to the present disclosure;

[0040] Figures 5A to 5C A perspective view showing an example of active region patterning and encapsulation according to the present disclosure;

[0041] Figures 6A to 6D A perspective view showing an example of character line or finfet gate patterning according to the present disclosure;

[0042] Figures 7A to 7C A perspective view showing an example of replacing sacrificial SiGe with a dielectric material according to the present disclosure;

[0043] Figures 8A to 8H A perspective view showing an example of further forming a first step (in a first direction) and a plurality of second steps according to the present disclosure;

[0044] Figures 9A to 9H A perspective view showing an example of further forming a first step in a second direction according to the present disclosure;

[0045] Figures 10A to 10I A perspective view showing an example of forming a horizontal capacitor according to the present disclosure;

[0046] Figures 11A to 12I A perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure;

[0047] Figures 13A to 13F A perspective view showing an example of bridging (capacitor contact) and bit line according to the present disclosure;

[0048] Figure 14A and 14B A plan view showing an example of a bit line shared by a plurality of write lines, transistors, and capacitors according to the present disclosure;

[0049] Figures 15A to 15C A perspective view showing an example of a 3D DRAM having a transistor stack and a bit line connected to the transistor according to the present disclosure;

[0050] Figure 15D A perspective view showing an example of a multi-bridge connection between a bit line and a transistor and between a capacitor and a transistor according to the present disclosure;

[0051] Figure 15E A perspective view showing an example of a capacitor according to the present disclosure;

[0052] Figure 16 Perspective view of an example of a multi - bridge of a 3D DRAM according to the present disclosure;

[0053] Figure 17 And 18A to 18E are perspective views of a sacrificial silicon layer perforated by vertical vias located at different heights according to the present disclosure;

[0054] Figure 19 Perspective view of an example of a multi - bridge during processing according to the present disclosure;

[0055] Figure 20 Flowchart of an example of a method for manufacturing a 3D DRAM according to the present disclosure;

[0056] Figure 21A And 21B Perspective view showing an example of active region patterning according to the present disclosure;

[0057] Figure 22A And 22B Perspective view showing an example of gate patterning according to the present disclosure;

[0058] Figures 23A to 23D Perspective view showing an example of nanosheet isolation according to the present disclosure;

[0059] Figures 24A to 24H Perspective view showing an example of forming a multi - bridge according to the present disclosure;

[0060] Figures 25A to 25D Perspective view showing another example of forming a multi - bridge according to the present disclosure;

[0061] Figures 26A to 26F Perspective view showing an example of bit - line patterning according to the present disclosure;

[0062] Figures 27A to 27H Perspective view showing an example of capacitor processing according to the present disclosure;

[0063] Figure 28 Perspective view showing an example of gate isolation according to the present disclosure;

[0064] Figures 29A to 29E Perspective view showing an example of forming a top contact of a bit - line according to the present disclosure;

[0065] Figures 30A to 30B Perspective view showing an example of forming a word - line and forming a capacitor according to the present disclosure; and

[0066] Figures 31A to 31C Shows a 3D DRAM with some outer layers omitted for illustration according to the present disclosure.

[0067] Among the drawings, reference numerals may be repeated to identify similar and / or identical elements. DETAILED DESCRIPTION

[0068] According to the present disclosure, the 3D-DRAM architecture rotates 2D DRAM cells on two planes (and then stacks 2D DRAM cells) to overcome the patterning challenges of current designs. The 3D-DRAM architecture includes horizontal nanosheet transistors (e.g., two transistors per bit). The 3D-DRAM architecture places storage node contacts and drain contacts on opposite sides of the nanosheet transistor. The 3D-DRAM architecture includes 2-D stairs that can connect the bit lines to the corresponding drains of the nanosheet transistors. The 3D-DRAM architecture also includes staggered (or alternating) upper and lower stairs to connect the horizontal stacked capacitors to the horizontal storage node contacts.

[0069] These features enable 3D-DRAM architectures to be implemented using horizontal nanosheet transistors. The 3D-DRAM architectures described herein can be processed using existing materials and processes that have already been developed for advanced logic / memory (in contrast, other FinFET-based transistor 3D-NAND designs have not yet been fully developed).

[0070] It is understood that the following description uses specific materials and integration steps to provide a further understanding of the 3D DRAM architecture according to the present disclosure. However, the 3D DRAM architecture according to the present disclosure is not limited to these examples, and other materials and / or other integration steps may be used without departing from the scope of the present disclosure.

[0071] Now refer to Figure 1A , a memory cell 50 of a 2D DRAM is shown. The memory cell 50 includes a vertically extending capacitor 54, a source 56, a storage node contact 58, a drain 62, and a gate 66. The memory cell 50 is provided with a capacitor 54 extending upward from the memory cell 50. Further improvements can be achieved by transitioning from 2D DRAM to 3D DRAM. However, implementing 3D DRAM has been difficult to achieve.

[0072] Now refer to Figure 1B and Figure 1C , the 3D DRAM integrated circuit according to the present disclosure will Figure 1A The 2DDRAM memory cell shown in FIG. is rotated in two orthogonal directions. Figure 1B middle, Figure 1A The memory cell 50 of the 2D DRAM is rotated 90° (eg, the z plane is rotated from the vertical direction to the horizontal direction), and then a plurality of memory cells 50 are stacked. Figure 1BThe arrangement in requires deep lateral etching and materials with different selectivities to the etching chemicals to achieve different lateral grooves.

[0073] In Figure 1C In it, the memory cells 50 of the 2D DRAM are rotated 90° along the second direction (for example, the x-plane rotates from the vertical direction to the horizontal direction). The capacitor 54 extends horizontally. It can be seen that the etching can be performed vertically instead of laterally (with different etching rates). However, this arrangement makes it more difficult to form contacts for the gates, drains, and sources of the nanosheet transistors.

[0074] Now refer to Figures 2A to 2C , which shows the features of a 3D DRAM integrated circuit (IC). The 3D DRAM integrated circuit includes a horizontally extending capacitor 54, and the capacitor 54 is connected to the storage node contact 58 through a bridge (or capacitor contact 110). The capacitor contact 110 uses an alternating up-and-down staircase to connect the capacitor 54 to the storage node contact 58, which will be further described below. The bit line 128 is connected to the drain 122 of the nanosheet transistor 118 through a bit line contact via a 2D staircase. The cross-sheet gate or word line 132 is connected to the gate of the nanosheet transistor 118.

[0075] It can be seen that the 3D DRAM architecture includes multiple 2D DRAM cells that are rotated 90° twice and stacked together. The multiple alternating up-and-down staircases allow the capacitor 54 (now horizontal) to be connected to the storage node contact 58 and the source 56 of the nanosheet transistor. The storage node contact 58 and the drain 122 are located on different sides of the nanosheet transistor 118.

[0076] Now refer to Figures 3A to 3C , which shows the first staircase, multiple second staircases, multiple third staircases, and contacts in a 3D DRAM integrated circuit. In Figure 3A , the first staircase 140 allows the bit line 128 to be connected to the bit line contact 141, and the bit line contact 141 is connected to the drain 122 of the nanosheet transistor 118. In Figure 3B and 3C , the multiple second staircases 144 provide connection positions to the capacitor 54. The multiple third staircases 142 allow the capacitor contact 110 to be connected to the capacitor 54 and the storage node contact 58. In some examples, the highest capacitor is connected to the lowest storage node contact, and vice versa.

[0077] Now refer to Figure 4 , which shows a method 300 for manufacturing a 3D DRAM integrated circuit. At 310, active region patterning and coating are performed (for example, as follows Figures 5A to 5Cas described). At 314, perform word line (or fin gate) patterning (e.g., the example described below in Figures 6A to 6D ).

[0078] At 318, perform SiGe replacement (e.g., the example described below in Figure 7A to 7D). At 320, dope the source as needed to dope portions of the nanosheet transistors. At 322, define a first step along a first direction and define a plurality of second steps (e.g., the example described below in Figures 8A to 8H ). At 326, further define a first step in a second direction orthogonal to the first direction (e.g., the example described below in Figures 9A to 9H ). At 330, form a horizontal capacitor (e.g., the example described below in Figures 10A to 10I ). At 334, define a plurality of third steps between the plurality of second steps (e.g., the example described below in Figures 11A to 12G ). At 338, define a bridge (capacitor contact) and a bit line (e.g., the example described below in Figures 13A to 13F ).

[0079] Now refer to Figures 5A to 5C , which shows the active region patterning and the deposition of the insulating layer. In Figure 5A , an alternating silicon (Si) layer 414 and a silicon germanium (SiGe) layer 416 (collectively referred to as the alternating Si / SiGe layer 418) are respectively deposited on a silicon substrate 410. The silicon germanium (SiGe) layer 416 serves as a sacrificial layer. An insulating layer 420 (e.g., silicon nitride (Si3N4)) is deposited on the last silicon layer of the alternating Si / SiGe layer 418.

[0080] In Figure 5B , the insulating layer 420 and the alternating Si / SiGe layer 418 are patterned into a horizontal capacitor shape 430 and a fin shape 434 using photolithography and one or more etching steps. In Figure 5C , after patterning, an oxide layer 424 (such as SiO2) is deposited around the insulating layer 420 and the alternating Si / SiGe layer 418.

[0081] Now refer to Figures 6A to 6D , which shows the word line (or fin gate) patterning. Figures 6A to 6C Shown is Figure 5C a cross-section of a memory cell for illustrative purposes in Figure 6A , vertical gate trenches 440 are created in the insulating layer 420 and the alternating Si / SiGe layer 418 using photolithography and etching steps.

[0082] In Figure 6BIn [reference], the SiGe layer 416 in the alternating Si / SiGe layers 418 is selectively laterally etched via the vertical gate trench 440 to create a lateral opening 444. The lateral etching is selective because significantly more of the SiGe layer 416 is etched relative to the silicon layer 414 in the alternating Si / SiGe layers 418.

[0083] In Figure 6C In [reference], gate metal 450 (e.g., tungsten W) for the word line is deposited in the lateral opening 444. In Figure 6D In [reference], polishing, such as chemical mechanical polishing (CMP), may be performed after deposition.

[0084] Now referring to Figures 7A to 7C , the figure shows replacing the sacrificial SiGe with a dielectric. In Figure 7A In [reference], etching is performed to open the storage node contact 490 and the drain contact 492 (corresponding to the dashed lines 460 and 464 in Figure 6D respectively). In Figure 7B In [reference], a lateral etching recess is performed to remove the SiGe layer 416 between the silicon layer 414 on the storage node contact 490 and the drain contact 492. In Figure 7C In [reference], deposition of the oxide 470 is performed.

[0085] Now referring to Figures 8A to 8H , the figure shows forming a first step on one side of the nanosheet transistor and multiple second steps on the other side of the nanosheet transistor using resist patterning and an etch / resist trim ring. In Figure 8A In [reference], a resist layer 510 is deposited on the substrate. In Figures 8B to 8G In [reference], the nitride layer and the oxide layer are continuously etched to expose the steps of the first step (at this time, the steps of the first step descend along the first direction) and the steps of the multiple second steps. In Figure 8B In [reference], selected portions of the resist layer 510, the insulating layer 420, and the oxide layer 424 are etched to expose the first step of the first step 514 and the first step of the multiple second steps 518 (located on the opposite side of the nanosheet transistor). The multiple second steps 518 are spaced apart in a direction transverse to the rising / falling direction.

[0086] In Figures 8C to 8G In [reference], selected portions of the resist layer 510, the insulating layer 420, and the oxide layer 424 are continuously etched, and additional steps of the first step 514 and additional steps of the multiple second steps 518 are defined. After defining the last steps of the first step 514 and the multiple second steps 518 in Figure 8G , in Figure 8HA nitride layer is deposited to cover the first step 514 and the plurality of second steps 518. It can be seen that the first step 514 and the plurality of second steps 518 descend in a direction away from the nanosheet transistor.

[0087] Now referring to Figures 9A to 9H , the figure shows further processing of the steps of the first step 514. More specifically, the steps of the first step 514 are further etched to descend along a second direction orthogonal to the first direction (making the first step a 2D step). In Figure 9A , in the region outside the first step 514, the resist layer 540 is patterned and deposited on the nitride layer 530. In Figure 9B , the nitride layer 530 is removed on the first step 514. In Figure 9C , the resist layer 540 is deposited. In Figure 9D , the resist layer 540 is patterned and etched to define the steps 548 of the first step 514 in the second direction.

[0088] In Figure 9E , the resist layer 540 is etched to define the steps 550 of the first step 514. In Figure 9F , the resist layer 540 is patterned and etched to define the steps 552 of the first step 514. In Figure 9G , the resist layer 540 is patterned and etched to define the steps 554 of the first step 514 (and expose the drain contact 492). In Figure 9H , the resist layer 540 is patterned and etched to define the steps 554 of the first step 514. As can be seen from Figure 9H , the steps 548, 550, 552, 554 and 556 transition downward in the first and second orthogonal directions (e.g., x and y directions).

[0089] Now referring to Figures 10A to 10I , the figure shows the formation of a horizontal capacitor. In Figure 10A , an insulating layer 580 (e.g., a nitride layer) is deposited and polished. In Figure 10B and 10C , an etch layer 590 is deposited on the insulating layer 580, and a trench opening 604 for the horizontal capacitor is etched. In Figure 10D , the trench opening 604 is further etched to expose the side surfaces of the silicon layer 414 and the silicon germanium layer 416. In Figure 10E , the SiGe layer 416 between the silicon layers 414 is laterally etched and removed. In Figure 10F , a capacitor material 620 (e.g., titanium nitride) is deposited to fill the trench opening 610 and polished.

[0090] In Figure 10G , a trench 624 is etched.Figures 10B to 10F The steps in replace the silicon germanium layer 416 with the capacitor material 620. In Figure 10H , the silicon layer 414 between the layers of the capacitor material 620 is etched laterally. In Figure 10I , an oxide layer 424 is deposited in the trench 624 and polished.

[0091] Now refer to Figures 11A to 12G , a plurality of third steps are defined between (or staggered between) the plurality of second steps 518. In Figure 11A , a resist layer 710 is deposited and patterned on the oxide layer 424 and the insulating layer 580 above the first step 514 and the plurality of second steps 518. An opening is formed in the resist layer 710 by photolithography and etching. In Figure 11C and 11D , the oxide layer 424 and the insulating layer 580 are etched to expose the upper surfaces of the paired horizontal capacitors (such as the capacitor material 620). In Figure 11E and 11F , the resist layer 710 is removed.

[0092] In Figures 12A to 12I , a resist pattern and an etch / resist trim ring are used to define the plurality of third steps. In Figure 12A and 12B , the resist layer 750 forms the portion of the insulating layer 580 above the horizontal capacitor (such as the capacitor material 620) and the area above the plurality of second steps 518. In Figures 12C to 12G , the resist layer 750 is successively removed, and the steps of the plurality of third steps 760 are successively etched. It can be seen that the plurality of third steps 760 descend in the direction of the nanosheet transistor and expose the connection positions of the horizontal capacitors. The resist layer 750 is removed.

[0093] Now refer to Figures 13A to 13F , the figure shows the bridging and bit line processing. In Figure 13A , the insulating layer 580 is deposited and polished. In Figure 13B , a resist layer 810 is deposited and a pattern 814 is created for bridging (or capacitor contacts) and bit lines (connected to bit lines or drain contacts). In Figure 13C , the bridging and bit lines are etched via the pattern 814. In Figure 13D , metal is deposited to form the bridging (or capacitor contacts) 820 and the bit lines 824, and the resist layer 810 is removed. In Figure 13E and 13F , other cross-sections are shown.

[0094] Now refer to Figure 14A and 14B, a portion of another example of 3D DRAM is shown. As described above, bit lines are provided on opposite sides of the nanosheet transistors and a gate fork design is employed. Other variations include using gates around the nanosheet transistors, widening the capacitors, and increasing the number of transistors per bit line. In Figure 14A , a plurality of transistors 920 and capacitors 926 share a bit line 910. The capacitor 926 is wider (compared to previous designs). The capacitor 926 is connected to the first side of the channel of the transistor 920. The word line 924 is connected around the gate terminals of the transistor 920. The bit line 910 is connected to the second side of the channel of the transistor 920. In Figure 14B , each bit line 910 can be connected to a plurality of end points of a plurality of transistors 920, which are symmetrically located on opposite sides on multiple layers.

[0095] Now referring to Figures 15A to 17 B, other features of 3D DRAM are shown. In Figure 15A , the stack of transistors 920 includes gates connected to vertically extending word lines 924. In Figure 15B , the silicon channel 954 of the transistor 920 in the gate metal is shown. An isolation layer 956 (high-k layer) is provided between the silicon channel 954 of the transistor 920 and the gate metal (or word line 924). In Figure 15A and 15C , the vertical bit line contacts 910-C extend to different heights and are connected to bit line layers 910-L extending in spaced parallel planes. In some examples, 28 layers of capacitors are used. In some examples, there are 28 layers of capacitors 926 on both sides of the unit cell, with 6 in each row of each unit cell (e.g., each unit cell has 28 * 6 * 2 = 336 transistors).

[0096] In Figure 15C , the vertical bit line contacts 910-C pass through the insulating portion 960 of the bit line layer 910-L to prevent short circuits and then connect to the corresponding portions of the bit line layer 910-L. In some examples, the bit line layer 910-C is provided between two columns of transistors, as shown in Figure 14B . In some examples, there are 28 layers of bit line layers 910-L. Each bit line layer 910-L is penetrated by bit line contacts 910-C connecting to other bit line layers 910-L (preventing contact through the insulating portion 960). In some examples, each bit line layer 910-L contacts 12 transistors and each bit line layer 910-L has one bit line contact 910-C. The horizontal bit line 910-H is connected to the vertical bit line contact 910-C, while the vertical bit line contact 910-C is connected to the bit line layer 910-L.

[0097] In Figure 15A and 15DIn [the figure], the multi - bridge 943 connects the bit - line layer 910 - L to the first side of the channel of the transistor 920, and the multi - bridge 945 connects the second side of the channel of the transistor 920 to the capacitor 926. In some examples, the gate length is greater than 30 nm to avoid the short - channel effect.

[0098] In Figure 15E [the figure], the capacitor 926 may include a metal - insulator - metal capacitor array 970. For example, the inner metal layer 972 includes a conductor such as titanium nitride (TiN), the insulator layer 974 includes a material with a high dielectric constant, and the outer layer 976 includes a conductor such as TiN. In some examples, the outer layer 976 is grounded through the Figure 15A contacts 940 in [the figure]. In some examples, there are 28 layers of capacitors 926 on both sides of each unit cell, and each unit cell has 6 rows (for example, each unit cell has 28 * 6 * 2 = 336 capacitors).

[0099] When the length L of the capacitor 926 increases, the diameter d of the inner metal layer 972 increases, the thickness of the insulator decreases, and the dielectric constant of the insulator increases, the metal - insulator - metal capacitance increases. In some examples, the capacitance of the metal - insulator - metal capacitor is greater than 5 femto - farads (fF), and the length L defines the acceptable footprint of the 3D DRAM.

[0100] Now refer to Figures 16 to 18E [the figure], which shows other features of the 3D DRAM. In Figure 16 [the figure], the multi - bridges 943, the transistor 920, the multi - bridge 945, and the capacitor 926 extend from opposite sides of the stacked sacrificial silicon layer 990 (replaced by the bit - line layer 910 - L). In Figures 17 to 18D [the figure], the sacrificial silicon layer 990 is perforated by two via arrays (corresponding to the bit - line contacts 910 - C) that are located at different heights of the stack of the sacrificial silicon layer 990. The silicon material in the sacrificial silicon layer 990 is replaced by a conductor material via the vias to form the bit - line contacts 910 - C, as will be further described below. In Figure 18E [the figure], the group of bit - line contacts including the bit - line contacts 910 - C corresponds to a very dense area of the 3D DRAM architecture.

[0101] Now refer to Figure 19 [the figure], the multi - bridges 943 and 945 have multiple functions. The multi - bridge 943 allows the bit - line layer 910 - L to contact the first side of the channel of the transistor 920. The multi - bridge 945 also allows the second side of the channel of the transistor 920 to contact the capacitor 926. Additionally, during the fabrication of the bit - line contacts 910 - C and the capacitor 926, the multi - bridges 943 and 945 act as silicon etch - stop layers when replacing the silicon at the replacement 927 (the future location of the capacitor 926).

[0102] Now refer to Figure 20 , which shows the method 1000 for manufacturing 3D DRAM in FIGS. 14 to Figure 19 . At 1010, the active region is patterned. At 1014, a gate is formed. At 1018, the nanosheet transistors are isolated. At 1020, multiple bridges are formed. At 1022, the bit line contact groups are patterned. At 1026, the capacitors are processed. At 1030, the gates are isolated. At 1034, the top contacts and bit lines are formed. At 1038, the word lines and capacitor grounds are formed.

[0103] Now refer to Figure 21A and 21B , which shows the patterning of the active region. In some examples, silicon layer 414 and silicon germanium layer 416 are alternately deposited on silicon substrate 410 and patterned in a manner similar to Figures 5A to 5C shown and described above.

[0104] Now refer to Figure 22A and 22B , for the initial formation of the gate (word line 924). The formation of the gate or word line 924 includes creating trenches, oxide etching and SiGe recess, depositing isolation layer 956 and metal gate filling.

[0105] Now refer to Figure 23A and 23D , for isolating the transistor 920. Now refer to Figure 23A and 23B , for oxide removal. A mask 921 is deposited to retain the pillars providing mechanical integrity. In Figure 23C , the silicon germanium layer 416 is laterally etched. In Figure 23D , an oxide cladding layer 923 is deposited.

[0106] Now refer to Figures 24A to 24H , which shows the first method for forming multiple bridges 943 and 945. In Figure 24A and 24B , trenches 1010 are patterned on opposite sides of the channel of the transistor 920, and the oxide 1012 is etched (selectively etching the oxide while leaving the silicon) to expose silicon bridges 1014 (eventually corresponding to multiple bridges 943 and 945 respectively) at different vertical heights. In Figure 24C and 24D , conformal deposition of a transition metal 1020 (such as cobalt (Co), nickel (Ni), etc.) is performed. Gas phase doping can be used to introduce dopants into the silicon bridges and extensions. In Figure 24E and 24F , salicide treatment (such as annealing) is performed to form an alloy of silicon and the transition metal, and multiple bridges 943 and 945 are formed. InFigure 24G and 24H remove the transition metal 1020 (except for the alloy forming the multi-bridges 943 and 945).

[0107] Now refer to Figures 25A to 25C , which shows a second method of forming the multi-bridges 943 and 945. In Figure 25A , trenches 1050 are patterned on opposite sides of the channel of the transistor 920. The oxide 1012 and silicon in the trenches 1050 are etched. In Figure 25B , a conductor 1060 (e.g., in-situ doped SiGe epitaxy) is selectively deposited onto the silicon with a merged leading edge to form the multi-bridges 943 and 945. In some examples, when using SiGe epitaxy, the direction of the capacitor lines is 100 for faster lateral growth (compared to horizontal growth between the transistors 920 or between the sacrificial silicon in the bit line layer or capacitor locations).

[0108] Now refer to Figures 26A to 26F , perform patterning of the bit line contacts 910-C forming the bit line contact group. In Figure 26A , an array of holes 1100 (e.g., a 4×7 hole array) is patterned in the nitride layer 1104. In Figure 26B and 26C , vias 1106 are etched through the oxide 1108 and silicon 1112 (in the silicon (future location of the bit line layer 910-L)) to reach different etch depths (in other words, different landing heights on the future bit line layer 910-L) (thereby defining the vertical bit lines 910-C). In Figure 26D , an isolation spacer (insulating portion 960) for the vias 1106 is deposited in the vias 1106. In Figure 26E , silicon (corresponding to the bit line layer 910-L) is removed using wet etching and stopped at the multi-bridges 943 and 945. In Figure 26F , the vias 1106 and other cavities are filled with a conductor material (thereby forming, for example, the vertical bit lines 910-C and the bit line layer 910-L).

[0109] Now refer to Figures 27A to 27H , process the capacitor. In Figure 27A , the trench 1210 is opened and the oxide 1108 is etched. In Figure 27B , the silicon layer 414 is etched to form a groove 1218. In Figure 27C , cavity widening is performed using isotropic oxide etching to increase the diameter of the groove 1218 for the inner metal layer 972 of the capacitor 926.

[0110] In Figure 27DIn [the process], metal is deposited in the groove 1218 to form the inner metal layer 972 of the capacitor 926. For example, one or more conformal deposition and anisotropic etching cycles are performed. In Figure 27E In [the process], oxide deposition and oxide selective etching with respect to TiN are performed. In Figure 27F In [the process], oxide removal is performed. In Figure 27G In [the process], an isolation layer 974 with a high dielectric constant k is deposited on the inner metal layer 972 of the capacitor 926. In Figure 27H In [the process], the outer layer 976 of the capacitor 926 is deposited on the isolation layer 974.

[0111] Now referring to Figure 28 , the gate or word line is separated or cut. Trenches 1240 are etched in the gate metal between the nanosheet transistors, and the dielectric 1242 is filled.

[0112] Now referring to Figures 29A to 30B , a horizontal bit line contact 910-H for the bit line 910-C is formed. In Figure 29A and 29B In [the process], horizontal bit line contacts 1310 (e.g., 6 horizontal bit line contacts) are formed for re-wiring on the capacitor 926. In Figure 29C In [the process], the horizontal bit line contacts 1314 (transverse to the horizontal bit line contacts 1310 and in a parallel plane) are patterned (e.g., 7 horizontal bit lines). In Figure 29D In [the process], additional horizontal bit line contacts 1318 (e.g., 6 horizontal bit line contacts) (above the horizontal bit line contacts) are formed for re-wiring on the capacitor 926. In Figure 29E In [the process], horizontal bit line patterning (e.g., 7 horizontal bit lines) is performed. In Figure 30A and 30B In [the process], forming the word line 924 and capacitor ground (contact 940) to the outer layer 976 of the capacitor 926 is performed.

[0113] Now referring to Figures 31A to 31C , some layers are removed from the 3D DRAM shown in the figure to view the underlying structure.

[0114] The foregoing description is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses. The broad teachings of the present disclosure can be implemented in a variety of forms. Thus, while the present disclosure includes specific examples, the true scope of the present disclosure should not be so limited since other modifications will become apparent upon study of the drawings, the specification, and the appended claims. It should be understood that one or more steps in a method can be performed in a different order (or concurrently) without altering the principles of the present disclosure. In addition, while each embodiment is described above as having certain features, any one or more of those features described with respect to any embodiment of the present disclosure can be implemented in and / or combined with the features of any other embodiment, even if the combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more of the embodiments with each other remain within the scope of the present disclosure.

[0115] Various terms are used to describe spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), and the various terms include "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless a relationship between a first and a second element is explicitly described as "direct," when such a relationship is described in the foregoing disclosure, the relationship can be a direct relationship in which no other intervening element exists between the first and second elements, but can also be an indirect relationship in which one or more intervening elements exist (spatially or functionally) between the first and second elements. As used herein, the phrase "at least one of A, B, and C" should be construed to mean a logical (A or B or C) using a non-exclusive logical OR, and should not be construed to mean "at least one of A, at least one of B, and at least one of C."

Claims

1. A three-dimensional (3D) dynamic random access memory (DRAM), comprising: Substrate; A plurality of nanosheet transistors vertically stacked on the surface of the substrate, wherein each of the nanosheet transistors includes a gate, a source, and a drain; First step; A plurality of bit line contacts; A plurality of bit lines connected to the corresponding drains among the drains of the nanosheet transistors at the first step through the plurality of bit line contacts; A plurality of second steps; A plurality of third steps; A plurality of capacitor contacts; A plurality of storage node contacts including a first end connected to the corresponding source among the sources of the plurality of nanosheet transistors; And A plurality of capacitors vertically stacked on the substrate and extending parallel to the surface of the substrate, wherein the first ends of the plurality of capacitors positioned adjacent to the plurality of nanosheet transistors are connected to the corresponding capacitor contacts among the plurality of capacitor contacts at the corresponding second steps of the plurality of second steps, wherein the second ends of the plurality of capacitor contacts are connected to the corresponding storage node contacts among the plurality of storage node contacts at the corresponding third steps of the plurality of third steps.

2. The 3D-DRAM according to claim 1, wherein the first step includes a two-dimensional (2D) step.

3. The 3D-DRAM according to claim 1, wherein the first step descends along a first orthogonal direction and a second orthogonal direction with respect to the surface of the substrate.

4. The 3D-DRAM according to claim 1, wherein at least a part of the first step extends below the surface of the substrate.

5. The 3D-DRAM according to claim 1, wherein the first step and the plurality of bit lines are disposed on one side of the plurality of nanosheet transistors.

6. The 3D-DRAM according to claim 4, wherein the plurality of second steps, the plurality of third steps, and the capacitors are disposed on the opposite side of the plurality of nanosheet transistors.

7. The 3D-DRAM according to claim 1, wherein the capacitor contact is J-shaped and has a plurality of vertical lengths in a direction transverse to the surface of the substrate.

8. The 3D-DRAM according to claim 1, wherein the plurality of second steps are staggered between the plurality of third steps.

9. The 3D-DRAM according to claim 8, wherein: The plurality of second steps descend in a direction toward the plurality of nanosheet transistors; and The plurality of third steps ascend in a direction toward the plurality of nanosheet transistors.

10. The 3D-DRAM according to claim 1, wherein the gates of the plurality of nanosheet transistors include cross-sheet gates corresponding to word lines.

11. A three-dimensional (3D) dynamic random access memory (DRAM), comprising: Substrate; A plurality of nanosheet transistors vertically stacked on the surface of the substrate, wherein each of the nanosheet transistors includes a gate, a source, and a drain; A plurality of bit lines connected to the corresponding drains among the drains of the nanosheet transistors on one side of the plurality of nanosheet transistors; And A plurality of capacitors vertically stacked on the substrate, extending parallel to the surface of the substrate, and connected to the corresponding sources among the sources on the opposite side of the plurality of nanosheet transistors.

12. The 3D-DRAM according to claim 11, further comprising: First step; And A plurality of bit line contacts; wherein the plurality of bit lines are connected to the corresponding drains among the drains of the nanosheet transistors at the first step through the plurality of bit line contacts.

13. The 3D-DRAM according to claim 12, further comprising: A plurality of second steps; A plurality of third steps; A plurality of capacitor contacts; And A plurality of storage node contacts including a first end connected to the corresponding source among the sources of the plurality of nanosheet transistors, wherein the first ends of the plurality of capacitors positioned adjacent to the plurality of nanosheet transistors are connected to the corresponding capacitor contacts among the plurality of capacitor contacts at the corresponding second steps of the plurality of second steps, and wherein the second ends of the plurality of capacitor contacts are connected to the corresponding storage node contacts among the plurality of storage node contacts at the corresponding third steps of the plurality of third steps.

14. The 3D-DRAM according to claim 12, wherein the first step includes a two-dimensional (2D) step.

15. The 3D-DRAM according to claim 12, wherein the first step descends along a first orthogonal direction and a second orthogonal direction with respect to the surface of the substrate.

16. The 3D-DRAM according to claim 12, wherein at least a portion of the first step extends below the surface of the substrate.

17. The 3D-DRAM according to claim 13, wherein the capacitor contact is J-shaped and has a plurality of vertical lengths in a direction transverse to the surface of the substrate.

18. The 3D-DRAM according to claim 13, wherein the plurality of second steps are staggered between the plurality of third steps.

19. The 3D-DRAM according to claim 18, wherein: The plurality of second steps descend in a direction toward the plurality of nanosheet transistors; and The plurality of third steps ascend in a direction toward the plurality of nanosheet transistors.

20. The 3D-DRAM according to claim 11, wherein the gates of the plurality of nanosheet transistors include cross-sheet gates corresponding to word lines.

21. A method for manufacturing a three-dimensional (3D) dynamic random access memory (DRAM), comprising: Deposit alternating first and second layers on the surface of the substrate; Pattern the active regions of the plurality of nanosheet transistors in the alternating first and second layers; Pattern the fin-like gates of the plurality of nanosheet transistors; Selectively dope portions of the plurality of nanosheet transistors; And A first step and a plurality of second steps are formed, the first step providing a plurality of connection positions for a plurality of bit line contacts on one side of the plurality of nanosheet transistors, and the plurality of second steps providing a plurality of connection positions for a plurality of storage node contacts on the opposite side of the plurality of nanosheet transistors.

22. The method according to claim 21, wherein the first step descends along a first orthogonal direction and a second orthogonal direction with respect to the surface of the substrate.

23. The method according to claim 21, further comprising forming a plurality of capacitors on opposite sides of the plurality of nanosheet transistors.

24. The method according to claim 21, wherein the plurality of capacitors are vertically stacked on the substrate and extend parallel to the surface of the substrate.

25. The method according to claim 23, further comprising forming a plurality of third steps between the plurality of second steps to provide connection positions for first ends of the plurality of capacitors.

26. The method according to claim 25, wherein the plurality of second steps ascend in a direction toward the plurality of nanosheet transistors, and the plurality of third steps descend in a direction toward the plurality of nanosheet transistors.

27. The method according to claim 24, further comprising patterning a plurality of capacitor contacts that connect the first ends of the plurality of capacitors to the plurality of storage node contacts.

28. The method according to claim 27, wherein the plurality of capacitor contacts are J-shaped and have a plurality of vertical lengths in a direction transverse to the surface of the substrate.

29. The method according to claim 27, further comprising patterning and depositing a plurality of bit lines that are connected to corresponding bit line contacts among the plurality of bit line contacts.

30. The method according to claim 21, wherein at least a portion of the first step extends below the surface of the substrate.

31. A three-dimensional (3D) dynamic random access memory (DRAM), comprising: A substrate; A first nanosheet transistor array disposed on the substrate in a first vertically stacked manner, wherein the first nanosheet transistor array includes N layers of rows, and each row includes M nanosheet transistors; A second nanosheet transistor array disposed on the substrate in a second vertically stacked manner, wherein the second nanosheet transistor array includes N layers of rows, and each row includes M nanosheet transistors, where M and N are integers greater than 1; and N bit line layers stacked and vertically aligned with the N layers of the first nanosheet transistor array and the second nanosheet transistor array, wherein, a first side of the channels of the M nanosheet transistors in each of the N layers of the first nanosheet transistor array is connected to a first side of a corresponding bit line layer among the N bit line layers, and a first side of the channels of the M nanosheet transistors in each of the N layers of the second nanosheet transistor array is connected to a second side of a corresponding bit line layer among the N bit line layers, such that each bit line layer among the N bit line layers is connected to 2×M nanosheet transistors.

32. The 3D DRAM according to claim 31, further comprising: N vertical bit lines, wherein, a first one of the N vertical bit lines is connected to a first one of the N bit line layers, and wherein, the others of the N vertical bit lines are connected to one of the N bit line layers, extend through one or more of the N bit line layers, and are isolated from one or more of the N bit line layers.

33. The 3D DRAM according to claim 32, further comprising 2M vertical word lines, the 2M vertical word lines being connected to the gates of the first nanosheet transistor array and the second nanosheet transistor array.

34. The 3D DRAM according to claim 33, wherein: M of the 2M vertical word lines are respectively connected to the gates of the vertically aligned ones in the first nanosheet transistor array; and M of the 2M vertical word lines are respectively connected to the gates of the vertically aligned ones in the second nanosheet transistor array.

35. The 3D DRAM according to claim 34, wherein the 2M vertical word lines surround the gates of the corresponding nanosheet transistors in the first nanosheet transistor array and the second nanosheet transistor array.

36. The 3D DRAM according to claim 32, further comprising: A first bridge array connecting the first side of the channels of the N bit line layers to the first nanosheet transistor array, wherein the first bridge array includes N layers of rows, and each row includes M bridges; And A second bridge array connecting the second side of the channels of the N bit line layers to the second nanosheet transistor array, wherein the second bridge array includes N layers of rows, and each row includes M bridges.

37. The 3D DRAM according to claim 32, further comprising: A first capacitor array connected to a second side of the channels of the first nanosheet transistor array, wherein the first capacitor array includes N layers of rows, and each row includes M capacitors; And A second capacitor array connected to a second side of the channels of the second nanosheet transistor array, wherein the second capacitor array includes N layers of rows, and each row includes M capacitors.

38. The 3D DRAM according to claim 37, further comprising: A first bridge array connecting the first capacitor array to the second side of the channels of the first nanosheet transistor array, wherein the first bridge array includes N layers of rows, and each row includes M bridges; And A second bridge array that connects the second capacitor array to the second side of the channels of the second nanosheet transistor array, where the second bridge array includes N rows, each row including M bridges.

39. The 3D DRAM according to claim 37, wherein the first capacitor array comprises metal-insulator-metal capacitors.

40. The 3D DRAM according to claim 37, wherein the first capacitor array comprises: An inner metal layer connected to the second side of the channels of the first nanosheet transistor array; An isolation layer surrounding the inner metal layer; And An outer layer surrounding the inner metal layer.

41. A method of manufacturing a three-dimensional (3D) dynamic random access memory (DRAM), comprising: The first nanosheet transistor array is disposed on the substrate in a first vertical stack, where the first nanosheet transistor array includes N rows, each row including M nanosheet transistors; The second nanosheet transistor array is disposed on the substrate in a second vertical stack, where the second nanosheet transistor array includes N rows, each row including M nanosheet transistors, where M and N are integers greater than 1; N bit line layers are stacked and vertically aligned with the N layers of the first nanosheet transistor array and the second nanosheet transistor array; And The first side of the channels of the M nanosheet transistors in each of the N layers of the first nanosheet transistor array is connected to the first side of the N bit line layers, and the first side of the channels of the M nanosheet transistors in each of the N layers of the second nanosheet transistor array is connected to the second side of the N bit line layers, such that each bit line layer in the N bit line layers is connected to 2×M nanosheet transistors.

42. The method according to claim 41, further comprising: Connect the first of the N vertical bit lines to one of the N bit line layers, and Connect the other of the N vertical bit lines to one of the N bit line layers, and extend through one or more of the N bit line layers, and be isolated from one or more of the N bit line layers.

43. The method according to claim 42, further comprising connecting 2M vertical character lines to the gates of the first nanosheet transistor array and the second nanosheet transistor array.

44. The method according to claim 43, further comprising: Connect M of the 2M vertical word lines to the gates of the vertically aligned ones in the first nanosheet transistor array respectively; And Connect M of the 2M vertical word lines to the gates of the vertically aligned ones in the second nanosheet transistor array respectively.

45. The method according to claim 44, wherein the 2M vertical character lines surround the gates of the corresponding nanosheet transistors in the first nanosheet transistor array and the second nanosheet transistor array.

46. The method according to claim 42, further comprising: Use a first bridge array to connect the first side of the channels of the N bit line layers to the first nanosheet transistor array, where the first bridge array includes N rows, each row including M bridges; And Use a second bridge array to connect the second side of the channels of the N bit line layers to the second nanosheet transistor array, where the second bridge array includes N rows, each row including M bridges.

47. The method according to claim 42, further comprising: Connect a first capacitor array to the second side of the channels of the first nanosheet transistor array, where the first capacitor array includes N rows, each row including M capacitors; And Connect a second capacitor array to the second side of the channels of the second nanosheet transistor array, where the second capacitor array includes N rows, each row including M capacitors.

48. The method according to claim 47, further comprising: Use a first bridge array to connect the first capacitor array to the second side of the channels of the first nanosheet transistor array, where the first bridge array includes N rows, each row including M bridges; And Connect the second capacitor array to the second side of the channel of the second nanosheet transistor array using a second bridge array, where the second bridge array includes N layers of rows, each row including M bridges.

49. The method according to claim 47, wherein the first capacitor array comprises metal-insulator-metal capacitors.

50. The method according to claim 47, wherein the first capacitor array comprises: An inner metal layer connected to the second side of the channel of the first nanosheet transistor array; An isolation layer surrounding the inner metal layer; And An outer layer surrounding the inner metal layer.

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