Semiconductor device

Abstract

A semiconductor device having an IGBT region and a diode region is provided with: a semiconductor substrate of a first conductivity type; a back surface-side main electrode; a first semiconductor layer of a second conductivity type, which is formed so as to extend from the IGBT region into the diode region, and which is in contact with the rear surface-side main electrode; a second semiconductor layer of the first conductivity type, which is formed in the diode region, and which is in contact with the rear surface-side main electrode; and a low lifetime region formed over the first semiconductor layer in the diode region within the semiconductor substrate. As a result, it is possible to suppress an increase in the ON voltage of the IGBT, prevent recovery failure, and reduce recovery loss.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] In a reverse conducting IGBT (RC-IGBT) in which an IGBT (Insulated Gate Bipolar Transistor) and a diode are formed in the same semiconductor device, it is required to optimize the characteristics of each device to achieve high efficiency and high breakdown tolerance.

[0003] In an RC-IGBT, the following method is known: by irradiating an electron beam, injecting light ions such as hydrogen and helium into a diode region, controlling the lifetime of a semiconductor substrate, and reducing carriers remaining in a drift layer during recovery to reduce recovery current and recovery loss.

[0004] For example, Patent Document 1 discloses a semiconductor device including a semiconductor substrate having one surface and the other surface. In a surface direction of one surface of the semiconductor substrate, a region that operates as an IGBT element is an IGBT region, and a region that operates as a diode element is a diode region. The IGBT region and the diode region are alternately and repeatedly arranged. In this semiconductor device, the semiconductor substrate has a low lifetime region at least on a boundary side between the IGBT region and the diode region in the IGBT region.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2012-43891 Summary of the Invention

[0008] Problems to be Solved by the Invention

[0009] In the above prior art, a low lifetime region is formed in a region on a base layer side (surface side) in a drift layer of the diode region, a boundary region between an n buffer layer in a drift layer of the IGBT region (back surface p collector layer side: back surface side), and a region on a surface side of a boundary region with the diode region. By suppressing hole injection from the back surface p collector layer of the IGBT region into the diode region, carriers contributing to the recovery current recombine and disappear, thereby suppressing the recovery loss.

[0010] However, since a low-lifetime region is formed on the back side of the IGBT region, when the IGBT is turned on, the carrier accumulation in the drift layer becomes insufficient, the IE effect (Injection Enhancement Effect) weakens, the conduction loss increases, and thus the turn-on voltage becomes high.

[0011] The present invention is a solution proposed in view of the above circumstances, and aims to provide a semiconductor device that can suppress the rise of the turn-on voltage of the IGBT, prevent reverse recovery breakdown, and reduce reverse recovery loss.

[0012] Solution to the problem

[0013] This application includes multiple solutions to the above problems. If one example is given, in a semiconductor device having an IGBT region and a diode region, it includes: a semiconductor substrate of a first conductivity type; a main electrode on the back side; a first semiconductor layer of a second conductivity type, which is formed to extend from the IGBT region into the diode region and is in contact with the main electrode on the back side; a second semiconductor layer of the first conductivity type, which is formed in the diode region and is in contact with the main electrode on the back side; and a low-lifetime region, which is formed above the first semiconductor layer in the diode region of the semiconductor substrate.

[0014] Effect of the invention

[0015] According to the present invention, it is possible to suppress the rise of the turn-on voltage of the IGBT, and to prevent reverse recovery breakdown and reduce reverse recovery loss. Description of the drawings

[0016] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0017] Figure 2 It is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0018] Figure 3 It is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0019] Figure 4 It is a cross-sectional view showing the structure of the semiconductor device of the fourth embodiment. Detailed description of the invention

[0020] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0021] <First Embodiment>

[0022] Refer to Figure 1 The first embodiment of the present invention will be described.

[0023] Figure 1 It is a cross-sectional view showing an example of the structure of the semiconductor device of the present embodiment. In the following description, the upper side of the drawing is referred to as the surface side of the semiconductor device, and the lower side is referred to as the back side.

[0024] In Figure 1 as an example of a semiconductor device, a reverse conducting IGBT (RC-IGBT: Reverse Conducting-Insulated Gate Bipolar Transistor) is integrally formed by an IGBT region 100 that realizes the function of an IGBT and a diode region 200 that realizes the function of a freewheeling diode, and includes: a semiconductor substrate 1 of a first conductivity type; a body layer 2 of a second conductivity type formed on the surface side of the semiconductor substrate 1; an emitter layer 3 of a first conductivity type formed on the surface side in the IGBT region 100 of the body layer 2; an emitter electrode 4 formed on the surface side of the body layer 2 so as to connect the body layer 2 and the emitter layer 3; a plurality of trenches 5 formed so as to extend from the surface side of the body layer 2 to the semiconductor substrate 1; an insulating film 7 formed so as to cover the inside of the plurality of trenches 5; a gate electrode 6 formed inside the trench 5 in the IGBT region 100 among the plurality of trenches 5 via the insulating film 7; an emitter electrode 8 formed inside the trench 5 in the diode region 200 among the plurality of trenches 5 via the insulating film 7; a buffer layer 10 of a first conductivity type formed on the back side of the semiconductor substrate 1; a collector layer 11 (first semiconductor layer) of a second conductivity type formed on the back side of the buffer layer 10 so as to extend from the IGBT region 100 to a part of the diode region 200; a cathode layer 12 (second semiconductor layer) of a first conductivity type formed in a region on the back side of the buffer layer 10 in the diode region 200 where the collector layer 11 is not formed; a collector electrode 13 (main electrode on the back side) formed on the back side of the collector layer 11 and the cathode layer 12 so as to connect them; and a low lifetime region 20a formed along the buffer layer 10 in a region where the collector layer 11 on the back side extends from the IGBT region 100 side inside the semiconductor substrate 1 in the diode region 200. Here, the low lifetime region 20a is a region formed by irradiating an electron beam and injecting light ions such as hydrogen and helium.

[0025] The operation and effect of the semiconductor device in the present embodiment configured as described above will be described.

[0026] In the semiconductor device of this embodiment, when the diode recovers, the carriers used for recombination with the carriers accumulated in the diode region 200 are mainly injected from the collector layer 11 under the diode region 200. At this time, a part of the carriers injected from the collector layer 11 also flows into the IGBT region 100. Since the carriers injected from the collector layer 11 are suppressed by the low-lifetime region 20a, the inflow of carriers into the IGBT region 100 can be prevented, and the latching of the IGBT can be prevented. Moreover, since the amount of carrier injection into the diode region 200 is also reduced, the recovery loss can be reduced. In addition, since the low-lifetime region 20a is not formed in the IGBT region 100, an increase in the turn-on voltage of the IGBT can be suppressed. That is, an increase in the turn-on voltage of the IGBT can be suppressed, and recovery breakdown can be prevented, and the recovery loss can be reduced.

[0027] <Second Embodiment>

[0028] Refer to Figure 2 The second embodiment of the present invention will be described.

[0029] This embodiment shows a case where a low-lifetime region is formed over the entire back side inside the semiconductor substrate 1 in the diode region 200.

[0030] In this embodiment, only the aspects different from the first embodiment will be described. In the drawings of this embodiment, the same reference numerals are given to the same components as in the first embodiment, and the description will be appropriately omitted.

[0031] Figure 2 It is a cross-sectional view showing an example of the structure of the semiconductor device of this embodiment.

[0032] In Figure 2 similar to the first embodiment, the semiconductor device in this embodiment includes a semiconductor substrate 1, a body layer 2, an emitter layer 3, an emitter electrode 4, a trench 5, a gate electrode 6, an insulating film 7, an emitter electrode 8, a buffer layer 10, a collector layer 11, a cathode layer 12, and a collector electrode 13.

[0033] In addition, a low-lifetime region 20b is formed along the buffer layer 10 on the back side inside the semiconductor substrate 1 in the diode region 200.

[0034] Other structures are the same as those in the first embodiment.

[0035] In the present embodiment configured as described above, the same effects as those in the first embodiment can also be obtained.

[0036] In addition, the disappearance of carriers on the back side of the diode region 200 becomes faster, the tail current during recovery decreases, and the recovery loss can be reduced.

[0037] <Third Embodiment>

[0038] Refer to Figure 3 The third embodiment of the present invention will be described.

[0039] This embodiment shows the following situation: a carrier injection layer is formed in the diode region 200, and a low lifetime region is formed in the region on the back side inside the semiconductor substrate 1 where the carrier injection layer is not formed.

[0040] In this embodiment, only the aspects different from the second embodiment will be described. In the drawings of this embodiment, the same components as those in the second embodiment are denoted by the same reference numerals, and the description will be appropriately omitted.

[0041] Figure 3 It is a cross-sectional view showing an example of the structure of the semiconductor device of this embodiment.

[0042] In Figure 3 , similar to the second embodiment, the semiconductor device in this embodiment includes a semiconductor substrate 1, a body layer 2, an emitter layer 3, an emitter electrode 4, a trench 5, a gate electrode 6, an insulating film 7, an emitter electrode 8, a buffer layer 10, a collector layer 11, a cathode layer 12, and a collector electrode 13.

[0043] In addition, at a position in the diode region 200 separated from the collector layer 11 of the cathode layer 12 (in other words, the position farthest from the IGBT region 100), a second conductivity type carrier injection layer 14 (third semiconductor layer) adjacent to the cathode layer 12 and connected to the collector electrode 13 is formed.

[0044] In addition, on the back side inside the semiconductor substrate 1 in the diode region 200, in the region where the collector layer 11 extends from the IGBT region 100 side and in the region where the cathode layer 12 is formed (in other words, the region where the carrier injection layer 14 is not formed), a low lifetime region 20c is formed along the buffer layer 10.

[0045] Other structures are the same as those in the second embodiment.

[0046] In the present embodiment configured as described above, the same effects as those in the second embodiment can also be obtained.

[0047] In addition, since carriers are injected from the carrier injection layer 14 during recovery, the carriers on the back side increase, the depletion of carriers can be suppressed, and soft recovery can be achieved. At this time, since the carrier injection layer 14 is formed at a position far from the IGBT region 100, there is no carrier injection from the carrier injection layer 14 to the IGBT region 100 during recovery, and no damage caused by the carrier inflow from the carrier injection layer 14 to the IGBT region 100 occurs.

[0048] <Fourth Embodiment>

[0049] Refer to Figure 4 The fourth embodiment of the present invention will be described.

[0050] This embodiment shows a case where low lifetime regions are formed in a part of the back side and the front side inside the semiconductor substrate 1 in the diode region 200.

[0051] In this embodiment, only the aspects different from the first embodiment will be described. In the drawings of this embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description will be appropriately omitted.

[0052] Figure 4 It is a cross-sectional view showing an example of the structure of the semiconductor device of this embodiment.

[0053] In Figure 4 similar to the first embodiment, the semiconductor device in this embodiment includes a semiconductor substrate 1, a body layer 2, an emitter layer 3, an emitter electrode 4, a trench 5, a gate electrode 6, an insulating film 7, an emitter electrode 8, a buffer layer 10, a collector layer 11, a cathode layer 12, and a collector electrode 13.

[0054] In addition, in the semiconductor substrate 1 inside the diode region 200, in the region where the collector layer 11 on the back side extends from the IGBT region 100 side, a low lifetime region 20a is formed along the buffer layer 10.

[0055] And, on the front side inside the semiconductor substrate 1 in the diode region 200, a low lifetime region 21 is formed along the body layer 2.

[0056] Other structures are the same as those in the first embodiment.

[0057] In the present embodiment configured as described above, the same effects as those in the first embodiment can also be obtained.

[0058] In addition, carriers on the front side of the diode region 200 can be reduced, and switching losses can be reduced. At this time, since a low lifetime layer is not formed in the IGBT region 100, this embodiment can be applied without considering the influence on IGBT characteristics.

[0059] <Supplementary Note>

[0060] In addition, the present invention is not limited to the above-described embodiments, and includes various modification examples and combinations within the scope not departing from its gist. In addition, the present invention is not limited to the technology having all the structures described in the above-described embodiments, and includes the technology in which a part of the structure is deleted.

[0061] Explanation of Symbols

[0062] 1 - Semiconductor substrate, 2 - Body layer, 3 - Emitter layer, 4 - Emitter electrode, 5 - Trench, 6 - Gate electrode, 7 - Insulating film, 8 - Emitter electrode, 10 - Buffer layer, 11 - Collector layer, 12

[0063] - Cathode layer, 13 - Collector electrode, 14 - Carrier injection layer, 20a, 20b, 20c, 21 - Low - lifetime regions, 100 - IGBT region, 200 - Diode region.

Claims

1. A semiconductor device having an IGBT region and a diode region, characterized in that, Comprising: A semiconductor substrate of a first conductivity type; A back-side main electrode; A first semiconductor layer of a second conductivity type, which is formed to extend from the IGBT region into the diode region and is connected to the back-side main electrode; A second semiconductor layer of a first conductivity type, which is formed in the diode region and is connected to the back-side main electrode; and A low-lifetime region, which is formed above the first semiconductor layer in the diode region within the semiconductor substrate.

2. The semiconductor device according to claim 1, characterized in that. The above-mentioned low-lifetime region is formed above the first semiconductor layer and the second semiconductor layer in the above-mentioned diode region within the above-mentioned semiconductor substrate.

3. The semiconductor device according to claim 2, characterized in that. A third semiconductor layer of a second conductivity type is further provided within the above-mentioned diode region. The third semiconductor layer of the second conductivity type is formed in such a manner as not to be in contact with the above-mentioned first semiconductor layer, and is formed in such a manner as to be in contact with the above-mentioned second semiconductor layer and the above-mentioned back-side main electrode. The above-mentioned low-lifetime region is formed above the first semiconductor layer and the second semiconductor layer in the above-mentioned diode region within the above-mentioned semiconductor substrate.

4. The semiconductor device according to claim 1, characterized in that. The above-mentioned low-lifetime region is formed not only above the first semiconductor layer and the second semiconductor layer in the above-mentioned diode region within the above-mentioned semiconductor substrate, but also on the surface side in the above-mentioned diode region within the above-mentioned semiconductor substrate.

Images