ATE interface suitable for later test of memory chip

Abstract

The invention relates to the field of integrated circuit automatic test equipment, in particular to an ATE interface suitable for a storage chip subsequent test, which comprises a support plate, a floating unit assembly, a DSA module and a heat insulation module, the DSA module comprises a DSA and a DSA support plate; the heat insulation module comprises a heat insulation block and a shielding coaming; the supporting plate is fixed to the ATE, the floating unit assembly is fixed to the supporting plate, the heat insulation block is fixed to the floating unit assembly, the DSA supporting plate is installed on the heat insulation block, and the DSA is fixed to the DSA supporting plate. The shielding coaming wraps the periphery of the heat insulation block. Through reasonable integration and layout of the interface structure, the ATE and the sorting machine can be mechanically connected to form a structural framework required by the whole test environment, and the structure problem of butt joint of the large parallel test multi-channel semiconductor chip test equipment and the sorting machine in the subsequent test process can be solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit automatic test equipment, and particularly to an ATE interface suitable for the back-end test of memory chips. Background Art

[0002] In the field of semiconductor testing, domestic ATE (Integrated Circuit Automatic Test Equipment) devices face many technical problems to be solved in the back-end test link. When the existing domestic ATE devices support the back-end FT (Final Test) test of large parallel test multi-channel resource boards, the equipped test interfaces do not have corresponding domestic interfaces. With the rapid growth of the demand for memory testing, there is an urgent need to design a set of domestic high-speed test interfaces suitable for ATE. Summary of the Invention

[0003] Regarding some problems existing in the prior art, the purpose of the present invention is to provide an ATE interface suitable for the back-end test of memory chips to solve the structural problem of docking with the sorter during the back-end test of large parallel test multi-channel semiconductor chip test equipment.

[0004] To achieve the above object, the present invention provides an ATE interface suitable for the back-end test of memory chips, including a support plate, a floating unit assembly, a DSA module, and a heat insulation module;

[0005] The DSA module includes a DSA and a DSA support plate;

[0006] The heat insulation module includes a heat insulation block and a shielding enclosure;

[0007] The support plate is fixed on the ATE, the floating unit assembly is fixed on the support plate, the heat insulation block is fixed on the floating unit assembly, the DSA support plate is installed on the heat insulation block, and the DSA is fixed on the DSA support plate; the shielding enclosure wraps around the periphery of the heat insulation block.

[0008] Preferably, the top of the floating unit assembly is distributed with a first threaded interface and a second threaded interface, and the floating unit assembly is connected to the heat insulation block by screwing a screw into the first threaded interface or the second threaded interface.

[0009] Preferably, the first threaded interface provides a floating gap of 3 - 8 mm in the horizontal direction and 1 - 5 mm in the vertical direction, and the second threaded interface is fastened on the floating unit assembly.

[0010] Preferably, the support plate is provided with rectangular through holes.

[0011] Preferably, 8 floating unit assemblies are uniformly fixed on the support plate.

[0012] Preferably, every four of the floating unit components support one DSA module and one heat insulation module.

[0013] Preferably, a single DSA module includes eight evenly distributed DSAs and one DSA support plate.

[0014] Preferably, there are 16 through holes distributed on a single DSA support plate, and the eight DSAs are respectively loaded on the single DSA support plate through the through holes; a single DSA is used to carry 32 DUTs.

[0015] Preferably, a single heat insulation module includes one heat insulation block and one shielding enclosure.

[0016] Preferably, a dry air blowing port is installed on the heat insulation block.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects:

[0018] By providing a floating unit component with a larger floating gap, the present invention improves the floating space and floating freedom degree, and achieves a better docking effect. At the same time, the present invention provides a heat insulation block and a shielding enclosure, which are used to isolate the temperature in the test interface cavity and the temperature in the sorter cavity from the outside during the three-temperature test, and prevent the occurrence of heat leakage.

[0019] In addition, through the reasonable integration and layout of the interface structure, the present invention enables the ATE and the sorter to be mechanically connected, forming a structural framework required for the overall test environment, and can solve the structural problem of docking with the sorter during the subsequent test process of large parallel test multi-channel semiconductor chip test equipment.

[0020] Moreover, by using a DSA that can carry a larger number of DUTs, the present invention improves the disassembly and assembly efficiency of the DSA. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is the overall structure diagram of the ATE interface in a specific embodiment of the present invention;

[0023] Figure 2 It is the exploded view of the ATE interface in a specific embodiment of the present invention;

[0024] Figure 3 Schematic diagram of the details of the support plate in a specific embodiment of the present invention;

[0025] Figure 4 Schematic diagram of the details of the floating unit assembly in a specific embodiment of the present invention;

[0026] Figure 5 Schematic diagram of the details of the heat insulation block in a specific embodiment of the present invention;

[0027] Figure 6 Schematic diagram of the connection between the floating unit assembly and the heat insulation block in a specific embodiment of the present invention;

[0028] Figure 7 Schematic diagram of the DSA structure in a specific embodiment of the present invention;

[0029] Figure 8 Exploded view of the DSA in a specific embodiment of the present invention;

[0030] Figure 9 Schematic diagram of the details of the DSA support plate in a specific embodiment of the present invention;

[0031] Figure 10 Schematic diagram of the shielding enclosure in a specific embodiment of the present invention.

[0032] In the figure: 1 - DSA module; 2 - heat insulation module; 3 - DSA; 4 - DSA support plate; 41 - through hole; 5 - heat insulation block; 51 - dry air blowing buckle; 52 - opening; 6 - floating unit assembly; 61 - third threaded interface; 62 - fourth threaded interface; 63 - second threaded interface; 7 - support plate; 71 - rectangular through hole; 72 - floating heightening block; 73 - first threaded interface; 8 - shielding enclosure; 9 - ATE; 10 - ATE interface; 11 - socket guide; 111 - fifth threaded interface; 12 - socket; 13 - DSA PCB; 131 - sixth threaded interface; 14 - DSA frame; 141 - seventh threaded interface. Detailed implementation manners

[0033] The following will describe in more detail an ATE interface applicable to the post - process testing of memory chips according to the present invention with reference to the schematic diagrams, in which the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a broad guidance for those skilled in the art and not as a limitation to the present invention.

[0034] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail, because they would obscure the present invention with unnecessary details. It should be recognized that in the development of any actual embodiment, numerous implementation details must be made to achieve the specific goals of the developer, such as adapting from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such development work may be complex and time-consuming, but is only routine work for those skilled in the art.

[0035] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer based on the following description and the claims. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0036] As mentioned in the background art, when existing domestic ATE devices support the back-end FT (Final Test) test of large parallel test multi-channel resource boards, the equipped test interfaces do not have corresponding domestic interfaces. In view of this, the present invention designs an ATE interface suitable for the back-end test of memory chips.

[0037] Specifically, please refer to Figure 1 and Figure 2 , this embodiment provides an ATE interface suitable for the back-end test of memory chips, including a support plate 7, a floating unit assembly 6, a DSA module 1, and a heat insulation module 2;

[0038] The DSA module 1 includes a DSA 3 and a DSA support plate 4;

[0039] The heat insulation module includes a heat insulation block 5 and a shielding enclosure 8;

[0040] The support plate 7 is fixed on the ATE 9, the floating unit assembly 6 is fixed on the support plate 7, the heat insulation block 5 is fixed on the floating unit assembly 6, the DSA support plate 4 is installed on the heat insulation block 5, and the DSA 3 is fixed on the DSA support plate 4; the shielding enclosure 8 is wrapped around the periphery of the heat insulation block 5.

[0041] Among them, DSA is the Device Socket Adapter, and for the convenience of introduction, it will be hereinafter simply referred to as DSA.

[0042] Specifically, please refer to Figure 3 , Figure 4 and Figure 5, there are two rectangular through-holes 71 provided on the support plate 7, and the resource board cables inside the ATE9 pass through the rectangular through-holes 71 and are connected to the DSA3 at the top. There are 8 floating heightening blocks 72 provided on the support plate 7, 4 first threaded interfaces 73 are provided on the floating heightening blocks 72, 4 second threaded interfaces 63 are provided on the floating unit assembly, and the first threaded interfaces 72 and the second threaded interfaces 63 are fixed by screws, so that the floating unit 6 is fixed on the support plate 7.

[0043] In this embodiment, third threaded interfaces 61 and fourth threaded interfaces 62 are distributed at the top of the floating unit assembly 6, and an opening 52 is provided on the side of the heat insulation block 5. The floating unit assembly 6 is connected to the heat insulation block 5 by screwing a screw through the opening 52 into the third threaded interface 61 or the fourth threaded interface 62. The third threaded interface 61 is shorter and is the fixed end, which is fastened on the floating unit assembly 6. When connected to the heat insulation block 5 through the third threaded interface 61, a fixed locking interface can be realized, and it can effectively prevent bumping and vibration during transportation. The fourth threaded interface 62 is longer and is the floating end. When connected to the heat insulation block 5 through the fourth threaded interface 62, a floating gap of 3 - 8 mm in the horizontal direction and 1 - 5 mm in the vertical direction can be realized. For example, a floating gap of 5 mm is provided in the horizontal direction, that is, the movable gap, to ensure its movement back and forth in the horizontal direction; a floating gap of 3 mm is provided in the vertical direction to ensure its up and down floating. Such a setting can prevent hard contact or hard friction from occurring when it is mechanically docked with the sorter, reduce the resistance generated during the docking process, increase the floating space and floating freedom, and thus achieve a better docking effect.

[0044] In a specific implementation, 8 floating unit assemblies 6 are fixed on the support plate 7, and each 4 floating unit assemblies 6 support one DSA module 1 and one heat insulation module 2. Each DSA module 1 includes 8 DSA3s and 1 DSA support plate 4, the 8 DSA3s are loaded on a single DSA support plate 4, and 16 through-holes 41 are distributed on the single DSA support plate 4, and one DSA3 is loaded between two adjacent through-holes. Each heat insulation module 2 includes 1 heat insulation block 5 and 1 shielding enclosure 8, and a dry air blowing port 51 is installed on the heat insulation block 5.

[0045] Specifically, the heat insulation block 5 can effectively isolate the temperature in the test interface cavity and the temperature in the sorter cavity from the outside during the three-temperature test to prevent heat leakage. The dry air blowing port 51 is used to prevent the condensation phenomenon that may occur during the three-temperature test.

[0046] Please refer to Figure 7 and Figure 8, in this embodiment, the DSA3 includes a Socket Guide 11, a Socket 12, a DSA PCB 13, and a DSA frame 14. A single DSA3 includes two pieces of Socket Guides 11, and each piece of Socket Guide 11 includes 16 Sockets 12. A fifth threaded interface 111 is provided on the Socket Guide 11, a sixth threaded interface 131 is provided on the DSA PCB 13, and a seventh threaded interface 141 is provided on the DSA frame 14. The Socket Guide 11 is installed on the DSA PCB 13, and the DSA PCB 13 is installed on the DSA frame 14 and fixed by screwing into the fifth threaded interface 111, the sixth threaded interface 131, and the seventh threaded interface 141.

[0047] Among them, the Socket 12 is a component for electrically connecting the DUT and the DSA PCB 13. The Socket Guide 11 is used to arrange the positions of the Sockets 12 according to the DUT map inside the sorter, so that the sorter can accurately send the DUT into the DSA3 during testing. The DSA PCB 13 can introduce and integrate the resource signals inside the ATE9, and then convey these signals to the DUT through the Socket 12. After receiving the feedback signal, the ATE9 gives the test result. The DSA frame 14 can carry the DSA PCB 13 and the Socket Guide 11.

[0048] In this embodiment, there are two pieces of DSA support plates 4 in the ATE interface 13. A single DSA support plate 4 can support 8 pieces of DSA3, and a single DSA3 can carry 32 DUTs. Therefore, the ATE interface 13 can carry a total of 512 DUTs.

[0049] In summary, this embodiment proposes an ATE interface applicable to the back-end testing of memory chips. By providing a floating unit component with a larger floating gap, the floating space and floating freedom are improved, and a better docking effect is achieved. At the same time, the present invention provides a heat insulation block and a shielding enclosure to isolate the temperature inside the test interface cavity and the temperature inside the sorter cavity from the outside during the three-temperature test to prevent heat leakage. In addition, through the reasonable integration and layout of the interface structure, the ATE and the sorter can be mechanically connected to form the structural framework required for the overall test environment, which can solve the structural problem of docking with the sorter during the back-end testing of large parallel test multi-channel semiconductor chip testing equipment. Moreover, by using a DSA that can carry a larger number of DUTs, the disassembly and assembly efficiency of the DSA is improved.

[0050] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, which are all within the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. An ATE interface suitable for back-end testing of a memory chip, characterized in that: It includes support plates, floating unit components, DSA modules and thermal insulation modules; The DSA module includes a DSA and a DSA support plate; The thermal insulation module includes a thermal insulation block and a shielding enclosure; The support plate is fixed on the ATE, the floating unit assembly is fixed on the support plate, the insulation block is fixed on the floating unit assembly, the DSA support plate is installed on the insulation block, and the DSA is fixed on the DSA support plate; the shielding enclosure is wrapped around the periphery of the insulation block.

2. The ATE interface according to claim 1, characterized in that: A first threaded interface and a second threaded interface are provided on the top of the floating unit assembly, and the floating unit assembly is connected to the insulation block by screwing screws into the first threaded interface or the second threaded interface.

3. The ATE interface according to claim 2, characterized in that: The first threaded interface provides a floating clearance of 3-8 mm in the horizontal direction and 1-5 mm in the vertical direction, and the second threaded interface is fastened to the floating unit assembly.

4. The ATE interface according to claim 1, characterized in that: The support plate is provided with a rectangular through hole.

5. The ATE interface according to claim 1, characterized in that: Eight floating unit assemblies are evenly fixed on the support plate.

6. The ATE interface according to claim 5, characterized in that: Every four of the floating unit assemblies support one DSA module and one thermal insulation module.

7. The ATE interface according to claim 1, characterized in that: A single DSA module includes one DSA support plate and eight evenly distributed DSAs.

8. The ATE interface according to claim 7, characterized in that: A single DSA support plate is provided with 16 through holes, and the 8 DSAs are respectively loaded on the single DSA support plate through the through holes; a single DSA is used to carry 32 DUTs.

9. The ATE interface according to claim 1, characterized in that: A single thermal insulation module includes one thermal insulation block and one shielding enclosure.

10. The ATE interface according to claim 1, characterized in that: A dry air blowing port is installed on the heat insulation block.

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