Establishment method of OPC simulation model

Abstract

The invention provides a method for establishing an OPC simulation model, which comprises the following steps of: establishing a plurality of photoresist models with different photoresists, acquiring the photoresistance of the OPC simulation model to be established, selecting a photoresist model which is the same as the photoresistance of the OPC simulation model to be established, and simulating a test pattern by using the photoresist model to generate key size data of a wafer so as to establish the OPC simulation model of the test pattern. According to the method, the strict photoresist model is established, and the photoresist model is used for simulating the test pattern to generate the simulated wafer data to replace real wafer data, so that the time for collecting the wafer data and the time for establishing the OPC simulation model are shortened. The time for establishing a strict photoresist model is about two weeks, the time for establishing the strict photoresist model for the first time needs to be additionally two weeks, but the time for exposure, development and wafer data collection can be shortened as long as a film layer with the same photoresist exists in the future; and in the process of establishing the OPC simulation model, the problem that data cleaning consumes a long time due to errors caused by SEM test noise does not exist.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a method for establishing an OPC simulation model. Background Art

[0002] With the continuous miniaturization of the process node, in order to improve the linewidth accuracy, OPC technology is an essential part. OPC can be divided into two methods: rule-based correction and model-based correction. Rule-based optical proximity correction relies on a predefined set of rules. According to the experience and rules of the lithography process, designers manually create a series of rules to correct the proximity effect. These rules may include increasing or decreasing the size of a specific area, changing the edge shape or spacing, etc. Rule-based optical proximity correction is usually empirical and applicable to corrections in specific processes and specific situations, without the need for complex models or calculations. However, this method may be difficult to cover complex situations and may require manual adjustment of the rules when the process changes. Model-based optical proximity correction uses physical models or simulation tools to simulate the optical effects during the lithography process, such as the propagation and diffraction of light beams. These models can be based on physical principles, such as the propagation of electromagnetic fields or statistical models, and are created by collecting and analyzing a large amount of experimental data. This method is more flexible and can adapt to a wider range of processes and situations. It can predict the effects in complex situations and can perform corrections automatically. However, it may require more computing resources and time to build the model and perform the simulation.

[0003] Especially in advanced nodes, model-based OPC not only has better accuracy in small linewidth correction but also can detect hot spots in advance through model simulation and solve problems in advance. Combining these two advantages, this method has become the mainstream in the industry. However, the prerequisite for using model-based OPC is that there must be an exposure and development model first. Establishing this exposure and development model requires collecting the pattern sizes after exposure and development on the wafer and feeding them back into the EDA tool. And for one node, about a dozen exposure and development models are needed. It takes about 5 weeks to establish the OPC model for one photoresist layer, and about 6 - 8 months to establish the OPC models for all photoresist layers. Therefore, the process of establishing the exposure and development model often requires a large amount of time and human resources, thereby increasing the R & D schedule. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for establishing an OPC simulation model to solve the problem that establishing the OPC simulation model consumes a large amount of time and human resources, thereby increasing the R & D schedule.

[0005] To solve the above technical problems, the present invention provides a method for establishing an OPC simulation model, including:

[0006] Multiple photoresist models are established, where the photoresists in different photoresist models are different. The photoresist models are established by using test data including wafer slice data and strict physical equations.

[0007] Obtain the photoresist of the OPC simulation model to be established, and select the photoresist model with the same photoresist as that of the OPC simulation model to be established. Use the photoresist model to simulate the test pattern to generate critical dimension simulation data of the wafer, so as to establish the OPC simulation model of the test pattern.

[0008] Optionally, the method for establishing the photoresist model includes:

[0009] Design the test pattern and determine the information required for establishing the photoresist model;

[0010] Transfer the test pattern to the wafer, form an actual pattern on the wafer, and obtain the test data of the actual pattern. The test data of the actual pattern includes slice data;

[0011] Clean the test data of the actual pattern to remove the test data that does not meet the requirements and establish an initial photoresist model;

[0012] Modify the initial photoresist model to remove the hot spots in the test pattern;

[0013] Verify the modified photoresist model to obtain a photoresist model that meets the standards.

[0014] Optionally, the information required for establishing the photoresist model includes: determining the pattern and setting rules for establishing the photoresist model, preparing the test pattern, and determining the exposure and development conditions.

[0015] Optionally, the test pattern includes dense test patterns, semi-sparse test patterns, sparse test patterns, and anchor points in the test pattern.

[0016] Optionally, the exposure and development conditions include baking before exposure or after coating, baking after exposure, development time, light source conditions, mask parameters, and the film layer of the wafer.

[0017] Optionally, the slice data in the test data of the actual pattern includes the thickness and shape of the photoresist along the Z direction of the wafer.

[0018] Optionally, the number of points in the test data of the actual pattern is less than 1000 points.

[0019] Optionally, the difference in photoresists in different photoresist models means that the photoresist materials in different photoresist models are different.

[0020] Optionally, the method for establishing the OPC simulation model of the test pattern includes:

[0021] Obtain the photoresist of the OPC simulation model to be established, and select the photoresist model that is the same as the photoresist of the OPC simulation model to be established;

[0022] Determine the design rules, prepare the test patterns, determine the exposure and development conditions, and determine the pattern type and the number of points;

[0023] Use the photoresist model to simulate the test patterns to generate critical dimension simulation data of the wafer;

[0024] Clean the critical dimension simulation data of the wafer to establish an initial OPC simulation model;

[0025] Modify the initial OPC simulation model to remove the hot spots in the test patterns;

[0026] Verify the modified OPC simulation model to obtain an OPC simulation model that meets the standards.

[0027] Optionally, the number of critical dimension simulation data of the wafer generated by using the photoresist model to simulate the test patterns is greater than 1000 points.

[0028] In the method for establishing an OPC simulation model provided by the present invention, by first establishing a plurality of photoresist models, the photoresists in different photoresist models are different, and the photoresist models are established by using test data including wafer slice data and strict physical equations; obtain the photoresist of the OPC simulation model to be established, and select the photoresist model that is the same as the photoresist of the OPC simulation model to be established, and use the photoresist model to simulate the test patterns to generate critical dimension simulation data of the wafer, so as to establish an OPC simulation model of the test patterns. The present invention uses a mainstream simulation software in the industry to establish a strict photoresist model, and the photoresist model is established by using test data including wafer slice data and strict physical equations, and the simulation result of the photoresist model is very close to the test result of the actual wafer; and use the photoresist model to simulate the test patterns to generate critical dimension simulation data of the wafer, so as to replace the real critical dimension data of the wafer, reduce the collection time of the real critical dimension data of the wafer and the time for establishing the OPC simulation model. It takes about 2 weeks to establish a strict photoresist model. When establishing the OPC simulation model for the first time, it takes an additional 2 weeks to establish a strict photoresist model, but in the future, as long as there is a film layer with the same photoresist, the exposure and development time and the wafer data collection time can be reduced, and there will be no problem that the data cleaning takes a long time due to the error caused by the SEM test noise of the critical dimension of the wafer during the process of establishing the OPC simulation model. Description of the Drawings

[0029] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0030] Figure 1 is a flowchart of the method for establishing an OPC simulation model according to an embodiment of the present invention.

[0031] Figure 2 is a schematic flowchart of the method for establishing a photoresist model according to an embodiment of the present invention.

[0032] Figure 3 is a detailed flowchart of the method for establishing an OPC simulation model according to an embodiment of the present invention. Detailed Embodiments

[0033] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in very simplified forms and are not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structure. In particular, the emphases to be shown in the respective drawings are different, and sometimes different scales are used.

[0034] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present invention, when an element is disposed on another element, it generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements can be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any position such as inside, outside, above, below or on one side of another element, unless otherwise explicitly stated in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] Figure 1 is a flowchart of the method for establishing an OPC simulation model according to an embodiment of the present invention. As Figure 1 shown, this embodiment provides a method for establishing an OPC simulation model, including:

[0036] Step S10: Establish multiple photoresist models with different photoresists in different photoresist models. The photoresist models are established by using test data including wafer slice data and strict physical equations.

[0037] Step S20: Obtain the photoresist of the OPC simulation model to be established, select the photoresist model with the same photoresist as that of the OPC simulation model to be established, and use the photoresist model to simulate the test pattern to generate critical dimension simulation data of the wafer, so as to establish the OPC simulation model of the test pattern.

[0038] Figure 2 It is a schematic flowchart of the method for establishing a photoresist model according to an embodiment of the present invention. The method for establishing the photoresist model includes:

[0039] Step S11: Design a test pattern and determine the information required for establishing a photoresist model.

[0040] Step S12: Transfer the test pattern to a wafer, form an actual pattern on the wafer, and obtain test data of the actual pattern. The test data of the actual pattern includes slice data.

[0041] Step S13: Clean the test data of the actual pattern to remove the test data that does not meet the requirements and establish an initial photoresist model.

[0042] Step S14: Modify the initial photoresist model to remove hot spots in the test pattern.

[0043] Step S15: Verify the modified photoresist model to obtain a photoresist model that meets the standards.

[0044] Specifically, the information required to establish a photoresist model includes: determining the test patterns and setting rules for which a photoresist model needs to be established, preparing the test patterns, and determining the exposure and development conditions. The test patterns include Anchor test patterns, Semi-ISO test patterns, and ISO test patterns. Among them, the pitch of the Anchor test pattern is, for example, 100 nm, the pitch of the Semi-ISO test pattern is, for example, 5000 nm, and the pitch of the ISO test pattern is, for example, 5000 nm. The exposure and development conditions include the process parameters of baking before exposure or after spin coating (Post Application Bake, PAB), the process parameters of baking after exposure (Post Exposure Bake, PEB), the development time (Develop time, Dev time), the light source conditions, the critical dimension parameters of the pattern on the mask, and the film layers of the wafer. Among them, the film layers of the wafer are, for example, the wafer, the hard mask layer, the bottom anti-reflection layer, and the photoresist from bottom to top in sequence.

[0045] In step S12, the test data of the actual pattern includes not only the non-destructive data of the wafer but also the destructive data of the wafer. The non-destructive data of the wafer is, for example, the photoresist process file and process window including Anchor test patterns, Semi-ISO test patterns, and ISO test patterns. The destructive data of the wafer is the sliced data of the wafer. The sliced data in the test data of the actual pattern includes the thickness and shape of the photoresist along the Z direction of the wafer. Since the sliced data of the wafer can accurately reflect the real situation of lithography, fewer test data points are required. In this embodiment, the number of points in the test data of the actual pattern is, for example, less than 1000 points.

[0046] In step S13, the test data of the actual pattern is cleaned to remove the test data that does not meet the requirements. The test data that does not meet the requirements refers to the test data with large test errors.

[0047] The photoresist model is calculated using the sliced data of the wafer and strict physical equations. Those skilled in the art are familiar with the strict physical equations and thus will not be elaborated here. The simulation results of the photoresist model are very close to the test results of the actual wafer. Therefore, the simulation critical dimension data of the test pattern can be used to replace the real wafer data by the photoresist model, reducing the time for collecting wafer data and building the OPC simulation model. And only 2 extra weeks are needed to build the strict photoresist model when establishing the photoresist model for the first time. Subsequently, as long as there are film layers with the same photoresist, the time for exposure and development and wafer data collection can be reduced, and there will be no problem that the data cleaning takes a long time due to the error caused by the SEM test noise of the critical dimension (CD) of the wafer during the modeling process of the OPC simulation model.

[0048] Figure 3 It is a detailed flowchart of the method for establishing the OPC simulation model according to the embodiment of the present invention. The method for establishing the OPC simulation model of the test pattern includes:

[0049] Step S21: Obtain the photoresist of the OPC simulation model to be established, and select the photoresist model that is the same as the photoresist of the OPC simulation model to be established;

[0050] Step S22: Determine the design rules, prepare the test pattern, determine the exposure and development conditions, and determine the pattern type and number of points;

[0051] Step S23: Use the photoresist model to simulate the test pattern to generate the critical dimension simulation data of the wafer;

[0052] Step S24: Clean the critical dimension simulation data of the wafer to establish an initial OPC simulation model;

[0053] Step S25: Modify the initial OPC simulation model to remove the hot spots in the test pattern;

[0054] Step S26: Verify the modified OPC simulation model to obtain an OPC simulation model that meets the standards.

[0055] In step S23, the time taken to generate critical dimension simulation data of the wafer by simulating the test pattern using the photoresist model is less than 1 day. Since the photoresist model uses the slice data of the wafer and strict physical equations for calculation, the simulation results of the photoresist model are very close to the test results of the actual wafer. Therefore, the critical dimension simulation data of the wafer obtained by simulating the test pattern using the photoresist model can be used to replace the real critical dimension data of the wafer, reducing the time for collecting the real critical dimension data of the wafer and the time for modeling the OPC simulation model. Also, since actual test data is not required, the number of critical dimension simulation data of the wafer generated by simulating the test pattern using the photoresist model is greater than 1000 points, and those skilled in the art can simulate more critical dimension simulation data of the wafer according to actual needs.

[0056] In step S24, since the critical dimension simulation data of the wafer is obtained by simulating the test pattern using the photoresist model, there will be no noise from SEM testing in the critical dimension simulation data of the wafer. Therefore, during the data cleaning process, it takes less time, that is, there will be no problem that the data cleaning takes a long time due to errors caused by SEM testing noise of the critical dimension (CD) during the modeling process of the OPC simulation model.

[0057] In this embodiment, the critical dimension simulation data of the wafer obtained by simulating the test pattern using the photoresist model is used to replace the real critical dimension data of the wafer, reducing the time for collecting the real critical dimension data of the wafer and the time for modeling the OPC simulation model. Therefore, the time taken to establish the OPC simulation model using the critical dimension simulation data of the wafer generated by simulating the test pattern using the photoresist model is less than 2 weeks.

[0058] In summary, in the method for establishing an OPC simulation model provided by the embodiments of the present invention, multiple photoresist models are first established, where the photoresists in different photoresist models are different, and the photoresist models are established by using test data including wafer slice data and strict physical equations; the photoresist of the to-be-established OPC simulation model is obtained, and the photoresist model with the same photoresist as the to-be-established OPC simulation model is selected, and the key dimension simulation data of the wafer is generated by simulating the test pattern with the photoresist model, so as to establish the OPC simulation model of the test pattern. The present invention uses a mainstream simulation software in the industry to establish a strict photoresist model, which is established by using test data including wafer slice data and strict physical equations, and the simulation result of the photoresist model is very close to the test result of the actual wafer; and the key dimension simulation data of the wafer is generated by simulating the test pattern with the photoresist model to replace the real key dimension data of the wafer, reducing the collection time of the real key dimension data of the wafer and the time for establishing the OPC simulation model. It takes about two weeks to establish a strict photoresist model. When establishing the OPC simulation model for the first time, an additional two weeks are required to establish the strict photoresist model. However, in the future, as long as there is a film layer with the same photoresist, the exposure and development time and the wafer data collection time can be reduced, and there will be no problem that the data cleaning takes a long time due to the error caused by the SEM test noise of the key dimension of the wafer during the process of establishing the OPC simulation model.

[0059] It should be noted that the embodiments in this specification are described in a progressive manner, and the key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other. In addition, the different parts among the embodiments can also be combined and used with each other, and the present invention does not limit this.

[0060] In addition, it should also be recognized that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the disclosed technical content above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.

Claims

1. A method for establishing an OPC simulation model, characterized in that: include: Establishing a plurality of photoresist models, wherein the photoresists in different photoresist models are different, and the photoresist models are established by using test data including wafer slicing data and strict physical equation calculations; Obtain the photoresist of the OPC simulation model to be established, select the photoresist model that is the same as the photoresist of the OPC simulation model to be established, and use the photoresist model to simulate the test pattern to generate critical dimension simulation data of the wafer to establish the OPC simulation model of the test pattern.

2. The method for establishing an OPC simulation model according to claim 1, characterized in that: The method for establishing the light resistance model comprises: Designing the test pattern and determining the information required to establish a light resistance model; Transferring the test pattern to a wafer, forming an actual pattern on the wafer, and acquiring test data of the actual pattern, wherein the test data of the actual pattern includes slice data; Cleaning the test data of the actual pattern to establish an initial photoresist model; Modifying the initial photoresist model to remove hot spots in the test pattern; The modified light resistance model is verified to obtain a light resistance model that meets the standard.

3. The method for establishing an OPC simulation model according to claim 2, characterized in that: The information required to establish a photoresist model includes: determining the pattern and setting rules for establishing the photoresist model, preparing test patterns, and determining exposure and development conditions.

4. The method for establishing an OPC simulation model according to claim 3, characterized in that: The test patterns include dense test patterns, semi-sparse test patterns, sparse test patterns, and anchor points in the test patterns.

5. The method for establishing an OPC simulation model according to claim 3, characterized in that: The exposure and development conditions include baking before exposure or after coating, baking after exposure, development time, light source conditions, mask parameters and film layers of the wafer.

6. The method for establishing an OPC simulation model according to claim 2, characterized in that: The slice data in the test data of the actual pattern includes the thickness and shape of the photoresist along the Z direction of the wafer.

7. The method for establishing an OPC simulation model according to claim 2, characterized in that: The number of points of the test data of the actual graph is less than 1000 points.

8. The method for establishing an OPC simulation model according to claim 1, characterized in that: The different photoresists in the different photoresist models are different in photoresist materials.

9. The method for establishing an OPC simulation model according to claim 1, characterized in that: The method of establishing an OPC simulation model of a test graphic includes: Acquire the photoresist of the OPC simulation model to be established, and select the photoresist model that is the same as the photoresist of the OPC simulation model to be established; Determine design rules, prepare test patterns, determine exposure and development conditions, and determine pattern type and number of dots; Using the photoresist model to simulate the test pattern to generate critical dimension simulation data of the wafer; Performing data cleaning on critical dimension simulation data of the wafer to establish an initial OPC simulation model; Modifying the initial OPC simulation model to remove hot spots in the test pattern; The modified OPC simulation model is verified to obtain an OPC simulation model that complies with the standard.

10. The method for establishing an OPC simulation model according to claim 9, characterized in that: The number of critical dimension simulation data of the wafer generated by simulating the test pattern using the photoresist model is greater than 1000 points.

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